drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dcbx.h"
  32 #include "ecore_l2.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /******************** Doorbell Recovery *******************/
  45 /* The doorbell recovery mechanism consists of a list of entries which represent
  46  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  47  * entity needs to register with the mechanism and provide the parameters
  48  * describing it's doorbell, including a location where last used doorbell data
  49  * can be found. The doorbell execute function will traverse the list and
  50  * doorbell all of the registered entries.
  51  */
  52 struct ecore_db_recovery_entry {
  53         osal_list_entry_t       list_entry;
  54         void OSAL_IOMEM         *db_addr;
  55         void                    *db_data;
  56         enum ecore_db_rec_width db_width;
  57         enum ecore_db_rec_space db_space;
  58         u8                      hwfn_idx;
  59 };
  60
  61 /* display a single doorbell recovery entry */
  62 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  63                                 struct ecore_db_recovery_entry *db_entry,
  64                                 const char *action)
  65 {
  66         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  67                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  68                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  69                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  70                    db_entry->hwfn_idx);
  71 }
  72
  73 /* doorbell address sanity (address within doorbell bar range) */
  74 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  75                          void *db_data)
  76 {
  77         /* make sure doorbell address  is within the doorbell bar */
  78         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  79                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  80                 OSAL_WARN(true,
  81                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  82                           db_addr, p_dev->doorbells,
  83                           (u8 *)p_dev->doorbells + p_dev->db_size);
  84                 return false;
  85         }
  86
  87         /* make sure doorbell data pointer is not null */
  88         if (!db_data) {
  89                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  90                 return false;
  91         }
  92
  93         return true;
  94 }
  95
  96 /* find hwfn according to the doorbell address */
  97 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
  98                                           void OSAL_IOMEM *db_addr)
  99 {
 100         struct ecore_hwfn *p_hwfn;
 101
 102         /* In CMT doorbell bar is split down the middle between engine 0 and
 103          * enigne 1
 104          */
 105         if (ECORE_IS_CMT(p_dev))
 106                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 107                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 108         else
 109                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 110
 111         return p_hwfn;
 112 }
 113
 114 /* add a new entry to the doorbell recovery mechanism */
 115 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 116                                            void OSAL_IOMEM *db_addr,
 117                                            void *db_data,
 118                                            enum ecore_db_rec_width db_width,
 119                                            enum ecore_db_rec_space db_space)
 120 {
 121         struct ecore_db_recovery_entry *db_entry;
 122         struct ecore_hwfn *p_hwfn;
 123
 124         /* shortcircuit VFs, for now */
 125         if (IS_VF(p_dev)) {
 126                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 127                 return ECORE_SUCCESS;
 128         }
 129
 130         /* sanitize doorbell address */
 131         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 132                 return ECORE_INVAL;
 133
 134         /* obtain hwfn from doorbell address */
 135         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 136
 137         /* create entry */
 138         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 139         if (!db_entry) {
 140                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 141                 return ECORE_NOMEM;
 142         }
 143
 144         /* populate entry */
 145         db_entry->db_addr = db_addr;
 146         db_entry->db_data = db_data;
 147         db_entry->db_width = db_width;
 148         db_entry->db_space = db_space;
 149         db_entry->hwfn_idx = p_hwfn->my_id;
 150
 151         /* display */
 152         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 153
 154         /* protect the list */
 155         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 156         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 157                             &p_hwfn->db_recovery_info.list);
 158         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 159
 160         return ECORE_SUCCESS;
 161 }
 162
 163 /* remove an entry from the doorbell recovery mechanism */
 164 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 165                                            void OSAL_IOMEM *db_addr,
 166                                            void *db_data)
 167 {
 168         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 169         enum _ecore_status_t rc = ECORE_INVAL;
 170         struct ecore_hwfn *p_hwfn;
 171
 172         /* shortcircuit VFs, for now */
 173         if (IS_VF(p_dev)) {
 174                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 175                 return ECORE_SUCCESS;
 176         }
 177
 178         /* sanitize doorbell address */
 179         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 180                 return ECORE_INVAL;
 181
 182         /* obtain hwfn from doorbell address */
 183         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 184
 185         /* protect the list */
 186         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 187         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 188                                  &p_hwfn->db_recovery_info.list,
 189                                  list_entry,
 190                                  struct ecore_db_recovery_entry) {
 191                 /* search according to db_data addr since db_addr is not unique
 192                  * (roce)
 193                  */
 194                 if (db_entry->db_data == db_data) {
 195                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 196                                                    "Deleting");
 197                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 198                                                &p_hwfn->db_recovery_info.list);
 199                         rc = ECORE_SUCCESS;
 200                         break;
 201                 }
 202         }
 203
 204         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 205
 206         if (rc == ECORE_INVAL)
 207                 /*OSAL_WARN(true,*/
 208                 DP_NOTICE(p_hwfn, false,
 209                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 210                           db_data, db_addr);
 211         else
 212                 OSAL_FREE(p_dev, db_entry);
 213
 214         return rc;
 215 }
 216
 217 /* initialize the doorbell recovery mechanism */
 218 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 219 {
 220         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 221
 222         /* make sure db_size was set in p_dev */
 223         if (!p_hwfn->p_dev->db_size) {
 224                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 225                 return ECORE_INVAL;
 226         }
 227
 228         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 229 #ifdef CONFIG_ECORE_LOCK_ALLOC
 230         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
 231 #endif
 232         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 233         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 234
 235         return ECORE_SUCCESS;
 236 }
 237
 238 /* destroy the doorbell recovery mechanism */
 239 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 240 {
 241         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 242
 243         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 244         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 245                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 246                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 247                         db_entry = OSAL_LIST_FIRST_ENTRY(
 248                                                 &p_hwfn->db_recovery_info.list,
 249                                                 struct ecore_db_recovery_entry,
 250                                                 list_entry);
 251                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 252                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 253                                                &p_hwfn->db_recovery_info.list);
 254                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 255                 }
 256         }
 257 #ifdef CONFIG_ECORE_LOCK_ALLOC
 258         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 259 #endif
 260         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 261 }
 262
 263 /* print the content of the doorbell recovery mechanism */
 264 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 265 {
 266         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 267
 268         DP_NOTICE(p_hwfn, false,
 269                   "Dispalying doorbell recovery database. Counter was %d\n",
 270                   p_hwfn->db_recovery_info.db_recovery_counter);
 271
 272         /* protect the list */
 273         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 274         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 275                                  &p_hwfn->db_recovery_info.list,
 276                                  list_entry,
 277                                  struct ecore_db_recovery_entry) {
 278                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 279         }
 280
 281         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 282 }
 283
 284 /* ring the doorbell of a single doorbell recovery entry */
 285 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 286                             struct ecore_db_recovery_entry *db_entry,
 287                             enum ecore_db_rec_exec db_exec)
 288 {
 289         /* Print according to width */
 290         if (db_entry->db_width == DB_REC_WIDTH_32B)
 291                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 292                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 293                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 294         else
 295                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 296                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 297                            db_entry->db_addr,
 298                            *(unsigned long *)(db_entry->db_data));
 299
 300         /* Sanity */
 301         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 302                                  db_entry->db_data))
 303                 return;
 304
 305         /* Flush the write combined buffer. Since there are multiple doorbelling
 306          * entities using the same address, if we don't flush, a transaction
 307          * could be lost.
 308          */
 309         OSAL_WMB(p_hwfn->p_dev);
 310
 311         /* Ring the doorbell */
 312         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 313                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 314                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 315                                       *(u32 *)(db_entry->db_data));
 316                 else
 317                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 318                                         *(u64 *)(db_entry->db_data));
 319         }
 320
 321         /* Flush the write combined buffer. Next doorbell may come from a
 322          * different entity to the same address...
 323          */
 324         OSAL_WMB(p_hwfn->p_dev);
 325 }
 326
 327 /* traverse the doorbell recovery entry list and ring all the doorbells */
 328 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 329                                enum ecore_db_rec_exec db_exec)
 330 {
 331         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 332
 333         if (db_exec != DB_REC_ONCE) {
 334                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 335                           p_hwfn->db_recovery_info.db_recovery_counter);
 336
 337                 /* track amount of times recovery was executed */
 338                 p_hwfn->db_recovery_info.db_recovery_counter++;
 339         }
 340
 341         /* protect the list */
 342         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 343         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 344                                  &p_hwfn->db_recovery_info.list,
 345                                  list_entry,
 346                                  struct ecore_db_recovery_entry) {
 347                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 348                 if (db_exec == DB_REC_ONCE)
 349                         break;
 350         }
 351
 352         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 353 }
 354 /******************** Doorbell Recovery end ****************/
 355
 356 /* Configurable */
 357 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
 358                                          * load the driver. The number was
 359                                          * arbitrarily set.
 360                                          */
 361
 362 /* Derived */
 363 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
 364
 365 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
 366                              struct ecore_ptt *p_ptt,
 367                              enum BAR_ID bar_id)
 368 {
 369         u32 bar_reg = (bar_id == BAR_ID_0 ?
 370                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 371         u32 val;
 372
 373         if (IS_VF(p_hwfn->p_dev))
 374                 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
 375
 376         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
 377         if (val)
 378                 return 1 << (val + 15);
 379
 380         /* The above registers were updated in the past only in CMT mode. Since
 381          * they were found to be useful MFW started updating them from 8.7.7.0.
 382          * In older MFW versions they are set to 0 which means disabled.
 383          */
 384         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
 385                 DP_INFO(p_hwfn,
 386                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 387                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 388         } else {
 389                 DP_INFO(p_hwfn,
 390                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 391                 val = 512 * 1024;
 392         }
 393
 394         return val;
 395 }
 396
 397 void ecore_init_dp(struct ecore_dev *p_dev,
 398                    u32 dp_module, u8 dp_level, void *dp_ctx)
 399 {
 400         u32 i;
 401
 402         p_dev->dp_level = dp_level;
 403         p_dev->dp_module = dp_module;
 404         p_dev->dp_ctx = dp_ctx;
 405         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 406                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 407
 408                 p_hwfn->dp_level = dp_level;
 409                 p_hwfn->dp_module = dp_module;
 410                 p_hwfn->dp_ctx = dp_ctx;
 411         }
 412 }
 413
 414 void ecore_init_struct(struct ecore_dev *p_dev)
 415 {
 416         u8 i;
 417
 418         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 419                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 420
 421                 p_hwfn->p_dev = p_dev;
 422                 p_hwfn->my_id = i;
 423                 p_hwfn->b_active = false;
 424
 425 #ifdef CONFIG_ECORE_LOCK_ALLOC
 426                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 427 #endif
 428                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 429         }
 430
 431         /* hwfn 0 is always active */
 432         p_dev->hwfns[0].b_active = true;
 433
 434         /* set the default cache alignment to 128 (may be overridden later) */
 435         p_dev->cache_shift = 7;
 436 }
 437
 438 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 439 {
 440         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 441
 442         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 443         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 444         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 445         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 446 }
 447
 448 void ecore_resc_free(struct ecore_dev *p_dev)
 449 {
 450         int i;
 451
 452         if (IS_VF(p_dev)) {
 453                 for_each_hwfn(p_dev, i)
 454                         ecore_l2_free(&p_dev->hwfns[i]);
 455                 return;
 456         }
 457
 458         OSAL_FREE(p_dev, p_dev->fw_data);
 459
 460         OSAL_FREE(p_dev, p_dev->reset_stats);
 461
 462         for_each_hwfn(p_dev, i) {
 463                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 464
 465                 ecore_cxt_mngr_free(p_hwfn);
 466                 ecore_qm_info_free(p_hwfn);
 467                 ecore_spq_free(p_hwfn);
 468                 ecore_eq_free(p_hwfn);
 469                 ecore_consq_free(p_hwfn);
 470                 ecore_int_free(p_hwfn);
 471                 ecore_iov_free(p_hwfn);
 472                 ecore_l2_free(p_hwfn);
 473                 ecore_dmae_info_free(p_hwfn);
 474                 ecore_dcbx_info_free(p_hwfn);
 475                 /* @@@TBD Flush work-queue ? */
 476
 477                 /* destroy doorbell recovery mechanism */
 478                 ecore_db_recovery_teardown(p_hwfn);
 479         }
 480 }
 481
 482 /******************** QM initialization *******************/
 483
 484 /* bitmaps for indicating active traffic classes.
 485  * Special case for Arrowhead 4 port
 486  */
 487 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 488 #define ACTIVE_TCS_BMAP 0x9f
 489 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 490 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 491
 492 /* determines the physical queue flags for a given PF. */
 493 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 494 {
 495         u32 flags;
 496
 497         /* common flags */
 498         flags = PQ_FLAGS_LB;
 499
 500         /* feature flags */
 501         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 502                 flags |= PQ_FLAGS_VFS;
 503
 504         /* protocol flags */
 505         switch (p_hwfn->hw_info.personality) {
 506         case ECORE_PCI_ETH:
 507                 flags |= PQ_FLAGS_MCOS;
 508                 break;
 509         case ECORE_PCI_FCOE:
 510                 flags |= PQ_FLAGS_OFLD;
 511                 break;
 512         case ECORE_PCI_ISCSI:
 513                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 514                 break;
 515         case ECORE_PCI_ETH_ROCE:
 516                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 517                 break;
 518         case ECORE_PCI_ETH_IWARP:
 519                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 520                          PQ_FLAGS_OFLD;
 521                 break;
 522         default:
 523                 DP_ERR(p_hwfn, "unknown personality %d\n",
 524                        p_hwfn->hw_info.personality);
 525                 return 0;
 526         }
 527         return flags;
 528 }
 529
 530 /* Getters for resource amounts necessary for qm initialization */
 531 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 532 {
 533         return p_hwfn->hw_info.num_hw_tc;
 534 }
 535
 536 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 537 {
 538         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 539                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 540 }
 541
 542 #define NUM_DEFAULT_RLS 1
 543
 544 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 545 {
 546         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 547
 548         /* @DPDK */
 549         /* num RLs can't exceed resource amount of rls or vports or the
 550          * dcqcn qps
 551          */
 552         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 553                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 554
 555         /* make sure after we reserve the default and VF rls we'll have
 556          * something left
 557          */
 558         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 559                 DP_NOTICE(p_hwfn, false,
 560                           "no rate limiters left for PF rate limiting"
 561                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 562                 return 0;
 563         }
 564
 565         /* subtract rls necessary for VFs and one default one for the PF */
 566         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 567
 568         return num_pf_rls;
 569 }
 570
 571 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 572 {
 573         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 574
 575         /* all pqs share the same vport (hence the 1 below), except for vfs
 576          * and pf_rl pqs
 577          */
 578         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 579                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 580                (!!(PQ_FLAGS_VFS & pq_flags)) *
 581                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 582 }
 583
 584 /* calc amount of PQs according to the requested flags */
 585 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 586 {
 587         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 588
 589         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 590                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 591                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 592                 ecore_init_qm_get_num_tcs(p_hwfn) +
 593                (!!(PQ_FLAGS_LB & pq_flags)) +
 594                (!!(PQ_FLAGS_OOO & pq_flags)) +
 595                (!!(PQ_FLAGS_ACK & pq_flags)) +
 596                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 597                (!!(PQ_FLAGS_VFS & pq_flags)) *
 598                 ecore_init_qm_get_num_vfs(p_hwfn);
 599 }
 600
 601 /* initialize the top level QM params */
 602 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 603 {
 604         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 605         bool four_port;
 606
 607         /* pq and vport bases for this PF */
 608         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 609         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 610
 611         /* rate limiting and weighted fair queueing are always enabled */
 612         qm_info->vport_rl_en = 1;
 613         qm_info->vport_wfq_en = 1;
 614
 615         /* TC config is different for AH 4 port */
 616         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 617
 618         /* in AH 4 port we have fewer TCs per port */
 619         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 620                                                      NUM_OF_PHYS_TCS;
 621
 622         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 623          * 4 otherwise
 624          */
 625         if (!qm_info->ooo_tc)
 626                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 627                                               DCBX_TCP_OOO_TC;
 628 }
 629
 630 /* initialize qm vport params */
 631 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 632 {
 633         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 634         u8 i;
 635
 636         /* all vports participate in weighted fair queueing */
 637         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 638                 qm_info->qm_vport_params[i].vport_wfq = 1;
 639 }
 640
 641 /* initialize qm port params */
 642 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 643 {
 644         /* Initialize qm port parameters */
 645         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
 646
 647         /* indicate how ooo and high pri traffic is dealt with */
 648         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 649                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 650
 651         for (i = 0; i < num_ports; i++) {
 652                 struct init_qm_port_params *p_qm_port =
 653                         &p_hwfn->qm_info.qm_port_params[i];
 654
 655                 p_qm_port->active = 1;
 656                 p_qm_port->active_phys_tcs = active_phys_tcs;
 657                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
 658                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 659         }
 660 }
 661
 662 /* Reset the params which must be reset for qm init. QM init may be called as
 663  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 664  * params may be affected by the init but would simply recalculate to the same
 665  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 666  * affected as these amounts stay the same.
 667  */
 668 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 669 {
 670         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 671
 672         qm_info->num_pqs = 0;
 673         qm_info->num_vports = 0;
 674         qm_info->num_pf_rls = 0;
 675         qm_info->num_vf_pqs = 0;
 676         qm_info->first_vf_pq = 0;
 677         qm_info->first_mcos_pq = 0;
 678         qm_info->first_rl_pq = 0;
 679 }
 680
 681 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 682 {
 683         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 684
 685         qm_info->num_vports++;
 686
 687         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 688                 DP_ERR(p_hwfn,
 689                        "vport overflow! qm_info->num_vports %d,"
 690                        " qm_init_get_num_vports() %d\n",
 691                        qm_info->num_vports,
 692                        ecore_init_qm_get_num_vports(p_hwfn));
 693 }
 694
 695 /* initialize a single pq and manage qm_info resources accounting.
 696  * The pq_init_flags param determines whether the PQ is rate limited
 697  * (for VF or PF)
 698  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 699  * shared)
 700  */
 701
 702 /* flags for pq init */
 703 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 704 #define PQ_INIT_PF_RL           (1 << 1)
 705 #define PQ_INIT_VF_RL           (1 << 2)
 706
 707 /* defines for pq init */
 708 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 709 #define PQ_INIT_DEFAULT_TC              0
 710 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 711
 712 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 713                              struct ecore_qm_info *qm_info,
 714                              u8 tc, u32 pq_init_flags)
 715 {
 716         u16 pq_idx = qm_info->num_pqs, max_pq =
 717                                         ecore_init_qm_get_num_pqs(p_hwfn);
 718
 719         if (pq_idx > max_pq)
 720                 DP_ERR(p_hwfn,
 721                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 722
 723         /* init pq params */
 724         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 725                                                  qm_info->num_vports;
 726         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 727         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 728         qm_info->qm_pq_params[pq_idx].rl_valid =
 729                 (pq_init_flags & PQ_INIT_PF_RL ||
 730                  pq_init_flags & PQ_INIT_VF_RL);
 731
 732         /* qm params accounting */
 733         qm_info->num_pqs++;
 734         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 735                 qm_info->num_vports++;
 736
 737         if (pq_init_flags & PQ_INIT_PF_RL)
 738                 qm_info->num_pf_rls++;
 739
 740         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 741                 DP_ERR(p_hwfn,
 742                        "vport overflow! qm_info->num_vports %d,"
 743                        " qm_init_get_num_vports() %d\n",
 744                        qm_info->num_vports,
 745                        ecore_init_qm_get_num_vports(p_hwfn));
 746
 747         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 748                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 749                        " qm_init_get_num_pf_rls() %d\n",
 750                        qm_info->num_pf_rls,
 751                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 752 }
 753
 754 /* get pq index according to PQ_FLAGS */
 755 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 756                                              u32 pq_flags)
 757 {
 758         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 759
 760         /* Can't have multiple flags set here */
 761         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 762                                 sizeof(pq_flags)) > 1)
 763                 goto err;
 764
 765         switch (pq_flags) {
 766         case PQ_FLAGS_RLS:
 767                 return &qm_info->first_rl_pq;
 768         case PQ_FLAGS_MCOS:
 769                 return &qm_info->first_mcos_pq;
 770         case PQ_FLAGS_LB:
 771                 return &qm_info->pure_lb_pq;
 772         case PQ_FLAGS_OOO:
 773                 return &qm_info->ooo_pq;
 774         case PQ_FLAGS_ACK:
 775                 return &qm_info->pure_ack_pq;
 776         case PQ_FLAGS_OFLD:
 777                 return &qm_info->offload_pq;
 778         case PQ_FLAGS_VFS:
 779                 return &qm_info->first_vf_pq;
 780         default:
 781                 goto err;
 782         }
 783
 784 err:
 785         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 786         return OSAL_NULL;
 787 }
 788
 789 /* save pq index in qm info */
 790 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 791                                   u32 pq_flags, u16 pq_val)
 792 {
 793         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 794
 795         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 796 }
 797
 798 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 799 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 800 {
 801         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 802
 803         return *base_pq_idx + CM_TX_PQ_BASE;
 804 }
 805
 806 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 807 {
 808         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 809
 810         if (tc > max_tc)
 811                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 812
 813         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 814 }
 815
 816 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 817 {
 818         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 819
 820         if (vf > max_vf)
 821                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 822
 823         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 824 }
 825
 826 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 827 {
 828         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 829
 830         if (rl > max_rl)
 831                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 832
 833         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 834 }
 835
 836 /* Functions for creating specific types of pqs */
 837 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 838 {
 839         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 840
 841         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 842                 return;
 843
 844         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 845         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 846 }
 847
 848 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 849 {
 850         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 851
 852         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 853                 return;
 854
 855         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 856         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 857 }
 858
 859 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 860 {
 861         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 862
 863         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 864                 return;
 865
 866         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 867         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 868 }
 869
 870 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 871 {
 872         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 873
 874         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 875                 return;
 876
 877         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 878         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 879 }
 880
 881 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 882 {
 883         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 884         u8 tc_idx;
 885
 886         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 887                 return;
 888
 889         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 890         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 891                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 892 }
 893
 894 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 895 {
 896         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 897         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 898
 899         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 900                 return;
 901
 902         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 903
 904         qm_info->num_vf_pqs = num_vfs;
 905         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 906                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 907                                  PQ_INIT_VF_RL);
 908 }
 909
 910 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 911 {
 912         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 913         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 914
 915         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 916                 return;
 917
 918         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 919         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 920                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 921                                  PQ_INIT_PF_RL);
 922 }
 923
 924 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 925 {
 926         /* rate limited pqs, must come first (FW assumption) */
 927         ecore_init_qm_rl_pqs(p_hwfn);
 928
 929         /* pqs for multi cos */
 930         ecore_init_qm_mcos_pqs(p_hwfn);
 931
 932         /* pure loopback pq */
 933         ecore_init_qm_lb_pq(p_hwfn);
 934
 935         /* out of order pq */
 936         ecore_init_qm_ooo_pq(p_hwfn);
 937
 938         /* pure ack pq */
 939         ecore_init_qm_pure_ack_pq(p_hwfn);
 940
 941         /* pq for offloaded protocol */
 942         ecore_init_qm_offload_pq(p_hwfn);
 943
 944         /* done sharing vports */
 945         ecore_init_qm_advance_vport(p_hwfn);
 946
 947         /* pqs for vfs */
 948         ecore_init_qm_vf_pqs(p_hwfn);
 949 }
 950
 951 /* compare values of getters against resources amounts */
 952 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 953 {
 954         if (ecore_init_qm_get_num_vports(p_hwfn) >
 955             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 956                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 957                 return ECORE_INVAL;
 958         }
 959
 960         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 961                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 962                 return ECORE_INVAL;
 963         }
 964
 965         return ECORE_SUCCESS;
 966 }
 967
 968 /*
 969  * Function for verbose printing of the qm initialization results
 970  */
 971 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 972 {
 973         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 974         struct init_qm_vport_params *vport;
 975         struct init_qm_port_params *port;
 976         struct init_qm_pq_params *pq;
 977         int i, tc;
 978
 979         /* top level params */
 980         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 981                    "qm init top level params: start_pq %d, start_vport %d,"
 982                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 983                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 984                    qm_info->offload_pq, qm_info->pure_ack_pq);
 985         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 986                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 987                    " num_vports %d, max_phys_tcs_per_port %d\n",
 988                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 989                    qm_info->num_vf_pqs, qm_info->num_vports,
 990                    qm_info->max_phys_tcs_per_port);
 991         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 992                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 993                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 994                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 995                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 996                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 997
 998         /* port table */
 999         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1000                 port = &qm_info->qm_port_params[i];
1001                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1002                            "port idx %d, active %d, active_phys_tcs %d,"
1003                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1004                            " reserved %d\n",
1005                            i, port->active, port->active_phys_tcs,
1006                            port->num_pbf_cmd_lines, port->num_btb_blocks,
1007                            port->reserved);
1008         }
1009
1010         /* vport table */
1011         for (i = 0; i < qm_info->num_vports; i++) {
1012                 vport = &qm_info->qm_vport_params[i];
1013                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1014                            "vport idx %d, vport_rl %d, wfq %d,"
1015                            " first_tx_pq_id [ ",
1016                            qm_info->start_vport + i, vport->vport_rl,
1017                            vport->vport_wfq);
1018                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1019                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1020                                    vport->first_tx_pq_id[tc]);
1021                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1022         }
1023
1024         /* pq table */
1025         for (i = 0; i < qm_info->num_pqs; i++) {
1026                 pq = &qm_info->qm_pq_params[i];
1027                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1028                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
1029                            " rl_valid %d\n",
1030                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
1031                            pq->wrr_group, pq->rl_valid);
1032         }
1033 }
1034
1035 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1036 {
1037         /* reset params required for init run */
1038         ecore_init_qm_reset_params(p_hwfn);
1039
1040         /* init QM top level params */
1041         ecore_init_qm_params(p_hwfn);
1042
1043         /* init QM port params */
1044         ecore_init_qm_port_params(p_hwfn);
1045
1046         /* init QM vport params */
1047         ecore_init_qm_vport_params(p_hwfn);
1048
1049         /* init QM physical queue params */
1050         ecore_init_qm_pq_params(p_hwfn);
1051
1052         /* display all that init */
1053         ecore_dp_init_qm_params(p_hwfn);
1054 }
1055
1056 /* This function reconfigures the QM pf on the fly.
1057  * For this purpose we:
1058  * 1. reconfigure the QM database
1059  * 2. set new values to runtime array
1060  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1061  * 4. activate init tool in QM_PF stage
1062  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1063  */
1064 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1065                                      struct ecore_ptt *p_ptt)
1066 {
1067         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1068         bool b_rc;
1069         enum _ecore_status_t rc;
1070
1071         /* initialize ecore's qm data structure */
1072         ecore_init_qm_info(p_hwfn);
1073
1074         /* stop PF's qm queues */
1075         OSAL_SPIN_LOCK(&qm_lock);
1076         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1077                                       qm_info->start_pq, qm_info->num_pqs);
1078         OSAL_SPIN_UNLOCK(&qm_lock);
1079         if (!b_rc)
1080                 return ECORE_INVAL;
1081
1082         /* clear the QM_PF runtime phase leftovers from previous init */
1083         ecore_init_clear_rt_data(p_hwfn);
1084
1085         /* prepare QM portion of runtime array */
1086         ecore_qm_init_pf(p_hwfn, p_ptt);
1087
1088         /* activate init tool on runtime array */
1089         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1090                             p_hwfn->hw_info.hw_mode);
1091         if (rc != ECORE_SUCCESS)
1092                 return rc;
1093
1094         /* start PF's qm queues */
1095         OSAL_SPIN_LOCK(&qm_lock);
1096         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1097                                       qm_info->start_pq, qm_info->num_pqs);
1098         OSAL_SPIN_UNLOCK(&qm_lock);
1099         if (!b_rc)
1100                 return ECORE_INVAL;
1101
1102         return ECORE_SUCCESS;
1103 }
1104
1105 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1106 {
1107         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1108         enum _ecore_status_t rc;
1109
1110         rc = ecore_init_qm_sanity(p_hwfn);
1111         if (rc != ECORE_SUCCESS)
1112                 goto alloc_err;
1113
1114         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1115                                             sizeof(struct init_qm_pq_params) *
1116                                             ecore_init_qm_get_num_pqs(p_hwfn));
1117         if (!qm_info->qm_pq_params)
1118                 goto alloc_err;
1119
1120         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1121                                        sizeof(struct init_qm_vport_params) *
1122                                        ecore_init_qm_get_num_vports(p_hwfn));
1123         if (!qm_info->qm_vport_params)
1124                 goto alloc_err;
1125
1126         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1127                                       sizeof(struct init_qm_port_params) *
1128                                       p_hwfn->p_dev->num_ports_in_engine);
1129         if (!qm_info->qm_port_params)
1130                 goto alloc_err;
1131
1132         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1133                                         sizeof(struct ecore_wfq_data) *
1134                                         ecore_init_qm_get_num_vports(p_hwfn));
1135         if (!qm_info->wfq_data)
1136                 goto alloc_err;
1137
1138         return ECORE_SUCCESS;
1139
1140 alloc_err:
1141         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1142         ecore_qm_info_free(p_hwfn);
1143         return ECORE_NOMEM;
1144 }
1145 /******************** End QM initialization ***************/
1146
1147 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1148 {
1149         enum _ecore_status_t rc = ECORE_SUCCESS;
1150         int i;
1151
1152         if (IS_VF(p_dev)) {
1153                 for_each_hwfn(p_dev, i) {
1154                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1155                         if (rc != ECORE_SUCCESS)
1156                                 return rc;
1157                 }
1158                 return rc;
1159         }
1160
1161         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1162                                      sizeof(*p_dev->fw_data));
1163         if (!p_dev->fw_data)
1164                 return ECORE_NOMEM;
1165
1166         for_each_hwfn(p_dev, i) {
1167                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1168                 u32 n_eqes, num_cons;
1169
1170                 /* initialize the doorbell recovery mechanism */
1171                 rc = ecore_db_recovery_setup(p_hwfn);
1172                 if (rc)
1173                         goto alloc_err;
1174
1175                 /* First allocate the context manager structure */
1176                 rc = ecore_cxt_mngr_alloc(p_hwfn);
1177                 if (rc)
1178                         goto alloc_err;
1179
1180                 /* Set the HW cid/tid numbers (in the context manager)
1181                  * Must be done prior to any further computations.
1182                  */
1183                 rc = ecore_cxt_set_pf_params(p_hwfn);
1184                 if (rc)
1185                         goto alloc_err;
1186
1187                 rc = ecore_alloc_qm_data(p_hwfn);
1188                 if (rc)
1189                         goto alloc_err;
1190
1191                 /* init qm info */
1192                 ecore_init_qm_info(p_hwfn);
1193
1194                 /* Compute the ILT client partition */
1195                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1196                 if (rc)
1197                         goto alloc_err;
1198
1199                 /* CID map / ILT shadow table / T2
1200                  * The talbes sizes are determined by the computations above
1201                  */
1202                 rc = ecore_cxt_tables_alloc(p_hwfn);
1203                 if (rc)
1204                         goto alloc_err;
1205
1206                 /* SPQ, must follow ILT because initializes SPQ context */
1207                 rc = ecore_spq_alloc(p_hwfn);
1208                 if (rc)
1209                         goto alloc_err;
1210
1211                 /* SP status block allocation */
1212                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1213                                                            RESERVED_PTT_DPC);
1214
1215                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1216                 if (rc)
1217                         goto alloc_err;
1218
1219                 rc = ecore_iov_alloc(p_hwfn);
1220                 if (rc)
1221                         goto alloc_err;
1222
1223                 /* EQ */
1224                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1225                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1226                         /* Calculate the EQ size
1227                          * ---------------------
1228                          * Each ICID may generate up to one event at a time i.e.
1229                          * the event must be handled/cleared before a new one
1230                          * can be generated. We calculate the sum of events per
1231                          * protocol and create an EQ deep enough to handle the
1232                          * worst case:
1233                          * - Core - according to SPQ.
1234                          * - RoCE - per QP there are a couple of ICIDs, one
1235                          *        responder and one requester, each can
1236                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
1237                          *        Each CQ can generate an EQE. There are 2 CQs
1238                          *        per QP => n_eqes_cq = 2 * n_qp.
1239                          *        Hence the RoCE total is 4 * n_qp or
1240                          *        2 * num_cons.
1241                          * - ENet - There can be up to two events per VF. One
1242                          *        for VF-PF channel and another for VF FLR
1243                          *        initial cleanup. The number of VFs is
1244                          *        bounded by MAX_NUM_VFS_BB, and is much
1245                          *        smaller than RoCE's so we avoid exact
1246                          *        calculation.
1247                          */
1248                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1249                                 num_cons =
1250                                     ecore_cxt_get_proto_cid_count(
1251                                                 p_hwfn,
1252                                                 PROTOCOLID_ROCE,
1253                                                 OSAL_NULL);
1254                                 num_cons *= 2;
1255                         } else {
1256                                 num_cons = ecore_cxt_get_proto_cid_count(
1257                                                 p_hwfn,
1258                                                 PROTOCOLID_IWARP,
1259                                                 OSAL_NULL);
1260                         }
1261                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1262                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1263                         num_cons =
1264                             ecore_cxt_get_proto_cid_count(p_hwfn,
1265                                                           PROTOCOLID_ISCSI,
1266                                                           OSAL_NULL);
1267                         n_eqes += 2 * num_cons;
1268                 }
1269
1270                 if (n_eqes > 0xFFFF) {
1271                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1272                                        "The maximum of a u16 chain is 0x%x\n",
1273                                n_eqes, 0xFFFF);
1274                         goto alloc_no_mem;
1275                 }
1276
1277                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1278                 if (rc)
1279                         goto alloc_err;
1280
1281                 rc = ecore_consq_alloc(p_hwfn);
1282                 if (rc)
1283                         goto alloc_err;
1284
1285                 rc = ecore_l2_alloc(p_hwfn);
1286                 if (rc != ECORE_SUCCESS)
1287                         goto alloc_err;
1288
1289                 /* DMA info initialization */
1290                 rc = ecore_dmae_info_alloc(p_hwfn);
1291                 if (rc) {
1292                         DP_NOTICE(p_hwfn, true,
1293                                   "Failed to allocate memory for dmae_info"
1294                                   " structure\n");
1295                         goto alloc_err;
1296                 }
1297
1298                 /* DCBX initialization */
1299                 rc = ecore_dcbx_info_alloc(p_hwfn);
1300                 if (rc) {
1301                         DP_NOTICE(p_hwfn, true,
1302                                   "Failed to allocate memory for dcbx structure\n");
1303                         goto alloc_err;
1304                 }
1305         }
1306
1307         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1308                                          sizeof(*p_dev->reset_stats));
1309         if (!p_dev->reset_stats) {
1310                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1311                 goto alloc_no_mem;
1312         }
1313
1314         return ECORE_SUCCESS;
1315
1316 alloc_no_mem:
1317         rc = ECORE_NOMEM;
1318 alloc_err:
1319         ecore_resc_free(p_dev);
1320         return rc;
1321 }
1322
1323 void ecore_resc_setup(struct ecore_dev *p_dev)
1324 {
1325         int i;
1326
1327         if (IS_VF(p_dev)) {
1328                 for_each_hwfn(p_dev, i)
1329                         ecore_l2_setup(&p_dev->hwfns[i]);
1330                 return;
1331         }
1332
1333         for_each_hwfn(p_dev, i) {
1334                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1335
1336                 ecore_cxt_mngr_setup(p_hwfn);
1337                 ecore_spq_setup(p_hwfn);
1338                 ecore_eq_setup(p_hwfn);
1339                 ecore_consq_setup(p_hwfn);
1340
1341                 /* Read shadow of current MFW mailbox */
1342                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1343                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1344                             p_hwfn->mcp_info->mfw_mb_cur,
1345                             p_hwfn->mcp_info->mfw_mb_length);
1346
1347                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1348
1349                 ecore_l2_setup(p_hwfn);
1350                 ecore_iov_setup(p_hwfn);
1351         }
1352 }
1353
1354 #define FINAL_CLEANUP_POLL_CNT  (100)
1355 #define FINAL_CLEANUP_POLL_TIME (10)
1356 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1357                                          struct ecore_ptt *p_ptt,
1358                                          u16 id, bool is_vf)
1359 {
1360         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1361         enum _ecore_status_t rc = ECORE_TIMEOUT;
1362
1363 #ifndef ASIC_ONLY
1364         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1365             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1366                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1367                 return ECORE_SUCCESS;
1368         }
1369 #endif
1370
1371         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1372             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1373
1374         if (is_vf)
1375                 id += 0x10;
1376
1377         command |= X_FINAL_CLEANUP_AGG_INT <<
1378             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1379         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1380         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1381         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1382
1383 /* Make sure notification is not set before initiating final cleanup */
1384
1385         if (REG_RD(p_hwfn, addr)) {
1386                 DP_NOTICE(p_hwfn, false,
1387                           "Unexpected; Found final cleanup notification");
1388                 DP_NOTICE(p_hwfn, false,
1389                           " before initiating final cleanup\n");
1390                 REG_WR(p_hwfn, addr, 0);
1391         }
1392
1393         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1394                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1395                    id, command);
1396
1397         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1398
1399         /* Poll until completion */
1400         while (!REG_RD(p_hwfn, addr) && count--)
1401                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1402
1403         if (REG_RD(p_hwfn, addr))
1404                 rc = ECORE_SUCCESS;
1405         else
1406                 DP_NOTICE(p_hwfn, true,
1407                           "Failed to receive FW final cleanup notification\n");
1408
1409         /* Cleanup afterwards */
1410         REG_WR(p_hwfn, addr, 0);
1411
1412         return rc;
1413 }
1414
1415 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1416 {
1417         int hw_mode = 0;
1418
1419         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1420                 hw_mode |= 1 << MODE_BB;
1421         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1422                 hw_mode |= 1 << MODE_K2;
1423         } else {
1424                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1425                           p_hwfn->p_dev->type);
1426                 return ECORE_INVAL;
1427         }
1428
1429         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1430         switch (p_hwfn->p_dev->num_ports_in_engine) {
1431         case 1:
1432                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1433                 break;
1434         case 2:
1435                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1436                 break;
1437         case 4:
1438                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1439                 break;
1440         default:
1441                 DP_NOTICE(p_hwfn, true,
1442                           "num_ports_in_engine = %d not supported\n",
1443                           p_hwfn->p_dev->num_ports_in_engine);
1444                 return ECORE_INVAL;
1445         }
1446
1447         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1448                           &p_hwfn->p_dev->mf_bits))
1449                 hw_mode |= 1 << MODE_MF_SD;
1450         else
1451                 hw_mode |= 1 << MODE_MF_SI;
1452
1453 #ifndef ASIC_ONLY
1454         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1455                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1456                         hw_mode |= 1 << MODE_FPGA;
1457                 } else {
1458                         if (p_hwfn->p_dev->b_is_emul_full)
1459                                 hw_mode |= 1 << MODE_EMUL_FULL;
1460                         else
1461                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1462                 }
1463         } else
1464 #endif
1465                 hw_mode |= 1 << MODE_ASIC;
1466
1467         if (ECORE_IS_CMT(p_hwfn->p_dev))
1468                 hw_mode |= 1 << MODE_100G;
1469
1470         p_hwfn->hw_info.hw_mode = hw_mode;
1471
1472         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1473                    "Configuring function for hw_mode: 0x%08x\n",
1474                    p_hwfn->hw_info.hw_mode);
1475
1476         return ECORE_SUCCESS;
1477 }
1478
1479 #ifndef ASIC_ONLY
1480 /* MFW-replacement initializations for non-ASIC */
1481 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1482                                                struct ecore_ptt *p_ptt)
1483 {
1484         struct ecore_dev *p_dev = p_hwfn->p_dev;
1485         u32 pl_hv = 1;
1486         int i;
1487
1488         if (CHIP_REV_IS_EMUL(p_dev)) {
1489                 if (ECORE_IS_AH(p_dev))
1490                         pl_hv |= 0x600;
1491         }
1492
1493         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1494
1495         if (CHIP_REV_IS_EMUL(p_dev) &&
1496             (ECORE_IS_AH(p_dev)))
1497                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1498                          0x3ffffff);
1499
1500         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1501         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1502         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1503                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1504
1505         if (CHIP_REV_IS_EMUL(p_dev)) {
1506                 if (ECORE_IS_AH(p_dev)) {
1507                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1508                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1509                                  (p_dev->num_ports_in_engine >> 1));
1510
1511                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1512                                  p_dev->num_ports_in_engine == 4 ? 0 : 3);
1513                 }
1514         }
1515
1516         /* Poll on RBC */
1517         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1518         for (i = 0; i < 100; i++) {
1519                 OSAL_UDELAY(50);
1520                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1521                         break;
1522         }
1523         if (i == 100)
1524                 DP_NOTICE(p_hwfn, true,
1525                           "RBC done failed to complete in PSWRQ2\n");
1526
1527         return ECORE_SUCCESS;
1528 }
1529 #endif
1530
1531 /* Init run time data for all PFs and their VFs on an engine.
1532  * TBD - for VFs - Once we have parent PF info for each VF in
1533  * shmem available as CAU requires knowledge of parent PF for each VF.
1534  */
1535 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1536 {
1537         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1538         int i, igu_sb_id;
1539
1540         for_each_hwfn(p_dev, i) {
1541                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1542                 struct ecore_igu_info *p_igu_info;
1543                 struct ecore_igu_block *p_block;
1544                 struct cau_sb_entry sb_entry;
1545
1546                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1547
1548                 for (igu_sb_id = 0;
1549                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1550                      igu_sb_id++) {
1551                         p_block = &p_igu_info->entry[igu_sb_id];
1552
1553                         if (!p_block->is_pf)
1554                                 continue;
1555
1556                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1557                                                 p_block->function_id, 0, 0);
1558                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1559                                          sb_entry);
1560                 }
1561         }
1562 }
1563
1564 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1565                                        struct ecore_ptt *p_ptt)
1566 {
1567         u32 val, wr_mbs, cache_line_size;
1568
1569         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1570         switch (val) {
1571         case 0:
1572                 wr_mbs = 128;
1573                 break;
1574         case 1:
1575                 wr_mbs = 256;
1576                 break;
1577         case 2:
1578                 wr_mbs = 512;
1579                 break;
1580         default:
1581                 DP_INFO(p_hwfn,
1582                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1583                         val);
1584                 return;
1585         }
1586
1587         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1588         switch (cache_line_size) {
1589         case 32:
1590                 val = 0;
1591                 break;
1592         case 64:
1593                 val = 1;
1594                 break;
1595         case 128:
1596                 val = 2;
1597                 break;
1598         case 256:
1599                 val = 3;
1600                 break;
1601         default:
1602                 DP_INFO(p_hwfn,
1603                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1604                         cache_line_size);
1605         }
1606
1607         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1608                 DP_INFO(p_hwfn,
1609                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1610                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1611
1612         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1613         if (val > 0) {
1614                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1615                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1616         }
1617 }
1618
1619 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1620                                                  struct ecore_ptt *p_ptt,
1621                                                  int hw_mode)
1622 {
1623         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1624         struct ecore_dev *p_dev = p_hwfn->p_dev;
1625         u8 vf_id, max_num_vfs;
1626         u16 num_pfs, pf_id;
1627         u32 concrete_fid;
1628         enum _ecore_status_t rc = ECORE_SUCCESS;
1629
1630         ecore_init_cau_rt_data(p_dev);
1631
1632         /* Program GTT windows */
1633         ecore_gtt_init(p_hwfn, p_ptt);
1634
1635 #ifndef ASIC_ONLY
1636         if (CHIP_REV_IS_EMUL(p_dev)) {
1637                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1638                 if (rc != ECORE_SUCCESS)
1639                         return rc;
1640         }
1641 #endif
1642
1643         if (p_hwfn->mcp_info) {
1644                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1645                         qm_info->pf_rl_en = 1;
1646                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1647                         qm_info->pf_wfq_en = 1;
1648         }
1649
1650         ecore_qm_common_rt_init(p_hwfn,
1651                                 p_dev->num_ports_in_engine,
1652                                 qm_info->max_phys_tcs_per_port,
1653                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1654                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1655                                 qm_info->qm_port_params);
1656
1657         ecore_cxt_hw_init_common(p_hwfn);
1658
1659         ecore_init_cache_line_size(p_hwfn, p_ptt);
1660
1661         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1662         if (rc != ECORE_SUCCESS)
1663                 return rc;
1664
1665         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1666          * need to decide with which value, maybe runtime
1667          */
1668         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1669         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1670
1671         if (ECORE_IS_BB(p_dev)) {
1672                 /* Workaround clears ROCE search for all functions to prevent
1673                  * involving non initialized function in processing ROCE packet.
1674                  */
1675                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1676                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1677                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1678                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1679                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1680                 }
1681                 /* pretend to original PF */
1682                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1683         }
1684
1685         /* Workaround for avoiding CCFC execution error when getting packets
1686          * with CRC errors, and allowing instead the invoking of the FW error
1687          * handler.
1688          * This is not done inside the init tool since it currently can't
1689          * perform a pretending to VFs.
1690          */
1691         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1692         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1693                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1694                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1695                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1696                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1697                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1698                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1699         }
1700         /* pretend to original PF */
1701         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1702
1703         return rc;
1704 }
1705
1706 #ifndef ASIC_ONLY
1707 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1708 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1709
1710 #define PMEG_IF_BYTE_COUNT      8
1711
1712 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1713                              struct ecore_ptt *p_ptt,
1714                              u32 addr, u64 data, u8 reg_type, u8 port)
1715 {
1716         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1717                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1718                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1719                    (8 << PMEG_IF_BYTE_COUNT),
1720                    (reg_type << 25) | (addr << 8) | port,
1721                    (u32)((data >> 32) & 0xffffffff),
1722                    (u32)(data & 0xffffffff));
1723
1724         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1725                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1726                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1727         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1728                  (reg_type << 25) | (addr << 8) | port);
1729         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1730         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1731                  (data >> 32) & 0xffffffff);
1732 }
1733
1734 #define XLPORT_MODE_REG (0x20a)
1735 #define XLPORT_MAC_CONTROL (0x210)
1736 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1737 #define XLPORT_ENABLE_REG (0x20b)
1738
1739 #define XLMAC_CTRL (0x600)
1740 #define XLMAC_MODE (0x601)
1741 #define XLMAC_RX_MAX_SIZE (0x608)
1742 #define XLMAC_TX_CTRL (0x604)
1743 #define XLMAC_PAUSE_CTRL (0x60d)
1744 #define XLMAC_PFC_CTRL (0x60e)
1745
1746 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1747                                     struct ecore_ptt *p_ptt)
1748 {
1749         u8 loopback = 0, port = p_hwfn->port_id * 2;
1750
1751         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1752
1753         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1754         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1755                          port);
1756         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1757         /* XLMAC: SOFT RESET */
1758         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1759         /* XLMAC: Port Speed >= 10Gbps */
1760         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1761         /* XLMAC: Max Size */
1762         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1763         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1764                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1765                          0, port);
1766         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1767         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1768                          0x30ffffc000ULL, 0, port);
1769         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1770                          port); /* XLMAC: TX_EN, RX_EN */
1771         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1772         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1773                          0x1003 | (loopback << 2), 0, port);
1774         /* Enabled Parallel PFC interface */
1775         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1776
1777         /* XLPORT port enable */
1778         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1779 }
1780
1781 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1782                                        struct ecore_ptt *p_ptt)
1783 {
1784         u8 port = p_hwfn->port_id;
1785         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1786
1787         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1788
1789         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1790                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1791                  (port <<
1792                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1793                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1794
1795         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1796                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1797
1798         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1799                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1800
1801         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1802                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1803
1804         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1805                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1806
1807         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1808                  (0xA <<
1809                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1810                  (8 <<
1811                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1812
1813         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1814                  0xa853);
1815 }
1816
1817 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1818                                  struct ecore_ptt *p_ptt)
1819 {
1820         if (ECORE_IS_AH(p_hwfn->p_dev))
1821                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1822         else /* BB */
1823                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1824 }
1825
1826 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1827                                struct ecore_ptt *p_ptt,  u8 port)
1828 {
1829         int port_offset = port ? 0x800 : 0;
1830         u32 xmac_rxctrl = 0;
1831
1832         /* Reset of XMAC */
1833         /* FIXME: move to common start */
1834         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1835                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1836         OSAL_MSLEEP(1);
1837         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1838                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1839
1840         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1841
1842         /* Set the number of ports on the Warp Core to 10G */
1843         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1844
1845         /* Soft reset of XMAC */
1846         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1847                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1848         OSAL_MSLEEP(1);
1849         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1850                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1851
1852         /* FIXME: move to common end */
1853         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1854                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1855
1856         /* Set Max packet size: initialize XMAC block register for port 0 */
1857         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1858
1859         /* CRC append for Tx packets: init XMAC block register for port 1 */
1860         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1861
1862         /* Enable TX and RX: initialize XMAC block register for port 1 */
1863         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1864                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1865         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1866                                XMAC_REG_RX_CTRL_BB + port_offset);
1867         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1868         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1869 }
1870 #endif
1871
1872 static enum _ecore_status_t
1873 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1874                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1875 {
1876         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1877         u32 min_dpis;
1878         u32 n_wids;
1879
1880         /* Calculate DPI size
1881          * ------------------
1882          * The PWM region contains Doorbell Pages. The first is reserverd for
1883          * the kernel for, e.g, L2. The others are free to be used by non-
1884          * trusted applications, typically from user space. Each page, called a
1885          * doorbell page is sectioned into windows that allow doorbells to be
1886          * issued in parallel by the kernel/application. The size of such a
1887          * window (a.k.a. WID) is 1kB.
1888          * Summary:
1889          *    1kB WID x N WIDS = DPI page size
1890          *    DPI page size x N DPIs = PWM region size
1891          * Notes:
1892          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1893          * in order to ensure that two applications won't share the same page.
1894          * It also must contain at least one WID per CPU to allow parallelism.
1895          * It also must be a power of 2, since it is stored as a bit shift.
1896          *
1897          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1898          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1899          * containing 4 WIDs.
1900          */
1901         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1902         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1903         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1904                         ~(OSAL_PAGE_SIZE - 1);
1905         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1906         dpi_count = pwm_region_size / dpi_page_size;
1907
1908         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1909         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1910
1911         /* Update hwfn */
1912         p_hwfn->dpi_size = dpi_page_size;
1913         p_hwfn->dpi_count = dpi_count;
1914
1915         /* Update registers */
1916         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1917
1918         if (dpi_count < min_dpis)
1919                 return ECORE_NORESOURCES;
1920
1921         return ECORE_SUCCESS;
1922 }
1923
1924 enum ECORE_ROCE_EDPM_MODE {
1925         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1926         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1927         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1928 };
1929
1930 static enum _ecore_status_t
1931 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1932                               struct ecore_ptt *p_ptt)
1933 {
1934         u32 pwm_regsize, norm_regsize;
1935         u32 non_pwm_conn, min_addr_reg1;
1936         u32 db_bar_size, n_cpus;
1937         u32 roce_edpm_mode;
1938         u32 pf_dems_shift;
1939         enum _ecore_status_t rc = ECORE_SUCCESS;
1940         u8 cond;
1941
1942         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1943         if (ECORE_IS_CMT(p_hwfn->p_dev))
1944                 db_bar_size /= 2;
1945
1946         /* Calculate doorbell regions
1947          * -----------------------------------
1948          * The doorbell BAR is made of two regions. The first is called normal
1949          * region and the second is called PWM region. In the normal region
1950          * each ICID has its own set of addresses so that writing to that
1951          * specific address identifies the ICID. In the Process Window Mode
1952          * region the ICID is given in the data written to the doorbell. The
1953          * above per PF register denotes the offset in the doorbell BAR in which
1954          * the PWM region begins.
1955          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1956          * non-PWM connection. The calculation below computes the total non-PWM
1957          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1958          * in units of 4,096 bytes.
1959          */
1960         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1961             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1962                                           OSAL_NULL) +
1963             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1964         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
1965                                OSAL_PAGE_SIZE);
1966         min_addr_reg1 = norm_regsize / 4096;
1967         pwm_regsize = db_bar_size - norm_regsize;
1968
1969         /* Check that the normal and PWM sizes are valid */
1970         if (db_bar_size < norm_regsize) {
1971                 DP_ERR(p_hwfn->p_dev,
1972                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1973                        db_bar_size, norm_regsize);
1974                 return ECORE_NORESOURCES;
1975         }
1976         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1977                 DP_ERR(p_hwfn->p_dev,
1978                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1979                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1980                        norm_regsize);
1981                 return ECORE_NORESOURCES;
1982         }
1983
1984         /* Calculate number of DPIs */
1985         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1986         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1987             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1988                 /* Either EDPM is mandatory, or we are attempting to allocate a
1989                  * WID per CPU.
1990                  */
1991                 n_cpus = OSAL_NUM_CPUS();
1992                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1993         }
1994
1995         cond = ((rc != ECORE_SUCCESS) &&
1996                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1997                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1998         if (cond || p_hwfn->dcbx_no_edpm) {
1999                 /* Either EDPM is disabled from user configuration, or it is
2000                  * disabled via DCBx, or it is not mandatory and we failed to
2001                  * allocated a WID per CPU.
2002                  */
2003                 n_cpus = 1;
2004                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2005
2006                 /* If we entered this flow due to DCBX then the DPM register is
2007                  * already configured.
2008                  */
2009         }
2010
2011         DP_INFO(p_hwfn,
2012                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2013                 norm_regsize, pwm_regsize);
2014         DP_INFO(p_hwfn,
2015                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2016                 p_hwfn->dpi_size, p_hwfn->dpi_count,
2017                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2018                 "disabled" : "enabled");
2019
2020         /* Check return codes from above calls */
2021         if (rc != ECORE_SUCCESS) {
2022                 DP_ERR(p_hwfn,
2023                        "Failed to allocate enough DPIs\n");
2024                 return ECORE_NORESOURCES;
2025         }
2026
2027         /* Update hwfn */
2028         p_hwfn->dpi_start_offset = norm_regsize;
2029
2030         /* Update registers */
2031         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2032         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2033         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2034         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2035
2036         return ECORE_SUCCESS;
2037 }
2038
2039 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2040                                                struct ecore_ptt *p_ptt,
2041                                                int hw_mode)
2042 {
2043         u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2044         u32 val;
2045         enum _ecore_status_t rc = ECORE_SUCCESS;
2046         u8 i;
2047
2048         /* In CMT for non-RoCE packets - use connection based classification */
2049         val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2050         for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2051                 ppf_to_eng_sel[i] = val;
2052         STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2053                          ppf_to_eng_sel);
2054
2055         /* In CMT the gate should be cleared by the 2nd hwfn */
2056         if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2057                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2058
2059         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2060                             hw_mode);
2061         if (rc != ECORE_SUCCESS)
2062                 return rc;
2063
2064         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2065
2066 #ifndef ASIC_ONLY
2067         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2068                 return ECORE_SUCCESS;
2069
2070         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2071                 if (ECORE_IS_AH(p_hwfn->p_dev))
2072                         return ECORE_SUCCESS;
2073                 else if (ECORE_IS_BB(p_hwfn->p_dev))
2074                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2075         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2076                 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2077                         /* Activate OPTE in CMT */
2078                         u32 val;
2079
2080                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2081                         val |= 0x10;
2082                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2083                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2084                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2085                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2086                         ecore_wr(p_hwfn, p_ptt,
2087                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2088                         ecore_wr(p_hwfn, p_ptt,
2089                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2090                         ecore_wr(p_hwfn, p_ptt,
2091                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2092                                  0x55555555);
2093                 }
2094
2095                 ecore_emul_link_init(p_hwfn, p_ptt);
2096         } else {
2097                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2098         }
2099 #endif
2100
2101         return rc;
2102 }
2103
2104 static enum _ecore_status_t
2105 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2106                  struct ecore_ptt *p_ptt,
2107                  struct ecore_tunnel_info *p_tunn,
2108                  int hw_mode,
2109                  bool b_hw_start,
2110                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2111 {
2112         u8 rel_pf_id = p_hwfn->rel_pf_id;
2113         u32 prs_reg;
2114         enum _ecore_status_t rc = ECORE_SUCCESS;
2115         u16 ctrl;
2116         int pos;
2117
2118         if (p_hwfn->mcp_info) {
2119                 struct ecore_mcp_function_info *p_info;
2120
2121                 p_info = &p_hwfn->mcp_info->func_info;
2122                 if (p_info->bandwidth_min)
2123                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2124
2125                 /* Update rate limit once we'll actually have a link */
2126                 p_hwfn->qm_info.pf_rl = 100000;
2127         }
2128         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2129
2130         ecore_int_igu_init_rt(p_hwfn);
2131
2132         /* Set VLAN in NIG if needed */
2133         if (hw_mode & (1 << MODE_MF_SD)) {
2134                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2135                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2136                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2137                              p_hwfn->hw_info.ovlan);
2138
2139                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2140                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2141                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2142                              1);
2143         }
2144
2145         /* Enable classification by MAC if needed */
2146         if (hw_mode & (1 << MODE_MF_SI)) {
2147                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2148                            "Configuring TAGMAC_CLS_TYPE\n");
2149                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2150                              1);
2151         }
2152
2153         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
2154         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2155                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2156         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2157                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2158         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2159
2160         /* perform debug configuration when chip is out of reset */
2161         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2162
2163         /* PF Init sequence */
2164         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2165         if (rc)
2166                 return rc;
2167
2168         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2169         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2170         if (rc)
2171                 return rc;
2172
2173         /* Pure runtime initializations - directly to the HW  */
2174         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2175
2176         /* PCI relaxed ordering causes a decrease in the performance on some
2177          * systems. Till a root cause is found, disable this attribute in the
2178          * PCI config space.
2179          */
2180         /* Not in use @DPDK
2181         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2182         * if (!pos) {
2183         *       DP_NOTICE(p_hwfn, true,
2184         *                 "Failed to find the PCIe Cap\n");
2185         *       return ECORE_IO;
2186         * }
2187         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2188         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2189         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2190         */
2191
2192         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2193         if (rc)
2194                 return rc;
2195         if (b_hw_start) {
2196                 /* enable interrupts */
2197                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2198                 if (rc != ECORE_SUCCESS)
2199                         return rc;
2200
2201                 /* send function start command */
2202                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2203                                        allow_npar_tx_switch);
2204                 if (rc) {
2205                         DP_NOTICE(p_hwfn, true,
2206                                   "Function start ramrod failed\n");
2207                 } else {
2208                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2209                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2210                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2211
2212                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2213                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2214                                          (1 << 2));
2215                                 ecore_wr(p_hwfn, p_ptt,
2216                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2217                                     0x100);
2218                         }
2219                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2220                                    "PRS_REG_SEARCH registers after start PFn\n");
2221                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2222                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2223                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2224                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2225                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2226                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2227                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2228                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2229                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2230                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2231                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2232                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2233                         prs_reg = ecore_rd(p_hwfn, p_ptt,
2234                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
2235                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2236                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2237                                    prs_reg);
2238                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2239                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2240                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2241                 }
2242         }
2243         return rc;
2244 }
2245
2246 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2247                                                   struct ecore_ptt *p_ptt,
2248                                                   bool b_enable)
2249 {
2250         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2251
2252         /* Configure the PF's internal FID_enable for master transactions */
2253         ecore_wr(p_hwfn, p_ptt,
2254                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2255
2256         /* Wait until value is set - try for 1 second every 50us */
2257         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2258                 val = ecore_rd(p_hwfn, p_ptt,
2259                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2260                 if (val == set_val)
2261                         break;
2262
2263                 OSAL_UDELAY(50);
2264         }
2265
2266         if (val != set_val) {
2267                 DP_NOTICE(p_hwfn, true,
2268                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2269                 return ECORE_UNKNOWN_ERROR;
2270         }
2271
2272         return ECORE_SUCCESS;
2273 }
2274
2275 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2276                                   struct ecore_ptt *p_main_ptt)
2277 {
2278         /* Read shadow of current MFW mailbox */
2279         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2280         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2281                     p_hwfn->mcp_info->mfw_mb_cur,
2282                     p_hwfn->mcp_info->mfw_mb_length);
2283 }
2284
2285 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2286                                      struct ecore_ptt *p_ptt)
2287 {
2288         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2289                  1 << p_hwfn->abs_pf_id);
2290 }
2291
2292 static void
2293 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2294                            struct ecore_drv_load_params *p_drv_load)
2295 {
2296         /* Make sure that if ecore-client didn't provide inputs, all the
2297          * expected defaults are indeed zero.
2298          */
2299         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2300         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2301         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2302
2303         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2304
2305         if (p_drv_load != OSAL_NULL) {
2306                 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2307                                        ECORE_DRV_ROLE_KDUMP :
2308                                        ECORE_DRV_ROLE_OS;
2309                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2310                 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2311                 p_load_req->override_force_load =
2312                         p_drv_load->override_force_load;
2313         }
2314 }
2315
2316 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2317                                     struct ecore_hw_init_params *p_params)
2318 {
2319         if (p_params->p_tunn) {
2320                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2321                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2322         }
2323
2324         p_hwfn->b_int_enabled = 1;
2325
2326         return ECORE_SUCCESS;
2327 }
2328
2329 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2330                                    struct ecore_hw_init_params *p_params)
2331 {
2332         struct ecore_load_req_params load_req_params;
2333         u32 load_code, resp, param, drv_mb_param;
2334         bool b_default_mtu = true;
2335         struct ecore_hwfn *p_hwfn;
2336         enum _ecore_status_t rc = ECORE_SUCCESS;
2337         int i;
2338
2339         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2340                 DP_NOTICE(p_dev, false,
2341                           "MSI mode is not supported for CMT devices\n");
2342                 return ECORE_INVAL;
2343         }
2344
2345         if (IS_PF(p_dev)) {
2346                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2347                 if (rc != ECORE_SUCCESS)
2348                         return rc;
2349         }
2350
2351         for_each_hwfn(p_dev, i) {
2352                 p_hwfn = &p_dev->hwfns[i];
2353
2354                 /* If management didn't provide a default, set one of our own */
2355                 if (!p_hwfn->hw_info.mtu) {
2356                         p_hwfn->hw_info.mtu = 1500;
2357                         b_default_mtu = false;
2358                 }
2359
2360                 if (IS_VF(p_dev)) {
2361                         ecore_vf_start(p_hwfn, p_params);
2362                         continue;
2363                 }
2364
2365                 rc = ecore_calc_hw_mode(p_hwfn);
2366                 if (rc != ECORE_SUCCESS)
2367                         return rc;
2368
2369                 ecore_fill_load_req_params(&load_req_params,
2370                                            p_params->p_drv_load_params);
2371                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2372                                         &load_req_params);
2373                 if (rc != ECORE_SUCCESS) {
2374                         DP_NOTICE(p_hwfn, true,
2375                                   "Failed sending a LOAD_REQ command\n");
2376                         return rc;
2377                 }
2378
2379                 load_code = load_req_params.load_code;
2380                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2381                            "Load request was sent. Load code: 0x%x\n",
2382                            load_code);
2383
2384                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2385
2386                 /* CQ75580:
2387                  * When coming back from hiberbate state, the registers from
2388                  * which shadow is read initially are not initialized. It turns
2389                  * out that these registers get initialized during the call to
2390                  * ecore_mcp_load_req request. So we need to reread them here
2391                  * to get the proper shadow register value.
2392                  * Note: This is a workaround for the missing MFW
2393                  * initialization. It may be removed once the implementation
2394                  * is done.
2395                  */
2396                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2397
2398                 /* Only relevant for recovery:
2399                  * Clear the indication after the LOAD_REQ command is responded
2400                  * by the MFW.
2401                  */
2402                 p_dev->recov_in_prog = false;
2403
2404                 p_hwfn->first_on_engine = (load_code ==
2405                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2406
2407                 if (!qm_lock_init) {
2408                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2409                         qm_lock_init = true;
2410                 }
2411
2412                 /* Clean up chip from previous driver if such remains exist.
2413                  * This is not needed when the PF is the first one on the
2414                  * engine, since afterwards we are going to init the FW.
2415                  */
2416                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2417                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2418                                                  p_hwfn->rel_pf_id, false);
2419                         if (rc != ECORE_SUCCESS) {
2420                                 ecore_hw_err_notify(p_hwfn,
2421                                                     ECORE_HW_ERR_RAMROD_FAIL);
2422                                 goto load_err;
2423                         }
2424                 }
2425
2426                 /* Log and clear previous pglue_b errors if such exist */
2427                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2428
2429                 /* Enable the PF's internal FID_enable in the PXP */
2430                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2431                                                   true);
2432                 if (rc != ECORE_SUCCESS)
2433                         goto load_err;
2434
2435                 /* Clear the pglue_b was_error indication.
2436                  * In E4 it must be done after the BME and the internal
2437                  * FID_enable for the PF are set, since VDMs may cause the
2438                  * indication to be set again.
2439                  */
2440                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2441
2442                 switch (load_code) {
2443                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2444                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2445                                                   p_hwfn->hw_info.hw_mode);
2446                         if (rc != ECORE_SUCCESS)
2447                                 break;
2448                         /* Fall into */
2449                 case FW_MSG_CODE_DRV_LOAD_PORT:
2450                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2451                                                 p_hwfn->hw_info.hw_mode);
2452                         if (rc != ECORE_SUCCESS)
2453                                 break;
2454                         /* Fall into */
2455                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2456                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2457                                               p_params->p_tunn,
2458                                               p_hwfn->hw_info.hw_mode,
2459                                               p_params->b_hw_start,
2460                                               p_params->int_mode,
2461                                               p_params->allow_npar_tx_switch);
2462                         break;
2463                 default:
2464                         DP_NOTICE(p_hwfn, false,
2465                                   "Unexpected load code [0x%08x]", load_code);
2466                         rc = ECORE_NOTIMPL;
2467                         break;
2468                 }
2469
2470                 if (rc != ECORE_SUCCESS) {
2471                         DP_NOTICE(p_hwfn, true,
2472                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2473                                   load_code, rc);
2474                         goto load_err;
2475                 }
2476
2477                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2478                 if (rc != ECORE_SUCCESS)
2479                         return rc;
2480
2481                 /* send DCBX attention request command */
2482                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2483                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2484                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2485                                    DRV_MSG_CODE_SET_DCBX,
2486                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2487                                    &param);
2488                 if (rc != ECORE_SUCCESS) {
2489                         DP_NOTICE(p_hwfn, true,
2490                                   "Failed to send DCBX attention request\n");
2491                         return rc;
2492                 }
2493
2494                 p_hwfn->hw_init_done = true;
2495         }
2496
2497         if (IS_PF(p_dev)) {
2498                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2499                 drv_mb_param = STORM_FW_VERSION;
2500                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2501                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2502                                    drv_mb_param, &resp, &param);
2503                 if (rc != ECORE_SUCCESS)
2504                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2505
2506                 if (!b_default_mtu)
2507                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2508                                                       p_hwfn->hw_info.mtu);
2509                 if (rc != ECORE_SUCCESS)
2510                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2511
2512                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2513                                                       p_hwfn->p_main_ptt,
2514                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2515                 if (rc != ECORE_SUCCESS)
2516                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2517         }
2518
2519         return rc;
2520
2521 load_err:
2522         /* The MFW load lock should be released regardless of success or failure
2523          * of initialization.
2524          * TODO: replace this with an attempt to send cancel_load.
2525          */
2526         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2527         return rc;
2528 }
2529
2530 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2531 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2532                                  struct ecore_hwfn *p_hwfn,
2533                                  struct ecore_ptt *p_ptt)
2534 {
2535         int i;
2536
2537         /* close timers */
2538         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2539         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2540         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2541                                                                         i++) {
2542                 if ((!ecore_rd(p_hwfn, p_ptt,
2543                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2544                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2545                         break;
2546
2547                 /* Dependent on number of connection/tasks, possibly
2548                  * 1ms sleep is required between polls
2549                  */
2550                 OSAL_MSLEEP(1);
2551         }
2552
2553         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2554                 return;
2555
2556         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2557                   " [Connection %02x Tasks %02x]\n",
2558                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2559                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2560 }
2561
2562 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2563 {
2564         int j;
2565
2566         for_each_hwfn(p_dev, j) {
2567                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2568                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2569
2570                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2571         }
2572 }
2573
2574 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2575                                                  struct ecore_ptt *p_ptt,
2576                                                  u32 addr, u32 expected_val)
2577 {
2578         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2579
2580         if (val != expected_val) {
2581                 DP_NOTICE(p_hwfn, true,
2582                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2583                           addr, val, expected_val);
2584                 return ECORE_UNKNOWN_ERROR;
2585         }
2586
2587         return ECORE_SUCCESS;
2588 }
2589
2590 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2591 {
2592         struct ecore_hwfn *p_hwfn;
2593         struct ecore_ptt *p_ptt;
2594         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2595         int j;
2596
2597         for_each_hwfn(p_dev, j) {
2598                 p_hwfn = &p_dev->hwfns[j];
2599                 p_ptt = p_hwfn->p_main_ptt;
2600
2601                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2602
2603                 if (IS_VF(p_dev)) {
2604                         ecore_vf_pf_int_cleanup(p_hwfn);
2605                         rc = ecore_vf_pf_reset(p_hwfn);
2606                         if (rc != ECORE_SUCCESS) {
2607                                 DP_NOTICE(p_hwfn, true,
2608                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2609                                           rc);
2610                                 rc2 = ECORE_UNKNOWN_ERROR;
2611                         }
2612                         continue;
2613                 }
2614
2615                 /* mark the hw as uninitialized... */
2616                 p_hwfn->hw_init_done = false;
2617
2618                 /* Send unload command to MCP */
2619                 if (!p_dev->recov_in_prog) {
2620                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2621                         if (rc != ECORE_SUCCESS) {
2622                                 DP_NOTICE(p_hwfn, true,
2623                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2624                                           rc);
2625                                 rc2 = ECORE_UNKNOWN_ERROR;
2626                         }
2627                 }
2628
2629                 OSAL_DPC_SYNC(p_hwfn);
2630
2631                 /* After this point no MFW attentions are expected, e.g. prevent
2632                  * race between pf stop and dcbx pf update.
2633                  */
2634
2635                 rc = ecore_sp_pf_stop(p_hwfn);
2636                 if (rc != ECORE_SUCCESS) {
2637                         DP_NOTICE(p_hwfn, true,
2638                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2639                                   rc);
2640                         rc2 = ECORE_UNKNOWN_ERROR;
2641                 }
2642
2643                 /* perform debug action after PF stop was sent */
2644                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2645
2646                 /* close NIG to BRB gate */
2647                 ecore_wr(p_hwfn, p_ptt,
2648                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2649
2650                 /* close parser */
2651                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2652                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2653                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2654                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2655                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2656
2657                 /* @@@TBD - clean transmission queues (5.b) */
2658                 /* @@@TBD - clean BTB (5.c) */
2659
2660                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2661
2662                 /* @@@TBD - verify DMAE requests are done (8) */
2663
2664                 /* Disable Attention Generation */
2665                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2666                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2667                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2668                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2669                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2670                 if (rc != ECORE_SUCCESS) {
2671                         DP_NOTICE(p_hwfn, true,
2672                                   "Failed to return IGU CAM to default\n");
2673                         rc2 = ECORE_UNKNOWN_ERROR;
2674                 }
2675
2676                 /* Need to wait 1ms to guarantee SBs are cleared */
2677                 OSAL_MSLEEP(1);
2678
2679                 if (!p_dev->recov_in_prog) {
2680                         ecore_verify_reg_val(p_hwfn, p_ptt,
2681                                              QM_REG_USG_CNT_PF_TX, 0);
2682                         ecore_verify_reg_val(p_hwfn, p_ptt,
2683                                              QM_REG_USG_CNT_PF_OTHER, 0);
2684                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2685                 }
2686
2687                 /* Disable PF in HW blocks */
2688                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2689                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2690
2691                 if (!p_dev->recov_in_prog) {
2692                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2693                         if (rc != ECORE_SUCCESS) {
2694                                 DP_NOTICE(p_hwfn, true,
2695                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2696                                           rc);
2697                                 rc2 = ECORE_UNKNOWN_ERROR;
2698                         }
2699                 }
2700         } /* hwfn loop */
2701
2702         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2703                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2704                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2705
2706                  /* Clear the PF's internal FID_enable in the PXP.
2707                   * In CMT this should only be done for first hw-function, and
2708                   * only after all transactions have stopped for all active
2709                   * hw-functions.
2710                   */
2711                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2712                                                   false);
2713                 if (rc != ECORE_SUCCESS) {
2714                         DP_NOTICE(p_hwfn, true,
2715                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2716                                   rc);
2717                         rc2 = ECORE_UNKNOWN_ERROR;
2718                 }
2719         }
2720
2721         return rc2;
2722 }
2723
2724 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2725 {
2726         int j;
2727
2728         for_each_hwfn(p_dev, j) {
2729                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2730                 struct ecore_ptt *p_ptt;
2731
2732                 if (IS_VF(p_dev)) {
2733                         ecore_vf_pf_int_cleanup(p_hwfn);
2734                         continue;
2735                 }
2736                 p_ptt = ecore_ptt_acquire(p_hwfn);
2737                 if (!p_ptt)
2738                         return ECORE_AGAIN;
2739
2740                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2741                            "Shutting down the fastpath\n");
2742
2743                 ecore_wr(p_hwfn, p_ptt,
2744                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2745
2746                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2747                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2748                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2749                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2750                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2751
2752                 /* @@@TBD - clean transmission queues (5.b) */
2753                 /* @@@TBD - clean BTB (5.c) */
2754
2755                 /* @@@TBD - verify DMAE requests are done (8) */
2756
2757                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2758                 /* Need to wait 1ms to guarantee SBs are cleared */
2759                 OSAL_MSLEEP(1);
2760                 ecore_ptt_release(p_hwfn, p_ptt);
2761         }
2762
2763         return ECORE_SUCCESS;
2764 }
2765
2766 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2767 {
2768         struct ecore_ptt *p_ptt;
2769
2770         if (IS_VF(p_hwfn->p_dev))
2771                 return ECORE_SUCCESS;
2772
2773         p_ptt = ecore_ptt_acquire(p_hwfn);
2774         if (!p_ptt)
2775                 return ECORE_AGAIN;
2776
2777         /* If roce info is allocated it means roce is initialized and should
2778          * be enabled in searcher.
2779          */
2780         if (p_hwfn->p_rdma_info) {
2781                 if (p_hwfn->b_rdma_enabled_in_prs)
2782                         ecore_wr(p_hwfn, p_ptt,
2783                                  p_hwfn->rdma_prs_search_reg, 0x1);
2784                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2785         }
2786
2787         /* Re-open incoming traffic */
2788         ecore_wr(p_hwfn, p_ptt,
2789                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2790         ecore_ptt_release(p_hwfn, p_ptt);
2791
2792         return ECORE_SUCCESS;
2793 }
2794
2795 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2796 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2797 {
2798         ecore_ptt_pool_free(p_hwfn);
2799         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2800 }
2801
2802 /* Setup bar access */
2803 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2804 {
2805         /* clear indirect access */
2806         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2807                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2808                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2809                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2810                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2811                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2812                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2813                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2814                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2815         } else {
2816                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2817                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2818                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2819                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2820                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2821                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2822                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2823                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2824         }
2825
2826         /* Clean previous pglue_b errors if such exist */
2827         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2828
2829         /* enable internal target-read */
2830         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2831                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2832 }
2833
2834 static void get_function_id(struct ecore_hwfn *p_hwfn)
2835 {
2836         /* ME Register */
2837         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2838                                                   PXP_PF_ME_OPAQUE_ADDR);
2839
2840         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2841
2842         /* Bits 16-19 from the ME registers are the pf_num */
2843         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2844         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2845                                       PXP_CONCRETE_FID_PFID);
2846         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2847                                     PXP_CONCRETE_FID_PORT);
2848
2849         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2850                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2851                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2852 }
2853
2854 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2855 {
2856         u32 *feat_num = p_hwfn->hw_info.feat_num;
2857         struct ecore_sb_cnt_info sb_cnt;
2858         u32 non_l2_sbs = 0;
2859
2860         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2861         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2862
2863         /* L2 Queues require each: 1 status block. 1 L2 queue */
2864         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2865                 /* Start by allocating VF queues, then PF's */
2866                 feat_num[ECORE_VF_L2_QUE] =
2867                         OSAL_MIN_T(u32,
2868                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2869                                    sb_cnt.iov_cnt);
2870                 feat_num[ECORE_PF_L2_QUE] =
2871                         OSAL_MIN_T(u32,
2872                                    sb_cnt.cnt - non_l2_sbs,
2873                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2874                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2875         }
2876
2877         if (ECORE_IS_FCOE_PERSONALITY(p_hwfn))
2878                 feat_num[ECORE_FCOE_CQ] =
2879                         OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2880                                                              ECORE_CMDQS_CQS));
2881
2882         if (ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
2883                 feat_num[ECORE_ISCSI_CQ] =
2884                         OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2885                                                              ECORE_CMDQS_CQS));
2886
2887         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2888                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2889                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2890                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2891                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2892                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2893                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2894                    (int)sb_cnt.cnt);
2895 }
2896
2897 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2898 {
2899         switch (res_id) {
2900         case ECORE_L2_QUEUE:
2901                 return "L2_QUEUE";
2902         case ECORE_VPORT:
2903                 return "VPORT";
2904         case ECORE_RSS_ENG:
2905                 return "RSS_ENG";
2906         case ECORE_PQ:
2907                 return "PQ";
2908         case ECORE_RL:
2909                 return "RL";
2910         case ECORE_MAC:
2911                 return "MAC";
2912         case ECORE_VLAN:
2913                 return "VLAN";
2914         case ECORE_RDMA_CNQ_RAM:
2915                 return "RDMA_CNQ_RAM";
2916         case ECORE_ILT:
2917                 return "ILT";
2918         case ECORE_LL2_QUEUE:
2919                 return "LL2_QUEUE";
2920         case ECORE_CMDQS_CQS:
2921                 return "CMDQS_CQS";
2922         case ECORE_RDMA_STATS_QUEUE:
2923                 return "RDMA_STATS_QUEUE";
2924         case ECORE_BDQ:
2925                 return "BDQ";
2926         case ECORE_SB:
2927                 return "SB";
2928         default:
2929                 return "UNKNOWN_RESOURCE";
2930         }
2931 }
2932
2933 static enum _ecore_status_t
2934 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2935                               struct ecore_ptt *p_ptt,
2936                               enum ecore_resources res_id,
2937                               u32 resc_max_val,
2938                               u32 *p_mcp_resp)
2939 {
2940         enum _ecore_status_t rc;
2941
2942         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2943                                         resc_max_val, p_mcp_resp);
2944         if (rc != ECORE_SUCCESS) {
2945                 DP_NOTICE(p_hwfn, true,
2946                           "MFW response failure for a max value setting of resource %d [%s]\n",
2947                           res_id, ecore_hw_get_resc_name(res_id));
2948                 return rc;
2949         }
2950
2951         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2952                 DP_INFO(p_hwfn,
2953                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2954                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2955
2956         return ECORE_SUCCESS;
2957 }
2958
2959 static enum _ecore_status_t
2960 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2961                             struct ecore_ptt *p_ptt)
2962 {
2963         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2964         u32 resc_max_val, mcp_resp;
2965         u8 res_id;
2966         enum _ecore_status_t rc;
2967
2968         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2969                 /* @DPDK */
2970                 switch (res_id) {
2971                 case ECORE_LL2_QUEUE:
2972                 case ECORE_RDMA_CNQ_RAM:
2973                 case ECORE_RDMA_STATS_QUEUE:
2974                 case ECORE_BDQ:
2975                         resc_max_val = 0;
2976                         break;
2977                 default:
2978                         continue;
2979                 }
2980
2981                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2982                                                    resc_max_val, &mcp_resp);
2983                 if (rc != ECORE_SUCCESS)
2984                         return rc;
2985
2986                 /* There's no point to continue to the next resource if the
2987                  * command is not supported by the MFW.
2988                  * We do continue if the command is supported but the resource
2989                  * is unknown to the MFW. Such a resource will be later
2990                  * configured with the default allocation values.
2991                  */
2992                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2993                         return ECORE_NOTIMPL;
2994         }
2995
2996         return ECORE_SUCCESS;
2997 }
2998
2999 static
3000 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
3001                                             enum ecore_resources res_id,
3002                                             u32 *p_resc_num, u32 *p_resc_start)
3003 {
3004         u8 num_funcs = p_hwfn->num_funcs_on_engine;
3005         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3006
3007         switch (res_id) {
3008         case ECORE_L2_QUEUE:
3009                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3010                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
3011                 break;
3012         case ECORE_VPORT:
3013                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3014                                  MAX_NUM_VPORTS_BB) / num_funcs;
3015                 break;
3016         case ECORE_RSS_ENG:
3017                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3018                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3019                 break;
3020         case ECORE_PQ:
3021                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3022                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
3023                 break;
3024         case ECORE_RL:
3025                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3026                 break;
3027         case ECORE_MAC:
3028         case ECORE_VLAN:
3029                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3030                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3031                 break;
3032         case ECORE_ILT:
3033                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3034                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3035                 break;
3036         case ECORE_LL2_QUEUE:
3037                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3038                 break;
3039         case ECORE_RDMA_CNQ_RAM:
3040         case ECORE_CMDQS_CQS:
3041                 /* CNQ/CMDQS are the same resource */
3042                 /* @DPDK */
3043                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3044                 break;
3045         case ECORE_RDMA_STATS_QUEUE:
3046                 /* @DPDK */
3047                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3048                                  MAX_NUM_VPORTS_BB) / num_funcs;
3049                 break;
3050         case ECORE_BDQ:
3051                 /* @DPDK */
3052                 *p_resc_num = 0;
3053                 break;
3054         default:
3055                 break;
3056         }
3057
3058
3059         switch (res_id) {
3060         case ECORE_BDQ:
3061                 if (!*p_resc_num)
3062                         *p_resc_start = 0;
3063                 break;
3064         case ECORE_SB:
3065                 /* Since we want its value to reflect whether MFW supports
3066                  * the new scheme, have a default of 0.
3067                  */
3068                 *p_resc_num = 0;
3069                 break;
3070         default:
3071                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3072                 break;
3073         }
3074
3075         return ECORE_SUCCESS;
3076 }
3077
3078 static enum _ecore_status_t
3079 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3080                          bool drv_resc_alloc)
3081 {
3082         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3083         u32 mcp_resp, *p_resc_num, *p_resc_start;
3084         enum _ecore_status_t rc;
3085
3086         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3087         p_resc_start = &RESC_START(p_hwfn, res_id);
3088
3089         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3090                                     &dflt_resc_start);
3091         if (rc != ECORE_SUCCESS) {
3092                 DP_ERR(p_hwfn,
3093                        "Failed to get default amount for resource %d [%s]\n",
3094                         res_id, ecore_hw_get_resc_name(res_id));
3095                 return rc;
3096         }
3097
3098 #ifndef ASIC_ONLY
3099         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3100                 *p_resc_num = dflt_resc_num;
3101                 *p_resc_start = dflt_resc_start;
3102                 goto out;
3103         }
3104 #endif
3105
3106         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3107                                      &mcp_resp, p_resc_num, p_resc_start);
3108         if (rc != ECORE_SUCCESS) {
3109                 DP_NOTICE(p_hwfn, true,
3110                           "MFW response failure for an allocation request for"
3111                           " resource %d [%s]\n",
3112                           res_id, ecore_hw_get_resc_name(res_id));
3113                 return rc;
3114         }
3115
3116         /* Default driver values are applied in the following cases:
3117          * - The resource allocation MB command is not supported by the MFW
3118          * - There is an internal error in the MFW while processing the request
3119          * - The resource ID is unknown to the MFW
3120          */
3121         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3122                 DP_INFO(p_hwfn,
3123                         "Failed to receive allocation info for resource %d [%s]."
3124                         " mcp_resp = 0x%x. Applying default values"
3125                         " [%d,%d].\n",
3126                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3127                         dflt_resc_num, dflt_resc_start);
3128
3129                 *p_resc_num = dflt_resc_num;
3130                 *p_resc_start = dflt_resc_start;
3131                 goto out;
3132         }
3133
3134         if ((*p_resc_num != dflt_resc_num ||
3135              *p_resc_start != dflt_resc_start) &&
3136             res_id != ECORE_SB) {
3137                 DP_INFO(p_hwfn,
3138                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3139                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3140                         *p_resc_start, dflt_resc_num, dflt_resc_start,
3141                         drv_resc_alloc ? " - Applying default values" : "");
3142                 if (drv_resc_alloc) {
3143                         *p_resc_num = dflt_resc_num;
3144                         *p_resc_start = dflt_resc_start;
3145                 }
3146         }
3147 out:
3148         return ECORE_SUCCESS;
3149 }
3150
3151 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3152                                                    bool drv_resc_alloc)
3153 {
3154         enum _ecore_status_t rc;
3155         u8 res_id;
3156
3157         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3158                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3159                 if (rc != ECORE_SUCCESS)
3160                         return rc;
3161         }
3162
3163         return ECORE_SUCCESS;
3164 }
3165
3166 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3167                                               struct ecore_ptt *p_ptt,
3168                                               bool drv_resc_alloc)
3169 {
3170         struct ecore_resc_unlock_params resc_unlock_params;
3171         struct ecore_resc_lock_params resc_lock_params;
3172         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3173         u8 res_id;
3174         enum _ecore_status_t rc;
3175 #ifndef ASIC_ONLY
3176         u32 *resc_start = p_hwfn->hw_info.resc_start;
3177         u32 *resc_num = p_hwfn->hw_info.resc_num;
3178         /* For AH, an equal share of the ILT lines between the maximal number of
3179          * PFs is not enough for RoCE. This would be solved by the future
3180          * resource allocation scheme, but isn't currently present for
3181          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3182          * to work - the BB number of ILT lines divided by its max PFs number.
3183          */
3184         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3185 #endif
3186
3187         /* Setting the max values of the soft resources and the following
3188          * resources allocation queries should be atomic. Since several PFs can
3189          * run in parallel - a resource lock is needed.
3190          * If either the resource lock or resource set value commands are not
3191          * supported - skip the the max values setting, release the lock if
3192          * needed, and proceed to the queries. Other failures, including a
3193          * failure to acquire the lock, will cause this function to fail.
3194          * Old drivers that don't acquire the lock can run in parallel, and
3195          * their allocation values won't be affected by the updated max values.
3196          */
3197         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3198                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
3199
3200         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3201         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3202                 return rc;
3203         } else if (rc == ECORE_NOTIMPL) {
3204                 DP_INFO(p_hwfn,
3205                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3206         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3207                 DP_NOTICE(p_hwfn, false,
3208                           "Failed to acquire the resource lock for the resource allocation commands\n");
3209                 rc = ECORE_BUSY;
3210                 goto unlock_and_exit;
3211         } else {
3212                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3213                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3214                         DP_NOTICE(p_hwfn, false,
3215                                   "Failed to set the max values of the soft resources\n");
3216                         goto unlock_and_exit;
3217                 } else if (rc == ECORE_NOTIMPL) {
3218                         DP_INFO(p_hwfn,
3219                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3220                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3221                                                    &resc_unlock_params);
3222                         if (rc != ECORE_SUCCESS)
3223                                 DP_INFO(p_hwfn,
3224                                         "Failed to release the resource lock for the resource allocation commands\n");
3225                 }
3226         }
3227
3228         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3229         if (rc != ECORE_SUCCESS)
3230                 goto unlock_and_exit;
3231
3232         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3233                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3234                                            &resc_unlock_params);
3235                 if (rc != ECORE_SUCCESS)
3236                         DP_INFO(p_hwfn,
3237                                 "Failed to release the resource lock for the resource allocation commands\n");
3238         }
3239
3240 #ifndef ASIC_ONLY
3241         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3242                 /* Reduced build contains less PQs */
3243                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3244                         resc_num[ECORE_PQ] = 32;
3245                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3246                             p_hwfn->enabled_func_idx;
3247                 }
3248
3249                 /* For AH emulation, since we have a possible maximal number of
3250                  * 16 enabled PFs, in case there are not enough ILT lines -
3251                  * allocate only first PF as RoCE and have all the other ETH
3252                  * only with less ILT lines.
3253                  */
3254                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3255                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3256                                                          resc_num[ECORE_ILT],
3257                                                          roce_min_ilt_lines);
3258         }
3259
3260         /* Correct the common ILT calculation if PF0 has more */
3261         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3262             p_hwfn->p_dev->b_is_emul_full &&
3263             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3264                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3265                     resc_num[ECORE_ILT];
3266 #endif
3267
3268         /* Sanity for ILT */
3269         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3270             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3271                 DP_NOTICE(p_hwfn, true,
3272                           "Can't assign ILT pages [%08x,...,%08x]\n",
3273                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3274                                                                   ECORE_ILT) -
3275                           1);
3276                 return ECORE_INVAL;
3277         }
3278
3279         /* This will also learn the number of SBs from MFW */
3280         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3281                 return ECORE_INVAL;
3282
3283         ecore_hw_set_feat(p_hwfn);
3284
3285         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3286                    "The numbers for each resource are:\n");
3287         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3288                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3289                            ecore_hw_get_resc_name(res_id),
3290                            RESC_NUM(p_hwfn, res_id),
3291                            RESC_START(p_hwfn, res_id));
3292
3293         return ECORE_SUCCESS;
3294
3295 unlock_and_exit:
3296         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3297                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3298                                       &resc_unlock_params);
3299         return rc;
3300 }
3301
3302 static enum _ecore_status_t
3303 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3304                       struct ecore_ptt *p_ptt,
3305                       struct ecore_hw_prepare_params *p_params)
3306 {
3307         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3308         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3309         struct ecore_mcp_link_capabilities *p_caps;
3310         struct ecore_mcp_link_params *link;
3311         enum _ecore_status_t rc;
3312
3313         /* Read global nvm_cfg address */
3314         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3315
3316         /* Verify MCP has initialized it */
3317         if (!nvm_cfg_addr) {
3318                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3319                 if (p_params->b_relaxed_probe)
3320                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3321                 return ECORE_INVAL;
3322         }
3323
3324 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3325
3326         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3327
3328         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3329                    OFFSETOF(struct nvm_cfg1, glob) +
3330                    OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3331
3332         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3333
3334         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3335                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3336         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3337                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3338                 break;
3339         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3340                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3341                 break;
3342         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3343                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3344                 break;
3345         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3346                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3347                 break;
3348         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3349                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3350                 break;
3351         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3352                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3353                 break;
3354         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3355                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3356                 break;
3357         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3358                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3359                 break;
3360         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3361                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3362                 break;
3363         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3364                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3365                 break;
3366         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3367                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3368                 break;
3369         default:
3370                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3371                           core_cfg);
3372                 break;
3373         }
3374
3375         /* Read DCBX configuration */
3376         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3377                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3378         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3379                              port_cfg_addr +
3380                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3381         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3382                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3383         switch (dcbx_mode) {
3384         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3385                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3386                 break;
3387         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3388                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3389                 break;
3390         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3391                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3392                 break;
3393         default:
3394                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3395         }
3396
3397         /* Read default link configuration */
3398         link = &p_hwfn->mcp_info->link_input;
3399         p_caps = &p_hwfn->mcp_info->link_capabilities;
3400         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3401             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3402         link_temp = ecore_rd(p_hwfn, p_ptt,
3403                              port_cfg_addr +
3404                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3405         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3406         link->speed.advertised_speeds = link_temp;
3407         p_caps->speed_capabilities = link->speed.advertised_speeds;
3408
3409         link_temp = ecore_rd(p_hwfn, p_ptt,
3410                                  port_cfg_addr +
3411                                  OFFSETOF(struct nvm_cfg1_port, link_settings));
3412         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3413                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3414         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3415                 link->speed.autoneg = true;
3416                 break;
3417         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3418                 link->speed.forced_speed = 1000;
3419                 break;
3420         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3421                 link->speed.forced_speed = 10000;
3422                 break;
3423         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3424                 link->speed.forced_speed = 25000;
3425                 break;
3426         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3427                 link->speed.forced_speed = 40000;
3428                 break;
3429         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3430                 link->speed.forced_speed = 50000;
3431                 break;
3432         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3433                 link->speed.forced_speed = 100000;
3434                 break;
3435         default:
3436                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3437         }
3438
3439         p_caps->default_speed = link->speed.forced_speed;
3440         p_caps->default_speed_autoneg = link->speed.autoneg;
3441
3442         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3443         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3444         link->pause.autoneg = !!(link_temp &
3445                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3446         link->pause.forced_rx = !!(link_temp &
3447                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3448         link->pause.forced_tx = !!(link_temp &
3449                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3450         link->loopback_mode = 0;
3451
3452         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3453                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3454                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3455                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3456                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3457                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3458                 link->eee.enable = true;
3459                 switch (link_temp) {
3460                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3461                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3462                         link->eee.enable = false;
3463                         break;
3464                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3465                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3466                         break;
3467                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3468                         p_caps->eee_lpi_timer =
3469                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3470                         break;
3471                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3472                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3473                         break;
3474                 }
3475
3476                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3477                 link->eee.tx_lpi_enable = link->eee.enable;
3478                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3479         } else {
3480                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3481         }
3482
3483         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3484                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3485                    link->speed.forced_speed, link->speed.advertised_speeds,
3486                    link->speed.autoneg, link->pause.autoneg,
3487                    p_caps->default_eee, p_caps->eee_lpi_timer);
3488
3489         /* Read Multi-function information from shmem */
3490         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3491                    OFFSETOF(struct nvm_cfg1, glob) +
3492                    OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3493
3494         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3495
3496         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3497             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3498
3499         switch (mf_mode) {
3500         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3501                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3502                 break;
3503         case NVM_CFG1_GLOB_MF_MODE_UFP:
3504                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3505                                          1 << ECORE_MF_UFP_SPECIFIC |
3506                                          1 << ECORE_MF_8021Q_TAGGING;
3507                 break;
3508         case NVM_CFG1_GLOB_MF_MODE_BD:
3509                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3510                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3511                                          1 << ECORE_MF_8021AD_TAGGING;
3512                 break;
3513         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3514                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3515                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3516                                          1 << ECORE_MF_LL2_NON_UNICAST |
3517                                          1 << ECORE_MF_INTER_PF_SWITCH |
3518                                          1 << ECORE_MF_DISABLE_ARFS;
3519                 break;
3520         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3521                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3522                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3523                                          1 << ECORE_MF_LL2_NON_UNICAST;
3524                 if (ECORE_IS_BB(p_hwfn->p_dev))
3525                         p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3526                 break;
3527         }
3528         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3529                 p_hwfn->p_dev->mf_bits);
3530
3531         if (ECORE_IS_CMT(p_hwfn->p_dev))
3532                 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3533
3534         /* It's funny since we have another switch, but it's easier
3535          * to throw this away in linux this way. Long term, it might be
3536          * better to have have getters for needed ECORE_MF_* fields,
3537          * convert client code and eliminate this.
3538          */
3539         switch (mf_mode) {
3540         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3541         case NVM_CFG1_GLOB_MF_MODE_BD:
3542                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3543                 break;
3544         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3545                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3546                 break;
3547         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3548                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3549                 break;
3550         case NVM_CFG1_GLOB_MF_MODE_UFP:
3551                 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3552                 break;
3553         }
3554
3555         /* Read Multi-function information from shmem */
3556         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3557                    OFFSETOF(struct nvm_cfg1, glob) +
3558                    OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3559
3560         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3561         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3562                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3563                                 &p_hwfn->hw_info.device_capabilities);
3564         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3565                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3566                                 &p_hwfn->hw_info.device_capabilities);
3567         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3568                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3569                                 &p_hwfn->hw_info.device_capabilities);
3570         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3571                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3572                                 &p_hwfn->hw_info.device_capabilities);
3573         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3574                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3575                                 &p_hwfn->hw_info.device_capabilities);
3576
3577         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3578         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3579                 rc = ECORE_SUCCESS;
3580                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3581         }
3582
3583         return rc;
3584 }
3585
3586 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3587                                 struct ecore_ptt *p_ptt)
3588 {
3589         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3590         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3591         struct ecore_dev *p_dev = p_hwfn->p_dev;
3592
3593         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3594
3595         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3596          * in the other bits are selected.
3597          * Bits 1-15 are for functions 1-15, respectively, and their value is
3598          * '0' only for enabled functions (function 0 always exists and
3599          * enabled).
3600          * In case of CMT in BB, only the "even" functions are enabled, and thus
3601          * the number of functions for both hwfns is learnt from the same bits.
3602          */
3603         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3604                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3605                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3606         } else { /* E5 */
3607                 reg_function_hide = 0;
3608         }
3609
3610         if (reg_function_hide & 0x1) {
3611                 if (ECORE_IS_BB(p_dev)) {
3612                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3613                                 num_funcs = 0;
3614                                 eng_mask = 0xaaaa;
3615                         } else {
3616                                 num_funcs = 1;
3617                                 eng_mask = 0x5554;
3618                         }
3619                 } else {
3620                         num_funcs = 1;
3621                         eng_mask = 0xfffe;
3622                 }
3623
3624                 /* Get the number of the enabled functions on the engine */
3625                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3626                 while (tmp) {
3627                         if (tmp & 0x1)
3628                                 num_funcs++;
3629                         tmp >>= 0x1;
3630                 }
3631
3632                 /* Get the PF index within the enabled functions */
3633                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3634                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3635                 while (tmp) {
3636                         if (tmp & 0x1)
3637                                 enabled_func_idx--;
3638                         tmp >>= 0x1;
3639                 }
3640         }
3641
3642         p_hwfn->num_funcs_on_engine = num_funcs;
3643         p_hwfn->enabled_func_idx = enabled_func_idx;
3644
3645 #ifndef ASIC_ONLY
3646         if (CHIP_REV_IS_FPGA(p_dev)) {
3647                 DP_NOTICE(p_hwfn, false,
3648                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3649                 p_hwfn->num_funcs_on_engine = 4;
3650         }
3651 #endif
3652
3653         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3654                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3655                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3656                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3657 }
3658
3659 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3660                                       struct ecore_ptt *p_ptt)
3661 {
3662         struct ecore_dev *p_dev = p_hwfn->p_dev;
3663         u32 port_mode;
3664
3665 #ifndef ASIC_ONLY
3666         /* Read the port mode */
3667         if (CHIP_REV_IS_FPGA(p_dev))
3668                 port_mode = 4;
3669         else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3670                 /* In CMT on emulation, assume 1 port */
3671                 port_mode = 1;
3672         else
3673 #endif
3674         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3675
3676         if (port_mode < 3) {
3677                 p_dev->num_ports_in_engine = 1;
3678         } else if (port_mode <= 5) {
3679                 p_dev->num_ports_in_engine = 2;
3680         } else {
3681                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3682                           p_dev->num_ports_in_engine);
3683
3684                 /* Default num_ports_in_engine to something */
3685                 p_dev->num_ports_in_engine = 1;
3686         }
3687 }
3688
3689 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3690                                          struct ecore_ptt *p_ptt)
3691 {
3692         struct ecore_dev *p_dev = p_hwfn->p_dev;
3693         u32 port;
3694         int i;
3695
3696         p_dev->num_ports_in_engine = 0;
3697
3698 #ifndef ASIC_ONLY
3699         if (CHIP_REV_IS_EMUL(p_dev)) {
3700                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3701                 switch ((port & 0xf000) >> 12) {
3702                 case 1:
3703                         p_dev->num_ports_in_engine = 1;
3704                         break;
3705                 case 3:
3706                         p_dev->num_ports_in_engine = 2;
3707                         break;
3708                 case 0xf:
3709                         p_dev->num_ports_in_engine = 4;
3710                         break;
3711                 default:
3712                         DP_NOTICE(p_hwfn, false,
3713                                   "Unknown port mode in ECO_RESERVED %08x\n",
3714                                   port);
3715                 }
3716         } else
3717 #endif
3718                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3719                         port = ecore_rd(p_hwfn, p_ptt,
3720                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3721                                         (i * 4));
3722                         if (port & 1)
3723                                 p_dev->num_ports_in_engine++;
3724                 }
3725
3726         if (!p_dev->num_ports_in_engine) {
3727                 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3728
3729                 /* Default num_ports_in_engine to something */
3730                 p_dev->num_ports_in_engine = 1;
3731         }
3732 }
3733
3734 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3735                                    struct ecore_ptt *p_ptt)
3736 {
3737         struct ecore_dev *p_dev = p_hwfn->p_dev;
3738
3739         /* Determine the number of ports per engine */
3740         if (ECORE_IS_BB(p_dev))
3741                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3742         else
3743                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3744
3745         /* Get the total number of ports of the device */
3746         if (ECORE_IS_CMT(p_dev)) {
3747                 /* In CMT there is always only one port */
3748                 p_dev->num_ports = 1;
3749 #ifndef ASIC_ONLY
3750         } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3751                 p_dev->num_ports = p_dev->num_ports_in_engine *
3752                                    ecore_device_num_engines(p_dev);
3753 #endif
3754         } else {
3755                 u32 addr, global_offsize, global_addr;
3756
3757                 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3758                                             PUBLIC_GLOBAL);
3759                 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3760                 global_addr = SECTION_ADDR(global_offsize, 0);
3761                 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3762                 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3763         }
3764 }
3765
3766 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3767                                    struct ecore_ptt *p_ptt)
3768 {
3769         struct ecore_mcp_link_capabilities *p_caps;
3770         u32 eee_status;
3771
3772         p_caps = &p_hwfn->mcp_info->link_capabilities;
3773         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3774                 return;
3775
3776         p_caps->eee_speed_caps = 0;
3777         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3778                               OFFSETOF(struct public_port, eee_status));
3779         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3780                         EEE_SUPPORTED_SPEED_OFFSET;
3781         if (eee_status & EEE_1G_SUPPORTED)
3782                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3783         if (eee_status & EEE_10G_ADV)
3784                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3785 }
3786
3787 static enum _ecore_status_t
3788 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3789                   enum ecore_pci_personality personality,
3790                   struct ecore_hw_prepare_params *p_params)
3791 {
3792         bool drv_resc_alloc = p_params->drv_resc_alloc;
3793         enum _ecore_status_t rc;
3794
3795         /* Since all information is common, only first hwfns should do this */
3796         if (IS_LEAD_HWFN(p_hwfn)) {
3797                 rc = ecore_iov_hw_info(p_hwfn);
3798                 if (rc != ECORE_SUCCESS) {
3799                         if (p_params->b_relaxed_probe)
3800                                 p_params->p_relaxed_res =
3801                                                 ECORE_HW_PREPARE_BAD_IOV;
3802                         else
3803                                 return rc;
3804                 }
3805         }
3806
3807         if (IS_LEAD_HWFN(p_hwfn))
3808                 ecore_hw_info_port_num(p_hwfn, p_ptt);
3809
3810         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3811
3812 #ifndef ASIC_ONLY
3813         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3814 #endif
3815         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3816         if (rc != ECORE_SUCCESS)
3817                 return rc;
3818 #ifndef ASIC_ONLY
3819         }
3820 #endif
3821
3822         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3823         if (rc != ECORE_SUCCESS) {
3824                 if (p_params->b_relaxed_probe)
3825                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3826                 else
3827                         return rc;
3828         }
3829
3830 #ifndef ASIC_ONLY
3831         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3832 #endif
3833                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3834                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3835 #ifndef ASIC_ONLY
3836         } else {
3837                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3838
3839                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3840                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3841         }
3842 #endif
3843
3844         if (ecore_mcp_is_init(p_hwfn)) {
3845                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3846                         p_hwfn->hw_info.ovlan =
3847                             p_hwfn->mcp_info->func_info.ovlan;
3848
3849                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3850
3851                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3852
3853                 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
3854         }
3855
3856         if (personality != ECORE_PCI_DEFAULT) {
3857                 p_hwfn->hw_info.personality = personality;
3858         } else if (ecore_mcp_is_init(p_hwfn)) {
3859                 enum ecore_pci_personality protocol;
3860
3861                 protocol = p_hwfn->mcp_info->func_info.protocol;
3862                 p_hwfn->hw_info.personality = protocol;
3863         }
3864
3865 #ifndef ASIC_ONLY
3866         /* To overcome ILT lack for emulation, until at least until we'll have
3867          * a definite answer from system about it, allow only PF0 to be RoCE.
3868          */
3869         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3870                 if (!p_hwfn->rel_pf_id)
3871                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3872                 else
3873                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3874         }
3875 #endif
3876
3877         /* although in BB some constellations may support more than 4 tcs,
3878          * that can result in performance penalty in some cases. 4
3879          * represents a good tradeoff between performance and flexibility.
3880          */
3881         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3882
3883         /* start out with a single active tc. This can be increased either
3884          * by dcbx negotiation or by upper layer driver
3885          */
3886         p_hwfn->hw_info.num_active_tc = 1;
3887
3888         ecore_get_num_funcs(p_hwfn, p_ptt);
3889
3890         if (ecore_mcp_is_init(p_hwfn))
3891                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3892
3893         /* In case of forcing the driver's default resource allocation, calling
3894          * ecore_hw_get_resc() should come after initializing the personality
3895          * and after getting the number of functions, since the calculation of
3896          * the resources/features depends on them.
3897          * This order is not harmful if not forcing.
3898          */
3899         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3900         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3901                 rc = ECORE_SUCCESS;
3902                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3903         }
3904
3905         return rc;
3906 }
3907
3908 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3909                                                struct ecore_ptt *p_ptt)
3910 {
3911         struct ecore_dev *p_dev = p_hwfn->p_dev;
3912         u16 device_id_mask;
3913         u32 tmp;
3914
3915         /* Read Vendor Id / Device Id */
3916         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3917                                   &p_dev->vendor_id);
3918         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3919                                   &p_dev->device_id);
3920
3921         /* Determine type */
3922         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3923         switch (device_id_mask) {
3924         case ECORE_DEV_ID_MASK_BB:
3925                 p_dev->type = ECORE_DEV_TYPE_BB;
3926                 break;
3927         case ECORE_DEV_ID_MASK_AH:
3928                 p_dev->type = ECORE_DEV_TYPE_AH;
3929                 break;
3930         default:
3931                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3932                           p_dev->device_id);
3933                 return ECORE_ABORTED;
3934         }
3935
3936         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3937         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
3938         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3939         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
3940
3941         /* Learn number of HW-functions */
3942         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3943
3944         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3945                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3946                 p_dev->num_hwfns = 2;
3947         } else {
3948                 p_dev->num_hwfns = 1;
3949         }
3950
3951 #ifndef ASIC_ONLY
3952         if (CHIP_REV_IS_EMUL(p_dev)) {
3953                 /* For some reason we have problems with this register
3954                  * in B0 emulation; Simply assume no CMT
3955                  */
3956                 DP_NOTICE(p_dev->hwfns, false,
3957                           "device on emul - assume no CMT\n");
3958                 p_dev->num_hwfns = 1;
3959         }
3960 #endif
3961
3962         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
3963         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
3964         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3965         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
3966
3967         DP_INFO(p_dev->hwfns,
3968                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
3969                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3970                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3971                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3972                 p_dev->chip_metal);
3973
3974         if (ECORE_IS_BB_A0(p_dev)) {
3975                 DP_NOTICE(p_dev->hwfns, false,
3976                           "The chip type/rev (BB A0) is not supported!\n");
3977                 return ECORE_ABORTED;
3978         }
3979 #ifndef ASIC_ONLY
3980         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3981                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3982
3983         if (CHIP_REV_IS_EMUL(p_dev)) {
3984                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3985                 if (tmp & (1 << 29)) {
3986                         DP_NOTICE(p_hwfn, false,
3987                                   "Emulation: Running on a FULL build\n");
3988                         p_dev->b_is_emul_full = true;
3989                 } else {
3990                         DP_NOTICE(p_hwfn, false,
3991                                   "Emulation: Running on a REDUCED build\n");
3992                 }
3993         }
3994 #endif
3995
3996         return ECORE_SUCCESS;
3997 }
3998
3999 #ifndef LINUX_REMOVE
4000 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
4001 {
4002         int j;
4003
4004         if (IS_VF(p_dev))
4005                 return;
4006
4007         for_each_hwfn(p_dev, j) {
4008                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4009
4010                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4011                            "Mark hw/fw uninitialized\n");
4012
4013                 p_hwfn->hw_init_done = false;
4014
4015                 ecore_ptt_invalidate(p_hwfn);
4016         }
4017 }
4018 #endif
4019
4020 static enum _ecore_status_t
4021 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4022                         void OSAL_IOMEM * p_regview,
4023                         void OSAL_IOMEM * p_doorbells,
4024                         struct ecore_hw_prepare_params *p_params)
4025 {
4026         struct ecore_mdump_retain_data mdump_retain;
4027         struct ecore_dev *p_dev = p_hwfn->p_dev;
4028         struct ecore_mdump_info mdump_info;
4029         enum _ecore_status_t rc = ECORE_SUCCESS;
4030
4031         /* Split PCI bars evenly between hwfns */
4032         p_hwfn->regview = p_regview;
4033         p_hwfn->doorbells = p_doorbells;
4034
4035         if (IS_VF(p_dev))
4036                 return ecore_vf_hw_prepare(p_hwfn);
4037
4038         /* Validate that chip access is feasible */
4039         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4040                 DP_ERR(p_hwfn,
4041                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4042                 if (p_params->b_relaxed_probe)
4043                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4044                 return ECORE_INVAL;
4045         }
4046
4047         get_function_id(p_hwfn);
4048
4049         /* Allocate PTT pool */
4050         rc = ecore_ptt_pool_alloc(p_hwfn);
4051         if (rc) {
4052                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
4053                 if (p_params->b_relaxed_probe)
4054                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4055                 goto err0;
4056         }
4057
4058         /* Allocate the main PTT */
4059         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4060
4061         /* First hwfn learns basic information, e.g., number of hwfns */
4062         if (!p_hwfn->my_id) {
4063                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4064                 if (rc != ECORE_SUCCESS) {
4065                         if (p_params->b_relaxed_probe)
4066                                 p_params->p_relaxed_res =
4067                                         ECORE_HW_PREPARE_FAILED_DEV;
4068                         goto err1;
4069                 }
4070         }
4071
4072         ecore_hw_hwfn_prepare(p_hwfn);
4073
4074         /* Initialize MCP structure */
4075         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4076         if (rc) {
4077                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
4078                 if (p_params->b_relaxed_probe)
4079                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4080                 goto err1;
4081         }
4082
4083         /* Read the device configuration information from the HW and SHMEM */
4084         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4085                                p_params->personality, p_params);
4086         if (rc) {
4087                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
4088                 goto err2;
4089         }
4090
4091         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4092          * called, since among others it sets the ports number in an engine.
4093          */
4094         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4095             !p_dev->recov_in_prog) {
4096                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4097                 if (rc != ECORE_SUCCESS)
4098                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4099         }
4100
4101         /* Check if mdump logs/data are present and update the epoch value */
4102         if (IS_LEAD_HWFN(p_hwfn)) {
4103 #ifndef ASIC_ONLY
4104                 if (!CHIP_REV_IS_EMUL(p_dev)) {
4105 #endif
4106                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4107                                               &mdump_info);
4108                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4109                         DP_NOTICE(p_hwfn, false,
4110                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4111
4112                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4113                                                 &mdump_retain);
4114                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4115                         DP_NOTICE(p_hwfn, false,
4116                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4117                                   mdump_retain.epoch, mdump_retain.pf,
4118                                   mdump_retain.status);
4119
4120                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4121                                            p_params->epoch);
4122 #ifndef ASIC_ONLY
4123                 }
4124 #endif
4125         }
4126
4127         /* Allocate the init RT array and initialize the init-ops engine */
4128         rc = ecore_init_alloc(p_hwfn);
4129         if (rc) {
4130                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
4131                 if (p_params->b_relaxed_probe)
4132                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4133                 goto err2;
4134         }
4135 #ifndef ASIC_ONLY
4136         if (CHIP_REV_IS_FPGA(p_dev)) {
4137                 DP_NOTICE(p_hwfn, false,
4138                           "FPGA: workaround; Prevent DMAE parities\n");
4139                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4140                          7);
4141
4142                 DP_NOTICE(p_hwfn, false,
4143                           "FPGA: workaround: Set VF bar0 size\n");
4144                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4145                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4146         }
4147 #endif
4148
4149         return rc;
4150 err2:
4151         if (IS_LEAD_HWFN(p_hwfn))
4152                 ecore_iov_free_hw_info(p_dev);
4153         ecore_mcp_free(p_hwfn);
4154 err1:
4155         ecore_hw_hwfn_free(p_hwfn);
4156 err0:
4157         return rc;
4158 }
4159
4160 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4161                                       struct ecore_hw_prepare_params *p_params)
4162 {
4163         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4164         enum _ecore_status_t rc;
4165
4166         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4167         p_dev->allow_mdump = p_params->allow_mdump;
4168
4169         if (p_params->b_relaxed_probe)
4170                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4171
4172         /* Store the precompiled init data ptrs */
4173         if (IS_PF(p_dev))
4174                 ecore_init_iro_array(p_dev);
4175
4176         /* Initialize the first hwfn - will learn number of hwfns */
4177         rc = ecore_hw_prepare_single(p_hwfn,
4178                                      p_dev->regview,
4179                                      p_dev->doorbells, p_params);
4180         if (rc != ECORE_SUCCESS)
4181                 return rc;
4182
4183         p_params->personality = p_hwfn->hw_info.personality;
4184
4185         /* initilalize 2nd hwfn if necessary */
4186         if (ECORE_IS_CMT(p_dev)) {
4187                 void OSAL_IOMEM *p_regview, *p_doorbell;
4188                 u8 OSAL_IOMEM *addr;
4189
4190                 /* adjust bar offset for second engine */
4191                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4192                                         ecore_hw_bar_size(p_hwfn,
4193                                                           p_hwfn->p_main_ptt,
4194                                                           BAR_ID_0) / 2;
4195                 p_regview = (void OSAL_IOMEM *)addr;
4196
4197                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4198                                         ecore_hw_bar_size(p_hwfn,
4199                                                           p_hwfn->p_main_ptt,
4200                                                           BAR_ID_1) / 2;
4201                 p_doorbell = (void OSAL_IOMEM *)addr;
4202
4203                 /* prepare second hw function */
4204                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4205                                              p_doorbell, p_params);
4206
4207                 /* in case of error, need to free the previously
4208                  * initiliazed hwfn 0.
4209                  */
4210                 if (rc != ECORE_SUCCESS) {
4211                         if (p_params->b_relaxed_probe)
4212                                 p_params->p_relaxed_res =
4213                                                 ECORE_HW_PREPARE_FAILED_ENG2;
4214
4215                         if (IS_PF(p_dev)) {
4216                                 ecore_init_free(p_hwfn);
4217                                 ecore_mcp_free(p_hwfn);
4218                                 ecore_hw_hwfn_free(p_hwfn);
4219                         } else {
4220                                 DP_NOTICE(p_dev, true,
4221                                           "What do we need to free when VF hwfn1 init fails\n");
4222                         }
4223                         return rc;
4224                 }
4225         }
4226
4227         return rc;
4228 }
4229
4230 void ecore_hw_remove(struct ecore_dev *p_dev)
4231 {
4232         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4233         int i;
4234
4235         if (IS_PF(p_dev))
4236                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4237                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
4238
4239         for_each_hwfn(p_dev, i) {
4240                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4241
4242                 if (IS_VF(p_dev)) {
4243                         ecore_vf_pf_release(p_hwfn);
4244                         continue;
4245                 }
4246
4247                 ecore_init_free(p_hwfn);
4248                 ecore_hw_hwfn_free(p_hwfn);
4249                 ecore_mcp_free(p_hwfn);
4250
4251 #ifdef CONFIG_ECORE_LOCK_ALLOC
4252                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
4253 #endif
4254         }
4255
4256         ecore_iov_free_hw_info(p_dev);
4257 }
4258
4259 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4260                                       struct ecore_chain *p_chain)
4261 {
4262         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4263         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4264         struct ecore_chain_next *p_next;
4265         u32 size, i;
4266
4267         if (!p_virt)
4268                 return;
4269
4270         size = p_chain->elem_size * p_chain->usable_per_page;
4271
4272         for (i = 0; i < p_chain->page_cnt; i++) {
4273                 if (!p_virt)
4274                         break;
4275
4276                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4277                 p_virt_next = p_next->next_virt;
4278                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4279
4280                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4281                                        ECORE_CHAIN_PAGE_SIZE);
4282
4283                 p_virt = p_virt_next;
4284                 p_phys = p_phys_next;
4285         }
4286 }
4287
4288 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4289                                     struct ecore_chain *p_chain)
4290 {
4291         if (!p_chain->p_virt_addr)
4292                 return;
4293
4294         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4295                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4296 }
4297
4298 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4299                                  struct ecore_chain *p_chain)
4300 {
4301         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4302         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4303         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4304
4305         if (!pp_virt_addr_tbl)
4306                 return;
4307
4308         if (!p_pbl_virt)
4309                 goto out;
4310
4311         for (i = 0; i < page_cnt; i++) {
4312                 if (!pp_virt_addr_tbl[i])
4313                         break;
4314
4315                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4316                                        *(dma_addr_t *)p_pbl_virt,
4317                                        ECORE_CHAIN_PAGE_SIZE);
4318
4319                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4320         }
4321
4322         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4323
4324         if (!p_chain->b_external_pbl)
4325                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4326                                        p_chain->pbl_sp.p_phys_table, pbl_size);
4327 out:
4328         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4329 }
4330
4331 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4332 {
4333         switch (p_chain->mode) {
4334         case ECORE_CHAIN_MODE_NEXT_PTR:
4335                 ecore_chain_free_next_ptr(p_dev, p_chain);
4336                 break;
4337         case ECORE_CHAIN_MODE_SINGLE:
4338                 ecore_chain_free_single(p_dev, p_chain);
4339                 break;
4340         case ECORE_CHAIN_MODE_PBL:
4341                 ecore_chain_free_pbl(p_dev, p_chain);
4342                 break;
4343         }
4344 }
4345
4346 static enum _ecore_status_t
4347 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4348                                enum ecore_chain_cnt_type cnt_type,
4349                                osal_size_t elem_size, u32 page_cnt)
4350 {
4351         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4352
4353         /* The actual chain size can be larger than the maximal possible value
4354          * after rounding up the requested elements number to pages, and after
4355          * taking into acount the unusuable elements (next-ptr elements).
4356          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4357          * size/capacity fields are of a u32 type.
4358          */
4359         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4360              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4361             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4362              chain_size > ECORE_U32_MAX)) {
4363                 DP_NOTICE(p_dev, true,
4364                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4365                           (unsigned long)chain_size);
4366                 return ECORE_INVAL;
4367         }
4368
4369         return ECORE_SUCCESS;
4370 }
4371
4372 static enum _ecore_status_t
4373 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4374 {
4375         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4376         dma_addr_t p_phys = 0;
4377         u32 i;
4378
4379         for (i = 0; i < p_chain->page_cnt; i++) {
4380                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4381                                                  ECORE_CHAIN_PAGE_SIZE);
4382                 if (!p_virt) {
4383                         DP_NOTICE(p_dev, true,
4384                                   "Failed to allocate chain memory\n");
4385                         return ECORE_NOMEM;
4386                 }
4387
4388                 if (i == 0) {
4389                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4390                         ecore_chain_reset(p_chain);
4391                 } else {
4392                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4393                                                        p_virt, p_phys);
4394                 }
4395
4396                 p_virt_prev = p_virt;
4397         }
4398         /* Last page's next element should point to the beginning of the
4399          * chain.
4400          */
4401         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4402                                        p_chain->p_virt_addr,
4403                                        p_chain->p_phys_addr);
4404
4405         return ECORE_SUCCESS;
4406 }
4407
4408 static enum _ecore_status_t
4409 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4410 {
4411         dma_addr_t p_phys = 0;
4412         void *p_virt = OSAL_NULL;
4413
4414         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4415         if (!p_virt) {
4416                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4417                 return ECORE_NOMEM;
4418         }
4419
4420         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4421         ecore_chain_reset(p_chain);
4422
4423         return ECORE_SUCCESS;
4424 }
4425
4426 static enum _ecore_status_t
4427 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4428                       struct ecore_chain *p_chain,
4429                       struct ecore_chain_ext_pbl *ext_pbl)
4430 {
4431         u32 page_cnt = p_chain->page_cnt, size, i;
4432         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4433         void **pp_virt_addr_tbl = OSAL_NULL;
4434         u8 *p_pbl_virt = OSAL_NULL;
4435         void *p_virt = OSAL_NULL;
4436
4437         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4438         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4439         if (!pp_virt_addr_tbl) {
4440                 DP_NOTICE(p_dev, true,
4441                           "Failed to allocate memory for the chain virtual addresses table\n");
4442                 return ECORE_NOMEM;
4443         }
4444
4445         /* The allocation of the PBL table is done with its full size, since it
4446          * is expected to be successive.
4447          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4448          * failure, since pp_virt_addr_tbl was previously allocated, and it
4449          * should be saved to allow its freeing during the error flow.
4450          */
4451         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4452
4453         if (ext_pbl == OSAL_NULL) {
4454                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4455         } else {
4456                 p_pbl_virt = ext_pbl->p_pbl_virt;
4457                 p_pbl_phys = ext_pbl->p_pbl_phys;
4458                 p_chain->b_external_pbl = true;
4459         }
4460
4461         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4462                                  pp_virt_addr_tbl);
4463         if (!p_pbl_virt) {
4464                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4465                 return ECORE_NOMEM;
4466         }
4467
4468         for (i = 0; i < page_cnt; i++) {
4469                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4470                                                  ECORE_CHAIN_PAGE_SIZE);
4471                 if (!p_virt) {
4472                         DP_NOTICE(p_dev, true,
4473                                   "Failed to allocate chain memory\n");
4474                         return ECORE_NOMEM;
4475                 }
4476
4477                 if (i == 0) {
4478                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4479                         ecore_chain_reset(p_chain);
4480                 }
4481
4482                 /* Fill the PBL table with the physical address of the page */
4483                 *(dma_addr_t *)p_pbl_virt = p_phys;
4484                 /* Keep the virtual address of the page */
4485                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4486
4487                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4488         }
4489
4490         return ECORE_SUCCESS;
4491 }
4492
4493 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4494                                        enum ecore_chain_use_mode intended_use,
4495                                        enum ecore_chain_mode mode,
4496                                        enum ecore_chain_cnt_type cnt_type,
4497                                        u32 num_elems, osal_size_t elem_size,
4498                                        struct ecore_chain *p_chain,
4499                                        struct ecore_chain_ext_pbl *ext_pbl)
4500 {
4501         u32 page_cnt;
4502         enum _ecore_status_t rc = ECORE_SUCCESS;
4503
4504         if (mode == ECORE_CHAIN_MODE_SINGLE)
4505                 page_cnt = 1;
4506         else
4507                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4508
4509         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4510                                             page_cnt);
4511         if (rc) {
4512                 DP_NOTICE(p_dev, true,
4513                           "Cannot allocate a chain with the given arguments:\n"
4514                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4515                           intended_use, mode, cnt_type, num_elems, elem_size);
4516                 return rc;
4517         }
4518
4519         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4520                                 mode, cnt_type, p_dev->dp_ctx);
4521
4522         switch (mode) {
4523         case ECORE_CHAIN_MODE_NEXT_PTR:
4524                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4525                 break;
4526         case ECORE_CHAIN_MODE_SINGLE:
4527                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4528                 break;
4529         case ECORE_CHAIN_MODE_PBL:
4530                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4531                 break;
4532         }
4533         if (rc)
4534                 goto nomem;
4535
4536         return ECORE_SUCCESS;
4537
4538 nomem:
4539         ecore_chain_free(p_dev, p_chain);
4540         return rc;
4541 }
4542
4543 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4544                                        u16 src_id, u16 *dst_id)
4545 {
4546         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4547                 u16 min, max;
4548
4549                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4550                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4551                 DP_NOTICE(p_hwfn, true,
4552                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4553                           src_id, min, max);
4554
4555                 return ECORE_INVAL;
4556         }
4557
4558         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4559
4560         return ECORE_SUCCESS;
4561 }
4562
4563 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4564                                     u8 src_id, u8 *dst_id)
4565 {
4566         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4567                 u8 min, max;
4568
4569                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4570                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4571                 DP_NOTICE(p_hwfn, true,
4572                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4573                           src_id, min, max);
4574
4575                 return ECORE_INVAL;
4576         }
4577
4578         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4579
4580         return ECORE_SUCCESS;
4581 }
4582
4583 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4584                                       u8 src_id, u8 *dst_id)
4585 {
4586         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4587                 u8 min, max;
4588
4589                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4590                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4591                 DP_NOTICE(p_hwfn, true,
4592                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4593                           src_id, min, max);
4594
4595                 return ECORE_INVAL;
4596         }
4597
4598         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4599
4600         return ECORE_SUCCESS;
4601 }
4602
4603 static enum _ecore_status_t
4604 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4605                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4606                                u32 *p_entry_num)
4607 {
4608         u32 en;
4609         int i;
4610
4611         /* Find a free entry and utilize it */
4612         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4613                 en = ecore_rd(p_hwfn, p_ptt,
4614                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4615                               i * sizeof(u32));
4616                 if (en)
4617                         continue;
4618                 ecore_wr(p_hwfn, p_ptt,
4619                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4620                          2 * i * sizeof(u32), low);
4621                 ecore_wr(p_hwfn, p_ptt,
4622                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4623                          (2 * i + 1) * sizeof(u32), high);
4624                 ecore_wr(p_hwfn, p_ptt,
4625                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4626                          i * sizeof(u32), 0);
4627                 ecore_wr(p_hwfn, p_ptt,
4628                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4629                          i * sizeof(u32), 0);
4630                 ecore_wr(p_hwfn, p_ptt,
4631                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4632                          i * sizeof(u32), 1);
4633                 break;
4634         }
4635
4636         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4637                 return ECORE_NORESOURCES;
4638
4639         *p_entry_num = i;
4640
4641         return ECORE_SUCCESS;
4642 }
4643
4644 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4645                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4646 {
4647         u32 high, low, entry_num;
4648         enum _ecore_status_t rc = ECORE_SUCCESS;
4649
4650         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4651                            &p_hwfn->p_dev->mf_bits))
4652                 return ECORE_SUCCESS;
4653
4654         high = p_filter[1] | (p_filter[0] << 8);
4655         low = p_filter[5] | (p_filter[4] << 8) |
4656               (p_filter[3] << 16) | (p_filter[2] << 24);
4657
4658         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4659                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4660                                                     &entry_num);
4661         if (rc != ECORE_SUCCESS) {
4662                 DP_NOTICE(p_hwfn, false,
4663                           "Failed to find an empty LLH filter to utilize\n");
4664                 return rc;
4665         }
4666
4667         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4668                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4669                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4670                    p_filter[4], p_filter[5], entry_num);
4671
4672         return rc;
4673 }
4674
4675 static enum _ecore_status_t
4676 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4677                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4678                                   u32 *p_entry_num)
4679 {
4680         int i;
4681
4682         /* Find the entry and clean it */
4683         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4684                 if (ecore_rd(p_hwfn, p_ptt,
4685                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4686                              2 * i * sizeof(u32)) != low)
4687                         continue;
4688                 if (ecore_rd(p_hwfn, p_ptt,
4689                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4690                              (2 * i + 1) * sizeof(u32)) != high)
4691                         continue;
4692
4693                 ecore_wr(p_hwfn, p_ptt,
4694                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4695                 ecore_wr(p_hwfn, p_ptt,
4696                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4697                          2 * i * sizeof(u32), 0);
4698                 ecore_wr(p_hwfn, p_ptt,
4699                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4700                          (2 * i + 1) * sizeof(u32), 0);
4701                 break;
4702         }
4703
4704         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4705                 return ECORE_INVAL;
4706
4707         *p_entry_num = i;
4708
4709         return ECORE_SUCCESS;
4710 }
4711
4712 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4713                              struct ecore_ptt *p_ptt, u8 *p_filter)
4714 {
4715         u32 high, low, entry_num;
4716         enum _ecore_status_t rc = ECORE_SUCCESS;
4717
4718         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4719                            &p_hwfn->p_dev->mf_bits))
4720                 return;
4721
4722         high = p_filter[1] | (p_filter[0] << 8);
4723         low = p_filter[5] | (p_filter[4] << 8) |
4724               (p_filter[3] << 16) | (p_filter[2] << 24);
4725
4726         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4727                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4728                                                        low, &entry_num);
4729         if (rc != ECORE_SUCCESS) {
4730                 DP_NOTICE(p_hwfn, false,
4731                           "Tried to remove a non-configured filter\n");
4732                 return;
4733         }
4734
4735
4736         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4737                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4738                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4739                    p_filter[4], p_filter[5], entry_num);
4740 }
4741
4742 static enum _ecore_status_t
4743 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4744                                     struct ecore_ptt *p_ptt,
4745                                     enum ecore_llh_port_filter_type_t type,
4746                                     u32 high, u32 low, u32 *p_entry_num)
4747 {
4748         u32 en;
4749         int i;
4750
4751         /* Find a free entry and utilize it */
4752         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4753                 en = ecore_rd(p_hwfn, p_ptt,
4754                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4755                               i * sizeof(u32));
4756                 if (en)
4757                         continue;
4758                 ecore_wr(p_hwfn, p_ptt,
4759                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4760                          2 * i * sizeof(u32), low);
4761                 ecore_wr(p_hwfn, p_ptt,
4762                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4763                          (2 * i + 1) * sizeof(u32), high);
4764                 ecore_wr(p_hwfn, p_ptt,
4765                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4766                          i * sizeof(u32), 1);
4767                 ecore_wr(p_hwfn, p_ptt,
4768                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4769                          i * sizeof(u32), 1 << type);
4770                 ecore_wr(p_hwfn, p_ptt,
4771                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4772                 break;
4773         }
4774
4775         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4776                 return ECORE_NORESOURCES;
4777
4778         *p_entry_num = i;
4779
4780         return ECORE_SUCCESS;
4781 }
4782
4783 enum _ecore_status_t
4784 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4785                               struct ecore_ptt *p_ptt,
4786                               u16 source_port_or_eth_type,
4787                               u16 dest_port,
4788                               enum ecore_llh_port_filter_type_t type)
4789 {
4790         u32 high, low, entry_num;
4791         enum _ecore_status_t rc = ECORE_SUCCESS;
4792
4793         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4794                            &p_hwfn->p_dev->mf_bits))
4795                 return rc;
4796
4797         high = 0;
4798         low = 0;
4799
4800         switch (type) {
4801         case ECORE_LLH_FILTER_ETHERTYPE:
4802                 high = source_port_or_eth_type;
4803                 break;
4804         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4805         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4806                 low = source_port_or_eth_type << 16;
4807                 break;
4808         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4809         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4810                 low = dest_port;
4811                 break;
4812         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4813         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4814                 low = (source_port_or_eth_type << 16) | dest_port;
4815                 break;
4816         default:
4817                 DP_NOTICE(p_hwfn, true,
4818                           "Non valid LLH protocol filter type %d\n", type);
4819                 return ECORE_INVAL;
4820         }
4821
4822         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4823                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4824                                                          high, low, &entry_num);
4825         if (rc != ECORE_SUCCESS) {
4826                 DP_NOTICE(p_hwfn, false,
4827                           "Failed to find an empty LLH filter to utilize\n");
4828                 return rc;
4829         }
4830         switch (type) {
4831         case ECORE_LLH_FILTER_ETHERTYPE:
4832                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4833                            "ETH type %x is added at %d\n",
4834                            source_port_or_eth_type, entry_num);
4835                 break;
4836         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4837                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4838                            "TCP src port %x is added at %d\n",
4839                            source_port_or_eth_type, entry_num);
4840                 break;
4841         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4842                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4843                            "UDP src port %x is added at %d\n",
4844                            source_port_or_eth_type, entry_num);
4845                 break;
4846         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4847                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4848                            "TCP dst port %x is added at %d\n", dest_port,
4849                            entry_num);
4850                 break;
4851         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4852                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4853                            "UDP dst port %x is added at %d\n", dest_port,
4854                            entry_num);
4855                 break;
4856         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4857                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4858                            "TCP src/dst ports %x/%x are added at %d\n",
4859                            source_port_or_eth_type, dest_port, entry_num);
4860                 break;
4861         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4862                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4863                            "UDP src/dst ports %x/%x are added at %d\n",
4864                            source_port_or_eth_type, dest_port, entry_num);
4865                 break;
4866         }
4867
4868         return rc;
4869 }
4870
4871 static enum _ecore_status_t
4872 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4873                                        struct ecore_ptt *p_ptt,
4874                                        enum ecore_llh_port_filter_type_t type,
4875                                        u32 high, u32 low, u32 *p_entry_num)
4876 {
4877         int i;
4878
4879         /* Find the entry and clean it */
4880         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4881                 if (!ecore_rd(p_hwfn, p_ptt,
4882                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4883                               i * sizeof(u32)))
4884                         continue;
4885                 if (!ecore_rd(p_hwfn, p_ptt,
4886                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4887                               i * sizeof(u32)))
4888                         continue;
4889                 if (!(ecore_rd(p_hwfn, p_ptt,
4890                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4891                                i * sizeof(u32)) & (1 << type)))
4892                         continue;
4893                 if (ecore_rd(p_hwfn, p_ptt,
4894                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4895                              2 * i * sizeof(u32)) != low)
4896                         continue;
4897                 if (ecore_rd(p_hwfn, p_ptt,
4898                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4899                              (2 * i + 1) * sizeof(u32)) != high)
4900                         continue;
4901
4902                 ecore_wr(p_hwfn, p_ptt,
4903                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4904                 ecore_wr(p_hwfn, p_ptt,
4905                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4906                          i * sizeof(u32), 0);
4907                 ecore_wr(p_hwfn, p_ptt,
4908                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4909                          i * sizeof(u32), 0);
4910                 ecore_wr(p_hwfn, p_ptt,
4911                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4912                          2 * i * sizeof(u32), 0);
4913                 ecore_wr(p_hwfn, p_ptt,
4914                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4915                          (2 * i + 1) * sizeof(u32), 0);
4916                 break;
4917         }
4918
4919         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4920                 return ECORE_INVAL;
4921
4922         *p_entry_num = i;
4923
4924         return ECORE_SUCCESS;
4925 }
4926
4927 void
4928 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4929                                  struct ecore_ptt *p_ptt,
4930                                  u16 source_port_or_eth_type,
4931                                  u16 dest_port,
4932                                  enum ecore_llh_port_filter_type_t type)
4933 {
4934         u32 high, low, entry_num;
4935         enum _ecore_status_t rc = ECORE_SUCCESS;
4936
4937         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4938                            &p_hwfn->p_dev->mf_bits))
4939                 return;
4940
4941         high = 0;
4942         low = 0;
4943
4944         switch (type) {
4945         case ECORE_LLH_FILTER_ETHERTYPE:
4946                 high = source_port_or_eth_type;
4947                 break;
4948         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4949         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4950                 low = source_port_or_eth_type << 16;
4951                 break;
4952         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4953         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4954                 low = dest_port;
4955                 break;
4956         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4957         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4958                 low = (source_port_or_eth_type << 16) | dest_port;
4959                 break;
4960         default:
4961                 DP_NOTICE(p_hwfn, true,
4962                           "Non valid LLH protocol filter type %d\n", type);
4963                 return;
4964         }
4965
4966         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4967                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4968                                                             high, low,
4969                                                             &entry_num);
4970         if (rc != ECORE_SUCCESS) {
4971                 DP_NOTICE(p_hwfn, false,
4972                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4973                           type, source_port_or_eth_type, dest_port);
4974                 return;
4975         }
4976
4977         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4978                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4979                    type, source_port_or_eth_type, dest_port, entry_num);
4980 }
4981
4982 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4983                                               struct ecore_ptt *p_ptt)
4984 {
4985         int i;
4986
4987         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4988                 return;
4989
4990         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4991                 ecore_wr(p_hwfn, p_ptt,
4992                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
4993                          i * sizeof(u32), 0);
4994                 ecore_wr(p_hwfn, p_ptt,
4995                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4996                          2 * i * sizeof(u32), 0);
4997                 ecore_wr(p_hwfn, p_ptt,
4998                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4999                          (2 * i + 1) * sizeof(u32), 0);
5000         }
5001 }
5002
5003 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
5004                              struct ecore_ptt *p_ptt)
5005 {
5006         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5007                            &p_hwfn->p_dev->mf_bits) &&
5008             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5009                            &p_hwfn->p_dev->mf_bits))
5010                 return;
5011
5012         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5013                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5014 }
5015
5016 enum _ecore_status_t
5017 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5018                                   struct ecore_ptt *p_ptt)
5019 {
5020         if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5021                 ecore_wr(p_hwfn, p_ptt,
5022                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5023                          1 << p_hwfn->abs_pf_id / 2);
5024                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5025                 return ECORE_SUCCESS;
5026         }
5027
5028         DP_NOTICE(p_hwfn, false,
5029                   "This function can't be set as default\n");
5030         return ECORE_INVAL;
5031 }
5032
5033 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5034                                                struct ecore_ptt *p_ptt,
5035                                                u32 hw_addr, void *p_eth_qzone,
5036                                                osal_size_t eth_qzone_size,
5037                                                u8 timeset)
5038 {
5039         struct coalescing_timeset *p_coal_timeset;
5040
5041         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5042                 DP_NOTICE(p_hwfn, true,
5043                           "Coalescing configuration not enabled\n");
5044                 return ECORE_INVAL;
5045         }
5046
5047         p_coal_timeset = p_eth_qzone;
5048         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5049         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5050         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5051         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5052
5053         return ECORE_SUCCESS;
5054 }
5055
5056 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5057                                               u16 rx_coal, u16 tx_coal,
5058                                               void *p_handle)
5059 {
5060         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5061         enum _ecore_status_t rc = ECORE_SUCCESS;
5062         struct ecore_ptt *p_ptt;
5063
5064         /* TODO - Configuring a single queue's coalescing but
5065          * claiming all queues are abiding same configuration
5066          * for PF and VF both.
5067          */
5068
5069         if (IS_VF(p_hwfn->p_dev))
5070                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5071                                                 tx_coal, p_cid);
5072
5073         p_ptt = ecore_ptt_acquire(p_hwfn);
5074         if (!p_ptt)
5075                 return ECORE_AGAIN;
5076
5077         if (rx_coal) {
5078                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5079                 if (rc)
5080                         goto out;
5081                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5082         }
5083
5084         if (tx_coal) {
5085                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5086                 if (rc)
5087                         goto out;
5088                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5089         }
5090 out:
5091         ecore_ptt_release(p_hwfn, p_ptt);
5092
5093         return rc;
5094 }
5095
5096 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5097                                             struct ecore_ptt *p_ptt,
5098                                             u16 coalesce,
5099                                             struct ecore_queue_cid *p_cid)
5100 {
5101         struct ustorm_eth_queue_zone eth_qzone;
5102         u8 timeset, timer_res;
5103         u32 address;
5104         enum _ecore_status_t rc;
5105
5106         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5107         if (coalesce <= 0x7F) {
5108                 timer_res = 0;
5109         } else if (coalesce <= 0xFF) {
5110                 timer_res = 1;
5111         } else if (coalesce <= 0x1FF) {
5112                 timer_res = 2;
5113         } else {
5114                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5115                 return ECORE_INVAL;
5116         }
5117         timeset = (u8)(coalesce >> timer_res);
5118
5119         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5120                                      p_cid->sb_igu_id, false);
5121         if (rc != ECORE_SUCCESS)
5122                 goto out;
5123
5124         address = BAR0_MAP_REG_USDM_RAM +
5125                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5126
5127         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5128                                 sizeof(struct ustorm_eth_queue_zone), timeset);
5129         if (rc != ECORE_SUCCESS)
5130                 goto out;
5131
5132 out:
5133         return rc;
5134 }
5135
5136 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5137                                             struct ecore_ptt *p_ptt,
5138                                             u16 coalesce,
5139                                             struct ecore_queue_cid *p_cid)
5140 {
5141         struct xstorm_eth_queue_zone eth_qzone;
5142         u8 timeset, timer_res;
5143         u32 address;
5144         enum _ecore_status_t rc;
5145
5146         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5147         if (coalesce <= 0x7F) {
5148                 timer_res = 0;
5149         } else if (coalesce <= 0xFF) {
5150                 timer_res = 1;
5151         } else if (coalesce <= 0x1FF) {
5152                 timer_res = 2;
5153         } else {
5154                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5155                 return ECORE_INVAL;
5156         }
5157
5158         timeset = (u8)(coalesce >> timer_res);
5159
5160         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5161                                      p_cid->sb_igu_id, true);
5162         if (rc != ECORE_SUCCESS)
5163                 goto out;
5164
5165         address = BAR0_MAP_REG_XSDM_RAM +
5166                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5167
5168         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5169                                 sizeof(struct xstorm_eth_queue_zone), timeset);
5170 out:
5171         return rc;
5172 }
5173
5174 /* Calculate final WFQ values for all vports and configure it.
5175  * After this configuration each vport must have
5176  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5177  */
5178 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5179                                                struct ecore_ptt *p_ptt,
5180                                                u32 min_pf_rate)
5181 {
5182         struct init_qm_vport_params *vport_params;
5183         int i;
5184
5185         vport_params = p_hwfn->qm_info.qm_vport_params;
5186
5187         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5188                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5189
5190                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5191                     min_pf_rate;
5192                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5193                                      vport_params[i].first_tx_pq_id,
5194                                      vport_params[i].vport_wfq);
5195         }
5196 }
5197
5198 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5199 {
5200         int i;
5201
5202         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5203                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5204 }
5205
5206 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5207                                              struct ecore_ptt *p_ptt)
5208 {
5209         struct init_qm_vport_params *vport_params;
5210         int i;
5211
5212         vport_params = p_hwfn->qm_info.qm_vport_params;
5213
5214         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5215                 ecore_init_wfq_default_param(p_hwfn);
5216                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5217                                      vport_params[i].first_tx_pq_id,
5218                                      vport_params[i].vport_wfq);
5219         }
5220 }
5221
5222 /* This function performs several validations for WFQ
5223  * configuration and required min rate for a given vport
5224  * 1. req_rate must be greater than one percent of min_pf_rate.
5225  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5226  *    rates to get less than one percent of min_pf_rate.
5227  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5228  */
5229 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5230                                                  u16 vport_id, u32 req_rate,
5231                                                  u32 min_pf_rate)
5232 {
5233         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5234         int non_requested_count = 0, req_count = 0, i, num_vports;
5235
5236         num_vports = p_hwfn->qm_info.num_vports;
5237
5238 /* Accounting for the vports which are configured for WFQ explicitly */
5239
5240         for (i = 0; i < num_vports; i++) {
5241                 u32 tmp_speed;
5242
5243                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5244                         req_count++;
5245                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5246                         total_req_min_rate += tmp_speed;
5247                 }
5248         }
5249
5250         /* Include current vport data as well */
5251         req_count++;
5252         total_req_min_rate += req_rate;
5253         non_requested_count = num_vports - req_count;
5254
5255         /* validate possible error cases */
5256         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5257                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5258                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5259                            vport_id, req_rate, min_pf_rate);
5260                 return ECORE_INVAL;
5261         }
5262
5263         /* TBD - for number of vports greater than 100 */
5264         if (num_vports > ECORE_WFQ_UNIT) {
5265                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5266                            "Number of vports is greater than %d\n",
5267                            ECORE_WFQ_UNIT);
5268                 return ECORE_INVAL;
5269         }
5270
5271         if (total_req_min_rate > min_pf_rate) {
5272                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5273                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5274                            total_req_min_rate, min_pf_rate);
5275                 return ECORE_INVAL;
5276         }
5277
5278         /* Data left for non requested vports */
5279         total_left_rate = min_pf_rate - total_req_min_rate;
5280         left_rate_per_vp = total_left_rate / non_requested_count;
5281
5282         /* validate if non requested get < 1% of min bw */
5283         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5284                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5285                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5286                            left_rate_per_vp, min_pf_rate);
5287                 return ECORE_INVAL;
5288         }
5289
5290         /* now req_rate for given vport passes all scenarios.
5291          * assign final wfq rates to all vports.
5292          */
5293         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5294         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5295
5296         for (i = 0; i < num_vports; i++) {
5297                 if (p_hwfn->qm_info.wfq_data[i].configured)
5298                         continue;
5299
5300                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5301         }
5302
5303         return ECORE_SUCCESS;
5304 }
5305
5306 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5307                                        struct ecore_ptt *p_ptt,
5308                                        u16 vp_id, u32 rate)
5309 {
5310         struct ecore_mcp_link_state *p_link;
5311         int rc = ECORE_SUCCESS;
5312
5313         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5314
5315         if (!p_link->min_pf_rate) {
5316                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5317                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5318                 return rc;
5319         }
5320
5321         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5322
5323         if (rc == ECORE_SUCCESS)
5324                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5325                                                    p_link->min_pf_rate);
5326         else
5327                 DP_NOTICE(p_hwfn, false,
5328                           "Validation failed while configuring min rate\n");
5329
5330         return rc;
5331 }
5332
5333 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5334                                                    struct ecore_ptt *p_ptt,
5335                                                    u32 min_pf_rate)
5336 {
5337         bool use_wfq = false;
5338         int rc = ECORE_SUCCESS;
5339         u16 i;
5340
5341         /* Validate all pre configured vports for wfq */
5342         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5343                 u32 rate;
5344
5345                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5346                         continue;
5347
5348                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5349                 use_wfq = true;
5350
5351                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5352                 if (rc != ECORE_SUCCESS) {
5353                         DP_NOTICE(p_hwfn, false,
5354                                   "WFQ validation failed while configuring min rate\n");
5355                         break;
5356                 }
5357         }
5358
5359         if (rc == ECORE_SUCCESS && use_wfq)
5360                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5361         else
5362                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5363
5364         return rc;
5365 }
5366
5367 /* Main API for ecore clients to configure vport min rate.
5368  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5369  * rate - Speed in Mbps needs to be assigned to a given vport.
5370  */
5371 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5372 {
5373         int i, rc = ECORE_INVAL;
5374
5375         /* TBD - for multiple hardware functions - that is 100 gig */
5376         if (ECORE_IS_CMT(p_dev)) {
5377                 DP_NOTICE(p_dev, false,
5378                           "WFQ configuration is not supported for this device\n");
5379                 return rc;
5380         }
5381
5382         for_each_hwfn(p_dev, i) {
5383                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5384                 struct ecore_ptt *p_ptt;
5385
5386                 p_ptt = ecore_ptt_acquire(p_hwfn);
5387                 if (!p_ptt)
5388                         return ECORE_TIMEOUT;
5389
5390                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5391
5392                 if (rc != ECORE_SUCCESS) {
5393                         ecore_ptt_release(p_hwfn, p_ptt);
5394                         return rc;
5395                 }
5396
5397                 ecore_ptt_release(p_hwfn, p_ptt);
5398         }
5399
5400         return rc;
5401 }
5402
5403 /* API to configure WFQ from mcp link change */
5404 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5405                                            struct ecore_ptt *p_ptt,
5406                                            u32 min_pf_rate)
5407 {
5408         int i;
5409
5410         /* TBD - for multiple hardware functions - that is 100 gig */
5411         if (ECORE_IS_CMT(p_dev)) {
5412                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5413                            "WFQ configuration is not supported for this device\n");
5414                 return;
5415         }
5416
5417         for_each_hwfn(p_dev, i) {
5418                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5419
5420                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5421                                                         min_pf_rate);
5422         }
5423 }
5424
5425 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5426                                        struct ecore_ptt *p_ptt,
5427                                        struct ecore_mcp_link_state *p_link,
5428                                        u8 max_bw)
5429 {
5430         int rc = ECORE_SUCCESS;
5431
5432         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5433
5434         if (!p_link->line_speed && (max_bw != 100))
5435                 return rc;
5436
5437         p_link->speed = (p_link->line_speed * max_bw) / 100;
5438         p_hwfn->qm_info.pf_rl = p_link->speed;
5439
5440         /* Since the limiter also affects Tx-switched traffic, we don't want it
5441          * to limit such traffic in case there's no actual limit.
5442          * In that case, set limit to imaginary high boundary.
5443          */
5444         if (max_bw == 100)
5445                 p_hwfn->qm_info.pf_rl = 100000;
5446
5447         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5448                               p_hwfn->qm_info.pf_rl);
5449
5450         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5451                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5452                    p_link->speed);
5453
5454         return rc;
5455 }
5456
5457 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5458 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5459 {
5460         int i, rc = ECORE_INVAL;
5461
5462         if (max_bw < 1 || max_bw > 100) {
5463                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5464                 return rc;
5465         }
5466
5467         for_each_hwfn(p_dev, i) {
5468                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5469                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5470                 struct ecore_mcp_link_state *p_link;
5471                 struct ecore_ptt *p_ptt;
5472
5473                 p_link = &p_lead->mcp_info->link_output;
5474
5475                 p_ptt = ecore_ptt_acquire(p_hwfn);
5476                 if (!p_ptt)
5477                         return ECORE_TIMEOUT;
5478
5479                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5480                                                         p_link, max_bw);
5481
5482                 ecore_ptt_release(p_hwfn, p_ptt);
5483
5484                 if (rc != ECORE_SUCCESS)
5485                         break;
5486         }
5487
5488         return rc;
5489 }
5490
5491 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5492                                        struct ecore_ptt *p_ptt,
5493                                        struct ecore_mcp_link_state *p_link,
5494                                        u8 min_bw)
5495 {
5496         int rc = ECORE_SUCCESS;
5497
5498         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5499         p_hwfn->qm_info.pf_wfq = min_bw;
5500
5501         if (!p_link->line_speed)
5502                 return rc;
5503
5504         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5505
5506         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5507
5508         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5509                    "Configured MIN bandwidth to be %d Mb/sec\n",
5510                    p_link->min_pf_rate);
5511
5512         return rc;
5513 }
5514
5515 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5516 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5517 {
5518         int i, rc = ECORE_INVAL;
5519
5520         if (min_bw < 1 || min_bw > 100) {
5521                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5522                 return rc;
5523         }
5524
5525         for_each_hwfn(p_dev, i) {
5526                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5527                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5528                 struct ecore_mcp_link_state *p_link;
5529                 struct ecore_ptt *p_ptt;
5530
5531                 p_link = &p_lead->mcp_info->link_output;
5532
5533                 p_ptt = ecore_ptt_acquire(p_hwfn);
5534                 if (!p_ptt)
5535                         return ECORE_TIMEOUT;
5536
5537                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5538                                                         p_link, min_bw);
5539                 if (rc != ECORE_SUCCESS) {
5540                         ecore_ptt_release(p_hwfn, p_ptt);
5541                         return rc;
5542                 }
5543
5544                 if (p_link->min_pf_rate) {
5545                         u32 min_rate = p_link->min_pf_rate;
5546
5547                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5548                                                                      p_ptt,
5549                                                                      min_rate);
5550                 }
5551
5552                 ecore_ptt_release(p_hwfn, p_ptt);
5553         }
5554
5555         return rc;
5556 }
5557
5558 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5559 {
5560         struct ecore_mcp_link_state *p_link;
5561
5562         p_link = &p_hwfn->mcp_info->link_output;
5563
5564         if (p_link->min_pf_rate)
5565                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5566
5567         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5568                     sizeof(*p_hwfn->qm_info.wfq_data) *
5569                     p_hwfn->qm_info.num_vports);
5570 }
5571
5572 int ecore_device_num_engines(struct ecore_dev *p_dev)
5573 {
5574         return ECORE_IS_BB(p_dev) ? 2 : 1;
5575 }
5576
5577 int ecore_device_num_ports(struct ecore_dev *p_dev)
5578 {
5579         return p_dev->num_ports;
5580 }
5581
5582 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5583                           __le16 *fw_mid,
5584                           __le16 *fw_lsb,
5585                           u8 *mac)
5586 {
5587         ((u8 *)fw_msb)[0] = mac[1];
5588         ((u8 *)fw_msb)[1] = mac[0];
5589         ((u8 *)fw_mid)[0] = mac[3];
5590         ((u8 *)fw_mid)[1] = mac[2];
5591         ((u8 *)fw_lsb)[0] = mac[5];
5592         ((u8 *)fw_lsb)[1] = mac[4];
5593 }