drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33 #include "ecore_l2.h"
  34
  35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  36  * registers involved are not split and thus configuration is a race where
  37  * some of the PFs configuration might be lost.
  38  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  39  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  40  * there's more than a single compiled ecore component in system].
  41  */
  42 static osal_spinlock_t qm_lock;
  43 static bool qm_lock_init;
  44
  45 /* Configurable */
  46 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  47                                          * load the driver. The number was
  48                                          * arbitrarily set.
  49                                          */
  50
  51 /* Derived */
  52 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  53
  54 enum BAR_ID {
  55         BAR_ID_0,               /* used for GRC */
  56         BAR_ID_1                /* Used for doorbells */
  57 };
  58
  59 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  60 {
  61         u32 bar_reg = (bar_id == BAR_ID_0 ?
  62                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  63         u32 val;
  64
  65         if (IS_VF(p_hwfn->p_dev)) {
  66                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  67                  * read from actual register, but we're currently not using
  68                  * it for actual doorbelling.
  69                  */
  70                 return 1 << 17;
  71         }
  72
  73         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  74         if (val)
  75                 return 1 << (val + 15);
  76
  77         /* The above registers were updated in the past only in CMT mode. Since
  78          * they were found to be useful MFW started updating them from 8.7.7.0.
  79          * In older MFW versions they are set to 0 which means disabled.
  80          */
  81         if (p_hwfn->p_dev->num_hwfns > 1) {
  82                 DP_NOTICE(p_hwfn, false,
  83                           "BAR size not configured. Assuming BAR size of 256kB"
  84                           " for GRC and 512kB for DB\n");
  85                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  86         } else {
  87                 DP_NOTICE(p_hwfn, false,
  88                           "BAR size not configured. Assuming BAR size of 512kB"
  89                           " for GRC and 512kB for DB\n");
  90                 val = 512 * 1024;
  91         }
  92
  93         return val;
  94 }
  95
  96 void ecore_init_dp(struct ecore_dev *p_dev,
  97                    u32 dp_module, u8 dp_level, void *dp_ctx)
  98 {
  99         u32 i;
 100
 101         p_dev->dp_level = dp_level;
 102         p_dev->dp_module = dp_module;
 103         p_dev->dp_ctx = dp_ctx;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109                 p_hwfn->dp_ctx = dp_ctx;
 110         }
 111 }
 112
 113 void ecore_init_struct(struct ecore_dev *p_dev)
 114 {
 115         u8 i;
 116
 117         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 118                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 119
 120                 p_hwfn->p_dev = p_dev;
 121                 p_hwfn->my_id = i;
 122                 p_hwfn->b_active = false;
 123
 124                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 125                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 126         }
 127
 128         /* hwfn 0 is always active */
 129         p_dev->hwfns[0].b_active = true;
 130
 131         /* set the default cache alignment to 128 (may be overridden later) */
 132         p_dev->cache_shift = 7;
 133 }
 134
 135 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 136 {
 137         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 138
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 142         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 143 }
 144
 145 void ecore_resc_free(struct ecore_dev *p_dev)
 146 {
 147         int i;
 148
 149         if (IS_VF(p_dev)) {
 150                 for_each_hwfn(p_dev, i)
 151                         ecore_l2_free(&p_dev->hwfns[i]);
 152                 return;
 153         }
 154
 155         OSAL_FREE(p_dev, p_dev->fw_data);
 156
 157         OSAL_FREE(p_dev, p_dev->reset_stats);
 158
 159         for_each_hwfn(p_dev, i) {
 160                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 161
 162                 ecore_cxt_mngr_free(p_hwfn);
 163                 ecore_qm_info_free(p_hwfn);
 164                 ecore_spq_free(p_hwfn);
 165                 ecore_eq_free(p_hwfn);
 166                 ecore_consq_free(p_hwfn);
 167                 ecore_int_free(p_hwfn);
 168                 ecore_iov_free(p_hwfn);
 169                 ecore_l2_free(p_hwfn);
 170                 ecore_dmae_info_free(p_hwfn);
 171                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 172                 /* @@@TBD Flush work-queue ? */
 173         }
 174 }
 175
 176 /******************** QM initialization *******************/
 177
 178 /* bitmaps for indicating active traffic classes.
 179  * Special case for Arrowhead 4 port
 180  */
 181 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 182 #define ACTIVE_TCS_BMAP 0x9f
 183 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 184 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 185
 186 /* determines the physical queue flags for a given PF. */
 187 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 188 {
 189         u32 flags;
 190
 191         /* common flags */
 192         flags = PQ_FLAGS_LB;
 193
 194         /* feature flags */
 195         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 196                 flags |= PQ_FLAGS_VFS;
 197
 198         /* protocol flags */
 199         switch (p_hwfn->hw_info.personality) {
 200         case ECORE_PCI_ETH:
 201                 flags |= PQ_FLAGS_MCOS;
 202                 break;
 203         case ECORE_PCI_FCOE:
 204                 flags |= PQ_FLAGS_OFLD;
 205                 break;
 206         case ECORE_PCI_ISCSI:
 207                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 208                 break;
 209         case ECORE_PCI_ETH_ROCE:
 210                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 211                 break;
 212         case ECORE_PCI_ETH_IWARP:
 213                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 214                          PQ_FLAGS_OFLD;
 215                 break;
 216         default:
 217                 DP_ERR(p_hwfn, "unknown personality %d\n",
 218                        p_hwfn->hw_info.personality);
 219                 return 0;
 220         }
 221         return flags;
 222 }
 223
 224 /* Getters for resource amounts necessary for qm initialization */
 225 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 226 {
 227         return p_hwfn->hw_info.num_hw_tc;
 228 }
 229
 230 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 231 {
 232         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 233                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 234 }
 235
 236 #define NUM_DEFAULT_RLS 1
 237
 238 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 239 {
 240         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 241
 242         /* @DPDK */
 243         /* num RLs can't exceed resource amount of rls or vports or the
 244          * dcqcn qps
 245          */
 246         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 247                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 248
 249         /* make sure after we reserve the default and VF rls we'll have
 250          * something left
 251          */
 252         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 253                 DP_NOTICE(p_hwfn, false,
 254                           "no rate limiters left for PF rate limiting"
 255                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 256                 return 0;
 257         }
 258
 259         /* subtract rls necessary for VFs and one default one for the PF */
 260         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 261
 262         return num_pf_rls;
 263 }
 264
 265 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 266 {
 267         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 268
 269         /* all pqs share the same vport (hence the 1 below), except for vfs
 270          * and pf_rl pqs
 271          */
 272         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 273                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 274                (!!(PQ_FLAGS_VFS & pq_flags)) *
 275                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 276 }
 277
 278 /* calc amount of PQs according to the requested flags */
 279 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 280 {
 281         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 282
 283         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 284                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 285                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 286                 ecore_init_qm_get_num_tcs(p_hwfn) +
 287                (!!(PQ_FLAGS_LB & pq_flags)) +
 288                (!!(PQ_FLAGS_OOO & pq_flags)) +
 289                (!!(PQ_FLAGS_ACK & pq_flags)) +
 290                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 291                (!!(PQ_FLAGS_VFS & pq_flags)) *
 292                 ecore_init_qm_get_num_vfs(p_hwfn);
 293 }
 294
 295 /* initialize the top level QM params */
 296 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 297 {
 298         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 299         bool four_port;
 300
 301         /* pq and vport bases for this PF */
 302         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 303         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 304
 305         /* rate limiting and weighted fair queueing are always enabled */
 306         qm_info->vport_rl_en = 1;
 307         qm_info->vport_wfq_en = 1;
 308
 309         /* TC config is different for AH 4 port */
 310         four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
 311
 312         /* in AH 4 port we have fewer TCs per port */
 313         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 314                                                      NUM_OF_PHYS_TCS;
 315
 316         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 317          * 4 otherwise
 318          */
 319         if (!qm_info->ooo_tc)
 320                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 321                                               DCBX_TCP_OOO_TC;
 322 }
 323
 324 /* initialize qm vport params */
 325 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 326 {
 327         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 328         u8 i;
 329
 330         /* all vports participate in weighted fair queueing */
 331         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 332                 qm_info->qm_vport_params[i].vport_wfq = 1;
 333 }
 334
 335 /* initialize qm port params */
 336 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 337 {
 338         /* Initialize qm port parameters */
 339         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
 340
 341         /* indicate how ooo and high pri traffic is dealt with */
 342         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 343                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 344
 345         for (i = 0; i < num_ports; i++) {
 346                 struct init_qm_port_params *p_qm_port =
 347                         &p_hwfn->qm_info.qm_port_params[i];
 348
 349                 p_qm_port->active = 1;
 350                 p_qm_port->active_phys_tcs = active_phys_tcs;
 351                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 352                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 353         }
 354 }
 355
 356 /* Reset the params which must be reset for qm init. QM init may be called as
 357  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 358  * params may be affected by the init but would simply recalculate to the same
 359  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 360  * affected as these amounts stay the same.
 361  */
 362 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 363 {
 364         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 365
 366         qm_info->num_pqs = 0;
 367         qm_info->num_vports = 0;
 368         qm_info->num_pf_rls = 0;
 369         qm_info->num_vf_pqs = 0;
 370         qm_info->first_vf_pq = 0;
 371         qm_info->first_mcos_pq = 0;
 372         qm_info->first_rl_pq = 0;
 373 }
 374
 375 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 376 {
 377         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 378
 379         qm_info->num_vports++;
 380
 381         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 382                 DP_ERR(p_hwfn,
 383                        "vport overflow! qm_info->num_vports %d,"
 384                        " qm_init_get_num_vports() %d\n",
 385                        qm_info->num_vports,
 386                        ecore_init_qm_get_num_vports(p_hwfn));
 387 }
 388
 389 /* initialize a single pq and manage qm_info resources accounting.
 390  * The pq_init_flags param determines whether the PQ is rate limited
 391  * (for VF or PF)
 392  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 393  * shared)
 394  */
 395
 396 /* flags for pq init */
 397 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 398 #define PQ_INIT_PF_RL           (1 << 1)
 399 #define PQ_INIT_VF_RL           (1 << 2)
 400
 401 /* defines for pq init */
 402 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 403 #define PQ_INIT_DEFAULT_TC              0
 404 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 405
 406 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 407                              struct ecore_qm_info *qm_info,
 408                              u8 tc, u32 pq_init_flags)
 409 {
 410         u16 pq_idx = qm_info->num_pqs, max_pq =
 411                                         ecore_init_qm_get_num_pqs(p_hwfn);
 412
 413         if (pq_idx > max_pq)
 414                 DP_ERR(p_hwfn,
 415                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 416
 417         /* init pq params */
 418         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 419                                                  qm_info->num_vports;
 420         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 421         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 422         qm_info->qm_pq_params[pq_idx].rl_valid =
 423                 (pq_init_flags & PQ_INIT_PF_RL ||
 424                  pq_init_flags & PQ_INIT_VF_RL);
 425
 426         /* qm params accounting */
 427         qm_info->num_pqs++;
 428         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 429                 qm_info->num_vports++;
 430
 431         if (pq_init_flags & PQ_INIT_PF_RL)
 432                 qm_info->num_pf_rls++;
 433
 434         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 435                 DP_ERR(p_hwfn,
 436                        "vport overflow! qm_info->num_vports %d,"
 437                        " qm_init_get_num_vports() %d\n",
 438                        qm_info->num_vports,
 439                        ecore_init_qm_get_num_vports(p_hwfn));
 440
 441         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 442                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 443                        " qm_init_get_num_pf_rls() %d\n",
 444                        qm_info->num_pf_rls,
 445                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 446 }
 447
 448 /* get pq index according to PQ_FLAGS */
 449 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 450                                              u32 pq_flags)
 451 {
 452         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 453
 454         /* Can't have multiple flags set here */
 455         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 456                                 sizeof(pq_flags)) > 1)
 457                 goto err;
 458
 459         switch (pq_flags) {
 460         case PQ_FLAGS_RLS:
 461                 return &qm_info->first_rl_pq;
 462         case PQ_FLAGS_MCOS:
 463                 return &qm_info->first_mcos_pq;
 464         case PQ_FLAGS_LB:
 465                 return &qm_info->pure_lb_pq;
 466         case PQ_FLAGS_OOO:
 467                 return &qm_info->ooo_pq;
 468         case PQ_FLAGS_ACK:
 469                 return &qm_info->pure_ack_pq;
 470         case PQ_FLAGS_OFLD:
 471                 return &qm_info->offload_pq;
 472         case PQ_FLAGS_VFS:
 473                 return &qm_info->first_vf_pq;
 474         default:
 475                 goto err;
 476         }
 477
 478 err:
 479         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 480         return OSAL_NULL;
 481 }
 482
 483 /* save pq index in qm info */
 484 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 485                                   u32 pq_flags, u16 pq_val)
 486 {
 487         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 488
 489         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 490 }
 491
 492 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 493 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 494 {
 495         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 496
 497         return *base_pq_idx + CM_TX_PQ_BASE;
 498 }
 499
 500 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 501 {
 502         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 503
 504         if (tc > max_tc)
 505                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 506
 507         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 508 }
 509
 510 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 511 {
 512         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 513
 514         if (vf > max_vf)
 515                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 516
 517         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 518 }
 519
 520 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 521 {
 522         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 523
 524         if (rl > max_rl)
 525                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 526
 527         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 528 }
 529
 530 /* Functions for creating specific types of pqs */
 531 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 532 {
 533         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 534
 535         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 536                 return;
 537
 538         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 539         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 540 }
 541
 542 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 543 {
 544         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 545
 546         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 547                 return;
 548
 549         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 550         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 551 }
 552
 553 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 554 {
 555         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 556
 557         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 558                 return;
 559
 560         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 561         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 562 }
 563
 564 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 565 {
 566         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 567
 568         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 569                 return;
 570
 571         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 572         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 573 }
 574
 575 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 576 {
 577         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 578         u8 tc_idx;
 579
 580         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 581                 return;
 582
 583         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 584         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 585                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 586 }
 587
 588 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 589 {
 590         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 591         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 592
 593         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 594                 return;
 595
 596         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 597
 598         qm_info->num_vf_pqs = num_vfs;
 599         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 600                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 601                                  PQ_INIT_VF_RL);
 602 }
 603
 604 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 605 {
 606         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 607         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 608
 609         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 610                 return;
 611
 612         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 613         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 614                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 615                                  PQ_INIT_PF_RL);
 616 }
 617
 618 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 619 {
 620         /* rate limited pqs, must come first (FW assumption) */
 621         ecore_init_qm_rl_pqs(p_hwfn);
 622
 623         /* pqs for multi cos */
 624         ecore_init_qm_mcos_pqs(p_hwfn);
 625
 626         /* pure loopback pq */
 627         ecore_init_qm_lb_pq(p_hwfn);
 628
 629         /* out of order pq */
 630         ecore_init_qm_ooo_pq(p_hwfn);
 631
 632         /* pure ack pq */
 633         ecore_init_qm_pure_ack_pq(p_hwfn);
 634
 635         /* pq for offloaded protocol */
 636         ecore_init_qm_offload_pq(p_hwfn);
 637
 638         /* done sharing vports */
 639         ecore_init_qm_advance_vport(p_hwfn);
 640
 641         /* pqs for vfs */
 642         ecore_init_qm_vf_pqs(p_hwfn);
 643 }
 644
 645 /* compare values of getters against resources amounts */
 646 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 647 {
 648         if (ecore_init_qm_get_num_vports(p_hwfn) >
 649             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 650                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 651                 return ECORE_INVAL;
 652         }
 653
 654         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 655                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 656                 return ECORE_INVAL;
 657         }
 658
 659         return ECORE_SUCCESS;
 660 }
 661
 662 /*
 663  * Function for verbose printing of the qm initialization results
 664  */
 665 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 666 {
 667         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 668         struct init_qm_vport_params *vport;
 669         struct init_qm_port_params *port;
 670         struct init_qm_pq_params *pq;
 671         int i, tc;
 672
 673         /* top level params */
 674         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 675                    "qm init top level params: start_pq %d, start_vport %d,"
 676                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 677                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 678                    qm_info->offload_pq, qm_info->pure_ack_pq);
 679         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 680                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 681                    " num_vports %d, max_phys_tcs_per_port %d\n",
 682                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 683                    qm_info->num_vf_pqs, qm_info->num_vports,
 684                    qm_info->max_phys_tcs_per_port);
 685         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 686                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 687                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 688                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 689                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 690                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 691
 692         /* port table */
 693         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
 694                 port = &qm_info->qm_port_params[i];
 695                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 696                            "port idx %d, active %d, active_phys_tcs %d,"
 697                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
 698                            " reserved %d\n",
 699                            i, port->active, port->active_phys_tcs,
 700                            port->num_pbf_cmd_lines, port->num_btb_blocks,
 701                            port->reserved);
 702         }
 703
 704         /* vport table */
 705         for (i = 0; i < qm_info->num_vports; i++) {
 706                 vport = &qm_info->qm_vport_params[i];
 707                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 708                            "vport idx %d, vport_rl %d, wfq %d,"
 709                            " first_tx_pq_id [ ",
 710                            qm_info->start_vport + i, vport->vport_rl,
 711                            vport->vport_wfq);
 712                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 713                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
 714                                    vport->first_tx_pq_id[tc]);
 715                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
 716         }
 717
 718         /* pq table */
 719         for (i = 0; i < qm_info->num_pqs; i++) {
 720                 pq = &qm_info->qm_pq_params[i];
 721                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 722                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
 723                            " rl_valid %d\n",
 724                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
 725                            pq->wrr_group, pq->rl_valid);
 726         }
 727 }
 728
 729 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
 730 {
 731         /* reset params required for init run */
 732         ecore_init_qm_reset_params(p_hwfn);
 733
 734         /* init QM top level params */
 735         ecore_init_qm_params(p_hwfn);
 736
 737         /* init QM port params */
 738         ecore_init_qm_port_params(p_hwfn);
 739
 740         /* init QM vport params */
 741         ecore_init_qm_vport_params(p_hwfn);
 742
 743         /* init QM physical queue params */
 744         ecore_init_qm_pq_params(p_hwfn);
 745
 746         /* display all that init */
 747         ecore_dp_init_qm_params(p_hwfn);
 748 }
 749
 750 /* This function reconfigures the QM pf on the fly.
 751  * For this purpose we:
 752  * 1. reconfigure the QM database
 753  * 2. set new values to runtime array
 754  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 755  * 4. activate init tool in QM_PF stage
 756  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 757  */
 758 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 759                                      struct ecore_ptt *p_ptt)
 760 {
 761         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 762         bool b_rc;
 763         enum _ecore_status_t rc;
 764
 765         /* initialize ecore's qm data structure */
 766         ecore_init_qm_info(p_hwfn);
 767
 768         /* stop PF's qm queues */
 769         OSAL_SPIN_LOCK(&qm_lock);
 770         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 771                                       qm_info->start_pq, qm_info->num_pqs);
 772         OSAL_SPIN_UNLOCK(&qm_lock);
 773         if (!b_rc)
 774                 return ECORE_INVAL;
 775
 776         /* clear the QM_PF runtime phase leftovers from previous init */
 777         ecore_init_clear_rt_data(p_hwfn);
 778
 779         /* prepare QM portion of runtime array */
 780         ecore_qm_init_pf(p_hwfn);
 781
 782         /* activate init tool on runtime array */
 783         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 784                             p_hwfn->hw_info.hw_mode);
 785         if (rc != ECORE_SUCCESS)
 786                 return rc;
 787
 788         /* start PF's qm queues */
 789         OSAL_SPIN_LOCK(&qm_lock);
 790         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 791                                       qm_info->start_pq, qm_info->num_pqs);
 792         OSAL_SPIN_UNLOCK(&qm_lock);
 793         if (!b_rc)
 794                 return ECORE_INVAL;
 795
 796         return ECORE_SUCCESS;
 797 }
 798
 799 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
 800 {
 801         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 802         enum _ecore_status_t rc;
 803
 804         rc = ecore_init_qm_sanity(p_hwfn);
 805         if (rc != ECORE_SUCCESS)
 806                 goto alloc_err;
 807
 808         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 809                                             sizeof(struct init_qm_pq_params) *
 810                                             ecore_init_qm_get_num_pqs(p_hwfn));
 811         if (!qm_info->qm_pq_params)
 812                 goto alloc_err;
 813
 814         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 815                                        sizeof(struct init_qm_vport_params) *
 816                                        ecore_init_qm_get_num_vports(p_hwfn));
 817         if (!qm_info->qm_vport_params)
 818                 goto alloc_err;
 819
 820         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 821                                       sizeof(struct init_qm_port_params) *
 822                                       p_hwfn->p_dev->num_ports_in_engines);
 823         if (!qm_info->qm_port_params)
 824                 goto alloc_err;
 825
 826         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 827                                         sizeof(struct ecore_wfq_data) *
 828                                         ecore_init_qm_get_num_vports(p_hwfn));
 829         if (!qm_info->wfq_data)
 830                 goto alloc_err;
 831
 832         return ECORE_SUCCESS;
 833
 834 alloc_err:
 835         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 836         ecore_qm_info_free(p_hwfn);
 837         return ECORE_NOMEM;
 838 }
 839 /******************** End QM initialization ***************/
 840
 841 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 842 {
 843         enum _ecore_status_t rc = ECORE_SUCCESS;
 844         int i;
 845
 846         if (IS_VF(p_dev)) {
 847                 for_each_hwfn(p_dev, i) {
 848                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
 849                         if (rc != ECORE_SUCCESS)
 850                                 return rc;
 851                 }
 852                 return rc;
 853         }
 854
 855         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 856                                      sizeof(*p_dev->fw_data));
 857         if (!p_dev->fw_data)
 858                 return ECORE_NOMEM;
 859
 860         for_each_hwfn(p_dev, i) {
 861                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 862                 u32 n_eqes, num_cons;
 863
 864                 /* First allocate the context manager structure */
 865                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 866                 if (rc)
 867                         goto alloc_err;
 868
 869                 /* Set the HW cid/tid numbers (in the contest manager)
 870                  * Must be done prior to any further computations.
 871                  */
 872                 rc = ecore_cxt_set_pf_params(p_hwfn);
 873                 if (rc)
 874                         goto alloc_err;
 875
 876                 rc = ecore_alloc_qm_data(p_hwfn);
 877                 if (rc)
 878                         goto alloc_err;
 879
 880                 /* init qm info */
 881                 ecore_init_qm_info(p_hwfn);
 882
 883                 /* Compute the ILT client partition */
 884                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 885                 if (rc)
 886                         goto alloc_err;
 887
 888                 /* CID map / ILT shadow table / T2
 889                  * The talbes sizes are determined by the computations above
 890                  */
 891                 rc = ecore_cxt_tables_alloc(p_hwfn);
 892                 if (rc)
 893                         goto alloc_err;
 894
 895                 /* SPQ, must follow ILT because initializes SPQ context */
 896                 rc = ecore_spq_alloc(p_hwfn);
 897                 if (rc)
 898                         goto alloc_err;
 899
 900                 /* SP status block allocation */
 901                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 902                                                            RESERVED_PTT_DPC);
 903
 904                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 905                 if (rc)
 906                         goto alloc_err;
 907
 908                 rc = ecore_iov_alloc(p_hwfn);
 909                 if (rc)
 910                         goto alloc_err;
 911
 912                 /* EQ */
 913                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 914                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
 915                         /* Calculate the EQ size
 916                          * ---------------------
 917                          * Each ICID may generate up to one event at a time i.e.
 918                          * the event must be handled/cleared before a new one
 919                          * can be generated. We calculate the sum of events per
 920                          * protocol and create an EQ deep enough to handle the
 921                          * worst case:
 922                          * - Core - according to SPQ.
 923                          * - RoCE - per QP there are a couple of ICIDs, one
 924                          *        responder and one requester, each can
 925                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
 926                          *        Each CQ can generate an EQE. There are 2 CQs
 927                          *        per QP => n_eqes_cq = 2 * n_qp.
 928                          *        Hence the RoCE total is 4 * n_qp or
 929                          *        2 * num_cons.
 930                          * - ENet - There can be up to two events per VF. One
 931                          *        for VF-PF channel and another for VF FLR
 932                          *        initial cleanup. The number of VFs is
 933                          *        bounded by MAX_NUM_VFS_BB, and is much
 934                          *        smaller than RoCE's so we avoid exact
 935                          *        calculation.
 936                          */
 937                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 938                                 num_cons =
 939                                     ecore_cxt_get_proto_cid_count(
 940                                                 p_hwfn,
 941                                                 PROTOCOLID_ROCE,
 942                                                 OSAL_NULL);
 943                                 num_cons *= 2;
 944                         } else {
 945                                 num_cons = ecore_cxt_get_proto_cid_count(
 946                                                 p_hwfn,
 947                                                 PROTOCOLID_IWARP,
 948                                                 OSAL_NULL);
 949                         }
 950                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 951                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 952                         num_cons =
 953                             ecore_cxt_get_proto_cid_count(p_hwfn,
 954                                                           PROTOCOLID_ISCSI,
 955                                                           OSAL_NULL);
 956                         n_eqes += 2 * num_cons;
 957                 }
 958
 959                 if (n_eqes > 0xFFFF) {
 960                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 961                                        "The maximum of a u16 chain is 0x%x\n",
 962                                n_eqes, 0xFFFF);
 963                         goto alloc_no_mem;
 964                 }
 965
 966                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 967                 if (rc)
 968                         goto alloc_err;
 969
 970                 rc = ecore_consq_alloc(p_hwfn);
 971                 if (rc)
 972                         goto alloc_err;
 973
 974                 rc = ecore_l2_alloc(p_hwfn);
 975                 if (rc != ECORE_SUCCESS)
 976                         goto alloc_err;
 977
 978                 /* DMA info initialization */
 979                 rc = ecore_dmae_info_alloc(p_hwfn);
 980                 if (rc) {
 981                         DP_NOTICE(p_hwfn, true,
 982                                   "Failed to allocate memory for dmae_info"
 983                                   " structure\n");
 984                         goto alloc_err;
 985                 }
 986
 987                 /* DCBX initialization */
 988                 rc = ecore_dcbx_info_alloc(p_hwfn);
 989                 if (rc) {
 990                         DP_NOTICE(p_hwfn, true,
 991                                   "Failed to allocate memory for dcbx structure\n");
 992                         goto alloc_err;
 993                 }
 994         }
 995
 996         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 997                                          sizeof(*p_dev->reset_stats));
 998         if (!p_dev->reset_stats) {
 999                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1000                 goto alloc_no_mem;
1001         }
1002
1003         return ECORE_SUCCESS;
1004
1005 alloc_no_mem:
1006         rc = ECORE_NOMEM;
1007 alloc_err:
1008         ecore_resc_free(p_dev);
1009         return rc;
1010 }
1011
1012 void ecore_resc_setup(struct ecore_dev *p_dev)
1013 {
1014         int i;
1015
1016         if (IS_VF(p_dev)) {
1017                 for_each_hwfn(p_dev, i)
1018                         ecore_l2_setup(&p_dev->hwfns[i]);
1019                 return;
1020         }
1021
1022         for_each_hwfn(p_dev, i) {
1023                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1024
1025                 ecore_cxt_mngr_setup(p_hwfn);
1026                 ecore_spq_setup(p_hwfn);
1027                 ecore_eq_setup(p_hwfn);
1028                 ecore_consq_setup(p_hwfn);
1029
1030                 /* Read shadow of current MFW mailbox */
1031                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1032                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1033                             p_hwfn->mcp_info->mfw_mb_cur,
1034                             p_hwfn->mcp_info->mfw_mb_length);
1035
1036                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1037
1038                 ecore_l2_setup(p_hwfn);
1039                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1040         }
1041 }
1042
1043 #define FINAL_CLEANUP_POLL_CNT  (100)
1044 #define FINAL_CLEANUP_POLL_TIME (10)
1045 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1046                                          struct ecore_ptt *p_ptt,
1047                                          u16 id, bool is_vf)
1048 {
1049         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1050         enum _ecore_status_t rc = ECORE_TIMEOUT;
1051
1052 #ifndef ASIC_ONLY
1053         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1054             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1055                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1056                 return ECORE_SUCCESS;
1057         }
1058 #endif
1059
1060         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1061             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1062
1063         if (is_vf)
1064                 id += 0x10;
1065
1066         command |= X_FINAL_CLEANUP_AGG_INT <<
1067             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1068         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1069         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1070         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1071
1072 /* Make sure notification is not set before initiating final cleanup */
1073
1074         if (REG_RD(p_hwfn, addr)) {
1075                 DP_NOTICE(p_hwfn, false,
1076                           "Unexpected; Found final cleanup notification");
1077                 DP_NOTICE(p_hwfn, false,
1078                           " before initiating final cleanup\n");
1079                 REG_WR(p_hwfn, addr, 0);
1080         }
1081
1082         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1083                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1084                    id, command);
1085
1086         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1087
1088         /* Poll until completion */
1089         while (!REG_RD(p_hwfn, addr) && count--)
1090                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1091
1092         if (REG_RD(p_hwfn, addr))
1093                 rc = ECORE_SUCCESS;
1094         else
1095                 DP_NOTICE(p_hwfn, true,
1096                           "Failed to receive FW final cleanup notification\n");
1097
1098         /* Cleanup afterwards */
1099         REG_WR(p_hwfn, addr, 0);
1100
1101         return rc;
1102 }
1103
1104 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1105 {
1106         int hw_mode = 0;
1107
1108         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1109                 hw_mode |= 1 << MODE_BB;
1110         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1111                 hw_mode |= 1 << MODE_K2;
1112         } else {
1113                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1114                           p_hwfn->p_dev->type);
1115                 return ECORE_INVAL;
1116         }
1117
1118         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1119         switch (p_hwfn->p_dev->num_ports_in_engines) {
1120         case 1:
1121                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1122                 break;
1123         case 2:
1124                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1125                 break;
1126         case 4:
1127                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1128                 break;
1129         default:
1130                 DP_NOTICE(p_hwfn, true,
1131                           "num_ports_in_engine = %d not supported\n",
1132                           p_hwfn->p_dev->num_ports_in_engines);
1133                 return ECORE_INVAL;
1134         }
1135
1136         switch (p_hwfn->p_dev->mf_mode) {
1137         case ECORE_MF_DEFAULT:
1138         case ECORE_MF_NPAR:
1139                 hw_mode |= 1 << MODE_MF_SI;
1140                 break;
1141         case ECORE_MF_OVLAN:
1142                 hw_mode |= 1 << MODE_MF_SD;
1143                 break;
1144         default:
1145                 DP_NOTICE(p_hwfn, true,
1146                           "Unsupported MF mode, init as DEFAULT\n");
1147                 hw_mode |= 1 << MODE_MF_SI;
1148         }
1149
1150 #ifndef ASIC_ONLY
1151         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1152                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1153                         hw_mode |= 1 << MODE_FPGA;
1154                 } else {
1155                         if (p_hwfn->p_dev->b_is_emul_full)
1156                                 hw_mode |= 1 << MODE_EMUL_FULL;
1157                         else
1158                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1159                 }
1160         } else
1161 #endif
1162                 hw_mode |= 1 << MODE_ASIC;
1163
1164         if (p_hwfn->p_dev->num_hwfns > 1)
1165                 hw_mode |= 1 << MODE_100G;
1166
1167         p_hwfn->hw_info.hw_mode = hw_mode;
1168
1169         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1170                    "Configuring function for hw_mode: 0x%08x\n",
1171                    p_hwfn->hw_info.hw_mode);
1172
1173         return ECORE_SUCCESS;
1174 }
1175
1176 #ifndef ASIC_ONLY
1177 /* MFW-replacement initializations for non-ASIC */
1178 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1179                                                struct ecore_ptt *p_ptt)
1180 {
1181         struct ecore_dev *p_dev = p_hwfn->p_dev;
1182         u32 pl_hv = 1;
1183         int i;
1184
1185         if (CHIP_REV_IS_EMUL(p_dev)) {
1186                 if (ECORE_IS_AH(p_dev))
1187                         pl_hv |= 0x600;
1188         }
1189
1190         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1191
1192         if (CHIP_REV_IS_EMUL(p_dev) &&
1193             (ECORE_IS_AH(p_dev)))
1194                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1195                          0x3ffffff);
1196
1197         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1198         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1199         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1200                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1201
1202         if (CHIP_REV_IS_EMUL(p_dev)) {
1203                 if (ECORE_IS_AH(p_dev)) {
1204                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1205                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1206                                  (p_dev->num_ports_in_engines >> 1));
1207
1208                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1209                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
1210                 }
1211         }
1212
1213         /* Poll on RBC */
1214         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1215         for (i = 0; i < 100; i++) {
1216                 OSAL_UDELAY(50);
1217                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1218                         break;
1219         }
1220         if (i == 100)
1221                 DP_NOTICE(p_hwfn, true,
1222                           "RBC done failed to complete in PSWRQ2\n");
1223
1224         return ECORE_SUCCESS;
1225 }
1226 #endif
1227
1228 /* Init run time data for all PFs and their VFs on an engine.
1229  * TBD - for VFs - Once we have parent PF info for each VF in
1230  * shmem available as CAU requires knowledge of parent PF for each VF.
1231  */
1232 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1233 {
1234         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1235         int i, sb_id;
1236
1237         for_each_hwfn(p_dev, i) {
1238                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1239                 struct ecore_igu_info *p_igu_info;
1240                 struct ecore_igu_block *p_block;
1241                 struct cau_sb_entry sb_entry;
1242
1243                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1244
1245                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1246                      sb_id++) {
1247                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1248
1249                         if (!p_block->is_pf)
1250                                 continue;
1251
1252                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1253                                                 p_block->function_id, 0, 0);
1254                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1255                 }
1256         }
1257 }
1258
1259 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1260                                                  struct ecore_ptt *p_ptt,
1261                                                  int hw_mode)
1262 {
1263         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1264         struct ecore_dev *p_dev = p_hwfn->p_dev;
1265         u8 vf_id, max_num_vfs;
1266         u16 num_pfs, pf_id;
1267         u32 concrete_fid;
1268         enum _ecore_status_t rc = ECORE_SUCCESS;
1269
1270         ecore_init_cau_rt_data(p_dev);
1271
1272         /* Program GTT windows */
1273         ecore_gtt_init(p_hwfn);
1274
1275 #ifndef ASIC_ONLY
1276         if (CHIP_REV_IS_EMUL(p_dev)) {
1277                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1278                 if (rc != ECORE_SUCCESS)
1279                         return rc;
1280         }
1281 #endif
1282
1283         if (p_hwfn->mcp_info) {
1284                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1285                         qm_info->pf_rl_en = 1;
1286                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1287                         qm_info->pf_wfq_en = 1;
1288         }
1289
1290         ecore_qm_common_rt_init(p_hwfn,
1291                                 p_dev->num_ports_in_engines,
1292                                 qm_info->max_phys_tcs_per_port,
1293                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1294                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1295                                 qm_info->qm_port_params);
1296
1297         ecore_cxt_hw_init_common(p_hwfn);
1298
1299         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1300         if (rc != ECORE_SUCCESS)
1301                 return rc;
1302
1303         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1304          * need to decide with which value, maybe runtime
1305          */
1306         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1307         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1308
1309         if (ECORE_IS_BB(p_dev)) {
1310                 /* Workaround clears ROCE search for all functions to prevent
1311                  * involving non initialized function in processing ROCE packet.
1312                  */
1313                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1314                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1315                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1316                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1317                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1318                 }
1319                 /* pretend to original PF */
1320                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1321         }
1322
1323         /* Workaround for avoiding CCFC execution error when getting packets
1324          * with CRC errors, and allowing instead the invoking of the FW error
1325          * handler.
1326          * This is not done inside the init tool since it currently can't
1327          * perform a pretending to VFs.
1328          */
1329         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1330         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1331                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1332                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1333                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1334                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1335                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1336                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1337         }
1338         /* pretend to original PF */
1339         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1340
1341         return rc;
1342 }
1343
1344 #ifndef ASIC_ONLY
1345 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1346 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1347
1348 #define PMEG_IF_BYTE_COUNT      8
1349
1350 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1351                              struct ecore_ptt *p_ptt,
1352                              u32 addr, u64 data, u8 reg_type, u8 port)
1353 {
1354         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1355                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1356                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1357                    (8 << PMEG_IF_BYTE_COUNT),
1358                    (reg_type << 25) | (addr << 8) | port,
1359                    (u32)((data >> 32) & 0xffffffff),
1360                    (u32)(data & 0xffffffff));
1361
1362         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1363                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1364                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1365         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1366                  (reg_type << 25) | (addr << 8) | port);
1367         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1368         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1369                  (data >> 32) & 0xffffffff);
1370 }
1371
1372 #define XLPORT_MODE_REG (0x20a)
1373 #define XLPORT_MAC_CONTROL (0x210)
1374 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1375 #define XLPORT_ENABLE_REG (0x20b)
1376
1377 #define XLMAC_CTRL (0x600)
1378 #define XLMAC_MODE (0x601)
1379 #define XLMAC_RX_MAX_SIZE (0x608)
1380 #define XLMAC_TX_CTRL (0x604)
1381 #define XLMAC_PAUSE_CTRL (0x60d)
1382 #define XLMAC_PFC_CTRL (0x60e)
1383
1384 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1385                                     struct ecore_ptt *p_ptt)
1386 {
1387         u8 loopback = 0, port = p_hwfn->port_id * 2;
1388
1389         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1390
1391         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1392         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1393                          port);
1394         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1395         /* XLMAC: SOFT RESET */
1396         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1397         /* XLMAC: Port Speed >= 10Gbps */
1398         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1399         /* XLMAC: Max Size */
1400         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1401         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1402                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1403                          0, port);
1404         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1405         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1406                          0x30ffffc000ULL, 0, port);
1407         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1408                          port); /* XLMAC: TX_EN, RX_EN */
1409         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1410         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1411                          0x1003 | (loopback << 2), 0, port);
1412         /* Enabled Parallel PFC interface */
1413         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1414
1415         /* XLPORT port enable */
1416         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1417 }
1418
1419 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1420                                        struct ecore_ptt *p_ptt)
1421 {
1422         u8 port = p_hwfn->port_id;
1423         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1424
1425         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1426
1427         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1428                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1429                  (port <<
1430                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1431                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1432
1433         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1434                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1435
1436         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1437                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1438
1439         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1440                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1441
1442         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1443                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1444
1445         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1446                  (0xA <<
1447                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1448                  (8 <<
1449                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1450
1451         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1452                  0xa853);
1453 }
1454
1455 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1456                                  struct ecore_ptt *p_ptt)
1457 {
1458         if (ECORE_IS_AH(p_hwfn->p_dev))
1459                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1460         else /* BB */
1461                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1462 }
1463
1464 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1465                                struct ecore_ptt *p_ptt,  u8 port)
1466 {
1467         int port_offset = port ? 0x800 : 0;
1468         u32 xmac_rxctrl = 0;
1469
1470         /* Reset of XMAC */
1471         /* FIXME: move to common start */
1472         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1473                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1474         OSAL_MSLEEP(1);
1475         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1476                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1477
1478         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1479
1480         /* Set the number of ports on the Warp Core to 10G */
1481         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1482
1483         /* Soft reset of XMAC */
1484         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1485                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1486         OSAL_MSLEEP(1);
1487         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1488                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1489
1490         /* FIXME: move to common end */
1491         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1492                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1493
1494         /* Set Max packet size: initialize XMAC block register for port 0 */
1495         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1496
1497         /* CRC append for Tx packets: init XMAC block register for port 1 */
1498         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1499
1500         /* Enable TX and RX: initialize XMAC block register for port 1 */
1501         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1502                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1503         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1504                                XMAC_REG_RX_CTRL_BB + port_offset);
1505         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1506         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1507 }
1508 #endif
1509
1510 static enum _ecore_status_t
1511 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1512                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1513 {
1514         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1515         u32 dpi_bit_shift, dpi_count;
1516         u32 min_dpis;
1517
1518         /* Calculate DPI size
1519          * ------------------
1520          * The PWM region contains Doorbell Pages. The first is reserverd for
1521          * the kernel for, e.g, L2. The others are free to be used by non-
1522          * trusted applications, typically from user space. Each page, called a
1523          * doorbell page is sectioned into windows that allow doorbells to be
1524          * issued in parallel by the kernel/application. The size of such a
1525          * window (a.k.a. WID) is 1kB.
1526          * Summary:
1527          *    1kB WID x N WIDS = DPI page size
1528          *    DPI page size x N DPIs = PWM region size
1529          * Notes:
1530          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1531          * in order to ensure that two applications won't share the same page.
1532          * It also must contain at least one WID per CPU to allow parallelism.
1533          * It also must be a power of 2, since it is stored as a bit shift.
1534          *
1535          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1536          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1537          * containing 4 WIDs.
1538          */
1539         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1540         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1541         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1542         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1543         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1544
1545         dpi_count = pwm_region_size / dpi_page_size;
1546
1547         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1548         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1549
1550         /* Update hwfn */
1551         p_hwfn->dpi_size = dpi_page_size;
1552         p_hwfn->dpi_count = dpi_count;
1553
1554         /* Update registers */
1555         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1556
1557         if (dpi_count < min_dpis)
1558                 return ECORE_NORESOURCES;
1559
1560         return ECORE_SUCCESS;
1561 }
1562
1563 enum ECORE_ROCE_EDPM_MODE {
1564         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1565         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1566         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1567 };
1568
1569 static enum _ecore_status_t
1570 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1571                               struct ecore_ptt *p_ptt)
1572 {
1573         u32 pwm_regsize, norm_regsize;
1574         u32 non_pwm_conn, min_addr_reg1;
1575         u32 db_bar_size, n_cpus;
1576         u32 roce_edpm_mode;
1577         u32 pf_dems_shift;
1578         enum _ecore_status_t rc = ECORE_SUCCESS;
1579         u8 cond;
1580
1581         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1582         if (p_hwfn->p_dev->num_hwfns > 1)
1583                 db_bar_size /= 2;
1584
1585         /* Calculate doorbell regions
1586          * -----------------------------------
1587          * The doorbell BAR is made of two regions. The first is called normal
1588          * region and the second is called PWM region. In the normal region
1589          * each ICID has its own set of addresses so that writing to that
1590          * specific address identifies the ICID. In the Process Window Mode
1591          * region the ICID is given in the data written to the doorbell. The
1592          * above per PF register denotes the offset in the doorbell BAR in which
1593          * the PWM region begins.
1594          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1595          * non-PWM connection. The calculation below computes the total non-PWM
1596          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1597          * in units of 4,096 bytes.
1598          */
1599         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1600             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1601                                           OSAL_NULL) +
1602             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1603         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1604         min_addr_reg1 = norm_regsize / 4096;
1605         pwm_regsize = db_bar_size - norm_regsize;
1606
1607         /* Check that the normal and PWM sizes are valid */
1608         if (db_bar_size < norm_regsize) {
1609                 DP_ERR(p_hwfn->p_dev,
1610                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1611                        db_bar_size, norm_regsize);
1612                 return ECORE_NORESOURCES;
1613         }
1614         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1615                 DP_ERR(p_hwfn->p_dev,
1616                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1617                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1618                        norm_regsize);
1619                 return ECORE_NORESOURCES;
1620         }
1621
1622         /* Calculate number of DPIs */
1623         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1624         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1625             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1626                 /* Either EDPM is mandatory, or we are attempting to allocate a
1627                  * WID per CPU.
1628                  */
1629                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1630                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1631         }
1632
1633         cond = ((rc != ECORE_SUCCESS) &&
1634                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1635                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1636         if (cond || p_hwfn->dcbx_no_edpm) {
1637                 /* Either EDPM is disabled from user configuration, or it is
1638                  * disabled via DCBx, or it is not mandatory and we failed to
1639                  * allocated a WID per CPU.
1640                  */
1641                 n_cpus = 1;
1642                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1643
1644                 /* If we entered this flow due to DCBX then the DPM register is
1645                  * already configured.
1646                  */
1647         }
1648
1649         DP_INFO(p_hwfn,
1650                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1651                 norm_regsize, pwm_regsize);
1652         DP_INFO(p_hwfn,
1653                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1654                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1655                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1656                 "disabled" : "enabled");
1657
1658         /* Check return codes from above calls */
1659         if (rc != ECORE_SUCCESS) {
1660                 DP_ERR(p_hwfn,
1661                        "Failed to allocate enough DPIs\n");
1662                 return ECORE_NORESOURCES;
1663         }
1664
1665         /* Update hwfn */
1666         p_hwfn->dpi_start_offset = norm_regsize;
1667
1668         /* Update registers */
1669         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1670         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1671         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1672         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1673
1674         return ECORE_SUCCESS;
1675 }
1676
1677 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1678                                                struct ecore_ptt *p_ptt,
1679                                                int hw_mode)
1680 {
1681         enum _ecore_status_t rc = ECORE_SUCCESS;
1682
1683         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1684                             hw_mode);
1685         if (rc != ECORE_SUCCESS)
1686                 return rc;
1687 #ifndef ASIC_ONLY
1688         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1689                 return ECORE_SUCCESS;
1690
1691         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1692                 if (ECORE_IS_AH(p_hwfn->p_dev))
1693                         return ECORE_SUCCESS;
1694                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1695                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1696         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1697                 if (p_hwfn->p_dev->num_hwfns > 1) {
1698                         /* Activate OPTE in CMT */
1699                         u32 val;
1700
1701                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1702                         val |= 0x10;
1703                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1704                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1705                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1706                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1707                         ecore_wr(p_hwfn, p_ptt,
1708                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1709                         ecore_wr(p_hwfn, p_ptt,
1710                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1711                         ecore_wr(p_hwfn, p_ptt,
1712                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1713                                  0x55555555);
1714                 }
1715
1716                 ecore_emul_link_init(p_hwfn, p_ptt);
1717         } else {
1718                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1719         }
1720 #endif
1721
1722         return rc;
1723 }
1724
1725 static enum _ecore_status_t
1726 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1727                  struct ecore_ptt *p_ptt,
1728                  struct ecore_tunnel_info *p_tunn,
1729                  int hw_mode,
1730                  bool b_hw_start,
1731                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1732 {
1733         u8 rel_pf_id = p_hwfn->rel_pf_id;
1734         u32 prs_reg;
1735         enum _ecore_status_t rc = ECORE_SUCCESS;
1736         u16 ctrl;
1737         int pos;
1738
1739         if (p_hwfn->mcp_info) {
1740                 struct ecore_mcp_function_info *p_info;
1741
1742                 p_info = &p_hwfn->mcp_info->func_info;
1743                 if (p_info->bandwidth_min)
1744                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1745
1746                 /* Update rate limit once we'll actually have a link */
1747                 p_hwfn->qm_info.pf_rl = 100000;
1748         }
1749         ecore_cxt_hw_init_pf(p_hwfn);
1750
1751         ecore_int_igu_init_rt(p_hwfn);
1752
1753         /* Set VLAN in NIG if needed */
1754         if (hw_mode & (1 << MODE_MF_SD)) {
1755                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1756                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1757                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1758                              p_hwfn->hw_info.ovlan);
1759         }
1760
1761         /* Enable classification by MAC if needed */
1762         if (hw_mode & (1 << MODE_MF_SI)) {
1763                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1764                            "Configuring TAGMAC_CLS_TYPE\n");
1765                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1766                              1);
1767         }
1768
1769         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1770         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1771                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1772         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1773                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1774         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1775
1776         /* perform debug configuration when chip is out of reset */
1777         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1778
1779         /* PF Init sequence */
1780         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1781         if (rc)
1782                 return rc;
1783
1784         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1785         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1786         if (rc)
1787                 return rc;
1788
1789         /* Pure runtime initializations - directly to the HW  */
1790         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1791
1792         /* PCI relaxed ordering causes a decrease in the performance on some
1793          * systems. Till a root cause is found, disable this attribute in the
1794          * PCI config space.
1795          */
1796         /* Not in use @DPDK
1797         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1798         * if (!pos) {
1799         *       DP_NOTICE(p_hwfn, true,
1800         *                 "Failed to find the PCIe Cap\n");
1801         *       return ECORE_IO;
1802         * }
1803         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1804         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1805         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1806         */
1807
1808         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1809         if (rc)
1810                 return rc;
1811         if (b_hw_start) {
1812                 /* enable interrupts */
1813                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1814                 if (rc != ECORE_SUCCESS)
1815                         return rc;
1816
1817                 /* send function start command */
1818                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1819                                        allow_npar_tx_switch);
1820                 if (rc) {
1821                         DP_NOTICE(p_hwfn, true,
1822                                   "Function start ramrod failed\n");
1823                 } else {
1824                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1825                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1826                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1827
1828                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1829                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1830                                          (1 << 2));
1831                                 ecore_wr(p_hwfn, p_ptt,
1832                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1833                                     0x100);
1834                         }
1835                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1836                                    "PRS_REG_SEARCH registers after start PFn\n");
1837                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1838                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1839                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1840                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1841                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1842                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1843                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1844                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1845                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1846                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1847                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1848                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1849                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1850                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1851                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1852                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1853                                    prs_reg);
1854                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1855                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1856                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1857                 }
1858         }
1859         return rc;
1860 }
1861
1862 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
1863                                                   struct ecore_ptt *p_ptt,
1864                                                   bool b_enable)
1865 {
1866         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
1867
1868         /* Configure the PF's internal FID_enable for master transactions */
1869         ecore_wr(p_hwfn, p_ptt,
1870                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1871
1872         /* Wait until value is set - try for 1 second every 50us */
1873         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1874                 val = ecore_rd(p_hwfn, p_ptt,
1875                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1876                 if (val == set_val)
1877                         break;
1878
1879                 OSAL_UDELAY(50);
1880         }
1881
1882         if (val != set_val) {
1883                 DP_NOTICE(p_hwfn, true,
1884                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1885                 return ECORE_UNKNOWN_ERROR;
1886         }
1887
1888         return ECORE_SUCCESS;
1889 }
1890
1891 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1892                                   struct ecore_ptt *p_main_ptt)
1893 {
1894         /* Read shadow of current MFW mailbox */
1895         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1896         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1897                     p_hwfn->mcp_info->mfw_mb_cur,
1898                     p_hwfn->mcp_info->mfw_mb_length);
1899 }
1900
1901 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1902                                     struct ecore_hw_init_params *p_params)
1903 {
1904         if (p_params->p_tunn) {
1905                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1906                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1907         }
1908
1909         p_hwfn->b_int_enabled = 1;
1910
1911         return ECORE_SUCCESS;
1912 }
1913
1914 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
1915                                      struct ecore_ptt *p_ptt)
1916 {
1917         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
1918                  1 << p_hwfn->abs_pf_id);
1919 }
1920
1921 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1922                                    struct ecore_hw_init_params *p_params)
1923 {
1924         struct ecore_load_req_params load_req_params;
1925         u32 load_code, resp, param, drv_mb_param;
1926         bool b_default_mtu = true;
1927         struct ecore_hwfn *p_hwfn;
1928         enum _ecore_status_t rc = ECORE_SUCCESS;
1929         int i;
1930
1931         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1932             (p_dev->num_hwfns > 1)) {
1933                 DP_NOTICE(p_dev, false,
1934                           "MSI mode is not supported for CMT devices\n");
1935                 return ECORE_INVAL;
1936         }
1937
1938         if (IS_PF(p_dev)) {
1939                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1940                 if (rc != ECORE_SUCCESS)
1941                         return rc;
1942         }
1943
1944         for_each_hwfn(p_dev, i) {
1945                 p_hwfn = &p_dev->hwfns[i];
1946
1947                 /* If management didn't provide a default, set one of our own */
1948                 if (!p_hwfn->hw_info.mtu) {
1949                         p_hwfn->hw_info.mtu = 1500;
1950                         b_default_mtu = false;
1951                 }
1952
1953                 if (IS_VF(p_dev)) {
1954                         ecore_vf_start(p_hwfn, p_params);
1955                         continue;
1956                 }
1957
1958                 rc = ecore_calc_hw_mode(p_hwfn);
1959                 if (rc != ECORE_SUCCESS)
1960                         return rc;
1961
1962                 OSAL_MEM_ZERO(&load_req_params, sizeof(load_req_params));
1963                 load_req_params.drv_role = p_params->is_crash_kernel ?
1964                                            ECORE_DRV_ROLE_KDUMP :
1965                                            ECORE_DRV_ROLE_OS;
1966                 load_req_params.timeout_val = p_params->mfw_timeout_val;
1967                 load_req_params.avoid_eng_reset = p_params->avoid_eng_reset;
1968                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1969                                         &load_req_params);
1970                 if (rc != ECORE_SUCCESS) {
1971                         DP_NOTICE(p_hwfn, true,
1972                                   "Failed sending a LOAD_REQ command\n");
1973                         return rc;
1974                 }
1975
1976                 load_code = load_req_params.load_code;
1977                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1978                            "Load request was sent. Load code: 0x%x\n",
1979                            load_code);
1980
1981                 /* CQ75580:
1982                  * When coming back from hiberbate state, the registers from
1983                  * which shadow is read initially are not initialized. It turns
1984                  * out that these registers get initialized during the call to
1985                  * ecore_mcp_load_req request. So we need to reread them here
1986                  * to get the proper shadow register value.
1987                  * Note: This is a workaround for the missing MFW
1988                  * initialization. It may be removed once the implementation
1989                  * is done.
1990                  */
1991                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1992
1993                 /* Only relevant for recovery:
1994                  * Clear the indication after the LOAD_REQ command is responded
1995                  * by the MFW.
1996                  */
1997                 p_dev->recov_in_prog = false;
1998
1999                 p_hwfn->first_on_engine = (load_code ==
2000                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2001
2002                 if (!qm_lock_init) {
2003                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2004                         qm_lock_init = true;
2005                 }
2006
2007                 /* Clean up chip from previous driver if such remains exist.
2008                  * This is not needed when the PF is the first one on the
2009                  * engine, since afterwards we are going to init the FW.
2010                  */
2011                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2012                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2013                                                  p_hwfn->rel_pf_id, false);
2014                         if (rc != ECORE_SUCCESS) {
2015                                 ecore_hw_err_notify(p_hwfn,
2016                                                     ECORE_HW_ERR_RAMROD_FAIL);
2017                                 goto load_err;
2018                         }
2019                 }
2020
2021                 /* Log and clean previous pglue_b errors if such exist */
2022                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2023                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2024
2025                 /* Enable the PF's internal FID_enable in the PXP */
2026                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2027                                                   true);
2028                 if (rc != ECORE_SUCCESS)
2029                         goto load_err;
2030
2031                 switch (load_code) {
2032                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2033                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2034                                                   p_hwfn->hw_info.hw_mode);
2035                         if (rc != ECORE_SUCCESS)
2036                                 break;
2037                         /* Fall into */
2038                 case FW_MSG_CODE_DRV_LOAD_PORT:
2039                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2040                                                 p_hwfn->hw_info.hw_mode);
2041                         if (rc != ECORE_SUCCESS)
2042                                 break;
2043                         /* Fall into */
2044                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2045                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2046                                               p_params->p_tunn,
2047                                               p_hwfn->hw_info.hw_mode,
2048                                               p_params->b_hw_start,
2049                                               p_params->int_mode,
2050                                               p_params->allow_npar_tx_switch);
2051                         break;
2052                 default:
2053                         DP_NOTICE(p_hwfn, false,
2054                                   "Unexpected load code [0x%08x]", load_code);
2055                         rc = ECORE_NOTIMPL;
2056                         break;
2057                 }
2058
2059                 if (rc != ECORE_SUCCESS) {
2060                         DP_NOTICE(p_hwfn, true,
2061                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2062                                   load_code, rc);
2063                         goto load_err;
2064                 }
2065
2066                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2067                 if (rc != ECORE_SUCCESS)
2068                         return rc;
2069
2070                 /* send DCBX attention request command */
2071                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2072                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2073                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2074                                    DRV_MSG_CODE_SET_DCBX,
2075                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, &resp,
2076                                    &param);
2077                 if (rc != ECORE_SUCCESS) {
2078                         DP_NOTICE(p_hwfn, true,
2079                                   "Failed to send DCBX attention request\n");
2080                         return rc;
2081                 }
2082
2083                 p_hwfn->hw_init_done = true;
2084         }
2085
2086         if (IS_PF(p_dev)) {
2087                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2088                 drv_mb_param = STORM_FW_VERSION;
2089                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2090                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2091                                    drv_mb_param, &resp, &param);
2092                 if (rc != ECORE_SUCCESS)
2093                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2094
2095                 if (!b_default_mtu)
2096                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2097                                                       p_hwfn->hw_info.mtu);
2098                 if (rc != ECORE_SUCCESS)
2099                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2100
2101                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2102                                                       p_hwfn->p_main_ptt,
2103                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2104                 if (rc != ECORE_SUCCESS)
2105                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2106         }
2107
2108         return rc;
2109
2110 load_err:
2111         /* The MFW load lock should be released regardless of success or failure
2112          * of initialization.
2113          * TODO: replace this with an attempt to send cancel_load.
2114          */
2115         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2116         return rc;
2117 }
2118
2119 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2120 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2121                                  struct ecore_hwfn *p_hwfn,
2122                                  struct ecore_ptt *p_ptt)
2123 {
2124         int i;
2125
2126         /* close timers */
2127         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2128         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2129         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2130                                                                         i++) {
2131                 if ((!ecore_rd(p_hwfn, p_ptt,
2132                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2133                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2134                         break;
2135
2136                 /* Dependent on number of connection/tasks, possibly
2137                  * 1ms sleep is required between polls
2138                  */
2139                 OSAL_MSLEEP(1);
2140         }
2141
2142         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2143                 return;
2144
2145         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2146                   " [Connection %02x Tasks %02x]\n",
2147                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2148                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2149 }
2150
2151 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2152 {
2153         int j;
2154
2155         for_each_hwfn(p_dev, j) {
2156                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2157                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2158
2159                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2160         }
2161 }
2162
2163 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2164                                                  struct ecore_ptt *p_ptt,
2165                                                  u32 addr, u32 expected_val)
2166 {
2167         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2168
2169         if (val != expected_val) {
2170                 DP_NOTICE(p_hwfn, true,
2171                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2172                           addr, val, expected_val);
2173                 return ECORE_UNKNOWN_ERROR;
2174         }
2175
2176         return ECORE_SUCCESS;
2177 }
2178
2179 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2180 {
2181         struct ecore_hwfn *p_hwfn;
2182         struct ecore_ptt *p_ptt;
2183         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2184         int j;
2185
2186         for_each_hwfn(p_dev, j) {
2187                 p_hwfn = &p_dev->hwfns[j];
2188                 p_ptt = p_hwfn->p_main_ptt;
2189
2190                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2191
2192                 if (IS_VF(p_dev)) {
2193                         ecore_vf_pf_int_cleanup(p_hwfn);
2194                         rc = ecore_vf_pf_reset(p_hwfn);
2195                         if (rc != ECORE_SUCCESS) {
2196                                 DP_NOTICE(p_hwfn, true,
2197                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2198                                           rc);
2199                                 rc2 = ECORE_UNKNOWN_ERROR;
2200                         }
2201                         continue;
2202                 }
2203
2204                 /* mark the hw as uninitialized... */
2205                 p_hwfn->hw_init_done = false;
2206
2207                 /* Send unload command to MCP */
2208                 if (!p_dev->recov_in_prog) {
2209                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2210                         if (rc != ECORE_SUCCESS) {
2211                                 DP_NOTICE(p_hwfn, true,
2212                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2213                                           rc);
2214                                 rc2 = ECORE_UNKNOWN_ERROR;
2215                         }
2216                 }
2217
2218                 OSAL_DPC_SYNC(p_hwfn);
2219
2220                 /* After this point no MFW attentions are expected, e.g. prevent
2221                  * race between pf stop and dcbx pf update.
2222                  */
2223
2224                 rc = ecore_sp_pf_stop(p_hwfn);
2225                 if (rc != ECORE_SUCCESS) {
2226                         DP_NOTICE(p_hwfn, true,
2227                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2228                                   rc);
2229                         rc2 = ECORE_UNKNOWN_ERROR;
2230                 }
2231
2232                 /* perform debug action after PF stop was sent */
2233                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2234
2235                 /* close NIG to BRB gate */
2236                 ecore_wr(p_hwfn, p_ptt,
2237                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2238
2239                 /* close parser */
2240                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2241                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2242                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2243                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2244                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2245
2246                 /* @@@TBD - clean transmission queues (5.b) */
2247                 /* @@@TBD - clean BTB (5.c) */
2248
2249                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2250
2251                 /* @@@TBD - verify DMAE requests are done (8) */
2252
2253                 /* Disable Attention Generation */
2254                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2255                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2256                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2257                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2258                 /* Need to wait 1ms to guarantee SBs are cleared */
2259                 OSAL_MSLEEP(1);
2260
2261                 if (!p_dev->recov_in_prog) {
2262                         ecore_verify_reg_val(p_hwfn, p_ptt,
2263                                              QM_REG_USG_CNT_PF_TX, 0);
2264                         ecore_verify_reg_val(p_hwfn, p_ptt,
2265                                              QM_REG_USG_CNT_PF_OTHER, 0);
2266                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2267                 }
2268
2269                 /* Disable PF in HW blocks */
2270                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2271                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2272
2273                 if (!p_dev->recov_in_prog) {
2274                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2275                         if (rc != ECORE_SUCCESS) {
2276                                 DP_NOTICE(p_hwfn, true,
2277                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2278                                           rc);
2279                                 rc2 = ECORE_UNKNOWN_ERROR;
2280                         }
2281                 }
2282         } /* hwfn loop */
2283
2284         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2285                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2286                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2287
2288                  /* Clear the PF's internal FID_enable in the PXP.
2289                   * In CMT this should only be done for first hw-function, and
2290                   * only after all transactions have stopped for all active
2291                   * hw-functions.
2292                   */
2293                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2294                                                   false);
2295                 if (rc != ECORE_SUCCESS) {
2296                         DP_NOTICE(p_hwfn, true,
2297                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2298                                   rc);
2299                         rc2 = ECORE_UNKNOWN_ERROR;
2300                 }
2301         }
2302
2303         return rc2;
2304 }
2305
2306 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2307 {
2308         int j;
2309
2310         for_each_hwfn(p_dev, j) {
2311                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2312                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2313
2314                 if (IS_VF(p_dev)) {
2315                         ecore_vf_pf_int_cleanup(p_hwfn);
2316                         continue;
2317                 }
2318
2319                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2320                            "Shutting down the fastpath\n");
2321
2322                 ecore_wr(p_hwfn, p_ptt,
2323                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2324
2325                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2326                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2327                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2328                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2329                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2330
2331                 /* @@@TBD - clean transmission queues (5.b) */
2332                 /* @@@TBD - clean BTB (5.c) */
2333
2334                 /* @@@TBD - verify DMAE requests are done (8) */
2335
2336                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2337                 /* Need to wait 1ms to guarantee SBs are cleared */
2338                 OSAL_MSLEEP(1);
2339         }
2340 }
2341
2342 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2343 {
2344         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2345
2346         if (IS_VF(p_hwfn->p_dev))
2347                 return;
2348
2349         /* If roce info is allocated it means roce is initialized and should
2350          * be enabled in searcher.
2351          */
2352         if (p_hwfn->p_rdma_info) {
2353                 if (p_hwfn->b_rdma_enabled_in_prs)
2354                         ecore_wr(p_hwfn, p_ptt,
2355                                  p_hwfn->rdma_prs_search_reg, 0x1);
2356                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2357         }
2358
2359         /* Re-open incoming traffic */
2360         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2361                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2362 }
2363
2364 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2365 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2366 {
2367         ecore_ptt_pool_free(p_hwfn);
2368         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2369 }
2370
2371 /* Setup bar access */
2372 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2373 {
2374         /* clear indirect access */
2375         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2376                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2377                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2378                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2379                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2380                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2381                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2382                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2383                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2384         } else {
2385                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2386                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2387                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2388                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2389                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2390                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2391                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2392                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2393         }
2394
2395         /* Clean previous pglue_b errors if such exist */
2396         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2397
2398         /* enable internal target-read */
2399         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2400                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2401 }
2402
2403 static void get_function_id(struct ecore_hwfn *p_hwfn)
2404 {
2405         /* ME Register */
2406         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2407                                                   PXP_PF_ME_OPAQUE_ADDR);
2408
2409         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2410
2411         /* Bits 16-19 from the ME registers are the pf_num */
2412         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2413         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2414                                       PXP_CONCRETE_FID_PFID);
2415         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2416                                     PXP_CONCRETE_FID_PORT);
2417
2418         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2419                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2420                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2421 }
2422
2423 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2424 {
2425         u32 *feat_num = p_hwfn->hw_info.feat_num;
2426         struct ecore_sb_cnt_info sb_cnt_info;
2427         int num_features = 1;
2428
2429         /* L2 Queues require each: 1 status block. 1 L2 queue */
2430         feat_num[ECORE_PF_L2_QUE] =
2431             OSAL_MIN_T(u32,
2432                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2433                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2434
2435         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2436         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2437         feat_num[ECORE_VF_L2_QUE] =
2438                 OSAL_MIN_T(u32,
2439                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2440                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2441                            sb_cnt_info.sb_iov_cnt);
2442
2443         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2444                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2445         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2446                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2447
2448         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2449                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2450                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2451                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2452                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2453                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2454                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2455                    RESC_NUM(p_hwfn, ECORE_SB));
2456 }
2457
2458 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2459 {
2460         switch (res_id) {
2461         case ECORE_SB:
2462                 return "SB";
2463         case ECORE_L2_QUEUE:
2464                 return "L2_QUEUE";
2465         case ECORE_VPORT:
2466                 return "VPORT";
2467         case ECORE_RSS_ENG:
2468                 return "RSS_ENG";
2469         case ECORE_PQ:
2470                 return "PQ";
2471         case ECORE_RL:
2472                 return "RL";
2473         case ECORE_MAC:
2474                 return "MAC";
2475         case ECORE_VLAN:
2476                 return "VLAN";
2477         case ECORE_RDMA_CNQ_RAM:
2478                 return "RDMA_CNQ_RAM";
2479         case ECORE_ILT:
2480                 return "ILT";
2481         case ECORE_LL2_QUEUE:
2482                 return "LL2_QUEUE";
2483         case ECORE_CMDQS_CQS:
2484                 return "CMDQS_CQS";
2485         case ECORE_RDMA_STATS_QUEUE:
2486                 return "RDMA_STATS_QUEUE";
2487         case ECORE_BDQ:
2488                 return "BDQ";
2489         default:
2490                 return "UNKNOWN_RESOURCE";
2491         }
2492 }
2493
2494 static enum _ecore_status_t
2495 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2496                               enum ecore_resources res_id, u32 resc_max_val,
2497                               u32 *p_mcp_resp)
2498 {
2499         enum _ecore_status_t rc;
2500
2501         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_hwfn->p_main_ptt, res_id,
2502                                         resc_max_val, p_mcp_resp);
2503         if (rc != ECORE_SUCCESS) {
2504                 DP_NOTICE(p_hwfn, true,
2505                           "MFW response failure for a max value setting of resource %d [%s]\n",
2506                           res_id, ecore_hw_get_resc_name(res_id));
2507                 return rc;
2508         }
2509
2510         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2511                 DP_INFO(p_hwfn,
2512                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2513                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2514
2515         return ECORE_SUCCESS;
2516 }
2517
2518 static enum _ecore_status_t
2519 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn)
2520 {
2521         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2522         u32 resc_max_val, mcp_resp;
2523         u8 res_id;
2524         enum _ecore_status_t rc;
2525
2526         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2527                 /* @DPDK */
2528                 switch (res_id) {
2529                 case ECORE_LL2_QUEUE:
2530                 case ECORE_RDMA_CNQ_RAM:
2531                 case ECORE_RDMA_STATS_QUEUE:
2532                 case ECORE_BDQ:
2533                         resc_max_val = 0;
2534                         break;
2535                 default:
2536                         continue;
2537                 }
2538
2539                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, res_id,
2540                                                    resc_max_val, &mcp_resp);
2541                 if (rc != ECORE_SUCCESS)
2542                         return rc;
2543
2544                 /* There's no point to continue to the next resource if the
2545                  * command is not supported by the MFW.
2546                  * We do continue if the command is supported but the resource
2547                  * is unknown to the MFW. Such a resource will be later
2548                  * configured with the default allocation values.
2549                  */
2550                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2551                         return ECORE_NOTIMPL;
2552         }
2553
2554         return ECORE_SUCCESS;
2555 }
2556
2557 static
2558 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2559                                             enum ecore_resources res_id,
2560                                             u32 *p_resc_num, u32 *p_resc_start)
2561 {
2562         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2563         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2564         struct ecore_sb_cnt_info sb_cnt_info;
2565
2566         switch (res_id) {
2567         case ECORE_SB:
2568                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2569                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2570                 *p_resc_num = sb_cnt_info.sb_cnt;
2571                 break;
2572         case ECORE_L2_QUEUE:
2573                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2574                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2575                 break;
2576         case ECORE_VPORT:
2577                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2578                                  MAX_NUM_VPORTS_BB) / num_funcs;
2579                 break;
2580         case ECORE_RSS_ENG:
2581                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2582                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2583                 break;
2584         case ECORE_PQ:
2585                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2586                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2587                 break;
2588         case ECORE_RL:
2589                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2590                 break;
2591         case ECORE_MAC:
2592         case ECORE_VLAN:
2593                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2594                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2595                 break;
2596         case ECORE_ILT:
2597                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2598                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2599                 break;
2600         case ECORE_LL2_QUEUE:
2601                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2602                 break;
2603         case ECORE_RDMA_CNQ_RAM:
2604         case ECORE_CMDQS_CQS:
2605                 /* CNQ/CMDQS are the same resource */
2606                 /* @DPDK */
2607                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2608                 break;
2609         case ECORE_RDMA_STATS_QUEUE:
2610                 /* @DPDK */
2611                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2612                                  MAX_NUM_VPORTS_BB) / num_funcs;
2613                 break;
2614         case ECORE_BDQ:
2615                 /* @DPDK */
2616                 *p_resc_num = 0;
2617                 break;
2618         default:
2619                 break;
2620         }
2621
2622
2623         switch (res_id) {
2624         case ECORE_BDQ:
2625                 if (!*p_resc_num)
2626                         *p_resc_start = 0;
2627                 break;
2628         default:
2629                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2630                 break;
2631         }
2632
2633         return ECORE_SUCCESS;
2634 }
2635
2636 static enum _ecore_status_t
2637 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
2638                          bool drv_resc_alloc)
2639 {
2640         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2641         u32 mcp_resp, *p_resc_num, *p_resc_start;
2642         enum _ecore_status_t rc;
2643
2644         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2645         p_resc_start = &RESC_START(p_hwfn, res_id);
2646
2647         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2648                                     &dflt_resc_start);
2649         if (rc != ECORE_SUCCESS) {
2650                 DP_ERR(p_hwfn,
2651                        "Failed to get default amount for resource %d [%s]\n",
2652                         res_id, ecore_hw_get_resc_name(res_id));
2653                 return rc;
2654         }
2655
2656 #ifndef ASIC_ONLY
2657         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2658                 *p_resc_num = dflt_resc_num;
2659                 *p_resc_start = dflt_resc_start;
2660                 goto out;
2661         }
2662 #endif
2663
2664         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2665                                      &mcp_resp, p_resc_num, p_resc_start);
2666         if (rc != ECORE_SUCCESS) {
2667                 DP_NOTICE(p_hwfn, true,
2668                           "MFW response failure for an allocation request for"
2669                           " resource %d [%s]\n",
2670                           res_id, ecore_hw_get_resc_name(res_id));
2671                 return rc;
2672         }
2673
2674         /* Default driver values are applied in the following cases:
2675          * - The resource allocation MB command is not supported by the MFW
2676          * - There is an internal error in the MFW while processing the request
2677          * - The resource ID is unknown to the MFW
2678          */
2679         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2680                 DP_INFO(p_hwfn,
2681                         "Failed to receive allocation info for resource %d [%s]."
2682                         " mcp_resp = 0x%x. Applying default values"
2683                         " [%d,%d].\n",
2684                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2685                         dflt_resc_num, dflt_resc_start);
2686
2687                 *p_resc_num = dflt_resc_num;
2688                 *p_resc_start = dflt_resc_start;
2689                 goto out;
2690         }
2691
2692         /* TBD - remove this when revising the handling of the SB resource */
2693         if (res_id == ECORE_SB) {
2694                 /* Excluding the slowpath SB */
2695                 *p_resc_num -= 1;
2696                 *p_resc_start -= p_hwfn->enabled_func_idx;
2697         }
2698
2699         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2700                 DP_INFO(p_hwfn,
2701                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
2702                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2703                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2704                         drv_resc_alloc ? " - Applying default values" : "");
2705                 if (drv_resc_alloc) {
2706                         *p_resc_num = dflt_resc_num;
2707                         *p_resc_start = dflt_resc_start;
2708                 }
2709         }
2710 out:
2711         return ECORE_SUCCESS;
2712 }
2713
2714 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2715                                                    bool drv_resc_alloc)
2716 {
2717         enum _ecore_status_t rc;
2718         u8 res_id;
2719
2720         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2721                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2722                 if (rc != ECORE_SUCCESS)
2723                         return rc;
2724         }
2725
2726         return ECORE_SUCCESS;
2727 }
2728
2729 #define ECORE_RESC_ALLOC_LOCK_RETRY_CNT         10
2730 #define ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US    10000 /* 10 msec */
2731
2732 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2733                                               bool drv_resc_alloc)
2734 {
2735         struct ecore_resc_unlock_params resc_unlock_params;
2736         struct ecore_resc_lock_params resc_lock_params;
2737         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2738         u8 res_id;
2739         enum _ecore_status_t rc;
2740 #ifndef ASIC_ONLY
2741         u32 *resc_start = p_hwfn->hw_info.resc_start;
2742         u32 *resc_num = p_hwfn->hw_info.resc_num;
2743         /* For AH, an equal share of the ILT lines between the maximal number of
2744          * PFs is not enough for RoCE. This would be solved by the future
2745          * resource allocation scheme, but isn't currently present for
2746          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2747          * to work - the BB number of ILT lines divided by its max PFs number.
2748          */
2749         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2750 #endif
2751
2752         /* Setting the max values of the soft resources and the following
2753          * resources allocation queries should be atomic. Since several PFs can
2754          * run in parallel - a resource lock is needed.
2755          * If either the resource lock or resource set value commands are not
2756          * supported - skip the the max values setting, release the lock if
2757          * needed, and proceed to the queries. Other failures, including a
2758          * failure to acquire the lock, will cause this function to fail.
2759          * Old drivers that don't acquire the lock can run in parallel, and
2760          * their allocation values won't be affected by the updated max values.
2761          */
2762         OSAL_MEM_ZERO(&resc_lock_params, sizeof(resc_lock_params));
2763         resc_lock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2764         resc_lock_params.retry_num = ECORE_RESC_ALLOC_LOCK_RETRY_CNT;
2765         resc_lock_params.retry_interval = ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2766         resc_lock_params.sleep_b4_retry = true;
2767         OSAL_MEM_ZERO(&resc_unlock_params, sizeof(resc_unlock_params));
2768         resc_unlock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2769
2770         rc = ecore_mcp_resc_lock(p_hwfn, p_hwfn->p_main_ptt, &resc_lock_params);
2771         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2772                 return rc;
2773         } else if (rc == ECORE_NOTIMPL) {
2774                 DP_INFO(p_hwfn,
2775                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2776         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
2777                 DP_NOTICE(p_hwfn, false,
2778                           "Failed to acquire the resource lock for the resource allocation commands\n");
2779                 rc = ECORE_BUSY;
2780                 goto unlock_and_exit;
2781         } else {
2782                 rc = ecore_hw_set_soft_resc_size(p_hwfn);
2783                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2784                         DP_NOTICE(p_hwfn, false,
2785                                   "Failed to set the max values of the soft resources\n");
2786                         goto unlock_and_exit;
2787                 } else if (rc == ECORE_NOTIMPL) {
2788                         DP_INFO(p_hwfn,
2789                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2790                         rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2791                                                    &resc_unlock_params);
2792                         if (rc != ECORE_SUCCESS)
2793                                 DP_INFO(p_hwfn,
2794                                         "Failed to release the resource lock for the resource allocation commands\n");
2795                 }
2796         }
2797
2798         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
2799         if (rc != ECORE_SUCCESS)
2800                 goto unlock_and_exit;
2801
2802         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2803                 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2804                                            &resc_unlock_params);
2805                 if (rc != ECORE_SUCCESS)
2806                         DP_INFO(p_hwfn,
2807                                 "Failed to release the resource lock for the resource allocation commands\n");
2808         }
2809
2810 #ifndef ASIC_ONLY
2811         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2812                 /* Reduced build contains less PQs */
2813                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2814                         resc_num[ECORE_PQ] = 32;
2815                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2816                             p_hwfn->enabled_func_idx;
2817                 }
2818
2819                 /* For AH emulation, since we have a possible maximal number of
2820                  * 16 enabled PFs, in case there are not enough ILT lines -
2821                  * allocate only first PF as RoCE and have all the other ETH
2822                  * only with less ILT lines.
2823                  */
2824                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2825                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2826                                                          resc_num[ECORE_ILT],
2827                                                          roce_min_ilt_lines);
2828         }
2829
2830         /* Correct the common ILT calculation if PF0 has more */
2831         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2832             p_hwfn->p_dev->b_is_emul_full &&
2833             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2834                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2835                     resc_num[ECORE_ILT];
2836 #endif
2837
2838         /* Sanity for ILT */
2839         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2840             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2841                 DP_NOTICE(p_hwfn, true,
2842                           "Can't assign ILT pages [%08x,...,%08x]\n",
2843                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2844                                                                   ECORE_ILT) -
2845                           1);
2846                 return ECORE_INVAL;
2847         }
2848
2849         ecore_hw_set_feat(p_hwfn);
2850
2851         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2852                    "The numbers for each resource are:\n");
2853         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2854                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2855                            ecore_hw_get_resc_name(res_id),
2856                            RESC_NUM(p_hwfn, res_id),
2857                            RESC_START(p_hwfn, res_id));
2858
2859         return ECORE_SUCCESS;
2860
2861 unlock_and_exit:
2862         ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt, &resc_unlock_params);
2863         return rc;
2864 }
2865
2866 static enum _ecore_status_t
2867 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2868                       struct ecore_ptt *p_ptt,
2869                       struct ecore_hw_prepare_params *p_params)
2870 {
2871         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2872         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2873         struct ecore_mcp_link_params *link;
2874         enum _ecore_status_t rc;
2875
2876         /* Read global nvm_cfg address */
2877         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2878
2879         /* Verify MCP has initialized it */
2880         if (!nvm_cfg_addr) {
2881                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2882                 if (p_params->b_relaxed_probe)
2883                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2884                 return ECORE_INVAL;
2885         }
2886
2887 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2888
2889         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2890
2891         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2892             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2893                                                        core_cfg);
2894
2895         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2896
2897         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2898                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2899         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2900                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2901                 break;
2902         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2903                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2904                 break;
2905         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2906                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2907                 break;
2908         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2909                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2910                 break;
2911         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2912                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2913                 break;
2914         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2915                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2916                 break;
2917         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2918                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2919                 break;
2920         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2921                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2922                 break;
2923         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2924                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2925                 break;
2926         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2927                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2928                 break;
2929         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2930                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2931                 break;
2932         default:
2933                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2934                           core_cfg);
2935                 break;
2936         }
2937
2938         /* Read DCBX configuration */
2939         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2940                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2941         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2942                              port_cfg_addr +
2943                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2944         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2945                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2946         switch (dcbx_mode) {
2947         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2948                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2949                 break;
2950         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2951                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2952                 break;
2953         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2954                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2955                 break;
2956         default:
2957                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2958         }
2959
2960         /* Read default link configuration */
2961         link = &p_hwfn->mcp_info->link_input;
2962         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2963             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2964         link_temp = ecore_rd(p_hwfn, p_ptt,
2965                              port_cfg_addr +
2966                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2967         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2968         link->speed.advertised_speeds = link_temp;
2969
2970         link_temp = link->speed.advertised_speeds;
2971         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2972
2973         link_temp = ecore_rd(p_hwfn, p_ptt,
2974                              port_cfg_addr +
2975                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2976         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2977                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2978         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2979                 link->speed.autoneg = true;
2980                 break;
2981         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2982                 link->speed.forced_speed = 1000;
2983                 break;
2984         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2985                 link->speed.forced_speed = 10000;
2986                 break;
2987         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2988                 link->speed.forced_speed = 25000;
2989                 break;
2990         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2991                 link->speed.forced_speed = 40000;
2992                 break;
2993         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2994                 link->speed.forced_speed = 50000;
2995                 break;
2996         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2997                 link->speed.forced_speed = 100000;
2998                 break;
2999         default:
3000                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3001         }
3002
3003         p_hwfn->mcp_info->link_capabilities.default_speed =
3004             link->speed.forced_speed;
3005         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
3006             link->speed.autoneg;
3007
3008         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3009         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3010         link->pause.autoneg = !!(link_temp &
3011                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3012         link->pause.forced_rx = !!(link_temp &
3013                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3014         link->pause.forced_tx = !!(link_temp &
3015                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3016         link->loopback_mode = 0;
3017
3018         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3019                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
3020                    link->speed.forced_speed, link->speed.advertised_speeds,
3021                    link->speed.autoneg, link->pause.autoneg);
3022
3023         /* Read Multi-function information from shmem */
3024         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3025             OFFSETOF(struct nvm_cfg1, glob) +
3026             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3027
3028         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3029
3030         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3031             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3032
3033         switch (mf_mode) {
3034         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3035                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3036                 break;
3037         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3038                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3039                 break;
3040         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3041                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3042                 break;
3043         }
3044         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3045                 p_hwfn->p_dev->mf_mode);
3046
3047         /* Read Multi-function information from shmem */
3048         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3049             OFFSETOF(struct nvm_cfg1, glob) +
3050             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3051
3052         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3053         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3054                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3055                              &p_hwfn->hw_info.device_capabilities);
3056         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3057                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3058                              &p_hwfn->hw_info.device_capabilities);
3059         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3060                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3061                              &p_hwfn->hw_info.device_capabilities);
3062         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3063                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3064                              &p_hwfn->hw_info.device_capabilities);
3065         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3066                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3067                              &p_hwfn->hw_info.device_capabilities);
3068
3069         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3070         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3071                 rc = ECORE_SUCCESS;
3072                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3073         }
3074
3075         return rc;
3076 }
3077
3078 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3079                                 struct ecore_ptt *p_ptt)
3080 {
3081         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3082         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3083         struct ecore_dev *p_dev = p_hwfn->p_dev;
3084
3085         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3086
3087         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3088          * in the other bits are selected.
3089          * Bits 1-15 are for functions 1-15, respectively, and their value is
3090          * '0' only for enabled functions (function 0 always exists and
3091          * enabled).
3092          * In case of CMT in BB, only the "even" functions are enabled, and thus
3093          * the number of functions for both hwfns is learnt from the same bits.
3094          */
3095         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3096                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3097                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3098         } else { /* E5 */
3099                 reg_function_hide = 0;
3100         }
3101
3102         if (reg_function_hide & 0x1) {
3103                 if (ECORE_IS_BB(p_dev)) {
3104                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3105                                 num_funcs = 0;
3106                                 eng_mask = 0xaaaa;
3107                         } else {
3108                                 num_funcs = 1;
3109                                 eng_mask = 0x5554;
3110                         }
3111                 } else {
3112                         num_funcs = 1;
3113                         eng_mask = 0xfffe;
3114                 }
3115
3116                 /* Get the number of the enabled functions on the engine */
3117                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3118                 while (tmp) {
3119                         if (tmp & 0x1)
3120                                 num_funcs++;
3121                         tmp >>= 0x1;
3122                 }
3123
3124                 /* Get the PF index within the enabled functions */
3125                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3126                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3127                 while (tmp) {
3128                         if (tmp & 0x1)
3129                                 enabled_func_idx--;
3130                         tmp >>= 0x1;
3131                 }
3132         }
3133
3134         p_hwfn->num_funcs_on_engine = num_funcs;
3135         p_hwfn->enabled_func_idx = enabled_func_idx;
3136
3137 #ifndef ASIC_ONLY
3138         if (CHIP_REV_IS_FPGA(p_dev)) {
3139                 DP_NOTICE(p_hwfn, false,
3140                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3141                 p_hwfn->num_funcs_on_engine = 4;
3142         }
3143 #endif
3144
3145         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3146                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3147                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3148                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3149 }
3150
3151 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3152                                       struct ecore_ptt *p_ptt)
3153 {
3154         u32 port_mode;
3155
3156 #ifndef ASIC_ONLY
3157         /* Read the port mode */
3158         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3159                 port_mode = 4;
3160         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3161                  (p_hwfn->p_dev->num_hwfns > 1))
3162                 /* In CMT on emulation, assume 1 port */
3163                 port_mode = 1;
3164         else
3165 #endif
3166         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3167
3168         if (port_mode < 3) {
3169                 p_hwfn->p_dev->num_ports_in_engines = 1;
3170         } else if (port_mode <= 5) {
3171                 p_hwfn->p_dev->num_ports_in_engines = 2;
3172         } else {
3173                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3174                           p_hwfn->p_dev->num_ports_in_engines);
3175
3176                 /* Default num_ports_in_engines to something */
3177                 p_hwfn->p_dev->num_ports_in_engines = 1;
3178         }
3179 }
3180
3181 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3182                                          struct ecore_ptt *p_ptt)
3183 {
3184         u32 port;
3185         int i;
3186
3187         p_hwfn->p_dev->num_ports_in_engines = 0;
3188
3189 #ifndef ASIC_ONLY
3190         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3191                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3192                 switch ((port & 0xf000) >> 12) {
3193                 case 1:
3194                         p_hwfn->p_dev->num_ports_in_engines = 1;
3195                         break;
3196                 case 3:
3197                         p_hwfn->p_dev->num_ports_in_engines = 2;
3198                         break;
3199                 case 0xf:
3200                         p_hwfn->p_dev->num_ports_in_engines = 4;
3201                         break;
3202                 default:
3203                         DP_NOTICE(p_hwfn, false,
3204                                   "Unknown port mode in ECO_RESERVED %08x\n",
3205                                   port);
3206                 }
3207         } else
3208 #endif
3209                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3210                         port = ecore_rd(p_hwfn, p_ptt,
3211                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3212                                         (i * 4));
3213                         if (port & 1)
3214                                 p_hwfn->p_dev->num_ports_in_engines++;
3215                 }
3216 }
3217
3218 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3219                                    struct ecore_ptt *p_ptt)
3220 {
3221         if (ECORE_IS_BB(p_hwfn->p_dev))
3222                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3223         else
3224                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3225 }
3226
3227 static enum _ecore_status_t
3228 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3229                   enum ecore_pci_personality personality,
3230                   struct ecore_hw_prepare_params *p_params)
3231 {
3232         bool drv_resc_alloc = p_params->drv_resc_alloc;
3233         enum _ecore_status_t rc;
3234
3235         /* Since all information is common, only first hwfns should do this */
3236         if (IS_LEAD_HWFN(p_hwfn)) {
3237                 rc = ecore_iov_hw_info(p_hwfn);
3238                 if (rc != ECORE_SUCCESS) {
3239                         if (p_params->b_relaxed_probe)
3240                                 p_params->p_relaxed_res =
3241                                                 ECORE_HW_PREPARE_BAD_IOV;
3242                         else
3243                                 return rc;
3244                 }
3245         }
3246
3247         /* TODO In get_hw_info, amoungst others:
3248          * Get MCP FW revision and determine according to it the supported
3249          * featrues (e.g. DCB)
3250          * Get boot mode
3251          * ecore_get_pcie_width_speed, WOL capability.
3252          * Number of global CQ-s (for storage
3253          */
3254         ecore_hw_info_port_num(p_hwfn, p_ptt);
3255
3256 #ifndef ASIC_ONLY
3257         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3258 #endif
3259         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3260         if (rc != ECORE_SUCCESS)
3261                 return rc;
3262 #ifndef ASIC_ONLY
3263         }
3264 #endif
3265
3266         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3267         if (rc != ECORE_SUCCESS) {
3268                 if (p_params->b_relaxed_probe)
3269                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3270                 else
3271                         return rc;
3272         }
3273
3274 #ifndef ASIC_ONLY
3275         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3276 #endif
3277                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3278                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3279 #ifndef ASIC_ONLY
3280         } else {
3281                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3282
3283                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3284                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3285         }
3286 #endif
3287
3288         if (ecore_mcp_is_init(p_hwfn)) {
3289                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3290                         p_hwfn->hw_info.ovlan =
3291                             p_hwfn->mcp_info->func_info.ovlan;
3292
3293                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3294         }
3295
3296         if (personality != ECORE_PCI_DEFAULT) {
3297                 p_hwfn->hw_info.personality = personality;
3298         } else if (ecore_mcp_is_init(p_hwfn)) {
3299                 enum ecore_pci_personality protocol;
3300
3301                 protocol = p_hwfn->mcp_info->func_info.protocol;
3302                 p_hwfn->hw_info.personality = protocol;
3303         }
3304
3305 #ifndef ASIC_ONLY
3306         /* To overcome ILT lack for emulation, until at least until we'll have
3307          * a definite answer from system about it, allow only PF0 to be RoCE.
3308          */
3309         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3310                 if (!p_hwfn->rel_pf_id)
3311                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3312                 else
3313                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3314         }
3315 #endif
3316
3317         /* although in BB some constellations may support more than 4 tcs,
3318          * that can result in performance penalty in some cases. 4
3319          * represents a good tradeoff between performance and flexibility.
3320          */
3321         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3322
3323         /* start out with a single active tc. This can be increased either
3324          * by dcbx negotiation or by upper layer driver
3325          */
3326         p_hwfn->hw_info.num_active_tc = 1;
3327
3328         ecore_get_num_funcs(p_hwfn, p_ptt);
3329
3330         if (ecore_mcp_is_init(p_hwfn))
3331                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3332
3333         /* In case of forcing the driver's default resource allocation, calling
3334          * ecore_hw_get_resc() should come after initializing the personality
3335          * and after getting the number of functions, since the calculation of
3336          * the resources/features depends on them.
3337          * This order is not harmful if not forcing.
3338          */
3339         rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3340         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3341                 rc = ECORE_SUCCESS;
3342                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3343         }
3344
3345         return rc;
3346 }
3347
3348 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3349 {
3350         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3351         u32 tmp;
3352
3353         /* Read Vendor Id / Device Id */
3354         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3355                                   &p_dev->vendor_id);
3356         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3357                                   &p_dev->device_id);
3358
3359         /* Determine type */
3360         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
3361                 p_dev->type = ECORE_DEV_TYPE_AH;
3362         else
3363                 p_dev->type = ECORE_DEV_TYPE_BB;
3364
3365         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3366                                          MISCS_REG_CHIP_NUM);
3367         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3368                                          MISCS_REG_CHIP_REV);
3369
3370         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3371
3372         /* Learn number of HW-functions */
3373         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3374                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
3375
3376         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3377                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3378                 p_dev->num_hwfns = 2;
3379         } else {
3380                 p_dev->num_hwfns = 1;
3381         }
3382
3383 #ifndef ASIC_ONLY
3384         if (CHIP_REV_IS_EMUL(p_dev)) {
3385                 /* For some reason we have problems with this register
3386                  * in B0 emulation; Simply assume no CMT
3387                  */
3388                 DP_NOTICE(p_dev->hwfns, false,
3389                           "device on emul - assume no CMT\n");
3390                 p_dev->num_hwfns = 1;
3391         }
3392 #endif
3393
3394         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3395                                        MISCS_REG_CHIP_TEST_REG) >> 4;
3396         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3397         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3398                                            MISCS_REG_CHIP_METAL);
3399         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3400         DP_INFO(p_dev->hwfns,
3401                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3402                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3403                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3404                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3405                 p_dev->chip_metal);
3406
3407         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3408                 DP_NOTICE(p_dev->hwfns, false,
3409                           "The chip type/rev (BB A0) is not supported!\n");
3410                 return ECORE_ABORTED;
3411         }
3412 #ifndef ASIC_ONLY
3413         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3414                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3415                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3416
3417         if (CHIP_REV_IS_EMUL(p_dev)) {
3418                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3419                                MISCS_REG_ECO_RESERVED);
3420                 if (tmp & (1 << 29)) {
3421                         DP_NOTICE(p_hwfn, false,
3422                                   "Emulation: Running on a FULL build\n");
3423                         p_dev->b_is_emul_full = true;
3424                 } else {
3425                         DP_NOTICE(p_hwfn, false,
3426                                   "Emulation: Running on a REDUCED build\n");
3427                 }
3428         }
3429 #endif
3430
3431         return ECORE_SUCCESS;
3432 }
3433
3434 #ifndef LINUX_REMOVE
3435 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3436 {
3437         int j;
3438
3439         if (IS_VF(p_dev))
3440                 return;
3441
3442         for_each_hwfn(p_dev, j) {
3443                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3444
3445                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3446                            "Mark hw/fw uninitialized\n");
3447
3448                 p_hwfn->hw_init_done = false;
3449                 p_hwfn->first_on_engine = false;
3450
3451                 ecore_ptt_invalidate(p_hwfn);
3452         }
3453 }
3454 #endif
3455
3456 static enum _ecore_status_t
3457 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3458                         void OSAL_IOMEM * p_regview,
3459                         void OSAL_IOMEM * p_doorbells,
3460                         struct ecore_hw_prepare_params *p_params)
3461 {
3462         struct ecore_dev *p_dev = p_hwfn->p_dev;
3463         struct ecore_mdump_info mdump_info;
3464         enum _ecore_status_t rc = ECORE_SUCCESS;
3465
3466         /* Split PCI bars evenly between hwfns */
3467         p_hwfn->regview = p_regview;
3468         p_hwfn->doorbells = p_doorbells;
3469
3470         if (IS_VF(p_dev))
3471                 return ecore_vf_hw_prepare(p_hwfn);
3472
3473         /* Validate that chip access is feasible */
3474         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3475                 DP_ERR(p_hwfn,
3476                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3477                 if (p_params->b_relaxed_probe)
3478                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3479                 return ECORE_INVAL;
3480         }
3481
3482         get_function_id(p_hwfn);
3483
3484         /* Allocate PTT pool */
3485         rc = ecore_ptt_pool_alloc(p_hwfn);
3486         if (rc) {
3487                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3488                 if (p_params->b_relaxed_probe)
3489                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3490                 goto err0;
3491         }
3492
3493         /* Allocate the main PTT */
3494         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3495
3496         /* First hwfn learns basic information, e.g., number of hwfns */
3497         if (!p_hwfn->my_id) {
3498                 rc = ecore_get_dev_info(p_dev);
3499                 if (rc != ECORE_SUCCESS) {
3500                         if (p_params->b_relaxed_probe)
3501                                 p_params->p_relaxed_res =
3502                                         ECORE_HW_PREPARE_FAILED_DEV;
3503                         goto err1;
3504                 }
3505         }
3506
3507         ecore_hw_hwfn_prepare(p_hwfn);
3508
3509         /* Initialize MCP structure */
3510         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3511         if (rc) {
3512                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3513                 if (p_params->b_relaxed_probe)
3514                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3515                 goto err1;
3516         }
3517
3518         /* Read the device configuration information from the HW and SHMEM */
3519         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3520                                p_params->personality, p_params);
3521         if (rc) {
3522                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3523                 goto err2;
3524         }
3525
3526         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3527          * called, since among others it sets the ports number in an engine.
3528          */
3529         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3530             !p_dev->recov_in_prog) {
3531                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3532                 if (rc != ECORE_SUCCESS)
3533                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3534         }
3535
3536         /* Check if mdump logs are present and update the epoch value */
3537         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3538                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3539                                               &mdump_info);
3540                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3541                         DP_NOTICE(p_hwfn, false,
3542                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3543                 }
3544
3545                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3546                                            p_params->epoch);
3547         }
3548
3549         /* Allocate the init RT array and initialize the init-ops engine */
3550         rc = ecore_init_alloc(p_hwfn);
3551         if (rc) {
3552                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3553                 if (p_params->b_relaxed_probe)
3554                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3555                 goto err2;
3556         }
3557 #ifndef ASIC_ONLY
3558         if (CHIP_REV_IS_FPGA(p_dev)) {
3559                 DP_NOTICE(p_hwfn, false,
3560                           "FPGA: workaround; Prevent DMAE parities\n");
3561                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3562                          7);
3563
3564                 DP_NOTICE(p_hwfn, false,
3565                           "FPGA: workaround: Set VF bar0 size\n");
3566                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3567                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3568         }
3569 #endif
3570
3571         return rc;
3572 err2:
3573         if (IS_LEAD_HWFN(p_hwfn))
3574                 ecore_iov_free_hw_info(p_dev);
3575         ecore_mcp_free(p_hwfn);
3576 err1:
3577         ecore_hw_hwfn_free(p_hwfn);
3578 err0:
3579         return rc;
3580 }
3581
3582 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3583                                       struct ecore_hw_prepare_params *p_params)
3584 {
3585         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3586         enum _ecore_status_t rc;
3587
3588         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3589         p_dev->allow_mdump = p_params->allow_mdump;
3590
3591         if (p_params->b_relaxed_probe)
3592                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3593
3594         /* Store the precompiled init data ptrs */
3595         if (IS_PF(p_dev))
3596                 ecore_init_iro_array(p_dev);
3597
3598         /* Initialize the first hwfn - will learn number of hwfns */
3599         rc = ecore_hw_prepare_single(p_hwfn,
3600                                      p_dev->regview,
3601                                      p_dev->doorbells, p_params);
3602         if (rc != ECORE_SUCCESS)
3603                 return rc;
3604
3605         p_params->personality = p_hwfn->hw_info.personality;
3606
3607         /* initilalize 2nd hwfn if necessary */
3608         if (p_dev->num_hwfns > 1) {
3609                 void OSAL_IOMEM *p_regview, *p_doorbell;
3610                 u8 OSAL_IOMEM *addr;
3611
3612                 /* adjust bar offset for second engine */
3613                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3614                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3615                 p_regview = (void OSAL_IOMEM *)addr;
3616
3617                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3618                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3619                 p_doorbell = (void OSAL_IOMEM *)addr;
3620
3621                 /* prepare second hw function */
3622                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3623                                              p_doorbell, p_params);
3624
3625                 /* in case of error, need to free the previously
3626                  * initiliazed hwfn 0.
3627                  */
3628                 if (rc != ECORE_SUCCESS) {
3629                         if (p_params->b_relaxed_probe)
3630                                 p_params->p_relaxed_res =
3631                                                 ECORE_HW_PREPARE_FAILED_ENG2;
3632
3633                         if (IS_PF(p_dev)) {
3634                                 ecore_init_free(p_hwfn);
3635                                 ecore_mcp_free(p_hwfn);
3636                                 ecore_hw_hwfn_free(p_hwfn);
3637                         } else {
3638                                 DP_NOTICE(p_dev, true,
3639                                           "What do we need to free when VF hwfn1 init fails\n");
3640                         }
3641                         return rc;
3642                 }
3643         }
3644
3645         return rc;
3646 }
3647
3648 void ecore_hw_remove(struct ecore_dev *p_dev)
3649 {
3650         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3651         int i;
3652
3653         if (IS_PF(p_dev))
3654                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3655                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3656
3657         for_each_hwfn(p_dev, i) {
3658                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3659
3660                 if (IS_VF(p_dev)) {
3661                         ecore_vf_pf_release(p_hwfn);
3662                         continue;
3663                 }
3664
3665                 ecore_init_free(p_hwfn);
3666                 ecore_hw_hwfn_free(p_hwfn);
3667                 ecore_mcp_free(p_hwfn);
3668
3669                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3670         }
3671
3672         ecore_iov_free_hw_info(p_dev);
3673 }
3674
3675 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3676                                       struct ecore_chain *p_chain)
3677 {
3678         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3679         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3680         struct ecore_chain_next *p_next;
3681         u32 size, i;
3682
3683         if (!p_virt)
3684                 return;
3685
3686         size = p_chain->elem_size * p_chain->usable_per_page;
3687
3688         for (i = 0; i < p_chain->page_cnt; i++) {
3689                 if (!p_virt)
3690                         break;
3691
3692                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3693                 p_virt_next = p_next->next_virt;
3694                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3695
3696                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3697                                        ECORE_CHAIN_PAGE_SIZE);
3698
3699                 p_virt = p_virt_next;
3700                 p_phys = p_phys_next;
3701         }
3702 }
3703
3704 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3705                                     struct ecore_chain *p_chain)
3706 {
3707         if (!p_chain->p_virt_addr)
3708                 return;
3709
3710         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3711                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3712 }
3713
3714 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3715                                  struct ecore_chain *p_chain)
3716 {
3717         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3718         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3719         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3720
3721         if (!pp_virt_addr_tbl)
3722                 return;
3723
3724         if (!p_pbl_virt)
3725                 goto out;
3726
3727         for (i = 0; i < page_cnt; i++) {
3728                 if (!pp_virt_addr_tbl[i])
3729                         break;
3730
3731                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3732                                        *(dma_addr_t *)p_pbl_virt,
3733                                        ECORE_CHAIN_PAGE_SIZE);
3734
3735                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3736         }
3737
3738         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3739
3740         if (!p_chain->b_external_pbl)
3741                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3742                                        p_chain->pbl_sp.p_phys_table, pbl_size);
3743 out:
3744         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3745 }
3746
3747 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3748 {
3749         switch (p_chain->mode) {
3750         case ECORE_CHAIN_MODE_NEXT_PTR:
3751                 ecore_chain_free_next_ptr(p_dev, p_chain);
3752                 break;
3753         case ECORE_CHAIN_MODE_SINGLE:
3754                 ecore_chain_free_single(p_dev, p_chain);
3755                 break;
3756         case ECORE_CHAIN_MODE_PBL:
3757                 ecore_chain_free_pbl(p_dev, p_chain);
3758                 break;
3759         }
3760 }
3761
3762 static enum _ecore_status_t
3763 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3764                                enum ecore_chain_cnt_type cnt_type,
3765                                osal_size_t elem_size, u32 page_cnt)
3766 {
3767         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3768
3769         /* The actual chain size can be larger than the maximal possible value
3770          * after rounding up the requested elements number to pages, and after
3771          * taking into acount the unusuable elements (next-ptr elements).
3772          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3773          * size/capacity fields are of a u32 type.
3774          */
3775         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3776              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3777             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3778              chain_size > ECORE_U32_MAX)) {
3779                 DP_NOTICE(p_dev, true,
3780                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3781                           (unsigned long)chain_size);
3782                 return ECORE_INVAL;
3783         }
3784
3785         return ECORE_SUCCESS;
3786 }
3787
3788 static enum _ecore_status_t
3789 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3790 {
3791         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3792         dma_addr_t p_phys = 0;
3793         u32 i;
3794
3795         for (i = 0; i < p_chain->page_cnt; i++) {
3796                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3797                                                  ECORE_CHAIN_PAGE_SIZE);
3798                 if (!p_virt) {
3799                         DP_NOTICE(p_dev, true,
3800                                   "Failed to allocate chain memory\n");
3801                         return ECORE_NOMEM;
3802                 }
3803
3804                 if (i == 0) {
3805                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3806                         ecore_chain_reset(p_chain);
3807                 } else {
3808                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3809                                                        p_virt, p_phys);
3810                 }
3811
3812                 p_virt_prev = p_virt;
3813         }
3814         /* Last page's next element should point to the beginning of the
3815          * chain.
3816          */
3817         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3818                                        p_chain->p_virt_addr,
3819                                        p_chain->p_phys_addr);
3820
3821         return ECORE_SUCCESS;
3822 }
3823
3824 static enum _ecore_status_t
3825 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3826 {
3827         dma_addr_t p_phys = 0;
3828         void *p_virt = OSAL_NULL;
3829
3830         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3831         if (!p_virt) {
3832                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3833                 return ECORE_NOMEM;
3834         }
3835
3836         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3837         ecore_chain_reset(p_chain);
3838
3839         return ECORE_SUCCESS;
3840 }
3841
3842 static enum _ecore_status_t
3843 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3844                       struct ecore_chain *p_chain,
3845                       struct ecore_chain_ext_pbl *ext_pbl)
3846 {
3847         void *p_virt = OSAL_NULL;
3848         u8 *p_pbl_virt = OSAL_NULL;
3849         void **pp_virt_addr_tbl = OSAL_NULL;
3850         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3851         u32 page_cnt = p_chain->page_cnt, size, i;
3852
3853         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3854         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
3855         if (!pp_virt_addr_tbl) {
3856                 DP_NOTICE(p_dev, true,
3857                           "Failed to allocate memory for the chain virtual addresses table\n");
3858                 return ECORE_NOMEM;
3859         }
3860
3861         /* The allocation of the PBL table is done with its full size, since it
3862          * is expected to be successive.
3863          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3864          * failure, since pp_virt_addr_tbl was previously allocated, and it
3865          * should be saved to allow its freeing during the error flow.
3866          */
3867         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3868
3869         if (ext_pbl == OSAL_NULL) {
3870                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3871         } else {
3872                 p_pbl_virt = ext_pbl->p_pbl_virt;
3873                 p_pbl_phys = ext_pbl->p_pbl_phys;
3874                 p_chain->b_external_pbl = true;
3875         }
3876
3877         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3878                                  pp_virt_addr_tbl);
3879         if (!p_pbl_virt) {
3880                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3881                 return ECORE_NOMEM;
3882         }
3883
3884         for (i = 0; i < page_cnt; i++) {
3885                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3886                                                  ECORE_CHAIN_PAGE_SIZE);
3887                 if (!p_virt) {
3888                         DP_NOTICE(p_dev, true,
3889                                   "Failed to allocate chain memory\n");
3890                         return ECORE_NOMEM;
3891                 }
3892
3893                 if (i == 0) {
3894                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3895                         ecore_chain_reset(p_chain);
3896                 }
3897
3898                 /* Fill the PBL table with the physical address of the page */
3899                 *(dma_addr_t *)p_pbl_virt = p_phys;
3900                 /* Keep the virtual address of the page */
3901                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3902
3903                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3904         }
3905
3906         return ECORE_SUCCESS;
3907 }
3908
3909 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3910                                        enum ecore_chain_use_mode intended_use,
3911                                        enum ecore_chain_mode mode,
3912                                        enum ecore_chain_cnt_type cnt_type,
3913                                        u32 num_elems, osal_size_t elem_size,
3914                                        struct ecore_chain *p_chain,
3915                                        struct ecore_chain_ext_pbl *ext_pbl)
3916 {
3917         u32 page_cnt;
3918         enum _ecore_status_t rc = ECORE_SUCCESS;
3919
3920         if (mode == ECORE_CHAIN_MODE_SINGLE)
3921                 page_cnt = 1;
3922         else
3923                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3924
3925         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3926                                             page_cnt);
3927         if (rc) {
3928                 DP_NOTICE(p_dev, true,
3929                           "Cannot allocate a chain with the given arguments:\n"
3930                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3931                           intended_use, mode, cnt_type, num_elems, elem_size);
3932                 return rc;
3933         }
3934
3935         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3936                                 mode, cnt_type, p_dev->dp_ctx);
3937
3938         switch (mode) {
3939         case ECORE_CHAIN_MODE_NEXT_PTR:
3940                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3941                 break;
3942         case ECORE_CHAIN_MODE_SINGLE:
3943                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3944                 break;
3945         case ECORE_CHAIN_MODE_PBL:
3946                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3947                 break;
3948         }
3949         if (rc)
3950                 goto nomem;
3951
3952         return ECORE_SUCCESS;
3953
3954 nomem:
3955         ecore_chain_free(p_dev, p_chain);
3956         return rc;
3957 }
3958
3959 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3960                                        u16 src_id, u16 *dst_id)
3961 {
3962         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3963                 u16 min, max;
3964
3965                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3966                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3967                 DP_NOTICE(p_hwfn, true,
3968                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3969                           src_id, min, max);
3970
3971                 return ECORE_INVAL;
3972         }
3973
3974         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3975
3976         return ECORE_SUCCESS;
3977 }
3978
3979 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3980                                     u8 src_id, u8 *dst_id)
3981 {
3982         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3983                 u8 min, max;
3984
3985                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3986                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3987                 DP_NOTICE(p_hwfn, true,
3988                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3989                           src_id, min, max);
3990
3991                 return ECORE_INVAL;
3992         }
3993
3994         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3995
3996         return ECORE_SUCCESS;
3997 }
3998
3999 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4000                                       u8 src_id, u8 *dst_id)
4001 {
4002         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4003                 u8 min, max;
4004
4005                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4006                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4007                 DP_NOTICE(p_hwfn, true,
4008                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4009                           src_id, min, max);
4010
4011                 return ECORE_INVAL;
4012         }
4013
4014         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4015
4016         return ECORE_SUCCESS;
4017 }
4018
4019 static enum _ecore_status_t
4020 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4021                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4022                                u32 *p_entry_num)
4023 {
4024         u32 en;
4025         int i;
4026
4027         /* Find a free entry and utilize it */
4028         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4029                 en = ecore_rd(p_hwfn, p_ptt,
4030                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4031                               i * sizeof(u32));
4032                 if (en)
4033                         continue;
4034                 ecore_wr(p_hwfn, p_ptt,
4035                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4036                          2 * i * sizeof(u32), low);
4037                 ecore_wr(p_hwfn, p_ptt,
4038                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4039                          (2 * i + 1) * sizeof(u32), high);
4040                 ecore_wr(p_hwfn, p_ptt,
4041                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4042                          i * sizeof(u32), 0);
4043                 ecore_wr(p_hwfn, p_ptt,
4044                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4045                          i * sizeof(u32), 0);
4046                 ecore_wr(p_hwfn, p_ptt,
4047                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4048                          i * sizeof(u32), 1);
4049                 break;
4050         }
4051
4052         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4053                 return ECORE_NORESOURCES;
4054
4055         *p_entry_num = i;
4056
4057         return ECORE_SUCCESS;
4058 }
4059
4060 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4061                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4062 {
4063         u32 high, low, entry_num;
4064         enum _ecore_status_t rc;
4065
4066         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4067                 return ECORE_SUCCESS;
4068
4069         high = p_filter[1] | (p_filter[0] << 8);
4070         low = p_filter[5] | (p_filter[4] << 8) |
4071               (p_filter[3] << 16) | (p_filter[2] << 24);
4072
4073         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4074                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4075                                                     &entry_num);
4076         if (rc != ECORE_SUCCESS) {
4077                 DP_NOTICE(p_hwfn, false,
4078                           "Failed to find an empty LLH filter to utilize\n");
4079                 return rc;
4080         }
4081
4082         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4083                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4084                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4085                    p_filter[4], p_filter[5], entry_num);
4086
4087         return ECORE_SUCCESS;
4088 }
4089
4090 static enum _ecore_status_t
4091 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4092                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4093                                   u32 *p_entry_num)
4094 {
4095         int i;
4096
4097         /* Find the entry and clean it */
4098         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4099                 if (ecore_rd(p_hwfn, p_ptt,
4100                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4101                              2 * i * sizeof(u32)) != low)
4102                         continue;
4103                 if (ecore_rd(p_hwfn, p_ptt,
4104                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4105                              (2 * i + 1) * sizeof(u32)) != high)
4106                         continue;
4107
4108                 ecore_wr(p_hwfn, p_ptt,
4109                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4110                 ecore_wr(p_hwfn, p_ptt,
4111                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4112                          2 * i * sizeof(u32), 0);
4113                 ecore_wr(p_hwfn, p_ptt,
4114                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4115                          (2 * i + 1) * sizeof(u32), 0);
4116                 break;
4117         }
4118
4119         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4120                 return ECORE_INVAL;
4121
4122         *p_entry_num = i;
4123
4124         return ECORE_SUCCESS;
4125 }
4126
4127 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4128                              struct ecore_ptt *p_ptt, u8 *p_filter)
4129 {
4130         u32 high, low, entry_num;
4131         enum _ecore_status_t rc;
4132
4133         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4134                 return;
4135
4136         high = p_filter[1] | (p_filter[0] << 8);
4137         low = p_filter[5] | (p_filter[4] << 8) |
4138               (p_filter[3] << 16) | (p_filter[2] << 24);
4139
4140         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4141                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4142                                                        low, &entry_num);
4143         if (rc != ECORE_SUCCESS) {
4144                 DP_NOTICE(p_hwfn, false,
4145                           "Tried to remove a non-configured filter\n");
4146                 return;
4147         }
4148
4149
4150         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4151                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4152                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4153                    p_filter[4], p_filter[5], entry_num);
4154 }
4155
4156 static enum _ecore_status_t
4157 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4158                                     struct ecore_ptt *p_ptt,
4159                                     enum ecore_llh_port_filter_type_t type,
4160                                     u32 high, u32 low, u32 *p_entry_num)
4161 {
4162         u32 en;
4163         int i;
4164
4165         /* Find a free entry and utilize it */
4166         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4167                 en = ecore_rd(p_hwfn, p_ptt,
4168                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4169                               i * sizeof(u32));
4170                 if (en)
4171                         continue;
4172                 ecore_wr(p_hwfn, p_ptt,
4173                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4174                          2 * i * sizeof(u32), low);
4175                 ecore_wr(p_hwfn, p_ptt,
4176                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4177                          (2 * i + 1) * sizeof(u32), high);
4178                 ecore_wr(p_hwfn, p_ptt,
4179                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4180                          i * sizeof(u32), 1);
4181                 ecore_wr(p_hwfn, p_ptt,
4182                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4183                          i * sizeof(u32), 1 << type);
4184                 ecore_wr(p_hwfn, p_ptt,
4185                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4186                 break;
4187         }
4188
4189         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4190                 return ECORE_NORESOURCES;
4191
4192         *p_entry_num = i;
4193
4194         return ECORE_SUCCESS;
4195 }
4196
4197 enum _ecore_status_t
4198 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4199                               struct ecore_ptt *p_ptt,
4200                               u16 source_port_or_eth_type,
4201                               u16 dest_port,
4202                               enum ecore_llh_port_filter_type_t type)
4203 {
4204         u32 high, low, entry_num;
4205         enum _ecore_status_t rc;
4206
4207         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4208                 return ECORE_SUCCESS;
4209
4210         high = 0;
4211         low = 0;
4212
4213         switch (type) {
4214         case ECORE_LLH_FILTER_ETHERTYPE:
4215                 high = source_port_or_eth_type;
4216                 break;
4217         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4218         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4219                 low = source_port_or_eth_type << 16;
4220                 break;
4221         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4222         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4223                 low = dest_port;
4224                 break;
4225         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4226         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4227                 low = (source_port_or_eth_type << 16) | dest_port;
4228                 break;
4229         default:
4230                 DP_NOTICE(p_hwfn, true,
4231                           "Non valid LLH protocol filter type %d\n", type);
4232                 return ECORE_INVAL;
4233         }
4234
4235         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4236                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4237                                                          high, low, &entry_num);
4238         if (rc != ECORE_SUCCESS) {
4239                 DP_NOTICE(p_hwfn, false,
4240                           "Failed to find an empty LLH filter to utilize\n");
4241                 return rc;
4242         }
4243         switch (type) {
4244         case ECORE_LLH_FILTER_ETHERTYPE:
4245                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4246                            "ETH type %x is added at %d\n",
4247                            source_port_or_eth_type, entry_num);
4248                 break;
4249         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4250                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4251                            "TCP src port %x is added at %d\n",
4252                            source_port_or_eth_type, entry_num);
4253                 break;
4254         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4255                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4256                            "UDP src port %x is added at %d\n",
4257                            source_port_or_eth_type, entry_num);
4258                 break;
4259         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4260                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4261                            "TCP dst port %x is added at %d\n", dest_port,
4262                            entry_num);
4263                 break;
4264         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4265                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4266                            "UDP dst port %x is added at %d\n", dest_port,
4267                            entry_num);
4268                 break;
4269         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4270                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4271                            "TCP src/dst ports %x/%x are added at %d\n",
4272                            source_port_or_eth_type, dest_port, entry_num);
4273                 break;
4274         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4275                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4276                            "UDP src/dst ports %x/%x are added at %d\n",
4277                            source_port_or_eth_type, dest_port, entry_num);
4278                 break;
4279         }
4280
4281         return ECORE_SUCCESS;
4282 }
4283
4284 static enum _ecore_status_t
4285 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4286                                        struct ecore_ptt *p_ptt,
4287                                        enum ecore_llh_port_filter_type_t type,
4288                                        u32 high, u32 low, u32 *p_entry_num)
4289 {
4290         int i;
4291
4292         /* Find the entry and clean it */
4293         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4294                 if (!ecore_rd(p_hwfn, p_ptt,
4295                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4296                               i * sizeof(u32)))
4297                         continue;
4298                 if (!ecore_rd(p_hwfn, p_ptt,
4299                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4300                               i * sizeof(u32)))
4301                         continue;
4302                 if (!(ecore_rd(p_hwfn, p_ptt,
4303                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4304                                i * sizeof(u32)) & (1 << type)))
4305                         continue;
4306                 if (ecore_rd(p_hwfn, p_ptt,
4307                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4308                              2 * i * sizeof(u32)) != low)
4309                         continue;
4310                 if (ecore_rd(p_hwfn, p_ptt,
4311                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4312                              (2 * i + 1) * sizeof(u32)) != high)
4313                         continue;
4314
4315                 ecore_wr(p_hwfn, p_ptt,
4316                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4317                 ecore_wr(p_hwfn, p_ptt,
4318                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4319                          i * sizeof(u32), 0);
4320                 ecore_wr(p_hwfn, p_ptt,
4321                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4322                          i * sizeof(u32), 0);
4323                 ecore_wr(p_hwfn, p_ptt,
4324                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4325                          2 * i * sizeof(u32), 0);
4326                 ecore_wr(p_hwfn, p_ptt,
4327                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4328                          (2 * i + 1) * sizeof(u32), 0);
4329                 break;
4330         }
4331
4332         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4333                 return ECORE_INVAL;
4334
4335         *p_entry_num = i;
4336
4337         return ECORE_SUCCESS;
4338 }
4339
4340 void
4341 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4342                                  struct ecore_ptt *p_ptt,
4343                                  u16 source_port_or_eth_type,
4344                                  u16 dest_port,
4345                                  enum ecore_llh_port_filter_type_t type)
4346 {
4347         u32 high, low, entry_num;
4348         enum _ecore_status_t rc;
4349
4350         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4351                 return;
4352
4353         high = 0;
4354         low = 0;
4355
4356         switch (type) {
4357         case ECORE_LLH_FILTER_ETHERTYPE:
4358                 high = source_port_or_eth_type;
4359                 break;
4360         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4361         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4362                 low = source_port_or_eth_type << 16;
4363                 break;
4364         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4365         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4366                 low = dest_port;
4367                 break;
4368         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4369         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4370                 low = (source_port_or_eth_type << 16) | dest_port;
4371                 break;
4372         default:
4373                 DP_NOTICE(p_hwfn, true,
4374                           "Non valid LLH protocol filter type %d\n", type);
4375                 return;
4376         }
4377
4378         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4379                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4380                                                             high, low,
4381                                                             &entry_num);
4382         if (rc != ECORE_SUCCESS) {
4383                 DP_NOTICE(p_hwfn, false,
4384                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4385                           type, source_port_or_eth_type, dest_port);
4386                 return;
4387         }
4388
4389         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4390                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4391                    type, source_port_or_eth_type, dest_port, entry_num);
4392 }
4393
4394 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4395                                               struct ecore_ptt *p_ptt)
4396 {
4397         int i;
4398
4399         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4400                 return;
4401
4402         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4403                 ecore_wr(p_hwfn, p_ptt,
4404                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
4405                          i * sizeof(u32), 0);
4406                 ecore_wr(p_hwfn, p_ptt,
4407                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4408                          2 * i * sizeof(u32), 0);
4409                 ecore_wr(p_hwfn, p_ptt,
4410                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4411                          (2 * i + 1) * sizeof(u32), 0);
4412         }
4413 }
4414
4415 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4416                              struct ecore_ptt *p_ptt)
4417 {
4418         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4419                 return;
4420
4421         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4422                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
4423 }
4424
4425 enum _ecore_status_t
4426 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4427                                   struct ecore_ptt *p_ptt)
4428 {
4429         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4430                 ecore_wr(p_hwfn, p_ptt,
4431                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4432                          1 << p_hwfn->abs_pf_id / 2);
4433                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4434                 return ECORE_SUCCESS;
4435         }
4436
4437         DP_NOTICE(p_hwfn, false,
4438                   "This function can't be set as default\n");
4439         return ECORE_INVAL;
4440 }
4441
4442 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4443                                                struct ecore_ptt *p_ptt,
4444                                                u32 hw_addr, void *p_eth_qzone,
4445                                                osal_size_t eth_qzone_size,
4446                                                u8 timeset)
4447 {
4448         struct coalescing_timeset *p_coal_timeset;
4449
4450         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4451                 DP_NOTICE(p_hwfn, true,
4452                           "Coalescing configuration not enabled\n");
4453                 return ECORE_INVAL;
4454         }
4455
4456         p_coal_timeset = p_eth_qzone;
4457         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4458         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4459         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4460         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4461
4462         return ECORE_SUCCESS;
4463 }
4464
4465 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4466                                               u16 rx_coal, u16 tx_coal,
4467                                               void *p_handle)
4468 {
4469         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
4470         enum _ecore_status_t rc = ECORE_SUCCESS;
4471         struct ecore_ptt *p_ptt;
4472
4473         /* TODO - Configuring a single queue's coalescing but
4474          * claiming all queues are abiding same configuration
4475          * for PF and VF both.
4476          */
4477
4478         if (IS_VF(p_hwfn->p_dev))
4479                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
4480                                                 tx_coal, p_cid);
4481
4482         p_ptt = ecore_ptt_acquire(p_hwfn);
4483         if (!p_ptt)
4484                 return ECORE_AGAIN;
4485
4486         if (rx_coal) {
4487                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4488                 if (rc)
4489                         goto out;
4490                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
4491         }
4492
4493         if (tx_coal) {
4494                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4495                 if (rc)
4496                         goto out;
4497                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
4498         }
4499 out:
4500         ecore_ptt_release(p_hwfn, p_ptt);
4501
4502         return rc;
4503 }
4504
4505 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4506                                             struct ecore_ptt *p_ptt,
4507                                             u16 coalesce,
4508                                             struct ecore_queue_cid *p_cid)
4509 {
4510         struct ustorm_eth_queue_zone eth_qzone;
4511         u8 timeset, timer_res;
4512         u32 address;
4513         enum _ecore_status_t rc;
4514
4515         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4516         if (coalesce <= 0x7F) {
4517                 timer_res = 0;
4518         } else if (coalesce <= 0xFF) {
4519                 timer_res = 1;
4520         } else if (coalesce <= 0x1FF) {
4521                 timer_res = 2;
4522         } else {
4523                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4524                 return ECORE_INVAL;
4525         }
4526         timeset = (u8)(coalesce >> timer_res);
4527
4528         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4529                                      p_cid->abs.sb_idx, false);
4530         if (rc != ECORE_SUCCESS)
4531                 goto out;
4532
4533         address = BAR0_MAP_REG_USDM_RAM +
4534                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4535
4536         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4537                                 sizeof(struct ustorm_eth_queue_zone), timeset);
4538         if (rc != ECORE_SUCCESS)
4539                 goto out;
4540
4541 out:
4542         return rc;
4543 }
4544
4545 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4546                                             struct ecore_ptt *p_ptt,
4547                                             u16 coalesce,
4548                                             struct ecore_queue_cid *p_cid)
4549 {
4550         struct xstorm_eth_queue_zone eth_qzone;
4551         u8 timeset, timer_res;
4552         u32 address;
4553         enum _ecore_status_t rc;
4554
4555         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4556         if (coalesce <= 0x7F) {
4557                 timer_res = 0;
4558         } else if (coalesce <= 0xFF) {
4559                 timer_res = 1;
4560         } else if (coalesce <= 0x1FF) {
4561                 timer_res = 2;
4562         } else {
4563                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4564                 return ECORE_INVAL;
4565         }
4566
4567         timeset = (u8)(coalesce >> timer_res);
4568
4569         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4570                                      p_cid->abs.sb_idx, true);
4571         if (rc != ECORE_SUCCESS)
4572                 goto out;
4573
4574         address = BAR0_MAP_REG_XSDM_RAM +
4575                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4576
4577         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4578                                 sizeof(struct xstorm_eth_queue_zone), timeset);
4579 out:
4580         return rc;
4581 }
4582
4583 /* Calculate final WFQ values for all vports and configure it.
4584  * After this configuration each vport must have
4585  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4586  */
4587 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4588                                                struct ecore_ptt *p_ptt,
4589                                                u32 min_pf_rate)
4590 {
4591         struct init_qm_vport_params *vport_params;
4592         int i;
4593
4594         vport_params = p_hwfn->qm_info.qm_vport_params;
4595
4596         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4597                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4598
4599                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4600                     min_pf_rate;
4601                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4602                                      vport_params[i].first_tx_pq_id,
4603                                      vport_params[i].vport_wfq);
4604         }
4605 }
4606
4607 static void
4608 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4609 {
4610         int i;
4611
4612         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4613                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4614 }
4615
4616 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4617                                              struct ecore_ptt *p_ptt,
4618                                              u32 min_pf_rate)
4619 {
4620         struct init_qm_vport_params *vport_params;
4621         int i;
4622
4623         vport_params = p_hwfn->qm_info.qm_vport_params;
4624
4625         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4626                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4627                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4628                                      vport_params[i].first_tx_pq_id,
4629                                      vport_params[i].vport_wfq);
4630         }
4631 }
4632
4633 /* This function performs several validations for WFQ
4634  * configuration and required min rate for a given vport
4635  * 1. req_rate must be greater than one percent of min_pf_rate.
4636  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4637  *    rates to get less than one percent of min_pf_rate.
4638  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4639  */
4640 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4641                                                  u16 vport_id, u32 req_rate,
4642                                                  u32 min_pf_rate)
4643 {
4644         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4645         int non_requested_count = 0, req_count = 0, i, num_vports;
4646
4647         num_vports = p_hwfn->qm_info.num_vports;
4648
4649 /* Accounting for the vports which are configured for WFQ explicitly */
4650
4651         for (i = 0; i < num_vports; i++) {
4652                 u32 tmp_speed;
4653
4654                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4655                         req_count++;
4656                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4657                         total_req_min_rate += tmp_speed;
4658                 }
4659         }
4660
4661         /* Include current vport data as well */
4662         req_count++;
4663         total_req_min_rate += req_rate;
4664         non_requested_count = num_vports - req_count;
4665
4666         /* validate possible error cases */
4667         if (req_rate > min_pf_rate) {
4668                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4669                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4670                            vport_id, req_rate, min_pf_rate);
4671                 return ECORE_INVAL;
4672         }
4673
4674         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4675                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4676                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4677                            vport_id, req_rate, min_pf_rate);
4678                 return ECORE_INVAL;
4679         }
4680
4681         /* TBD - for number of vports greater than 100 */
4682         if (num_vports > ECORE_WFQ_UNIT) {
4683                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4684                            "Number of vports is greater than %d\n",
4685                            ECORE_WFQ_UNIT);
4686                 return ECORE_INVAL;
4687         }
4688
4689         if (total_req_min_rate > min_pf_rate) {
4690                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4691                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4692                            total_req_min_rate, min_pf_rate);
4693                 return ECORE_INVAL;
4694         }
4695
4696         /* Data left for non requested vports */
4697         total_left_rate = min_pf_rate - total_req_min_rate;
4698         left_rate_per_vp = total_left_rate / non_requested_count;
4699
4700         /* validate if non requested get < 1% of min bw */
4701         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4702                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4703                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4704                            left_rate_per_vp, min_pf_rate);
4705                 return ECORE_INVAL;
4706         }
4707
4708         /* now req_rate for given vport passes all scenarios.
4709          * assign final wfq rates to all vports.
4710          */
4711         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4712         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4713
4714         for (i = 0; i < num_vports; i++) {
4715                 if (p_hwfn->qm_info.wfq_data[i].configured)
4716                         continue;
4717
4718                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4719         }
4720
4721         return ECORE_SUCCESS;
4722 }
4723
4724 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4725                                        struct ecore_ptt *p_ptt,
4726                                        u16 vp_id, u32 rate)
4727 {
4728         struct ecore_mcp_link_state *p_link;
4729         int rc = ECORE_SUCCESS;
4730
4731         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4732
4733         if (!p_link->min_pf_rate) {
4734                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4735                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4736                 return rc;
4737         }
4738
4739         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4740
4741         if (rc == ECORE_SUCCESS)
4742                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4743                                                    p_link->min_pf_rate);
4744         else
4745                 DP_NOTICE(p_hwfn, false,
4746                           "Validation failed while configuring min rate\n");
4747
4748         return rc;
4749 }
4750
4751 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4752                                                    struct ecore_ptt *p_ptt,
4753                                                    u32 min_pf_rate)
4754 {
4755         bool use_wfq = false;
4756         int rc = ECORE_SUCCESS;
4757         u16 i;
4758
4759         /* Validate all pre configured vports for wfq */
4760         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4761                 u32 rate;
4762
4763                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4764                         continue;
4765
4766                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4767                 use_wfq = true;
4768
4769                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4770                 if (rc != ECORE_SUCCESS) {
4771                         DP_NOTICE(p_hwfn, false,
4772                                   "WFQ validation failed while configuring min rate\n");
4773                         break;
4774                 }
4775         }
4776
4777         if (rc == ECORE_SUCCESS && use_wfq)
4778                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4779         else
4780                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4781
4782         return rc;
4783 }
4784
4785 /* Main API for ecore clients to configure vport min rate.
4786  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4787  * rate - Speed in Mbps needs to be assigned to a given vport.
4788  */
4789 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4790 {
4791         int i, rc = ECORE_INVAL;
4792
4793         /* TBD - for multiple hardware functions - that is 100 gig */
4794         if (p_dev->num_hwfns > 1) {
4795                 DP_NOTICE(p_dev, false,
4796                           "WFQ configuration is not supported for this device\n");
4797                 return rc;
4798         }
4799
4800         for_each_hwfn(p_dev, i) {
4801                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4802                 struct ecore_ptt *p_ptt;
4803
4804                 p_ptt = ecore_ptt_acquire(p_hwfn);
4805                 if (!p_ptt)
4806                         return ECORE_TIMEOUT;
4807
4808                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4809
4810                 if (rc != ECORE_SUCCESS) {
4811                         ecore_ptt_release(p_hwfn, p_ptt);
4812                         return rc;
4813                 }
4814
4815                 ecore_ptt_release(p_hwfn, p_ptt);
4816         }
4817
4818         return rc;
4819 }
4820
4821 /* API to configure WFQ from mcp link change */
4822 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4823                                            u32 min_pf_rate)
4824 {
4825         int i;
4826
4827         /* TBD - for multiple hardware functions - that is 100 gig */
4828         if (p_dev->num_hwfns > 1) {
4829                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4830                            "WFQ configuration is not supported for this device\n");
4831                 return;
4832         }
4833
4834         for_each_hwfn(p_dev, i) {
4835                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4836
4837                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4838                                                         p_hwfn->p_dpc_ptt,
4839                                                         min_pf_rate);
4840         }
4841 }
4842
4843 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4844                                        struct ecore_ptt *p_ptt,
4845                                        struct ecore_mcp_link_state *p_link,
4846                                        u8 max_bw)
4847 {
4848         int rc = ECORE_SUCCESS;
4849
4850         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4851
4852         if (!p_link->line_speed && (max_bw != 100))
4853                 return rc;
4854
4855         p_link->speed = (p_link->line_speed * max_bw) / 100;
4856         p_hwfn->qm_info.pf_rl = p_link->speed;
4857
4858         /* Since the limiter also affects Tx-switched traffic, we don't want it
4859          * to limit such traffic in case there's no actual limit.
4860          * In that case, set limit to imaginary high boundary.
4861          */
4862         if (max_bw == 100)
4863                 p_hwfn->qm_info.pf_rl = 100000;
4864
4865         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4866                               p_hwfn->qm_info.pf_rl);
4867
4868         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4869                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4870                    p_link->speed);
4871
4872         return rc;
4873 }
4874
4875 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4876 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4877 {
4878         int i, rc = ECORE_INVAL;
4879
4880         if (max_bw < 1 || max_bw > 100) {
4881                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4882                 return rc;
4883         }
4884
4885         for_each_hwfn(p_dev, i) {
4886                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4887                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4888                 struct ecore_mcp_link_state *p_link;
4889                 struct ecore_ptt *p_ptt;
4890
4891                 p_link = &p_lead->mcp_info->link_output;
4892
4893                 p_ptt = ecore_ptt_acquire(p_hwfn);
4894                 if (!p_ptt)
4895                         return ECORE_TIMEOUT;
4896
4897                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4898                                                         p_link, max_bw);
4899
4900                 ecore_ptt_release(p_hwfn, p_ptt);
4901
4902                 if (rc != ECORE_SUCCESS)
4903                         break;
4904         }
4905
4906         return rc;
4907 }
4908
4909 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4910                                        struct ecore_ptt *p_ptt,
4911                                        struct ecore_mcp_link_state *p_link,
4912                                        u8 min_bw)
4913 {
4914         int rc = ECORE_SUCCESS;
4915
4916         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4917         p_hwfn->qm_info.pf_wfq = min_bw;
4918
4919         if (!p_link->line_speed)
4920                 return rc;
4921
4922         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4923
4924         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4925
4926         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4927                    "Configured MIN bandwidth to be %d Mb/sec\n",
4928                    p_link->min_pf_rate);
4929
4930         return rc;
4931 }
4932
4933 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4934 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4935 {
4936         int i, rc = ECORE_INVAL;
4937
4938         if (min_bw < 1 || min_bw > 100) {
4939                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4940                 return rc;
4941         }
4942
4943         for_each_hwfn(p_dev, i) {
4944                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4945                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4946                 struct ecore_mcp_link_state *p_link;
4947                 struct ecore_ptt *p_ptt;
4948
4949                 p_link = &p_lead->mcp_info->link_output;
4950
4951                 p_ptt = ecore_ptt_acquire(p_hwfn);
4952                 if (!p_ptt)
4953                         return ECORE_TIMEOUT;
4954
4955                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4956                                                         p_link, min_bw);
4957                 if (rc != ECORE_SUCCESS) {
4958                         ecore_ptt_release(p_hwfn, p_ptt);
4959                         return rc;
4960                 }
4961
4962                 if (p_link->min_pf_rate) {
4963                         u32 min_rate = p_link->min_pf_rate;
4964
4965                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4966                                                                      p_ptt,
4967                                                                      min_rate);
4968                 }
4969
4970                 ecore_ptt_release(p_hwfn, p_ptt);
4971         }
4972
4973         return rc;
4974 }
4975
4976 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4977 {
4978         struct ecore_mcp_link_state *p_link;
4979
4980         p_link = &p_hwfn->mcp_info->link_output;
4981
4982         if (p_link->min_pf_rate)
4983                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4984                                                  p_link->min_pf_rate);
4985
4986         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4987                     sizeof(*p_hwfn->qm_info.wfq_data) *
4988                     p_hwfn->qm_info.num_vports);
4989 }
4990
4991 int ecore_device_num_engines(struct ecore_dev *p_dev)
4992 {
4993         return ECORE_IS_BB(p_dev) ? 2 : 1;
4994 }
4995
4996 int ecore_device_num_ports(struct ecore_dev *p_dev)
4997 {
4998         /* in CMT always only one port */
4999         if (p_dev->num_hwfns > 1)
5000                 return 1;
5001
5002         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
5003 }
5004
5005 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5006                           __le16 *fw_mid,
5007                           __le16 *fw_lsb,
5008                           u8 *mac)
5009 {
5010         ((u8 *)fw_msb)[0] = mac[1];
5011         ((u8 *)fw_msb)[1] = mac[0];
5012         ((u8 *)fw_mid)[0] = mac[3];
5013         ((u8 *)fw_mid)[1] = mac[2];
5014         ((u8 *)fw_lsb)[0] = mac[5];
5015         ((u8 *)fw_lsb)[1] = mac[4];
5016 }