drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dev_api.h"
  32 #include "ecore_dcbx.h"
  33 #include "ecore_l2.h"
  34
  35 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  36  * registers involved are not split and thus configuration is a race where
  37  * some of the PFs configuration might be lost.
  38  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  39  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  40  * there's more than a single compiled ecore component in system].
  41  */
  42 static osal_spinlock_t qm_lock;
  43 static bool qm_lock_init;
  44
  45 /* Configurable */
  46 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
  47                                          * load the driver. The number was
  48                                          * arbitrarily set.
  49                                          */
  50
  51 /* Derived */
  52 #define ECORE_MIN_PWM_REGION    ((ECORE_WID_SIZE) * (ECORE_MIN_DPIS))
  53
  54 enum BAR_ID {
  55         BAR_ID_0,               /* used for GRC */
  56         BAR_ID_1                /* Used for doorbells */
  57 };
  58
  59 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn, enum BAR_ID bar_id)
  60 {
  61         u32 bar_reg = (bar_id == BAR_ID_0 ?
  62                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  63         u32 val;
  64
  65         if (IS_VF(p_hwfn->p_dev)) {
  66                 /* TODO - assume each VF hwfn has 64Kb for Bar0; Bar1 can be
  67                  * read from actual register, but we're currently not using
  68                  * it for actual doorbelling.
  69                  */
  70                 return 1 << 17;
  71         }
  72
  73         val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);
  74         if (val)
  75                 return 1 << (val + 15);
  76
  77         /* The above registers were updated in the past only in CMT mode. Since
  78          * they were found to be useful MFW started updating them from 8.7.7.0.
  79          * In older MFW versions they are set to 0 which means disabled.
  80          */
  81         if (p_hwfn->p_dev->num_hwfns > 1) {
  82                 DP_NOTICE(p_hwfn, false,
  83                           "BAR size not configured. Assuming BAR size of 256kB"
  84                           " for GRC and 512kB for DB\n");
  85                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  86         } else {
  87                 DP_NOTICE(p_hwfn, false,
  88                           "BAR size not configured. Assuming BAR size of 512kB"
  89                           " for GRC and 512kB for DB\n");
  90                 val = 512 * 1024;
  91         }
  92
  93         return val;
  94 }
  95
  96 void ecore_init_dp(struct ecore_dev *p_dev,
  97                    u32 dp_module, u8 dp_level, void *dp_ctx)
  98 {
  99         u32 i;
 100
 101         p_dev->dp_level = dp_level;
 102         p_dev->dp_module = dp_module;
 103         p_dev->dp_ctx = dp_ctx;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109                 p_hwfn->dp_ctx = dp_ctx;
 110         }
 111 }
 112
 113 void ecore_init_struct(struct ecore_dev *p_dev)
 114 {
 115         u8 i;
 116
 117         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 118                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 119
 120                 p_hwfn->p_dev = p_dev;
 121                 p_hwfn->my_id = i;
 122                 p_hwfn->b_active = false;
 123
 124                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 125                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 126         }
 127
 128         /* hwfn 0 is always active */
 129         p_dev->hwfns[0].b_active = true;
 130
 131         /* set the default cache alignment to 128 (may be overridden later) */
 132         p_dev->cache_shift = 7;
 133 }
 134
 135 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 136 {
 137         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 138
 139         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 140         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 141         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 142         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 143 }
 144
 145 void ecore_resc_free(struct ecore_dev *p_dev)
 146 {
 147         int i;
 148
 149         if (IS_VF(p_dev)) {
 150                 for_each_hwfn(p_dev, i)
 151                         ecore_l2_free(&p_dev->hwfns[i]);
 152                 return;
 153         }
 154
 155         OSAL_FREE(p_dev, p_dev->fw_data);
 156
 157         OSAL_FREE(p_dev, p_dev->reset_stats);
 158
 159         for_each_hwfn(p_dev, i) {
 160                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 161
 162                 ecore_cxt_mngr_free(p_hwfn);
 163                 ecore_qm_info_free(p_hwfn);
 164                 ecore_spq_free(p_hwfn);
 165                 ecore_eq_free(p_hwfn);
 166                 ecore_consq_free(p_hwfn);
 167                 ecore_int_free(p_hwfn);
 168                 ecore_iov_free(p_hwfn);
 169                 ecore_l2_free(p_hwfn);
 170                 ecore_dmae_info_free(p_hwfn);
 171                 ecore_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info);
 172                 /* @@@TBD Flush work-queue ? */
 173         }
 174 }
 175
 176 /******************** QM initialization *******************/
 177
 178 /* bitmaps for indicating active traffic classes.
 179  * Special case for Arrowhead 4 port
 180  */
 181 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 182 #define ACTIVE_TCS_BMAP 0x9f
 183 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 184 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 185
 186 /* determines the physical queue flags for a given PF. */
 187 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 188 {
 189         u32 flags;
 190
 191         /* common flags */
 192         flags = PQ_FLAGS_LB;
 193
 194         /* feature flags */
 195         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 196                 flags |= PQ_FLAGS_VFS;
 197
 198         /* protocol flags */
 199         switch (p_hwfn->hw_info.personality) {
 200         case ECORE_PCI_ETH:
 201                 flags |= PQ_FLAGS_MCOS;
 202                 break;
 203         case ECORE_PCI_FCOE:
 204                 flags |= PQ_FLAGS_OFLD;
 205                 break;
 206         case ECORE_PCI_ISCSI:
 207                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 208                 break;
 209         case ECORE_PCI_ETH_ROCE:
 210                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 211                 break;
 212         case ECORE_PCI_ETH_IWARP:
 213                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 214                          PQ_FLAGS_OFLD;
 215                 break;
 216         default:
 217                 DP_ERR(p_hwfn, "unknown personality %d\n",
 218                        p_hwfn->hw_info.personality);
 219                 return 0;
 220         }
 221         return flags;
 222 }
 223
 224 /* Getters for resource amounts necessary for qm initialization */
 225 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 226 {
 227         return p_hwfn->hw_info.num_hw_tc;
 228 }
 229
 230 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 231 {
 232         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 233                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 234 }
 235
 236 #define NUM_DEFAULT_RLS 1
 237
 238 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 239 {
 240         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 241
 242         /* @DPDK */
 243         /* num RLs can't exceed resource amount of rls or vports or the
 244          * dcqcn qps
 245          */
 246         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 247                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 248
 249         /* make sure after we reserve the default and VF rls we'll have
 250          * something left
 251          */
 252         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 253                 DP_NOTICE(p_hwfn, false,
 254                           "no rate limiters left for PF rate limiting"
 255                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 256                 return 0;
 257         }
 258
 259         /* subtract rls necessary for VFs and one default one for the PF */
 260         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 261
 262         return num_pf_rls;
 263 }
 264
 265 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 266 {
 267         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 268
 269         /* all pqs share the same vport (hence the 1 below), except for vfs
 270          * and pf_rl pqs
 271          */
 272         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 273                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 274                (!!(PQ_FLAGS_VFS & pq_flags)) *
 275                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 276 }
 277
 278 /* calc amount of PQs according to the requested flags */
 279 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 280 {
 281         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 282
 283         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 284                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 285                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 286                 ecore_init_qm_get_num_tcs(p_hwfn) +
 287                (!!(PQ_FLAGS_LB & pq_flags)) +
 288                (!!(PQ_FLAGS_OOO & pq_flags)) +
 289                (!!(PQ_FLAGS_ACK & pq_flags)) +
 290                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 291                (!!(PQ_FLAGS_VFS & pq_flags)) *
 292                 ecore_init_qm_get_num_vfs(p_hwfn);
 293 }
 294
 295 /* initialize the top level QM params */
 296 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 297 {
 298         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 299         bool four_port;
 300
 301         /* pq and vport bases for this PF */
 302         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 303         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 304
 305         /* rate limiting and weighted fair queueing are always enabled */
 306         qm_info->vport_rl_en = 1;
 307         qm_info->vport_wfq_en = 1;
 308
 309         /* TC config is different for AH 4 port */
 310         four_port = p_hwfn->p_dev->num_ports_in_engines == MAX_NUM_PORTS_K2;
 311
 312         /* in AH 4 port we have fewer TCs per port */
 313         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 314                                                      NUM_OF_PHYS_TCS;
 315
 316         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 317          * 4 otherwise
 318          */
 319         if (!qm_info->ooo_tc)
 320                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 321                                               DCBX_TCP_OOO_TC;
 322 }
 323
 324 /* initialize qm vport params */
 325 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 326 {
 327         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 328         u8 i;
 329
 330         /* all vports participate in weighted fair queueing */
 331         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 332                 qm_info->qm_vport_params[i].vport_wfq = 1;
 333 }
 334
 335 /* initialize qm port params */
 336 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 337 {
 338         /* Initialize qm port parameters */
 339         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engines;
 340
 341         /* indicate how ooo and high pri traffic is dealt with */
 342         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 343                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 344
 345         for (i = 0; i < num_ports; i++) {
 346                 struct init_qm_port_params *p_qm_port =
 347                         &p_hwfn->qm_info.qm_port_params[i];
 348
 349                 p_qm_port->active = 1;
 350                 p_qm_port->active_phys_tcs = active_phys_tcs;
 351                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 352                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 353         }
 354 }
 355
 356 /* Reset the params which must be reset for qm init. QM init may be called as
 357  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 358  * params may be affected by the init but would simply recalculate to the same
 359  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 360  * affected as these amounts stay the same.
 361  */
 362 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 363 {
 364         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 365
 366         qm_info->num_pqs = 0;
 367         qm_info->num_vports = 0;
 368         qm_info->num_pf_rls = 0;
 369         qm_info->num_vf_pqs = 0;
 370         qm_info->first_vf_pq = 0;
 371         qm_info->first_mcos_pq = 0;
 372         qm_info->first_rl_pq = 0;
 373 }
 374
 375 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 376 {
 377         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 378
 379         qm_info->num_vports++;
 380
 381         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 382                 DP_ERR(p_hwfn,
 383                        "vport overflow! qm_info->num_vports %d,"
 384                        " qm_init_get_num_vports() %d\n",
 385                        qm_info->num_vports,
 386                        ecore_init_qm_get_num_vports(p_hwfn));
 387 }
 388
 389 /* initialize a single pq and manage qm_info resources accounting.
 390  * The pq_init_flags param determines whether the PQ is rate limited
 391  * (for VF or PF)
 392  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 393  * shared)
 394  */
 395
 396 /* flags for pq init */
 397 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 398 #define PQ_INIT_PF_RL           (1 << 1)
 399 #define PQ_INIT_VF_RL           (1 << 2)
 400
 401 /* defines for pq init */
 402 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 403 #define PQ_INIT_DEFAULT_TC              0
 404 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 405
 406 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 407                              struct ecore_qm_info *qm_info,
 408                              u8 tc, u32 pq_init_flags)
 409 {
 410         u16 pq_idx = qm_info->num_pqs, max_pq =
 411                                         ecore_init_qm_get_num_pqs(p_hwfn);
 412
 413         if (pq_idx > max_pq)
 414                 DP_ERR(p_hwfn,
 415                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 416
 417         /* init pq params */
 418         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 419                                                  qm_info->num_vports;
 420         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 421         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 422         qm_info->qm_pq_params[pq_idx].rl_valid =
 423                 (pq_init_flags & PQ_INIT_PF_RL ||
 424                  pq_init_flags & PQ_INIT_VF_RL);
 425
 426         /* qm params accounting */
 427         qm_info->num_pqs++;
 428         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 429                 qm_info->num_vports++;
 430
 431         if (pq_init_flags & PQ_INIT_PF_RL)
 432                 qm_info->num_pf_rls++;
 433
 434         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 435                 DP_ERR(p_hwfn,
 436                        "vport overflow! qm_info->num_vports %d,"
 437                        " qm_init_get_num_vports() %d\n",
 438                        qm_info->num_vports,
 439                        ecore_init_qm_get_num_vports(p_hwfn));
 440
 441         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 442                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 443                        " qm_init_get_num_pf_rls() %d\n",
 444                        qm_info->num_pf_rls,
 445                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 446 }
 447
 448 /* get pq index according to PQ_FLAGS */
 449 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 450                                              u32 pq_flags)
 451 {
 452         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 453
 454         /* Can't have multiple flags set here */
 455         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 456                                 sizeof(pq_flags)) > 1)
 457                 goto err;
 458
 459         switch (pq_flags) {
 460         case PQ_FLAGS_RLS:
 461                 return &qm_info->first_rl_pq;
 462         case PQ_FLAGS_MCOS:
 463                 return &qm_info->first_mcos_pq;
 464         case PQ_FLAGS_LB:
 465                 return &qm_info->pure_lb_pq;
 466         case PQ_FLAGS_OOO:
 467                 return &qm_info->ooo_pq;
 468         case PQ_FLAGS_ACK:
 469                 return &qm_info->pure_ack_pq;
 470         case PQ_FLAGS_OFLD:
 471                 return &qm_info->offload_pq;
 472         case PQ_FLAGS_VFS:
 473                 return &qm_info->first_vf_pq;
 474         default:
 475                 goto err;
 476         }
 477
 478 err:
 479         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 480         return OSAL_NULL;
 481 }
 482
 483 /* save pq index in qm info */
 484 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 485                                   u32 pq_flags, u16 pq_val)
 486 {
 487         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 488
 489         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 490 }
 491
 492 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 493 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 494 {
 495         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 496
 497         return *base_pq_idx + CM_TX_PQ_BASE;
 498 }
 499
 500 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 501 {
 502         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 503
 504         if (tc > max_tc)
 505                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 506
 507         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 508 }
 509
 510 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 511 {
 512         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 513
 514         if (vf > max_vf)
 515                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 516
 517         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 518 }
 519
 520 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 521 {
 522         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 523
 524         if (rl > max_rl)
 525                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 526
 527         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 528 }
 529
 530 /* Functions for creating specific types of pqs */
 531 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 532 {
 533         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 534
 535         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 536                 return;
 537
 538         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 539         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 540 }
 541
 542 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 543 {
 544         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 545
 546         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 547                 return;
 548
 549         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 550         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 551 }
 552
 553 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 554 {
 555         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 556
 557         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 558                 return;
 559
 560         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 561         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 562 }
 563
 564 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 565 {
 566         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 567
 568         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 569                 return;
 570
 571         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 572         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 573 }
 574
 575 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 576 {
 577         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 578         u8 tc_idx;
 579
 580         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 581                 return;
 582
 583         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 584         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 585                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 586 }
 587
 588 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 589 {
 590         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 591         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 592
 593         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 594                 return;
 595
 596         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 597
 598         qm_info->num_vf_pqs = num_vfs;
 599         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 600                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 601                                  PQ_INIT_VF_RL);
 602 }
 603
 604 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 605 {
 606         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 607         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 608
 609         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 610                 return;
 611
 612         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 613         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 614                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 615                                  PQ_INIT_PF_RL);
 616 }
 617
 618 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 619 {
 620         /* rate limited pqs, must come first (FW assumption) */
 621         ecore_init_qm_rl_pqs(p_hwfn);
 622
 623         /* pqs for multi cos */
 624         ecore_init_qm_mcos_pqs(p_hwfn);
 625
 626         /* pure loopback pq */
 627         ecore_init_qm_lb_pq(p_hwfn);
 628
 629         /* out of order pq */
 630         ecore_init_qm_ooo_pq(p_hwfn);
 631
 632         /* pure ack pq */
 633         ecore_init_qm_pure_ack_pq(p_hwfn);
 634
 635         /* pq for offloaded protocol */
 636         ecore_init_qm_offload_pq(p_hwfn);
 637
 638         /* done sharing vports */
 639         ecore_init_qm_advance_vport(p_hwfn);
 640
 641         /* pqs for vfs */
 642         ecore_init_qm_vf_pqs(p_hwfn);
 643 }
 644
 645 /* compare values of getters against resources amounts */
 646 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 647 {
 648         if (ecore_init_qm_get_num_vports(p_hwfn) >
 649             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 650                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 651                 return ECORE_INVAL;
 652         }
 653
 654         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 655                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 656                 return ECORE_INVAL;
 657         }
 658
 659         return ECORE_SUCCESS;
 660 }
 661
 662 /*
 663  * Function for verbose printing of the qm initialization results
 664  */
 665 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 666 {
 667         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 668         struct init_qm_vport_params *vport;
 669         struct init_qm_port_params *port;
 670         struct init_qm_pq_params *pq;
 671         int i, tc;
 672
 673         /* top level params */
 674         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 675                    "qm init top level params: start_pq %d, start_vport %d,"
 676                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 677                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 678                    qm_info->offload_pq, qm_info->pure_ack_pq);
 679         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 680                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 681                    " num_vports %d, max_phys_tcs_per_port %d\n",
 682                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 683                    qm_info->num_vf_pqs, qm_info->num_vports,
 684                    qm_info->max_phys_tcs_per_port);
 685         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 686                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 687                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 688                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 689                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 690                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 691
 692         /* port table */
 693         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engines; i++) {
 694                 port = &qm_info->qm_port_params[i];
 695                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 696                            "port idx %d, active %d, active_phys_tcs %d,"
 697                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
 698                            " reserved %d\n",
 699                            i, port->active, port->active_phys_tcs,
 700                            port->num_pbf_cmd_lines, port->num_btb_blocks,
 701                            port->reserved);
 702         }
 703
 704         /* vport table */
 705         for (i = 0; i < qm_info->num_vports; i++) {
 706                 vport = &qm_info->qm_vport_params[i];
 707                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 708                            "vport idx %d, vport_rl %d, wfq %d,"
 709                            " first_tx_pq_id [ ",
 710                            qm_info->start_vport + i, vport->vport_rl,
 711                            vport->vport_wfq);
 712                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 713                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
 714                                    vport->first_tx_pq_id[tc]);
 715                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
 716         }
 717
 718         /* pq table */
 719         for (i = 0; i < qm_info->num_pqs; i++) {
 720                 pq = &qm_info->qm_pq_params[i];
 721                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 722                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
 723                            " rl_valid %d\n",
 724                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
 725                            pq->wrr_group, pq->rl_valid);
 726         }
 727 }
 728
 729 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
 730 {
 731         /* reset params required for init run */
 732         ecore_init_qm_reset_params(p_hwfn);
 733
 734         /* init QM top level params */
 735         ecore_init_qm_params(p_hwfn);
 736
 737         /* init QM port params */
 738         ecore_init_qm_port_params(p_hwfn);
 739
 740         /* init QM vport params */
 741         ecore_init_qm_vport_params(p_hwfn);
 742
 743         /* init QM physical queue params */
 744         ecore_init_qm_pq_params(p_hwfn);
 745
 746         /* display all that init */
 747         ecore_dp_init_qm_params(p_hwfn);
 748 }
 749
 750 /* This function reconfigures the QM pf on the fly.
 751  * For this purpose we:
 752  * 1. reconfigure the QM database
 753  * 2. set new values to runtime array
 754  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 755  * 4. activate init tool in QM_PF stage
 756  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 757  */
 758 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
 759                                      struct ecore_ptt *p_ptt)
 760 {
 761         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 762         bool b_rc;
 763         enum _ecore_status_t rc;
 764
 765         /* initialize ecore's qm data structure */
 766         ecore_init_qm_info(p_hwfn);
 767
 768         /* stop PF's qm queues */
 769         OSAL_SPIN_LOCK(&qm_lock);
 770         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 771                                       qm_info->start_pq, qm_info->num_pqs);
 772         OSAL_SPIN_UNLOCK(&qm_lock);
 773         if (!b_rc)
 774                 return ECORE_INVAL;
 775
 776         /* clear the QM_PF runtime phase leftovers from previous init */
 777         ecore_init_clear_rt_data(p_hwfn);
 778
 779         /* prepare QM portion of runtime array */
 780         ecore_qm_init_pf(p_hwfn);
 781
 782         /* activate init tool on runtime array */
 783         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 784                             p_hwfn->hw_info.hw_mode);
 785         if (rc != ECORE_SUCCESS)
 786                 return rc;
 787
 788         /* start PF's qm queues */
 789         OSAL_SPIN_LOCK(&qm_lock);
 790         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 791                                       qm_info->start_pq, qm_info->num_pqs);
 792         OSAL_SPIN_UNLOCK(&qm_lock);
 793         if (!b_rc)
 794                 return ECORE_INVAL;
 795
 796         return ECORE_SUCCESS;
 797 }
 798
 799 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
 800 {
 801         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 802         enum _ecore_status_t rc;
 803
 804         rc = ecore_init_qm_sanity(p_hwfn);
 805         if (rc != ECORE_SUCCESS)
 806                 goto alloc_err;
 807
 808         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 809                                             sizeof(struct init_qm_pq_params) *
 810                                             ecore_init_qm_get_num_pqs(p_hwfn));
 811         if (!qm_info->qm_pq_params)
 812                 goto alloc_err;
 813
 814         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 815                                        sizeof(struct init_qm_vport_params) *
 816                                        ecore_init_qm_get_num_vports(p_hwfn));
 817         if (!qm_info->qm_vport_params)
 818                 goto alloc_err;
 819
 820         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 821                                       sizeof(struct init_qm_port_params) *
 822                                       p_hwfn->p_dev->num_ports_in_engines);
 823         if (!qm_info->qm_port_params)
 824                 goto alloc_err;
 825
 826         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 827                                         sizeof(struct ecore_wfq_data) *
 828                                         ecore_init_qm_get_num_vports(p_hwfn));
 829         if (!qm_info->wfq_data)
 830                 goto alloc_err;
 831
 832         return ECORE_SUCCESS;
 833
 834 alloc_err:
 835         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
 836         ecore_qm_info_free(p_hwfn);
 837         return ECORE_NOMEM;
 838 }
 839 /******************** End QM initialization ***************/
 840
 841 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
 842 {
 843         enum _ecore_status_t rc = ECORE_SUCCESS;
 844         int i;
 845
 846         if (IS_VF(p_dev)) {
 847                 for_each_hwfn(p_dev, i) {
 848                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
 849                         if (rc != ECORE_SUCCESS)
 850                                 return rc;
 851                 }
 852                 return rc;
 853         }
 854
 855         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 856                                      sizeof(*p_dev->fw_data));
 857         if (!p_dev->fw_data)
 858                 return ECORE_NOMEM;
 859
 860         for_each_hwfn(p_dev, i) {
 861                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 862                 u32 n_eqes, num_cons;
 863
 864                 /* First allocate the context manager structure */
 865                 rc = ecore_cxt_mngr_alloc(p_hwfn);
 866                 if (rc)
 867                         goto alloc_err;
 868
 869                 /* Set the HW cid/tid numbers (in the contest manager)
 870                  * Must be done prior to any further computations.
 871                  */
 872                 rc = ecore_cxt_set_pf_params(p_hwfn);
 873                 if (rc)
 874                         goto alloc_err;
 875
 876                 rc = ecore_alloc_qm_data(p_hwfn);
 877                 if (rc)
 878                         goto alloc_err;
 879
 880                 /* init qm info */
 881                 ecore_init_qm_info(p_hwfn);
 882
 883                 /* Compute the ILT client partition */
 884                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
 885                 if (rc)
 886                         goto alloc_err;
 887
 888                 /* CID map / ILT shadow table / T2
 889                  * The talbes sizes are determined by the computations above
 890                  */
 891                 rc = ecore_cxt_tables_alloc(p_hwfn);
 892                 if (rc)
 893                         goto alloc_err;
 894
 895                 /* SPQ, must follow ILT because initializes SPQ context */
 896                 rc = ecore_spq_alloc(p_hwfn);
 897                 if (rc)
 898                         goto alloc_err;
 899
 900                 /* SP status block allocation */
 901                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
 902                                                            RESERVED_PTT_DPC);
 903
 904                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 905                 if (rc)
 906                         goto alloc_err;
 907
 908                 rc = ecore_iov_alloc(p_hwfn);
 909                 if (rc)
 910                         goto alloc_err;
 911
 912                 /* EQ */
 913                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
 914                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
 915                         /* Calculate the EQ size
 916                          * ---------------------
 917                          * Each ICID may generate up to one event at a time i.e.
 918                          * the event must be handled/cleared before a new one
 919                          * can be generated. We calculate the sum of events per
 920                          * protocol and create an EQ deep enough to handle the
 921                          * worst case:
 922                          * - Core - according to SPQ.
 923                          * - RoCE - per QP there are a couple of ICIDs, one
 924                          *        responder and one requester, each can
 925                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
 926                          *        Each CQ can generate an EQE. There are 2 CQs
 927                          *        per QP => n_eqes_cq = 2 * n_qp.
 928                          *        Hence the RoCE total is 4 * n_qp or
 929                          *        2 * num_cons.
 930                          * - ENet - There can be up to two events per VF. One
 931                          *        for VF-PF channel and another for VF FLR
 932                          *        initial cleanup. The number of VFs is
 933                          *        bounded by MAX_NUM_VFS_BB, and is much
 934                          *        smaller than RoCE's so we avoid exact
 935                          *        calculation.
 936                          */
 937                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 938                                 num_cons =
 939                                     ecore_cxt_get_proto_cid_count(
 940                                                 p_hwfn,
 941                                                 PROTOCOLID_ROCE,
 942                                                 OSAL_NULL);
 943                                 num_cons *= 2;
 944                         } else {
 945                                 num_cons = ecore_cxt_get_proto_cid_count(
 946                                                 p_hwfn,
 947                                                 PROTOCOLID_IWARP,
 948                                                 OSAL_NULL);
 949                         }
 950                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 951                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
 952                         num_cons =
 953                             ecore_cxt_get_proto_cid_count(p_hwfn,
 954                                                           PROTOCOLID_ISCSI,
 955                                                           OSAL_NULL);
 956                         n_eqes += 2 * num_cons;
 957                 }
 958
 959                 if (n_eqes > 0xFFFF) {
 960                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
 961                                        "The maximum of a u16 chain is 0x%x\n",
 962                                n_eqes, 0xFFFF);
 963                         goto alloc_no_mem;
 964                 }
 965
 966                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
 967                 if (rc)
 968                         goto alloc_err;
 969
 970                 rc = ecore_consq_alloc(p_hwfn);
 971                 if (rc)
 972                         goto alloc_err;
 973
 974                 rc = ecore_l2_alloc(p_hwfn);
 975                 if (rc != ECORE_SUCCESS)
 976                         goto alloc_err;
 977
 978                 /* DMA info initialization */
 979                 rc = ecore_dmae_info_alloc(p_hwfn);
 980                 if (rc) {
 981                         DP_NOTICE(p_hwfn, true,
 982                                   "Failed to allocate memory for dmae_info"
 983                                   " structure\n");
 984                         goto alloc_err;
 985                 }
 986
 987                 /* DCBX initialization */
 988                 rc = ecore_dcbx_info_alloc(p_hwfn);
 989                 if (rc) {
 990                         DP_NOTICE(p_hwfn, true,
 991                                   "Failed to allocate memory for dcbx structure\n");
 992                         goto alloc_err;
 993                 }
 994         }
 995
 996         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 997                                          sizeof(*p_dev->reset_stats));
 998         if (!p_dev->reset_stats) {
 999                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1000                 goto alloc_no_mem;
1001         }
1002
1003         return ECORE_SUCCESS;
1004
1005 alloc_no_mem:
1006         rc = ECORE_NOMEM;
1007 alloc_err:
1008         ecore_resc_free(p_dev);
1009         return rc;
1010 }
1011
1012 void ecore_resc_setup(struct ecore_dev *p_dev)
1013 {
1014         int i;
1015
1016         if (IS_VF(p_dev)) {
1017                 for_each_hwfn(p_dev, i)
1018                         ecore_l2_setup(&p_dev->hwfns[i]);
1019                 return;
1020         }
1021
1022         for_each_hwfn(p_dev, i) {
1023                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1024
1025                 ecore_cxt_mngr_setup(p_hwfn);
1026                 ecore_spq_setup(p_hwfn);
1027                 ecore_eq_setup(p_hwfn);
1028                 ecore_consq_setup(p_hwfn);
1029
1030                 /* Read shadow of current MFW mailbox */
1031                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1032                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1033                             p_hwfn->mcp_info->mfw_mb_cur,
1034                             p_hwfn->mcp_info->mfw_mb_length);
1035
1036                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1037
1038                 ecore_l2_setup(p_hwfn);
1039                 ecore_iov_setup(p_hwfn, p_hwfn->p_main_ptt);
1040         }
1041 }
1042
1043 #define FINAL_CLEANUP_POLL_CNT  (100)
1044 #define FINAL_CLEANUP_POLL_TIME (10)
1045 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1046                                          struct ecore_ptt *p_ptt,
1047                                          u16 id, bool is_vf)
1048 {
1049         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1050         enum _ecore_status_t rc = ECORE_TIMEOUT;
1051
1052 #ifndef ASIC_ONLY
1053         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1054             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1055                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1056                 return ECORE_SUCCESS;
1057         }
1058 #endif
1059
1060         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1061             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1062
1063         if (is_vf)
1064                 id += 0x10;
1065
1066         command |= X_FINAL_CLEANUP_AGG_INT <<
1067             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1068         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1069         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1070         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1071
1072 /* Make sure notification is not set before initiating final cleanup */
1073
1074         if (REG_RD(p_hwfn, addr)) {
1075                 DP_NOTICE(p_hwfn, false,
1076                           "Unexpected; Found final cleanup notification");
1077                 DP_NOTICE(p_hwfn, false,
1078                           " before initiating final cleanup\n");
1079                 REG_WR(p_hwfn, addr, 0);
1080         }
1081
1082         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1083                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1084                    id, command);
1085
1086         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1087
1088         /* Poll until completion */
1089         while (!REG_RD(p_hwfn, addr) && count--)
1090                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1091
1092         if (REG_RD(p_hwfn, addr))
1093                 rc = ECORE_SUCCESS;
1094         else
1095                 DP_NOTICE(p_hwfn, true,
1096                           "Failed to receive FW final cleanup notification\n");
1097
1098         /* Cleanup afterwards */
1099         REG_WR(p_hwfn, addr, 0);
1100
1101         return rc;
1102 }
1103
1104 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1105 {
1106         int hw_mode = 0;
1107
1108         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1109                 hw_mode |= 1 << MODE_BB;
1110         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1111                 hw_mode |= 1 << MODE_K2;
1112         } else {
1113                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1114                           p_hwfn->p_dev->type);
1115                 return ECORE_INVAL;
1116         }
1117
1118         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1119         switch (p_hwfn->p_dev->num_ports_in_engines) {
1120         case 1:
1121                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1122                 break;
1123         case 2:
1124                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1125                 break;
1126         case 4:
1127                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1128                 break;
1129         default:
1130                 DP_NOTICE(p_hwfn, true,
1131                           "num_ports_in_engine = %d not supported\n",
1132                           p_hwfn->p_dev->num_ports_in_engines);
1133                 return ECORE_INVAL;
1134         }
1135
1136         switch (p_hwfn->p_dev->mf_mode) {
1137         case ECORE_MF_DEFAULT:
1138         case ECORE_MF_NPAR:
1139                 hw_mode |= 1 << MODE_MF_SI;
1140                 break;
1141         case ECORE_MF_OVLAN:
1142                 hw_mode |= 1 << MODE_MF_SD;
1143                 break;
1144         default:
1145                 DP_NOTICE(p_hwfn, true,
1146                           "Unsupported MF mode, init as DEFAULT\n");
1147                 hw_mode |= 1 << MODE_MF_SI;
1148         }
1149
1150 #ifndef ASIC_ONLY
1151         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1152                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1153                         hw_mode |= 1 << MODE_FPGA;
1154                 } else {
1155                         if (p_hwfn->p_dev->b_is_emul_full)
1156                                 hw_mode |= 1 << MODE_EMUL_FULL;
1157                         else
1158                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1159                 }
1160         } else
1161 #endif
1162                 hw_mode |= 1 << MODE_ASIC;
1163
1164         if (p_hwfn->p_dev->num_hwfns > 1)
1165                 hw_mode |= 1 << MODE_100G;
1166
1167         p_hwfn->hw_info.hw_mode = hw_mode;
1168
1169         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1170                    "Configuring function for hw_mode: 0x%08x\n",
1171                    p_hwfn->hw_info.hw_mode);
1172
1173         return ECORE_SUCCESS;
1174 }
1175
1176 #ifndef ASIC_ONLY
1177 /* MFW-replacement initializations for non-ASIC */
1178 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1179                                                struct ecore_ptt *p_ptt)
1180 {
1181         struct ecore_dev *p_dev = p_hwfn->p_dev;
1182         u32 pl_hv = 1;
1183         int i;
1184
1185         if (CHIP_REV_IS_EMUL(p_dev)) {
1186                 if (ECORE_IS_AH(p_dev))
1187                         pl_hv |= 0x600;
1188         }
1189
1190         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1191
1192         if (CHIP_REV_IS_EMUL(p_dev) &&
1193             (ECORE_IS_AH(p_dev)))
1194                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1195                          0x3ffffff);
1196
1197         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1198         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1199         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1200                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1201
1202         if (CHIP_REV_IS_EMUL(p_dev)) {
1203                 if (ECORE_IS_AH(p_dev)) {
1204                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1205                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1206                                  (p_dev->num_ports_in_engines >> 1));
1207
1208                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1209                                  p_dev->num_ports_in_engines == 4 ? 0 : 3);
1210                 }
1211         }
1212
1213         /* Poll on RBC */
1214         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1215         for (i = 0; i < 100; i++) {
1216                 OSAL_UDELAY(50);
1217                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1218                         break;
1219         }
1220         if (i == 100)
1221                 DP_NOTICE(p_hwfn, true,
1222                           "RBC done failed to complete in PSWRQ2\n");
1223
1224         return ECORE_SUCCESS;
1225 }
1226 #endif
1227
1228 /* Init run time data for all PFs and their VFs on an engine.
1229  * TBD - for VFs - Once we have parent PF info for each VF in
1230  * shmem available as CAU requires knowledge of parent PF for each VF.
1231  */
1232 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1233 {
1234         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1235         int i, sb_id;
1236
1237         for_each_hwfn(p_dev, i) {
1238                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1239                 struct ecore_igu_info *p_igu_info;
1240                 struct ecore_igu_block *p_block;
1241                 struct cau_sb_entry sb_entry;
1242
1243                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1244
1245                 for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1246                      sb_id++) {
1247                         p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1248
1249                         if (!p_block->is_pf)
1250                                 continue;
1251
1252                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1253                                                 p_block->function_id, 0, 0);
1254                         STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry);
1255                 }
1256         }
1257 }
1258
1259 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1260                                                  struct ecore_ptt *p_ptt,
1261                                                  int hw_mode)
1262 {
1263         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1264         struct ecore_dev *p_dev = p_hwfn->p_dev;
1265         u8 vf_id, max_num_vfs;
1266         u16 num_pfs, pf_id;
1267         u32 concrete_fid;
1268         enum _ecore_status_t rc = ECORE_SUCCESS;
1269
1270         ecore_init_cau_rt_data(p_dev);
1271
1272         /* Program GTT windows */
1273         ecore_gtt_init(p_hwfn);
1274
1275 #ifndef ASIC_ONLY
1276         if (CHIP_REV_IS_EMUL(p_dev)) {
1277                 rc = ecore_hw_init_chip(p_hwfn, p_hwfn->p_main_ptt);
1278                 if (rc != ECORE_SUCCESS)
1279                         return rc;
1280         }
1281 #endif
1282
1283         if (p_hwfn->mcp_info) {
1284                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1285                         qm_info->pf_rl_en = 1;
1286                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1287                         qm_info->pf_wfq_en = 1;
1288         }
1289
1290         ecore_qm_common_rt_init(p_hwfn,
1291                                 p_dev->num_ports_in_engines,
1292                                 qm_info->max_phys_tcs_per_port,
1293                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1294                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1295                                 qm_info->qm_port_params);
1296
1297         ecore_cxt_hw_init_common(p_hwfn);
1298
1299         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1300         if (rc != ECORE_SUCCESS)
1301                 return rc;
1302
1303         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1304          * need to decide with which value, maybe runtime
1305          */
1306         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1307         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1308
1309         if (ECORE_IS_BB(p_dev)) {
1310                 /* Workaround clears ROCE search for all functions to prevent
1311                  * involving non initialized function in processing ROCE packet.
1312                  */
1313                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1314                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1315                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1316                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1317                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1318                 }
1319                 /* pretend to original PF */
1320                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1321         }
1322
1323         /* Workaround for avoiding CCFC execution error when getting packets
1324          * with CRC errors, and allowing instead the invoking of the FW error
1325          * handler.
1326          * This is not done inside the init tool since it currently can't
1327          * perform a pretending to VFs.
1328          */
1329         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1330         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1331                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1332                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1333                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1334                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1335                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1336                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1337         }
1338         /* pretend to original PF */
1339         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1340
1341         return rc;
1342 }
1343
1344 #ifndef ASIC_ONLY
1345 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1346 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1347
1348 #define PMEG_IF_BYTE_COUNT      8
1349
1350 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1351                              struct ecore_ptt *p_ptt,
1352                              u32 addr, u64 data, u8 reg_type, u8 port)
1353 {
1354         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1355                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1356                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1357                    (8 << PMEG_IF_BYTE_COUNT),
1358                    (reg_type << 25) | (addr << 8) | port,
1359                    (u32)((data >> 32) & 0xffffffff),
1360                    (u32)(data & 0xffffffff));
1361
1362         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1363                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1364                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1365         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1366                  (reg_type << 25) | (addr << 8) | port);
1367         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1368         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1369                  (data >> 32) & 0xffffffff);
1370 }
1371
1372 #define XLPORT_MODE_REG (0x20a)
1373 #define XLPORT_MAC_CONTROL (0x210)
1374 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1375 #define XLPORT_ENABLE_REG (0x20b)
1376
1377 #define XLMAC_CTRL (0x600)
1378 #define XLMAC_MODE (0x601)
1379 #define XLMAC_RX_MAX_SIZE (0x608)
1380 #define XLMAC_TX_CTRL (0x604)
1381 #define XLMAC_PAUSE_CTRL (0x60d)
1382 #define XLMAC_PFC_CTRL (0x60e)
1383
1384 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1385                                     struct ecore_ptt *p_ptt)
1386 {
1387         u8 loopback = 0, port = p_hwfn->port_id * 2;
1388
1389         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1390
1391         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1392         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1393                          port);
1394         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1395         /* XLMAC: SOFT RESET */
1396         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1397         /* XLMAC: Port Speed >= 10Gbps */
1398         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1399         /* XLMAC: Max Size */
1400         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1401         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1402                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1403                          0, port);
1404         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1405         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1406                          0x30ffffc000ULL, 0, port);
1407         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1408                          port); /* XLMAC: TX_EN, RX_EN */
1409         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1410         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1411                          0x1003 | (loopback << 2), 0, port);
1412         /* Enabled Parallel PFC interface */
1413         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1414
1415         /* XLPORT port enable */
1416         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1417 }
1418
1419 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1420                                        struct ecore_ptt *p_ptt)
1421 {
1422         u8 port = p_hwfn->port_id;
1423         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1424
1425         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1426
1427         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1428                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1429                  (port <<
1430                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1431                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1432
1433         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1434                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1435
1436         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1437                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1438
1439         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1440                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1441
1442         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1443                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1444
1445         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1446                  (0xA <<
1447                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1448                  (8 <<
1449                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1450
1451         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1452                  0xa853);
1453 }
1454
1455 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1456                                  struct ecore_ptt *p_ptt)
1457 {
1458         if (ECORE_IS_AH(p_hwfn->p_dev))
1459                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1460         else /* BB */
1461                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1462 }
1463
1464 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1465                                struct ecore_ptt *p_ptt,  u8 port)
1466 {
1467         int port_offset = port ? 0x800 : 0;
1468         u32 xmac_rxctrl = 0;
1469
1470         /* Reset of XMAC */
1471         /* FIXME: move to common start */
1472         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1473                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1474         OSAL_MSLEEP(1);
1475         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1476                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1477
1478         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1479
1480         /* Set the number of ports on the Warp Core to 10G */
1481         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1482
1483         /* Soft reset of XMAC */
1484         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1485                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1486         OSAL_MSLEEP(1);
1487         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1488                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1489
1490         /* FIXME: move to common end */
1491         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1492                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1493
1494         /* Set Max packet size: initialize XMAC block register for port 0 */
1495         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1496
1497         /* CRC append for Tx packets: init XMAC block register for port 1 */
1498         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1499
1500         /* Enable TX and RX: initialize XMAC block register for port 1 */
1501         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1502                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1503         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1504                                XMAC_REG_RX_CTRL_BB + port_offset);
1505         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1506         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1507 }
1508 #endif
1509
1510 static enum _ecore_status_t
1511 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1512                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1513 {
1514         u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size;
1515         u32 dpi_bit_shift, dpi_count;
1516         u32 min_dpis;
1517
1518         /* Calculate DPI size
1519          * ------------------
1520          * The PWM region contains Doorbell Pages. The first is reserverd for
1521          * the kernel for, e.g, L2. The others are free to be used by non-
1522          * trusted applications, typically from user space. Each page, called a
1523          * doorbell page is sectioned into windows that allow doorbells to be
1524          * issued in parallel by the kernel/application. The size of such a
1525          * window (a.k.a. WID) is 1kB.
1526          * Summary:
1527          *    1kB WID x N WIDS = DPI page size
1528          *    DPI page size x N DPIs = PWM region size
1529          * Notes:
1530          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1531          * in order to ensure that two applications won't share the same page.
1532          * It also must contain at least one WID per CPU to allow parallelism.
1533          * It also must be a power of 2, since it is stored as a bit shift.
1534          *
1535          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1536          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1537          * containing 4 WIDs.
1538          */
1539         dpi_page_size_1 = ECORE_WID_SIZE * n_cpus;
1540         dpi_page_size_2 = OSAL_MAX_T(u32, ECORE_WID_SIZE, OSAL_PAGE_SIZE);
1541         dpi_page_size = OSAL_MAX_T(u32, dpi_page_size_1, dpi_page_size_2);
1542         dpi_page_size = OSAL_ROUNDUP_POW_OF_TWO(dpi_page_size);
1543         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1544
1545         dpi_count = pwm_region_size / dpi_page_size;
1546
1547         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1548         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1549
1550         /* Update hwfn */
1551         p_hwfn->dpi_size = dpi_page_size;
1552         p_hwfn->dpi_count = dpi_count;
1553
1554         /* Update registers */
1555         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1556
1557         if (dpi_count < min_dpis)
1558                 return ECORE_NORESOURCES;
1559
1560         return ECORE_SUCCESS;
1561 }
1562
1563 enum ECORE_ROCE_EDPM_MODE {
1564         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1565         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1566         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1567 };
1568
1569 static enum _ecore_status_t
1570 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1571                               struct ecore_ptt *p_ptt)
1572 {
1573         u32 pwm_regsize, norm_regsize;
1574         u32 non_pwm_conn, min_addr_reg1;
1575         u32 db_bar_size, n_cpus;
1576         u32 roce_edpm_mode;
1577         u32 pf_dems_shift;
1578         enum _ecore_status_t rc = ECORE_SUCCESS;
1579         u8 cond;
1580
1581         db_bar_size = ecore_hw_bar_size(p_hwfn, BAR_ID_1);
1582         if (p_hwfn->p_dev->num_hwfns > 1)
1583                 db_bar_size /= 2;
1584
1585         /* Calculate doorbell regions
1586          * -----------------------------------
1587          * The doorbell BAR is made of two regions. The first is called normal
1588          * region and the second is called PWM region. In the normal region
1589          * each ICID has its own set of addresses so that writing to that
1590          * specific address identifies the ICID. In the Process Window Mode
1591          * region the ICID is given in the data written to the doorbell. The
1592          * above per PF register denotes the offset in the doorbell BAR in which
1593          * the PWM region begins.
1594          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1595          * non-PWM connection. The calculation below computes the total non-PWM
1596          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1597          * in units of 4,096 bytes.
1598          */
1599         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1600             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1601                                           OSAL_NULL) +
1602             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1603         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn, 4096);
1604         min_addr_reg1 = norm_regsize / 4096;
1605         pwm_regsize = db_bar_size - norm_regsize;
1606
1607         /* Check that the normal and PWM sizes are valid */
1608         if (db_bar_size < norm_regsize) {
1609                 DP_ERR(p_hwfn->p_dev,
1610                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1611                        db_bar_size, norm_regsize);
1612                 return ECORE_NORESOURCES;
1613         }
1614         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1615                 DP_ERR(p_hwfn->p_dev,
1616                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1617                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1618                        norm_regsize);
1619                 return ECORE_NORESOURCES;
1620         }
1621
1622         /* Calculate number of DPIs */
1623         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1624         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1625             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1626                 /* Either EDPM is mandatory, or we are attempting to allocate a
1627                  * WID per CPU.
1628                  */
1629                 n_cpus = OSAL_NUM_ACTIVE_CPU();
1630                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1631         }
1632
1633         cond = ((rc != ECORE_SUCCESS) &&
1634                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1635                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1636         if (cond || p_hwfn->dcbx_no_edpm) {
1637                 /* Either EDPM is disabled from user configuration, or it is
1638                  * disabled via DCBx, or it is not mandatory and we failed to
1639                  * allocated a WID per CPU.
1640                  */
1641                 n_cpus = 1;
1642                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1643
1644                 /* If we entered this flow due to DCBX then the DPM register is
1645                  * already configured.
1646                  */
1647         }
1648
1649         DP_INFO(p_hwfn,
1650                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
1651                 norm_regsize, pwm_regsize);
1652         DP_INFO(p_hwfn,
1653                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1654                 p_hwfn->dpi_size, p_hwfn->dpi_count,
1655                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1656                 "disabled" : "enabled");
1657
1658         /* Check return codes from above calls */
1659         if (rc != ECORE_SUCCESS) {
1660                 DP_ERR(p_hwfn,
1661                        "Failed to allocate enough DPIs\n");
1662                 return ECORE_NORESOURCES;
1663         }
1664
1665         /* Update hwfn */
1666         p_hwfn->dpi_start_offset = norm_regsize;
1667
1668         /* Update registers */
1669         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1670         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
1671         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1672         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1673
1674         return ECORE_SUCCESS;
1675 }
1676
1677 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
1678                                                struct ecore_ptt *p_ptt,
1679                                                int hw_mode)
1680 {
1681         enum _ecore_status_t rc = ECORE_SUCCESS;
1682
1683         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
1684                             hw_mode);
1685         if (rc != ECORE_SUCCESS)
1686                 return rc;
1687 #ifndef ASIC_ONLY
1688         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
1689                 return ECORE_SUCCESS;
1690
1691         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1692                 if (ECORE_IS_AH(p_hwfn->p_dev))
1693                         return ECORE_SUCCESS;
1694                 else if (ECORE_IS_BB(p_hwfn->p_dev))
1695                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
1696         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1697                 if (p_hwfn->p_dev->num_hwfns > 1) {
1698                         /* Activate OPTE in CMT */
1699                         u32 val;
1700
1701                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
1702                         val |= 0x10;
1703                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
1704                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
1705                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
1706                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
1707                         ecore_wr(p_hwfn, p_ptt,
1708                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
1709                         ecore_wr(p_hwfn, p_ptt,
1710                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
1711                         ecore_wr(p_hwfn, p_ptt,
1712                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
1713                                  0x55555555);
1714                 }
1715
1716                 ecore_emul_link_init(p_hwfn, p_ptt);
1717         } else {
1718                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
1719         }
1720 #endif
1721
1722         return rc;
1723 }
1724
1725 static enum _ecore_status_t
1726 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
1727                  struct ecore_ptt *p_ptt,
1728                  struct ecore_tunnel_info *p_tunn,
1729                  int hw_mode,
1730                  bool b_hw_start,
1731                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
1732 {
1733         u8 rel_pf_id = p_hwfn->rel_pf_id;
1734         u32 prs_reg;
1735         enum _ecore_status_t rc = ECORE_SUCCESS;
1736         u16 ctrl;
1737         int pos;
1738
1739         if (p_hwfn->mcp_info) {
1740                 struct ecore_mcp_function_info *p_info;
1741
1742                 p_info = &p_hwfn->mcp_info->func_info;
1743                 if (p_info->bandwidth_min)
1744                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1745
1746                 /* Update rate limit once we'll actually have a link */
1747                 p_hwfn->qm_info.pf_rl = 100000;
1748         }
1749         ecore_cxt_hw_init_pf(p_hwfn);
1750
1751         ecore_int_igu_init_rt(p_hwfn);
1752
1753         /* Set VLAN in NIG if needed */
1754         if (hw_mode & (1 << MODE_MF_SD)) {
1755                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1756                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1757                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1758                              p_hwfn->hw_info.ovlan);
1759         }
1760
1761         /* Enable classification by MAC if needed */
1762         if (hw_mode & (1 << MODE_MF_SI)) {
1763                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1764                            "Configuring TAGMAC_CLS_TYPE\n");
1765                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
1766                              1);
1767         }
1768
1769         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
1770         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1771                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
1772         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1773                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
1774         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1775
1776         /* perform debug configuration when chip is out of reset */
1777         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
1778
1779         /* Cleanup chip from previous driver if such remains exist */
1780         rc = ecore_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1781         if (rc != ECORE_SUCCESS) {
1782                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_RAMROD_FAIL);
1783                 return rc;
1784         }
1785
1786         /* PF Init sequence */
1787         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1788         if (rc)
1789                 return rc;
1790
1791         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1792         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1793         if (rc)
1794                 return rc;
1795
1796         /* Pure runtime initializations - directly to the HW  */
1797         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1798
1799         /* PCI relaxed ordering causes a decrease in the performance on some
1800          * systems. Till a root cause is found, disable this attribute in the
1801          * PCI config space.
1802          */
1803         /* Not in use @DPDK
1804         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
1805         * if (!pos) {
1806         *       DP_NOTICE(p_hwfn, true,
1807         *                 "Failed to find the PCIe Cap\n");
1808         *       return ECORE_IO;
1809         * }
1810         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
1811         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1812         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
1813         */
1814
1815         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1816         if (rc)
1817                 return rc;
1818         if (b_hw_start) {
1819                 /* enable interrupts */
1820                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
1821                 if (rc != ECORE_SUCCESS)
1822                         return rc;
1823
1824                 /* send function start command */
1825                 rc = ecore_sp_pf_start(p_hwfn, p_tunn, p_hwfn->p_dev->mf_mode,
1826                                        allow_npar_tx_switch);
1827                 if (rc) {
1828                         DP_NOTICE(p_hwfn, true,
1829                                   "Function start ramrod failed\n");
1830                 } else {
1831                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1832                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1833                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1834
1835                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
1836                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
1837                                          (1 << 2));
1838                                 ecore_wr(p_hwfn, p_ptt,
1839                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1840                                     0x100);
1841                         }
1842                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1843                                    "PRS_REG_SEARCH registers after start PFn\n");
1844                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
1845                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1846                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
1847                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
1848                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1849                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
1850                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
1851                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1852                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
1853                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
1854                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1855                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
1856                         prs_reg = ecore_rd(p_hwfn, p_ptt,
1857                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
1858                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1859                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
1860                                    prs_reg);
1861                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
1862                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
1863                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
1864                 }
1865         }
1866         return rc;
1867 }
1868
1869 static enum _ecore_status_t
1870 ecore_change_pci_hwfn(struct ecore_hwfn *p_hwfn,
1871                       struct ecore_ptt *p_ptt, u8 enable)
1872 {
1873         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1874
1875         /* Change PF in PXP */
1876         ecore_wr(p_hwfn, p_ptt,
1877                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1878
1879         /* wait until value is set - try for 1 second every 50us */
1880         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1881                 val = ecore_rd(p_hwfn, p_ptt,
1882                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1883                 if (val == set_val)
1884                         break;
1885
1886                 OSAL_UDELAY(50);
1887         }
1888
1889         if (val != set_val) {
1890                 DP_NOTICE(p_hwfn, true,
1891                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1892                 return ECORE_UNKNOWN_ERROR;
1893         }
1894
1895         return ECORE_SUCCESS;
1896 }
1897
1898 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
1899                                   struct ecore_ptt *p_main_ptt)
1900 {
1901         /* Read shadow of current MFW mailbox */
1902         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
1903         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1904                     p_hwfn->mcp_info->mfw_mb_cur,
1905                     p_hwfn->mcp_info->mfw_mb_length);
1906 }
1907
1908 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
1909                                     struct ecore_hw_init_params *p_params)
1910 {
1911         if (p_params->p_tunn) {
1912                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1913                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1914         }
1915
1916         p_hwfn->b_int_enabled = 1;
1917
1918         return ECORE_SUCCESS;
1919 }
1920
1921 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
1922                                    struct ecore_hw_init_params *p_params)
1923 {
1924         struct ecore_load_req_params load_req_params;
1925         u32 load_code, param, drv_mb_param;
1926         bool b_default_mtu = true;
1927         struct ecore_hwfn *p_hwfn;
1928         enum _ecore_status_t rc = ECORE_SUCCESS, mfw_rc;
1929         int i;
1930
1931         if ((p_params->int_mode == ECORE_INT_MODE_MSI) &&
1932             (p_dev->num_hwfns > 1)) {
1933                 DP_NOTICE(p_dev, false,
1934                           "MSI mode is not supported for CMT devices\n");
1935                 return ECORE_INVAL;
1936         }
1937
1938         if (IS_PF(p_dev)) {
1939                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
1940                 if (rc != ECORE_SUCCESS)
1941                         return rc;
1942         }
1943
1944         for_each_hwfn(p_dev, i) {
1945                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1946
1947                 /* If management didn't provide a default, set one of our own */
1948                 if (!p_hwfn->hw_info.mtu) {
1949                         p_hwfn->hw_info.mtu = 1500;
1950                         b_default_mtu = false;
1951                 }
1952
1953                 if (IS_VF(p_dev)) {
1954                         ecore_vf_start(p_hwfn, p_params);
1955                         continue;
1956                 }
1957
1958                 /* Enable DMAE in PXP */
1959                 rc = ecore_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1960                 if (rc != ECORE_SUCCESS)
1961                         return rc;
1962
1963                 rc = ecore_calc_hw_mode(p_hwfn);
1964                 if (rc != ECORE_SUCCESS)
1965                         return rc;
1966
1967                 OSAL_MEM_ZERO(&load_req_params, sizeof(load_req_params));
1968                 load_req_params.drv_role = p_params->is_crash_kernel ?
1969                                            ECORE_DRV_ROLE_KDUMP :
1970                                            ECORE_DRV_ROLE_OS;
1971                 load_req_params.timeout_val = p_params->mfw_timeout_val;
1972                 load_req_params.avoid_eng_reset = p_params->avoid_eng_reset;
1973                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1974                                         &load_req_params);
1975                 if (rc != ECORE_SUCCESS) {
1976                         DP_NOTICE(p_hwfn, true,
1977                                   "Failed sending a LOAD_REQ command\n");
1978                         return rc;
1979                 }
1980
1981                 load_code = load_req_params.load_code;
1982                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1983                            "Load request was sent. Load code: 0x%x\n",
1984                            load_code);
1985
1986                 /* CQ75580:
1987                  * When coming back from hiberbate state, the registers from
1988                  * which shadow is read initially are not initialized. It turns
1989                  * out that these registers get initialized during the call to
1990                  * ecore_mcp_load_req request. So we need to reread them here
1991                  * to get the proper shadow register value.
1992                  * Note: This is a workaround for the missing MFW
1993                  * initialization. It may be removed once the implementation
1994                  * is done.
1995                  */
1996                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1997
1998                 /* Only relevant for recovery:
1999                  * Clear the indication after the LOAD_REQ command is responded
2000                  * by the MFW.
2001                  */
2002                 p_dev->recov_in_prog = false;
2003
2004                 p_hwfn->first_on_engine = (load_code ==
2005                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2006
2007                 if (!qm_lock_init) {
2008                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2009                         qm_lock_init = true;
2010                 }
2011
2012                 switch (load_code) {
2013                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2014                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2015                                                   p_hwfn->hw_info.hw_mode);
2016                         if (rc != ECORE_SUCCESS)
2017                                 break;
2018                         /* Fall into */
2019                 case FW_MSG_CODE_DRV_LOAD_PORT:
2020                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2021                                                 p_hwfn->hw_info.hw_mode);
2022                         if (rc != ECORE_SUCCESS)
2023                                 break;
2024                         /* Fall into */
2025                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2026                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2027                                               p_params->p_tunn,
2028                                               p_hwfn->hw_info.hw_mode,
2029                                               p_params->b_hw_start,
2030                                               p_params->int_mode,
2031                                               p_params->allow_npar_tx_switch);
2032                         break;
2033                 default:
2034                         DP_NOTICE(p_hwfn, false,
2035                                   "Unexpected load code [0x%08x]", load_code);
2036                         rc = ECORE_NOTIMPL;
2037                         break;
2038                 }
2039
2040                 if (rc != ECORE_SUCCESS)
2041                         DP_NOTICE(p_hwfn, true,
2042                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2043                                   load_code, rc);
2044
2045                 /* ACK mfw regardless of success or failure of initialization */
2046                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2047                                        DRV_MSG_CODE_LOAD_DONE,
2048                                        0, &load_code, &param);
2049                 if (rc != ECORE_SUCCESS)
2050                         return rc;
2051
2052                 if (mfw_rc != ECORE_SUCCESS) {
2053                         DP_NOTICE(p_hwfn, true,
2054                                   "Failed sending a LOAD_DONE command\n");
2055                         return mfw_rc;
2056                 }
2057
2058                 /* send DCBX attention request command */
2059                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2060                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2061                 mfw_rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2062                                        DRV_MSG_CODE_SET_DCBX,
2063                                        1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
2064                                        &load_code, &param);
2065                 if (mfw_rc != ECORE_SUCCESS) {
2066                         DP_NOTICE(p_hwfn, true,
2067                                   "Failed to send DCBX attention request\n");
2068                         return mfw_rc;
2069                 }
2070
2071                 p_hwfn->hw_init_done = true;
2072         }
2073
2074         if (IS_PF(p_dev)) {
2075                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2076                 drv_mb_param = STORM_FW_VERSION;
2077                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2078                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2079                                    drv_mb_param, &load_code, &param);
2080                 if (rc != ECORE_SUCCESS)
2081                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2082
2083                 if (!b_default_mtu)
2084                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2085                                                       p_hwfn->hw_info.mtu);
2086                 if (rc != ECORE_SUCCESS)
2087                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2088
2089                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2090                                                       p_hwfn->p_main_ptt,
2091                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2092                 if (rc != ECORE_SUCCESS)
2093                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2094         }
2095
2096         return rc;
2097 }
2098
2099 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2100 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2101                                  struct ecore_hwfn *p_hwfn,
2102                                  struct ecore_ptt *p_ptt)
2103 {
2104         int i;
2105
2106         /* close timers */
2107         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2108         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2109         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2110                                                                         i++) {
2111                 if ((!ecore_rd(p_hwfn, p_ptt,
2112                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2113                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2114                         break;
2115
2116                 /* Dependent on number of connection/tasks, possibly
2117                  * 1ms sleep is required between polls
2118                  */
2119                 OSAL_MSLEEP(1);
2120         }
2121
2122         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2123                 return;
2124
2125         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2126                   " [Connection %02x Tasks %02x]\n",
2127                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2128                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2129 }
2130
2131 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2132 {
2133         int j;
2134
2135         for_each_hwfn(p_dev, j) {
2136                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2137                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2138
2139                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2140         }
2141 }
2142
2143 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2144                                                  struct ecore_ptt *p_ptt,
2145                                                  u32 addr, u32 expected_val)
2146 {
2147         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2148
2149         if (val != expected_val) {
2150                 DP_NOTICE(p_hwfn, true,
2151                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2152                           addr, val, expected_val);
2153                 return ECORE_UNKNOWN_ERROR;
2154         }
2155
2156         return ECORE_SUCCESS;
2157 }
2158
2159 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2160 {
2161         struct ecore_hwfn *p_hwfn;
2162         struct ecore_ptt *p_ptt;
2163         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2164         int j;
2165
2166         for_each_hwfn(p_dev, j) {
2167                 p_hwfn = &p_dev->hwfns[j];
2168                 p_ptt = p_hwfn->p_main_ptt;
2169
2170                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2171
2172                 if (IS_VF(p_dev)) {
2173                         ecore_vf_pf_int_cleanup(p_hwfn);
2174                         rc = ecore_vf_pf_reset(p_hwfn);
2175                         if (rc != ECORE_SUCCESS) {
2176                                 DP_NOTICE(p_hwfn, true,
2177                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2178                                           rc);
2179                                 rc2 = ECORE_UNKNOWN_ERROR;
2180                         }
2181                         continue;
2182                 }
2183
2184                 /* mark the hw as uninitialized... */
2185                 p_hwfn->hw_init_done = false;
2186
2187                 /* Send unload command to MCP */
2188                 if (!p_dev->recov_in_prog) {
2189                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2190                         if (rc != ECORE_SUCCESS) {
2191                                 DP_NOTICE(p_hwfn, true,
2192                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2193                                           rc);
2194                                 rc2 = ECORE_UNKNOWN_ERROR;
2195                         }
2196                 }
2197
2198                 OSAL_DPC_SYNC(p_hwfn);
2199
2200                 /* After this point no MFW attentions are expected, e.g. prevent
2201                  * race between pf stop and dcbx pf update.
2202                  */
2203
2204                 rc = ecore_sp_pf_stop(p_hwfn);
2205                 if (rc != ECORE_SUCCESS) {
2206                         DP_NOTICE(p_hwfn, true,
2207                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2208                                   rc);
2209                         rc2 = ECORE_UNKNOWN_ERROR;
2210                 }
2211
2212                 /* perform debug action after PF stop was sent */
2213                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2214
2215                 /* close NIG to BRB gate */
2216                 ecore_wr(p_hwfn, p_ptt,
2217                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2218
2219                 /* close parser */
2220                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2221                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2222                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2223                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2224                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2225
2226                 /* @@@TBD - clean transmission queues (5.b) */
2227                 /* @@@TBD - clean BTB (5.c) */
2228
2229                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2230
2231                 /* @@@TBD - verify DMAE requests are done (8) */
2232
2233                 /* Disable Attention Generation */
2234                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2235                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2236                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2237                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2238                 /* Need to wait 1ms to guarantee SBs are cleared */
2239                 OSAL_MSLEEP(1);
2240
2241                 if (!p_dev->recov_in_prog) {
2242                         ecore_verify_reg_val(p_hwfn, p_ptt,
2243                                              QM_REG_USG_CNT_PF_TX, 0);
2244                         ecore_verify_reg_val(p_hwfn, p_ptt,
2245                                              QM_REG_USG_CNT_PF_OTHER, 0);
2246                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2247                 }
2248
2249                 /* Disable PF in HW blocks */
2250                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2251                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2252
2253                 if (!p_dev->recov_in_prog) {
2254                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2255                         if (rc != ECORE_SUCCESS) {
2256                                 DP_NOTICE(p_hwfn, true,
2257                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2258                                           rc);
2259                                 rc2 = ECORE_UNKNOWN_ERROR;
2260                         }
2261                 }
2262         } /* hwfn loop */
2263
2264         if (IS_PF(p_dev)) {
2265                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2266                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2267
2268                 /* Disable DMAE in PXP - in CMT, this should only be done for
2269                  * first hw-function, and only after all transactions have
2270                  * stopped for all active hw-functions.
2271                  */
2272                 rc = ecore_change_pci_hwfn(p_hwfn, p_ptt, false);
2273                 if (rc != ECORE_SUCCESS) {
2274                         DP_NOTICE(p_hwfn, true,
2275                                   "ecore_change_pci_hwfn failed. rc = %d.\n",
2276                                   rc);
2277                         rc2 = ECORE_UNKNOWN_ERROR;
2278                 }
2279         }
2280
2281         return rc2;
2282 }
2283
2284 void ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2285 {
2286         int j;
2287
2288         for_each_hwfn(p_dev, j) {
2289                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2290                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2291
2292                 if (IS_VF(p_dev)) {
2293                         ecore_vf_pf_int_cleanup(p_hwfn);
2294                         continue;
2295                 }
2296
2297                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2298                            "Shutting down the fastpath\n");
2299
2300                 ecore_wr(p_hwfn, p_ptt,
2301                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2302
2303                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2304                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2305                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2306                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2307                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2308
2309                 /* @@@TBD - clean transmission queues (5.b) */
2310                 /* @@@TBD - clean BTB (5.c) */
2311
2312                 /* @@@TBD - verify DMAE requests are done (8) */
2313
2314                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2315                 /* Need to wait 1ms to guarantee SBs are cleared */
2316                 OSAL_MSLEEP(1);
2317         }
2318 }
2319
2320 void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2321 {
2322         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2323
2324         if (IS_VF(p_hwfn->p_dev))
2325                 return;
2326
2327         /* If roce info is allocated it means roce is initialized and should
2328          * be enabled in searcher.
2329          */
2330         if (p_hwfn->p_rdma_info) {
2331                 if (p_hwfn->b_rdma_enabled_in_prs)
2332                         ecore_wr(p_hwfn, p_ptt,
2333                                  p_hwfn->rdma_prs_search_reg, 0x1);
2334                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2335         }
2336
2337         /* Re-open incoming traffic */
2338         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2339                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2340 }
2341
2342 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2343 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2344 {
2345         ecore_ptt_pool_free(p_hwfn);
2346         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2347 }
2348
2349 /* Setup bar access */
2350 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2351 {
2352         /* clear indirect access */
2353         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2354                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2355                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2356                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2357                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2358                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2359                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2360                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2361                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2362         } else {
2363                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2364                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2365                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2366                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2367                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2368                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2369                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2370                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2371         }
2372
2373         /* Clean Previous errors if such exist */
2374         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2375                  PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2376
2377         /* enable internal target-read */
2378         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2379                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2380 }
2381
2382 static void get_function_id(struct ecore_hwfn *p_hwfn)
2383 {
2384         /* ME Register */
2385         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2386                                                   PXP_PF_ME_OPAQUE_ADDR);
2387
2388         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2389
2390         /* Bits 16-19 from the ME registers are the pf_num */
2391         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2392         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2393                                       PXP_CONCRETE_FID_PFID);
2394         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2395                                     PXP_CONCRETE_FID_PORT);
2396
2397         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2398                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2399                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2400 }
2401
2402 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2403 {
2404         u32 *feat_num = p_hwfn->hw_info.feat_num;
2405         struct ecore_sb_cnt_info sb_cnt_info;
2406         int num_features = 1;
2407
2408         /* L2 Queues require each: 1 status block. 1 L2 queue */
2409         feat_num[ECORE_PF_L2_QUE] =
2410             OSAL_MIN_T(u32,
2411                        RESC_NUM(p_hwfn, ECORE_SB) / num_features,
2412                        RESC_NUM(p_hwfn, ECORE_L2_QUEUE));
2413
2414         OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2415         ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2416         feat_num[ECORE_VF_L2_QUE] =
2417                 OSAL_MIN_T(u32,
2418                            RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2419                            FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2420                            sb_cnt_info.sb_iov_cnt);
2421
2422         feat_num[ECORE_FCOE_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2423                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2424         feat_num[ECORE_ISCSI_CQ] = OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_SB),
2425                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
2426
2427         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2428                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2429                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2430                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2431                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2432                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2433                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2434                    RESC_NUM(p_hwfn, ECORE_SB));
2435 }
2436
2437 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2438 {
2439         switch (res_id) {
2440         case ECORE_SB:
2441                 return "SB";
2442         case ECORE_L2_QUEUE:
2443                 return "L2_QUEUE";
2444         case ECORE_VPORT:
2445                 return "VPORT";
2446         case ECORE_RSS_ENG:
2447                 return "RSS_ENG";
2448         case ECORE_PQ:
2449                 return "PQ";
2450         case ECORE_RL:
2451                 return "RL";
2452         case ECORE_MAC:
2453                 return "MAC";
2454         case ECORE_VLAN:
2455                 return "VLAN";
2456         case ECORE_RDMA_CNQ_RAM:
2457                 return "RDMA_CNQ_RAM";
2458         case ECORE_ILT:
2459                 return "ILT";
2460         case ECORE_LL2_QUEUE:
2461                 return "LL2_QUEUE";
2462         case ECORE_CMDQS_CQS:
2463                 return "CMDQS_CQS";
2464         case ECORE_RDMA_STATS_QUEUE:
2465                 return "RDMA_STATS_QUEUE";
2466         case ECORE_BDQ:
2467                 return "BDQ";
2468         default:
2469                 return "UNKNOWN_RESOURCE";
2470         }
2471 }
2472
2473 static enum _ecore_status_t
2474 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2475                               enum ecore_resources res_id, u32 resc_max_val,
2476                               u32 *p_mcp_resp)
2477 {
2478         enum _ecore_status_t rc;
2479
2480         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_hwfn->p_main_ptt, res_id,
2481                                         resc_max_val, p_mcp_resp);
2482         if (rc != ECORE_SUCCESS) {
2483                 DP_NOTICE(p_hwfn, true,
2484                           "MFW response failure for a max value setting of resource %d [%s]\n",
2485                           res_id, ecore_hw_get_resc_name(res_id));
2486                 return rc;
2487         }
2488
2489         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2490                 DP_INFO(p_hwfn,
2491                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2492                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2493
2494         return ECORE_SUCCESS;
2495 }
2496
2497 static enum _ecore_status_t
2498 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn)
2499 {
2500         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2501         u32 resc_max_val, mcp_resp;
2502         u8 res_id;
2503         enum _ecore_status_t rc;
2504
2505         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2506                 /* @DPDK */
2507                 switch (res_id) {
2508                 case ECORE_LL2_QUEUE:
2509                 case ECORE_RDMA_CNQ_RAM:
2510                 case ECORE_RDMA_STATS_QUEUE:
2511                 case ECORE_BDQ:
2512                         resc_max_val = 0;
2513                         break;
2514                 default:
2515                         continue;
2516                 }
2517
2518                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, res_id,
2519                                                    resc_max_val, &mcp_resp);
2520                 if (rc != ECORE_SUCCESS)
2521                         return rc;
2522
2523                 /* There's no point to continue to the next resource if the
2524                  * command is not supported by the MFW.
2525                  * We do continue if the command is supported but the resource
2526                  * is unknown to the MFW. Such a resource will be later
2527                  * configured with the default allocation values.
2528                  */
2529                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2530                         return ECORE_NOTIMPL;
2531         }
2532
2533         return ECORE_SUCCESS;
2534 }
2535
2536 static
2537 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2538                                             enum ecore_resources res_id,
2539                                             u32 *p_resc_num, u32 *p_resc_start)
2540 {
2541         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2542         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2543         struct ecore_sb_cnt_info sb_cnt_info;
2544
2545         switch (res_id) {
2546         case ECORE_SB:
2547                 OSAL_MEM_ZERO(&sb_cnt_info, sizeof(sb_cnt_info));
2548                 ecore_int_get_num_sbs(p_hwfn, &sb_cnt_info);
2549                 *p_resc_num = sb_cnt_info.sb_cnt;
2550                 break;
2551         case ECORE_L2_QUEUE:
2552                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2553                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
2554                 break;
2555         case ECORE_VPORT:
2556                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2557                                  MAX_NUM_VPORTS_BB) / num_funcs;
2558                 break;
2559         case ECORE_RSS_ENG:
2560                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2561                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2562                 break;
2563         case ECORE_PQ:
2564                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2565                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
2566                 break;
2567         case ECORE_RL:
2568                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2569                 break;
2570         case ECORE_MAC:
2571         case ECORE_VLAN:
2572                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2573                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2574                 break;
2575         case ECORE_ILT:
2576                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2577                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2578                 break;
2579         case ECORE_LL2_QUEUE:
2580                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2581                 break;
2582         case ECORE_RDMA_CNQ_RAM:
2583         case ECORE_CMDQS_CQS:
2584                 /* CNQ/CMDQS are the same resource */
2585                 /* @DPDK */
2586                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
2587                 break;
2588         case ECORE_RDMA_STATS_QUEUE:
2589                 /* @DPDK */
2590                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2591                                  MAX_NUM_VPORTS_BB) / num_funcs;
2592                 break;
2593         case ECORE_BDQ:
2594                 /* @DPDK */
2595                 *p_resc_num = 0;
2596                 break;
2597         default:
2598                 break;
2599         }
2600
2601
2602         switch (res_id) {
2603         case ECORE_BDQ:
2604                 if (!*p_resc_num)
2605                         *p_resc_start = 0;
2606                 break;
2607         default:
2608                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2609                 break;
2610         }
2611
2612         return ECORE_SUCCESS;
2613 }
2614
2615 static enum _ecore_status_t
2616 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
2617                          bool drv_resc_alloc)
2618 {
2619         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2620         u32 mcp_resp, *p_resc_num, *p_resc_start;
2621         enum _ecore_status_t rc;
2622
2623         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2624         p_resc_start = &RESC_START(p_hwfn, res_id);
2625
2626         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2627                                     &dflt_resc_start);
2628         if (rc != ECORE_SUCCESS) {
2629                 DP_ERR(p_hwfn,
2630                        "Failed to get default amount for resource %d [%s]\n",
2631                         res_id, ecore_hw_get_resc_name(res_id));
2632                 return rc;
2633         }
2634
2635 #ifndef ASIC_ONLY
2636         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2637                 *p_resc_num = dflt_resc_num;
2638                 *p_resc_start = dflt_resc_start;
2639                 goto out;
2640         }
2641 #endif
2642
2643         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2644                                      &mcp_resp, p_resc_num, p_resc_start);
2645         if (rc != ECORE_SUCCESS) {
2646                 DP_NOTICE(p_hwfn, true,
2647                           "MFW response failure for an allocation request for"
2648                           " resource %d [%s]\n",
2649                           res_id, ecore_hw_get_resc_name(res_id));
2650                 return rc;
2651         }
2652
2653         /* Default driver values are applied in the following cases:
2654          * - The resource allocation MB command is not supported by the MFW
2655          * - There is an internal error in the MFW while processing the request
2656          * - The resource ID is unknown to the MFW
2657          */
2658         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2659                 DP_INFO(p_hwfn,
2660                         "Failed to receive allocation info for resource %d [%s]."
2661                         " mcp_resp = 0x%x. Applying default values"
2662                         " [%d,%d].\n",
2663                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
2664                         dflt_resc_num, dflt_resc_start);
2665
2666                 *p_resc_num = dflt_resc_num;
2667                 *p_resc_start = dflt_resc_start;
2668                 goto out;
2669         }
2670
2671         /* TBD - remove this when revising the handling of the SB resource */
2672         if (res_id == ECORE_SB) {
2673                 /* Excluding the slowpath SB */
2674                 *p_resc_num -= 1;
2675                 *p_resc_start -= p_hwfn->enabled_func_idx;
2676         }
2677
2678         if (*p_resc_num != dflt_resc_num || *p_resc_start != dflt_resc_start) {
2679                 DP_INFO(p_hwfn,
2680                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
2681                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
2682                         *p_resc_start, dflt_resc_num, dflt_resc_start,
2683                         drv_resc_alloc ? " - Applying default values" : "");
2684                 if (drv_resc_alloc) {
2685                         *p_resc_num = dflt_resc_num;
2686                         *p_resc_start = dflt_resc_start;
2687                 }
2688         }
2689 out:
2690         return ECORE_SUCCESS;
2691 }
2692
2693 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
2694                                                    bool drv_resc_alloc)
2695 {
2696         enum _ecore_status_t rc;
2697         u8 res_id;
2698
2699         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2700                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
2701                 if (rc != ECORE_SUCCESS)
2702                         return rc;
2703         }
2704
2705         return ECORE_SUCCESS;
2706 }
2707
2708 #define ECORE_RESC_ALLOC_LOCK_RETRY_CNT         10
2709 #define ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US    10000 /* 10 msec */
2710
2711 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
2712                                               bool drv_resc_alloc)
2713 {
2714         struct ecore_resc_unlock_params resc_unlock_params;
2715         struct ecore_resc_lock_params resc_lock_params;
2716         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2717         u8 res_id;
2718         enum _ecore_status_t rc;
2719 #ifndef ASIC_ONLY
2720         u32 *resc_start = p_hwfn->hw_info.resc_start;
2721         u32 *resc_num = p_hwfn->hw_info.resc_num;
2722         /* For AH, an equal share of the ILT lines between the maximal number of
2723          * PFs is not enough for RoCE. This would be solved by the future
2724          * resource allocation scheme, but isn't currently present for
2725          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
2726          * to work - the BB number of ILT lines divided by its max PFs number.
2727          */
2728         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
2729 #endif
2730
2731         /* Setting the max values of the soft resources and the following
2732          * resources allocation queries should be atomic. Since several PFs can
2733          * run in parallel - a resource lock is needed.
2734          * If either the resource lock or resource set value commands are not
2735          * supported - skip the the max values setting, release the lock if
2736          * needed, and proceed to the queries. Other failures, including a
2737          * failure to acquire the lock, will cause this function to fail.
2738          * Old drivers that don't acquire the lock can run in parallel, and
2739          * their allocation values won't be affected by the updated max values.
2740          */
2741         OSAL_MEM_ZERO(&resc_lock_params, sizeof(resc_lock_params));
2742         resc_lock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2743         resc_lock_params.retry_num = ECORE_RESC_ALLOC_LOCK_RETRY_CNT;
2744         resc_lock_params.retry_interval = ECORE_RESC_ALLOC_LOCK_RETRY_INTVL_US;
2745         resc_lock_params.sleep_b4_retry = true;
2746         OSAL_MEM_ZERO(&resc_unlock_params, sizeof(resc_unlock_params));
2747         resc_unlock_params.resource = ECORE_RESC_LOCK_RESC_ALLOC;
2748
2749         rc = ecore_mcp_resc_lock(p_hwfn, p_hwfn->p_main_ptt, &resc_lock_params);
2750         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2751                 return rc;
2752         } else if (rc == ECORE_NOTIMPL) {
2753                 DP_INFO(p_hwfn,
2754                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2755         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
2756                 DP_NOTICE(p_hwfn, false,
2757                           "Failed to acquire the resource lock for the resource allocation commands\n");
2758                 rc = ECORE_BUSY;
2759                 goto unlock_and_exit;
2760         } else {
2761                 rc = ecore_hw_set_soft_resc_size(p_hwfn);
2762                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
2763                         DP_NOTICE(p_hwfn, false,
2764                                   "Failed to set the max values of the soft resources\n");
2765                         goto unlock_and_exit;
2766                 } else if (rc == ECORE_NOTIMPL) {
2767                         DP_INFO(p_hwfn,
2768                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2769                         rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2770                                                    &resc_unlock_params);
2771                         if (rc != ECORE_SUCCESS)
2772                                 DP_INFO(p_hwfn,
2773                                         "Failed to release the resource lock for the resource allocation commands\n");
2774                 }
2775         }
2776
2777         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
2778         if (rc != ECORE_SUCCESS)
2779                 goto unlock_and_exit;
2780
2781         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2782                 rc = ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt,
2783                                            &resc_unlock_params);
2784                 if (rc != ECORE_SUCCESS)
2785                         DP_INFO(p_hwfn,
2786                                 "Failed to release the resource lock for the resource allocation commands\n");
2787         }
2788
2789 #ifndef ASIC_ONLY
2790         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2791                 /* Reduced build contains less PQs */
2792                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
2793                         resc_num[ECORE_PQ] = 32;
2794                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
2795                             p_hwfn->enabled_func_idx;
2796                 }
2797
2798                 /* For AH emulation, since we have a possible maximal number of
2799                  * 16 enabled PFs, in case there are not enough ILT lines -
2800                  * allocate only first PF as RoCE and have all the other ETH
2801                  * only with less ILT lines.
2802                  */
2803                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
2804                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
2805                                                          resc_num[ECORE_ILT],
2806                                                          roce_min_ilt_lines);
2807         }
2808
2809         /* Correct the common ILT calculation if PF0 has more */
2810         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
2811             p_hwfn->p_dev->b_is_emul_full &&
2812             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
2813                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
2814                     resc_num[ECORE_ILT];
2815 #endif
2816
2817         /* Sanity for ILT */
2818         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2819             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2820                 DP_NOTICE(p_hwfn, true,
2821                           "Can't assign ILT pages [%08x,...,%08x]\n",
2822                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
2823                                                                   ECORE_ILT) -
2824                           1);
2825                 return ECORE_INVAL;
2826         }
2827
2828         ecore_hw_set_feat(p_hwfn);
2829
2830         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2831                    "The numbers for each resource are:\n");
2832         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
2833                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
2834                            ecore_hw_get_resc_name(res_id),
2835                            RESC_NUM(p_hwfn, res_id),
2836                            RESC_START(p_hwfn, res_id));
2837
2838         return ECORE_SUCCESS;
2839
2840 unlock_and_exit:
2841         ecore_mcp_resc_unlock(p_hwfn, p_hwfn->p_main_ptt, &resc_unlock_params);
2842         return rc;
2843 }
2844
2845 static enum _ecore_status_t
2846 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
2847                       struct ecore_ptt *p_ptt,
2848                       struct ecore_hw_prepare_params *p_params)
2849 {
2850         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
2851         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2852         struct ecore_mcp_link_params *link;
2853         enum _ecore_status_t rc;
2854
2855         /* Read global nvm_cfg address */
2856         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2857
2858         /* Verify MCP has initialized it */
2859         if (!nvm_cfg_addr) {
2860                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
2861                 if (p_params->b_relaxed_probe)
2862                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
2863                 return ECORE_INVAL;
2864         }
2865
2866 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2867
2868         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2869
2870         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2871             OFFSETOF(struct nvm_cfg1, glob) + OFFSETOF(struct nvm_cfg1_glob,
2872                                                        core_cfg);
2873
2874         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
2875
2876         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2877                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2878         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2879                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
2880                 break;
2881         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2882                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
2883                 break;
2884         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2885                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
2886                 break;
2887         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2888                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
2889                 break;
2890         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2891                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
2892                 break;
2893         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2894                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
2895                 break;
2896         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2897                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
2898                 break;
2899         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2900                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
2901                 break;
2902         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2903                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
2904                 break;
2905         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2906                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
2907                 break;
2908         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2909                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
2910                 break;
2911         default:
2912                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
2913                           core_cfg);
2914                 break;
2915         }
2916
2917         /* Read DCBX configuration */
2918         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2919                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2920         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
2921                              port_cfg_addr +
2922                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
2923         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
2924                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
2925         switch (dcbx_mode) {
2926         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
2927                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
2928                 break;
2929         case NVM_CFG1_PORT_DCBX_MODE_CEE:
2930                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
2931                 break;
2932         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
2933                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
2934                 break;
2935         default:
2936                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
2937         }
2938
2939         /* Read default link configuration */
2940         link = &p_hwfn->mcp_info->link_input;
2941         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2942             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2943         link_temp = ecore_rd(p_hwfn, p_ptt,
2944                              port_cfg_addr +
2945                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
2946         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2947         link->speed.advertised_speeds = link_temp;
2948
2949         link_temp = link->speed.advertised_speeds;
2950         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2951
2952         link_temp = ecore_rd(p_hwfn, p_ptt,
2953                              port_cfg_addr +
2954                              OFFSETOF(struct nvm_cfg1_port, link_settings));
2955         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2956                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2957         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2958                 link->speed.autoneg = true;
2959                 break;
2960         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2961                 link->speed.forced_speed = 1000;
2962                 break;
2963         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2964                 link->speed.forced_speed = 10000;
2965                 break;
2966         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2967                 link->speed.forced_speed = 25000;
2968                 break;
2969         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2970                 link->speed.forced_speed = 40000;
2971                 break;
2972         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2973                 link->speed.forced_speed = 50000;
2974                 break;
2975         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2976                 link->speed.forced_speed = 100000;
2977                 break;
2978         default:
2979                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
2980         }
2981
2982         p_hwfn->mcp_info->link_capabilities.default_speed =
2983             link->speed.forced_speed;
2984         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2985             link->speed.autoneg;
2986
2987         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2988         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2989         link->pause.autoneg = !!(link_temp &
2990                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2991         link->pause.forced_rx = !!(link_temp &
2992                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2993         link->pause.forced_tx = !!(link_temp &
2994                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2995         link->loopback_mode = 0;
2996
2997         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2998                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
2999                    link->speed.forced_speed, link->speed.advertised_speeds,
3000                    link->speed.autoneg, link->pause.autoneg);
3001
3002         /* Read Multi-function information from shmem */
3003         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3004             OFFSETOF(struct nvm_cfg1, glob) +
3005             OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3006
3007         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3008
3009         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3010             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3011
3012         switch (mf_mode) {
3013         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3014                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3015                 break;
3016         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3017                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3018                 break;
3019         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3020                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3021                 break;
3022         }
3023         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
3024                 p_hwfn->p_dev->mf_mode);
3025
3026         /* Read Multi-function information from shmem */
3027         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3028             OFFSETOF(struct nvm_cfg1, glob) +
3029             OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3030
3031         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3032         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3033                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3034                              &p_hwfn->hw_info.device_capabilities);
3035         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3036                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3037                              &p_hwfn->hw_info.device_capabilities);
3038         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3039                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3040                              &p_hwfn->hw_info.device_capabilities);
3041         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3042                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3043                              &p_hwfn->hw_info.device_capabilities);
3044         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3045                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3046                              &p_hwfn->hw_info.device_capabilities);
3047
3048         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3049         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3050                 rc = ECORE_SUCCESS;
3051                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3052         }
3053
3054         return rc;
3055 }
3056
3057 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3058                                 struct ecore_ptt *p_ptt)
3059 {
3060         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3061         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3062         struct ecore_dev *p_dev = p_hwfn->p_dev;
3063
3064         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3065
3066         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3067          * in the other bits are selected.
3068          * Bits 1-15 are for functions 1-15, respectively, and their value is
3069          * '0' only for enabled functions (function 0 always exists and
3070          * enabled).
3071          * In case of CMT in BB, only the "even" functions are enabled, and thus
3072          * the number of functions for both hwfns is learnt from the same bits.
3073          */
3074         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3075                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3076                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3077         } else { /* E5 */
3078                 reg_function_hide = 0;
3079         }
3080
3081         if (reg_function_hide & 0x1) {
3082                 if (ECORE_IS_BB(p_dev)) {
3083                         if (ECORE_PATH_ID(p_hwfn) && p_dev->num_hwfns == 1) {
3084                                 num_funcs = 0;
3085                                 eng_mask = 0xaaaa;
3086                         } else {
3087                                 num_funcs = 1;
3088                                 eng_mask = 0x5554;
3089                         }
3090                 } else {
3091                         num_funcs = 1;
3092                         eng_mask = 0xfffe;
3093                 }
3094
3095                 /* Get the number of the enabled functions on the engine */
3096                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3097                 while (tmp) {
3098                         if (tmp & 0x1)
3099                                 num_funcs++;
3100                         tmp >>= 0x1;
3101                 }
3102
3103                 /* Get the PF index within the enabled functions */
3104                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3105                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3106                 while (tmp) {
3107                         if (tmp & 0x1)
3108                                 enabled_func_idx--;
3109                         tmp >>= 0x1;
3110                 }
3111         }
3112
3113         p_hwfn->num_funcs_on_engine = num_funcs;
3114         p_hwfn->enabled_func_idx = enabled_func_idx;
3115
3116 #ifndef ASIC_ONLY
3117         if (CHIP_REV_IS_FPGA(p_dev)) {
3118                 DP_NOTICE(p_hwfn, false,
3119                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3120                 p_hwfn->num_funcs_on_engine = 4;
3121         }
3122 #endif
3123
3124         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3125                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3126                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3127                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3128 }
3129
3130 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3131                                       struct ecore_ptt *p_ptt)
3132 {
3133         u32 port_mode;
3134
3135 #ifndef ASIC_ONLY
3136         /* Read the port mode */
3137         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3138                 port_mode = 4;
3139         else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) &&
3140                  (p_hwfn->p_dev->num_hwfns > 1))
3141                 /* In CMT on emulation, assume 1 port */
3142                 port_mode = 1;
3143         else
3144 #endif
3145         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3146
3147         if (port_mode < 3) {
3148                 p_hwfn->p_dev->num_ports_in_engines = 1;
3149         } else if (port_mode <= 5) {
3150                 p_hwfn->p_dev->num_ports_in_engines = 2;
3151         } else {
3152                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3153                           p_hwfn->p_dev->num_ports_in_engines);
3154
3155                 /* Default num_ports_in_engines to something */
3156                 p_hwfn->p_dev->num_ports_in_engines = 1;
3157         }
3158 }
3159
3160 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3161                                          struct ecore_ptt *p_ptt)
3162 {
3163         u32 port;
3164         int i;
3165
3166         p_hwfn->p_dev->num_ports_in_engines = 0;
3167
3168 #ifndef ASIC_ONLY
3169         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3170                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3171                 switch ((port & 0xf000) >> 12) {
3172                 case 1:
3173                         p_hwfn->p_dev->num_ports_in_engines = 1;
3174                         break;
3175                 case 3:
3176                         p_hwfn->p_dev->num_ports_in_engines = 2;
3177                         break;
3178                 case 0xf:
3179                         p_hwfn->p_dev->num_ports_in_engines = 4;
3180                         break;
3181                 default:
3182                         DP_NOTICE(p_hwfn, false,
3183                                   "Unknown port mode in ECO_RESERVED %08x\n",
3184                                   port);
3185                 }
3186         } else
3187 #endif
3188                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3189                         port = ecore_rd(p_hwfn, p_ptt,
3190                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3191                                         (i * 4));
3192                         if (port & 1)
3193                                 p_hwfn->p_dev->num_ports_in_engines++;
3194                 }
3195 }
3196
3197 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3198                                    struct ecore_ptt *p_ptt)
3199 {
3200         if (ECORE_IS_BB(p_hwfn->p_dev))
3201                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3202         else
3203                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3204 }
3205
3206 static enum _ecore_status_t
3207 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3208                   enum ecore_pci_personality personality,
3209                   struct ecore_hw_prepare_params *p_params)
3210 {
3211         bool drv_resc_alloc = p_params->drv_resc_alloc;
3212         enum _ecore_status_t rc;
3213
3214         /* Since all information is common, only first hwfns should do this */
3215         if (IS_LEAD_HWFN(p_hwfn)) {
3216                 rc = ecore_iov_hw_info(p_hwfn);
3217                 if (rc != ECORE_SUCCESS) {
3218                         if (p_params->b_relaxed_probe)
3219                                 p_params->p_relaxed_res =
3220                                                 ECORE_HW_PREPARE_BAD_IOV;
3221                         else
3222                                 return rc;
3223                 }
3224         }
3225
3226         /* TODO In get_hw_info, amoungst others:
3227          * Get MCP FW revision and determine according to it the supported
3228          * featrues (e.g. DCB)
3229          * Get boot mode
3230          * ecore_get_pcie_width_speed, WOL capability.
3231          * Number of global CQ-s (for storage
3232          */
3233         ecore_hw_info_port_num(p_hwfn, p_ptt);
3234
3235 #ifndef ASIC_ONLY
3236         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3237 #endif
3238         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3239         if (rc != ECORE_SUCCESS)
3240                 return rc;
3241 #ifndef ASIC_ONLY
3242         }
3243 #endif
3244
3245         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3246         if (rc != ECORE_SUCCESS) {
3247                 if (p_params->b_relaxed_probe)
3248                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3249                 else
3250                         return rc;
3251         }
3252
3253 #ifndef ASIC_ONLY
3254         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3255 #endif
3256                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3257                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3258 #ifndef ASIC_ONLY
3259         } else {
3260                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3261
3262                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3263                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3264         }
3265 #endif
3266
3267         if (ecore_mcp_is_init(p_hwfn)) {
3268                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3269                         p_hwfn->hw_info.ovlan =
3270                             p_hwfn->mcp_info->func_info.ovlan;
3271
3272                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3273         }
3274
3275         if (personality != ECORE_PCI_DEFAULT) {
3276                 p_hwfn->hw_info.personality = personality;
3277         } else if (ecore_mcp_is_init(p_hwfn)) {
3278                 enum ecore_pci_personality protocol;
3279
3280                 protocol = p_hwfn->mcp_info->func_info.protocol;
3281                 p_hwfn->hw_info.personality = protocol;
3282         }
3283
3284 #ifndef ASIC_ONLY
3285         /* To overcome ILT lack for emulation, until at least until we'll have
3286          * a definite answer from system about it, allow only PF0 to be RoCE.
3287          */
3288         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3289                 if (!p_hwfn->rel_pf_id)
3290                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3291                 else
3292                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3293         }
3294 #endif
3295
3296         /* although in BB some constellations may support more than 4 tcs,
3297          * that can result in performance penalty in some cases. 4
3298          * represents a good tradeoff between performance and flexibility.
3299          */
3300         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3301
3302         /* start out with a single active tc. This can be increased either
3303          * by dcbx negotiation or by upper layer driver
3304          */
3305         p_hwfn->hw_info.num_active_tc = 1;
3306
3307         ecore_get_num_funcs(p_hwfn, p_ptt);
3308
3309         if (ecore_mcp_is_init(p_hwfn))
3310                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3311
3312         /* In case of forcing the driver's default resource allocation, calling
3313          * ecore_hw_get_resc() should come after initializing the personality
3314          * and after getting the number of functions, since the calculation of
3315          * the resources/features depends on them.
3316          * This order is not harmful if not forcing.
3317          */
3318         rc = ecore_hw_get_resc(p_hwfn, drv_resc_alloc);
3319         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3320                 rc = ECORE_SUCCESS;
3321                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3322         }
3323
3324         return rc;
3325 }
3326
3327 static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev)
3328 {
3329         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3330         u32 tmp;
3331
3332         /* Read Vendor Id / Device Id */
3333         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3334                                   &p_dev->vendor_id);
3335         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3336                                   &p_dev->device_id);
3337
3338         /* Determine type */
3339         if ((p_dev->device_id & ECORE_DEV_ID_MASK) == ECORE_DEV_ID_MASK_AH)
3340                 p_dev->type = ECORE_DEV_TYPE_AH;
3341         else
3342                 p_dev->type = ECORE_DEV_TYPE_BB;
3343
3344         p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3345                                          MISCS_REG_CHIP_NUM);
3346         p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3347                                          MISCS_REG_CHIP_REV);
3348
3349         MASK_FIELD(CHIP_REV, p_dev->chip_rev);
3350
3351         /* Learn number of HW-functions */
3352         tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3353                        MISCS_REG_CMT_ENABLED_FOR_PAIR);
3354
3355         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3356                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3357                 p_dev->num_hwfns = 2;
3358         } else {
3359                 p_dev->num_hwfns = 1;
3360         }
3361
3362 #ifndef ASIC_ONLY
3363         if (CHIP_REV_IS_EMUL(p_dev)) {
3364                 /* For some reason we have problems with this register
3365                  * in B0 emulation; Simply assume no CMT
3366                  */
3367                 DP_NOTICE(p_dev->hwfns, false,
3368                           "device on emul - assume no CMT\n");
3369                 p_dev->num_hwfns = 1;
3370         }
3371 #endif
3372
3373         p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3374                                        MISCS_REG_CHIP_TEST_REG) >> 4;
3375         MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id);
3376         p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3377                                            MISCS_REG_CHIP_METAL);
3378         MASK_FIELD(CHIP_METAL, p_dev->chip_metal);
3379         DP_INFO(p_dev->hwfns,
3380                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3381                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3382                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3383                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3384                 p_dev->chip_metal);
3385
3386         if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) {
3387                 DP_NOTICE(p_dev->hwfns, false,
3388                           "The chip type/rev (BB A0) is not supported!\n");
3389                 return ECORE_ABORTED;
3390         }
3391 #ifndef ASIC_ONLY
3392         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3393                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3394                          MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3395
3396         if (CHIP_REV_IS_EMUL(p_dev)) {
3397                 tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
3398                                MISCS_REG_ECO_RESERVED);
3399                 if (tmp & (1 << 29)) {
3400                         DP_NOTICE(p_hwfn, false,
3401                                   "Emulation: Running on a FULL build\n");
3402                         p_dev->b_is_emul_full = true;
3403                 } else {
3404                         DP_NOTICE(p_hwfn, false,
3405                                   "Emulation: Running on a REDUCED build\n");
3406                 }
3407         }
3408 #endif
3409
3410         return ECORE_SUCCESS;
3411 }
3412
3413 #ifndef LINUX_REMOVE
3414 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3415 {
3416         int j;
3417
3418         if (IS_VF(p_dev))
3419                 return;
3420
3421         for_each_hwfn(p_dev, j) {
3422                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3423
3424                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
3425                            "Mark hw/fw uninitialized\n");
3426
3427                 p_hwfn->hw_init_done = false;
3428                 p_hwfn->first_on_engine = false;
3429
3430                 ecore_ptt_invalidate(p_hwfn);
3431         }
3432 }
3433 #endif
3434
3435 static enum _ecore_status_t
3436 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
3437                         void OSAL_IOMEM * p_regview,
3438                         void OSAL_IOMEM * p_doorbells,
3439                         struct ecore_hw_prepare_params *p_params)
3440 {
3441         struct ecore_dev *p_dev = p_hwfn->p_dev;
3442         struct ecore_mdump_info mdump_info;
3443         enum _ecore_status_t rc = ECORE_SUCCESS;
3444
3445         /* Split PCI bars evenly between hwfns */
3446         p_hwfn->regview = p_regview;
3447         p_hwfn->doorbells = p_doorbells;
3448
3449         if (IS_VF(p_dev))
3450                 return ecore_vf_hw_prepare(p_hwfn);
3451
3452         /* Validate that chip access is feasible */
3453         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3454                 DP_ERR(p_hwfn,
3455                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3456                 if (p_params->b_relaxed_probe)
3457                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
3458                 return ECORE_INVAL;
3459         }
3460
3461         get_function_id(p_hwfn);
3462
3463         /* Allocate PTT pool */
3464         rc = ecore_ptt_pool_alloc(p_hwfn);
3465         if (rc) {
3466                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
3467                 if (p_params->b_relaxed_probe)
3468                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3469                 goto err0;
3470         }
3471
3472         /* Allocate the main PTT */
3473         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3474
3475         /* First hwfn learns basic information, e.g., number of hwfns */
3476         if (!p_hwfn->my_id) {
3477                 rc = ecore_get_dev_info(p_dev);
3478                 if (rc != ECORE_SUCCESS) {
3479                         if (p_params->b_relaxed_probe)
3480                                 p_params->p_relaxed_res =
3481                                         ECORE_HW_PREPARE_FAILED_DEV;
3482                         goto err1;
3483                 }
3484         }
3485
3486         ecore_hw_hwfn_prepare(p_hwfn);
3487
3488         /* Initialize MCP structure */
3489         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3490         if (rc) {
3491                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
3492                 if (p_params->b_relaxed_probe)
3493                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3494                 goto err1;
3495         }
3496
3497         /* Read the device configuration information from the HW and SHMEM */
3498         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
3499                                p_params->personality, p_params);
3500         if (rc) {
3501                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
3502                 goto err2;
3503         }
3504
3505         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
3506          * called, since among others it sets the ports number in an engine.
3507          */
3508         if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
3509             !p_dev->recov_in_prog) {
3510                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3511                 if (rc != ECORE_SUCCESS)
3512                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
3513         }
3514
3515         /* Check if mdump logs are present and update the epoch value */
3516         if (p_hwfn == ECORE_LEADING_HWFN(p_hwfn->p_dev)) {
3517                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
3518                                               &mdump_info);
3519                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs > 0) {
3520                         DP_NOTICE(p_hwfn, false,
3521                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
3522                 }
3523
3524                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
3525                                            p_params->epoch);
3526         }
3527
3528         /* Allocate the init RT array and initialize the init-ops engine */
3529         rc = ecore_init_alloc(p_hwfn);
3530         if (rc) {
3531                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
3532                 if (p_params->b_relaxed_probe)
3533                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
3534                 goto err2;
3535         }
3536 #ifndef ASIC_ONLY
3537         if (CHIP_REV_IS_FPGA(p_dev)) {
3538                 DP_NOTICE(p_hwfn, false,
3539                           "FPGA: workaround; Prevent DMAE parities\n");
3540                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
3541                          7);
3542
3543                 DP_NOTICE(p_hwfn, false,
3544                           "FPGA: workaround: Set VF bar0 size\n");
3545                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
3546                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
3547         }
3548 #endif
3549
3550         return rc;
3551 err2:
3552         if (IS_LEAD_HWFN(p_hwfn))
3553                 ecore_iov_free_hw_info(p_dev);
3554         ecore_mcp_free(p_hwfn);
3555 err1:
3556         ecore_hw_hwfn_free(p_hwfn);
3557 err0:
3558         return rc;
3559 }
3560
3561 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
3562                                       struct ecore_hw_prepare_params *p_params)
3563 {
3564         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3565         enum _ecore_status_t rc;
3566
3567         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
3568
3569         if (p_params->b_relaxed_probe)
3570                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
3571
3572         /* Store the precompiled init data ptrs */
3573         if (IS_PF(p_dev))
3574                 ecore_init_iro_array(p_dev);
3575
3576         /* Initialize the first hwfn - will learn number of hwfns */
3577         rc = ecore_hw_prepare_single(p_hwfn,
3578                                      p_dev->regview,
3579                                      p_dev->doorbells, p_params);
3580         if (rc != ECORE_SUCCESS)
3581                 return rc;
3582
3583         p_params->personality = p_hwfn->hw_info.personality;
3584
3585         /* initilalize 2nd hwfn if necessary */
3586         if (p_dev->num_hwfns > 1) {
3587                 void OSAL_IOMEM *p_regview, *p_doorbell;
3588                 u8 OSAL_IOMEM *addr;
3589
3590                 /* adjust bar offset for second engine */
3591                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
3592                     ecore_hw_bar_size(p_hwfn, BAR_ID_0) / 2;
3593                 p_regview = (void OSAL_IOMEM *)addr;
3594
3595                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
3596                     ecore_hw_bar_size(p_hwfn, BAR_ID_1) / 2;
3597                 p_doorbell = (void OSAL_IOMEM *)addr;
3598
3599                 /* prepare second hw function */
3600                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
3601                                              p_doorbell, p_params);
3602
3603                 /* in case of error, need to free the previously
3604                  * initiliazed hwfn 0.
3605                  */
3606                 if (rc != ECORE_SUCCESS) {
3607                         if (p_params->b_relaxed_probe)
3608                                 p_params->p_relaxed_res =
3609                                                 ECORE_HW_PREPARE_FAILED_ENG2;
3610
3611                         if (IS_PF(p_dev)) {
3612                                 ecore_init_free(p_hwfn);
3613                                 ecore_mcp_free(p_hwfn);
3614                                 ecore_hw_hwfn_free(p_hwfn);
3615                         } else {
3616                                 DP_NOTICE(p_dev, true,
3617                                           "What do we need to free when VF hwfn1 init fails\n");
3618                         }
3619                         return rc;
3620                 }
3621         }
3622
3623         return rc;
3624 }
3625
3626 void ecore_hw_remove(struct ecore_dev *p_dev)
3627 {
3628         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3629         int i;
3630
3631         if (IS_PF(p_dev))
3632                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3633                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
3634
3635         for_each_hwfn(p_dev, i) {
3636                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
3637
3638                 if (IS_VF(p_dev)) {
3639                         ecore_vf_pf_release(p_hwfn);
3640                         continue;
3641                 }
3642
3643                 ecore_init_free(p_hwfn);
3644                 ecore_hw_hwfn_free(p_hwfn);
3645                 ecore_mcp_free(p_hwfn);
3646
3647                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
3648         }
3649
3650         ecore_iov_free_hw_info(p_dev);
3651 }
3652
3653 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
3654                                       struct ecore_chain *p_chain)
3655 {
3656         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
3657         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3658         struct ecore_chain_next *p_next;
3659         u32 size, i;
3660
3661         if (!p_virt)
3662                 return;
3663
3664         size = p_chain->elem_size * p_chain->usable_per_page;
3665
3666         for (i = 0; i < p_chain->page_cnt; i++) {
3667                 if (!p_virt)
3668                         break;
3669
3670                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
3671                 p_virt_next = p_next->next_virt;
3672                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3673
3674                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
3675                                        ECORE_CHAIN_PAGE_SIZE);
3676
3677                 p_virt = p_virt_next;
3678                 p_phys = p_phys_next;
3679         }
3680 }
3681
3682 static void ecore_chain_free_single(struct ecore_dev *p_dev,
3683                                     struct ecore_chain *p_chain)
3684 {
3685         if (!p_chain->p_virt_addr)
3686                 return;
3687
3688         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
3689                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
3690 }
3691
3692 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
3693                                  struct ecore_chain *p_chain)
3694 {
3695         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3696         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
3697         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3698
3699         if (!pp_virt_addr_tbl)
3700                 return;
3701
3702         if (!p_pbl_virt)
3703                 goto out;
3704
3705         for (i = 0; i < page_cnt; i++) {
3706                 if (!pp_virt_addr_tbl[i])
3707                         break;
3708
3709                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
3710                                        *(dma_addr_t *)p_pbl_virt,
3711                                        ECORE_CHAIN_PAGE_SIZE);
3712
3713                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3714         }
3715
3716         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3717
3718         if (!p_chain->b_external_pbl)
3719                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
3720                                        p_chain->pbl_sp.p_phys_table, pbl_size);
3721  out:
3722         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
3723 }
3724
3725 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3726 {
3727         switch (p_chain->mode) {
3728         case ECORE_CHAIN_MODE_NEXT_PTR:
3729                 ecore_chain_free_next_ptr(p_dev, p_chain);
3730                 break;
3731         case ECORE_CHAIN_MODE_SINGLE:
3732                 ecore_chain_free_single(p_dev, p_chain);
3733                 break;
3734         case ECORE_CHAIN_MODE_PBL:
3735                 ecore_chain_free_pbl(p_dev, p_chain);
3736                 break;
3737         }
3738 }
3739
3740 static enum _ecore_status_t
3741 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
3742                                enum ecore_chain_cnt_type cnt_type,
3743                                osal_size_t elem_size, u32 page_cnt)
3744 {
3745         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3746
3747         /* The actual chain size can be larger than the maximal possible value
3748          * after rounding up the requested elements number to pages, and after
3749          * taking into acount the unusuable elements (next-ptr elements).
3750          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3751          * size/capacity fields are of a u32 type.
3752          */
3753         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
3754              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
3755             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
3756              chain_size > ECORE_U32_MAX)) {
3757                 DP_NOTICE(p_dev, true,
3758                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
3759                           (unsigned long)chain_size);
3760                 return ECORE_INVAL;
3761         }
3762
3763         return ECORE_SUCCESS;
3764 }
3765
3766 static enum _ecore_status_t
3767 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3768 {
3769         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
3770         dma_addr_t p_phys = 0;
3771         u32 i;
3772
3773         for (i = 0; i < p_chain->page_cnt; i++) {
3774                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3775                                                  ECORE_CHAIN_PAGE_SIZE);
3776                 if (!p_virt) {
3777                         DP_NOTICE(p_dev, true,
3778                                   "Failed to allocate chain memory\n");
3779                         return ECORE_NOMEM;
3780                 }
3781
3782                 if (i == 0) {
3783                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3784                         ecore_chain_reset(p_chain);
3785                 } else {
3786                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3787                                                        p_virt, p_phys);
3788                 }
3789
3790                 p_virt_prev = p_virt;
3791         }
3792         /* Last page's next element should point to the beginning of the
3793          * chain.
3794          */
3795         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3796                                        p_chain->p_virt_addr,
3797                                        p_chain->p_phys_addr);
3798
3799         return ECORE_SUCCESS;
3800 }
3801
3802 static enum _ecore_status_t
3803 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
3804 {
3805         dma_addr_t p_phys = 0;
3806         void *p_virt = OSAL_NULL;
3807
3808         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
3809         if (!p_virt) {
3810                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
3811                 return ECORE_NOMEM;
3812         }
3813
3814         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3815         ecore_chain_reset(p_chain);
3816
3817         return ECORE_SUCCESS;
3818 }
3819
3820 static enum _ecore_status_t
3821 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
3822                       struct ecore_chain *p_chain,
3823                       struct ecore_chain_ext_pbl *ext_pbl)
3824 {
3825         void *p_virt = OSAL_NULL;
3826         u8 *p_pbl_virt = OSAL_NULL;
3827         void **pp_virt_addr_tbl = OSAL_NULL;
3828         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3829         u32 page_cnt = p_chain->page_cnt, size, i;
3830
3831         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3832         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
3833         if (!pp_virt_addr_tbl) {
3834                 DP_NOTICE(p_dev, true,
3835                           "Failed to allocate memory for the chain virtual addresses table\n");
3836                 return ECORE_NOMEM;
3837         }
3838
3839         /* The allocation of the PBL table is done with its full size, since it
3840          * is expected to be successive.
3841          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
3842          * failure, since pp_virt_addr_tbl was previously allocated, and it
3843          * should be saved to allow its freeing during the error flow.
3844          */
3845         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
3846
3847         if (ext_pbl == OSAL_NULL) {
3848                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
3849         } else {
3850                 p_pbl_virt = ext_pbl->p_pbl_virt;
3851                 p_pbl_phys = ext_pbl->p_pbl_phys;
3852                 p_chain->b_external_pbl = true;
3853         }
3854
3855         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3856                                  pp_virt_addr_tbl);
3857         if (!p_pbl_virt) {
3858                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
3859                 return ECORE_NOMEM;
3860         }
3861
3862         for (i = 0; i < page_cnt; i++) {
3863                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
3864                                                  ECORE_CHAIN_PAGE_SIZE);
3865                 if (!p_virt) {
3866                         DP_NOTICE(p_dev, true,
3867                                   "Failed to allocate chain memory\n");
3868                         return ECORE_NOMEM;
3869                 }
3870
3871                 if (i == 0) {
3872                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
3873                         ecore_chain_reset(p_chain);
3874                 }
3875
3876                 /* Fill the PBL table with the physical address of the page */
3877                 *(dma_addr_t *)p_pbl_virt = p_phys;
3878                 /* Keep the virtual address of the page */
3879                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3880
3881                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
3882         }
3883
3884         return ECORE_SUCCESS;
3885 }
3886
3887 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
3888                                        enum ecore_chain_use_mode intended_use,
3889                                        enum ecore_chain_mode mode,
3890                                        enum ecore_chain_cnt_type cnt_type,
3891                                        u32 num_elems, osal_size_t elem_size,
3892                                        struct ecore_chain *p_chain,
3893                                        struct ecore_chain_ext_pbl *ext_pbl)
3894 {
3895         u32 page_cnt;
3896         enum _ecore_status_t rc = ECORE_SUCCESS;
3897
3898         if (mode == ECORE_CHAIN_MODE_SINGLE)
3899                 page_cnt = 1;
3900         else
3901                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3902
3903         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
3904                                             page_cnt);
3905         if (rc) {
3906                 DP_NOTICE(p_dev, true,
3907                           "Cannot allocate a chain with the given arguments:\n"
3908                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3909                           intended_use, mode, cnt_type, num_elems, elem_size);
3910                 return rc;
3911         }
3912
3913         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
3914                                 mode, cnt_type, p_dev->dp_ctx);
3915
3916         switch (mode) {
3917         case ECORE_CHAIN_MODE_NEXT_PTR:
3918                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
3919                 break;
3920         case ECORE_CHAIN_MODE_SINGLE:
3921                 rc = ecore_chain_alloc_single(p_dev, p_chain);
3922                 break;
3923         case ECORE_CHAIN_MODE_PBL:
3924                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
3925                 break;
3926         }
3927         if (rc)
3928                 goto nomem;
3929
3930         return ECORE_SUCCESS;
3931
3932 nomem:
3933         ecore_chain_free(p_dev, p_chain);
3934         return rc;
3935 }
3936
3937 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
3938                                        u16 src_id, u16 *dst_id)
3939 {
3940         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
3941                 u16 min, max;
3942
3943                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
3944                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
3945                 DP_NOTICE(p_hwfn, true,
3946                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3947                           src_id, min, max);
3948
3949                 return ECORE_INVAL;
3950         }
3951
3952         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
3953
3954         return ECORE_SUCCESS;
3955 }
3956
3957 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
3958                                     u8 src_id, u8 *dst_id)
3959 {
3960         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
3961                 u8 min, max;
3962
3963                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
3964                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
3965                 DP_NOTICE(p_hwfn, true,
3966                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3967                           src_id, min, max);
3968
3969                 return ECORE_INVAL;
3970         }
3971
3972         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
3973
3974         return ECORE_SUCCESS;
3975 }
3976
3977 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
3978                                       u8 src_id, u8 *dst_id)
3979 {
3980         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
3981                 u8 min, max;
3982
3983                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
3984                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
3985                 DP_NOTICE(p_hwfn, true,
3986                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3987                           src_id, min, max);
3988
3989                 return ECORE_INVAL;
3990         }
3991
3992         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
3993
3994         return ECORE_SUCCESS;
3995 }
3996
3997 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
3998                                               struct ecore_ptt *p_ptt,
3999                                               u8 *p_filter)
4000 {
4001         u32 high, low, en;
4002         int i;
4003
4004         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4005                 return ECORE_SUCCESS;
4006
4007         high = p_filter[1] | (p_filter[0] << 8);
4008         low = p_filter[5] | (p_filter[4] << 8) |
4009             (p_filter[3] << 16) | (p_filter[2] << 24);
4010
4011         /* Find a free entry and utilize it */
4012         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4013                 en = ecore_rd(p_hwfn, p_ptt,
4014                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4015                 if (en)
4016                         continue;
4017                 ecore_wr(p_hwfn, p_ptt,
4018                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4019                          2 * i * sizeof(u32), low);
4020                 ecore_wr(p_hwfn, p_ptt,
4021                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4022                          (2 * i + 1) * sizeof(u32), high);
4023                 ecore_wr(p_hwfn, p_ptt,
4024                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4025                 ecore_wr(p_hwfn, p_ptt,
4026                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4027                          i * sizeof(u32), 0);
4028                 ecore_wr(p_hwfn, p_ptt,
4029                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4030                 break;
4031         }
4032         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4033                 DP_NOTICE(p_hwfn, false,
4034                           "Failed to find an empty LLH filter to utilize\n");
4035                 return ECORE_INVAL;
4036         }
4037
4038         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4039                    "MAC: %x:%x:%x:%x:%x:%x is added at %d\n",
4040                    p_filter[0], p_filter[1], p_filter[2],
4041                    p_filter[3], p_filter[4], p_filter[5], i);
4042
4043         return ECORE_SUCCESS;
4044 }
4045
4046 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4047                                  struct ecore_ptt *p_ptt, u8 *p_filter)
4048 {
4049         u32 high, low;
4050         int i;
4051
4052         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4053                 return;
4054
4055         high = p_filter[1] | (p_filter[0] << 8);
4056         low = p_filter[5] | (p_filter[4] << 8) |
4057             (p_filter[3] << 16) | (p_filter[2] << 24);
4058
4059         /* Find the entry and clean it */
4060         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4061                 if (ecore_rd(p_hwfn, p_ptt,
4062                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4063                              2 * i * sizeof(u32)) != low)
4064                         continue;
4065                 if (ecore_rd(p_hwfn, p_ptt,
4066                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4067                              (2 * i + 1) * sizeof(u32)) != high)
4068                         continue;
4069
4070                 ecore_wr(p_hwfn, p_ptt,
4071                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4072                 ecore_wr(p_hwfn, p_ptt,
4073                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4074                          2 * i * sizeof(u32), 0);
4075                 ecore_wr(p_hwfn, p_ptt,
4076                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4077                          (2 * i + 1) * sizeof(u32), 0);
4078                 break;
4079         }
4080         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4081                 DP_NOTICE(p_hwfn, false,
4082                           "Tried to remove a non-configured filter\n");
4083 }
4084
4085 enum _ecore_status_t
4086 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4087                               struct ecore_ptt *p_ptt,
4088                               u16 source_port_or_eth_type,
4089                               u16 dest_port,
4090                               enum ecore_llh_port_filter_type_t type)
4091 {
4092         u32 high, low, en;
4093         int i;
4094
4095         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4096                 return ECORE_SUCCESS;
4097
4098         high = 0;
4099         low = 0;
4100         switch (type) {
4101         case ECORE_LLH_FILTER_ETHERTYPE:
4102                 high = source_port_or_eth_type;
4103                 break;
4104         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4105         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4106                 low = source_port_or_eth_type << 16;
4107                 break;
4108         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4109         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4110                 low = dest_port;
4111                 break;
4112         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4113         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4114                 low = (source_port_or_eth_type << 16) | dest_port;
4115                 break;
4116         default:
4117                 DP_NOTICE(p_hwfn, true,
4118                           "Non valid LLH protocol filter type %d\n", type);
4119                 return ECORE_INVAL;
4120         }
4121         /* Find a free entry and utilize it */
4122         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4123                 en = ecore_rd(p_hwfn, p_ptt,
4124                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
4125                 if (en)
4126                         continue;
4127                 ecore_wr(p_hwfn, p_ptt,
4128                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4129                          2 * i * sizeof(u32), low);
4130                 ecore_wr(p_hwfn, p_ptt,
4131                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4132                          (2 * i + 1) * sizeof(u32), high);
4133                 ecore_wr(p_hwfn, p_ptt,
4134                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
4135                 ecore_wr(p_hwfn, p_ptt,
4136                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4137                          i * sizeof(u32), 1 << type);
4138                 ecore_wr(p_hwfn, p_ptt,
4139                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
4140                 break;
4141         }
4142         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
4143                 DP_NOTICE(p_hwfn, false,
4144                           "Failed to find an empty LLH filter to utilize\n");
4145                 return ECORE_NORESOURCES;
4146         }
4147         switch (type) {
4148         case ECORE_LLH_FILTER_ETHERTYPE:
4149                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4150                            "ETH type %x is added at %d\n",
4151                            source_port_or_eth_type, i);
4152                 break;
4153         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4154                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4155                            "TCP src port %x is added at %d\n",
4156                            source_port_or_eth_type, i);
4157                 break;
4158         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4159                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4160                            "UDP src port %x is added at %d\n",
4161                            source_port_or_eth_type, i);
4162                 break;
4163         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4164                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4165                            "TCP dst port %x is added at %d\n", dest_port, i);
4166                 break;
4167         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4168                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4169                            "UDP dst port %x is added at %d\n", dest_port, i);
4170                 break;
4171         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4172                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4173                            "TCP src/dst ports %x/%x are added at %d\n",
4174                            source_port_or_eth_type, dest_port, i);
4175                 break;
4176         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4177                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4178                            "UDP src/dst ports %x/%x are added at %d\n",
4179                            source_port_or_eth_type, dest_port, i);
4180                 break;
4181         }
4182         return ECORE_SUCCESS;
4183 }
4184
4185 void
4186 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4187                                  struct ecore_ptt *p_ptt,
4188                                  u16 source_port_or_eth_type,
4189                                  u16 dest_port,
4190                                  enum ecore_llh_port_filter_type_t type)
4191 {
4192         u32 high, low;
4193         int i;
4194
4195         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4196                 return;
4197
4198         high = 0;
4199         low = 0;
4200         switch (type) {
4201         case ECORE_LLH_FILTER_ETHERTYPE:
4202                 high = source_port_or_eth_type;
4203                 break;
4204         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4205         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4206                 low = source_port_or_eth_type << 16;
4207                 break;
4208         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4209         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4210                 low = dest_port;
4211                 break;
4212         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4213         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4214                 low = (source_port_or_eth_type << 16) | dest_port;
4215                 break;
4216         default:
4217                 DP_NOTICE(p_hwfn, true,
4218                           "Non valid LLH protocol filter type %d\n", type);
4219                 return;
4220         }
4221
4222         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4223                 if (!ecore_rd(p_hwfn, p_ptt,
4224                               NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
4225                         continue;
4226                 if (!ecore_rd(p_hwfn, p_ptt,
4227                               NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
4228                         continue;
4229                 if (!(ecore_rd(p_hwfn, p_ptt,
4230                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4231                                i * sizeof(u32)) & (1 << type)))
4232                         continue;
4233                 if (ecore_rd(p_hwfn, p_ptt,
4234                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4235                              2 * i * sizeof(u32)) != low)
4236                         continue;
4237                 if (ecore_rd(p_hwfn, p_ptt,
4238                              NIG_REG_LLH_FUNC_FILTER_VALUE +
4239                              (2 * i + 1) * sizeof(u32)) != high)
4240                         continue;
4241
4242                 ecore_wr(p_hwfn, p_ptt,
4243                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4244                 ecore_wr(p_hwfn, p_ptt,
4245                          NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
4246                 ecore_wr(p_hwfn, p_ptt,
4247                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
4248                          i * sizeof(u32), 0);
4249                 ecore_wr(p_hwfn, p_ptt,
4250                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4251                          2 * i * sizeof(u32), 0);
4252                 ecore_wr(p_hwfn, p_ptt,
4253                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4254                          (2 * i + 1) * sizeof(u32), 0);
4255                 break;
4256         }
4257
4258         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4259                 DP_NOTICE(p_hwfn, false,
4260                           "Tried to remove a non-configured filter\n");
4261 }
4262
4263 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4264                                  struct ecore_ptt *p_ptt)
4265 {
4266         int i;
4267
4268         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4269                 return;
4270
4271         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4272                 ecore_wr(p_hwfn, p_ptt,
4273                          NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
4274                 ecore_wr(p_hwfn, p_ptt,
4275                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4276                          2 * i * sizeof(u32), 0);
4277                 ecore_wr(p_hwfn, p_ptt,
4278                          NIG_REG_LLH_FUNC_FILTER_VALUE +
4279                          (2 * i + 1) * sizeof(u32), 0);
4280         }
4281 }
4282
4283 enum _ecore_status_t
4284 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
4285                                   struct ecore_ptt *p_ptt)
4286 {
4287         if (IS_MF_DEFAULT(p_hwfn) && ECORE_IS_BB(p_hwfn->p_dev)) {
4288                 ecore_wr(p_hwfn, p_ptt,
4289                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
4290                          1 << p_hwfn->abs_pf_id / 2);
4291                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
4292                 return ECORE_SUCCESS;
4293         }
4294
4295         DP_NOTICE(p_hwfn, false,
4296                   "This function can't be set as default\n");
4297         return ECORE_INVAL;
4298 }
4299
4300 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
4301                                                struct ecore_ptt *p_ptt,
4302                                                u32 hw_addr, void *p_eth_qzone,
4303                                                osal_size_t eth_qzone_size,
4304                                                u8 timeset)
4305 {
4306         struct coalescing_timeset *p_coal_timeset;
4307
4308         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
4309                 DP_NOTICE(p_hwfn, true,
4310                           "Coalescing configuration not enabled\n");
4311                 return ECORE_INVAL;
4312         }
4313
4314         p_coal_timeset = p_eth_qzone;
4315         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
4316         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4317         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4318         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4319
4320         return ECORE_SUCCESS;
4321 }
4322
4323 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
4324                                               u16 rx_coal, u16 tx_coal,
4325                                               void *p_handle)
4326 {
4327         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
4328         enum _ecore_status_t rc = ECORE_SUCCESS;
4329         struct ecore_ptt *p_ptt;
4330
4331         /* TODO - Configuring a single queue's coalescing but
4332          * claiming all queues are abiding same configuration
4333          * for PF and VF both.
4334          */
4335
4336         if (IS_VF(p_hwfn->p_dev))
4337                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
4338                                                 tx_coal, p_cid);
4339
4340         p_ptt = ecore_ptt_acquire(p_hwfn);
4341         if (!p_ptt)
4342                 return ECORE_AGAIN;
4343
4344         if (rx_coal) {
4345                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4346                 if (rc)
4347                         goto out;
4348                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
4349         }
4350
4351         if (tx_coal) {
4352                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4353                 if (rc)
4354                         goto out;
4355                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
4356         }
4357 out:
4358         ecore_ptt_release(p_hwfn, p_ptt);
4359
4360         return rc;
4361 }
4362
4363 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
4364                                             struct ecore_ptt *p_ptt,
4365                                             u16 coalesce,
4366                                             struct ecore_queue_cid *p_cid)
4367 {
4368         struct ustorm_eth_queue_zone eth_qzone;
4369         u8 timeset, timer_res;
4370         u32 address;
4371         enum _ecore_status_t rc;
4372
4373         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4374         if (coalesce <= 0x7F) {
4375                 timer_res = 0;
4376         } else if (coalesce <= 0xFF) {
4377                 timer_res = 1;
4378         } else if (coalesce <= 0x1FF) {
4379                 timer_res = 2;
4380         } else {
4381                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4382                 return ECORE_INVAL;
4383         }
4384         timeset = (u8)(coalesce >> timer_res);
4385
4386         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4387                                      p_cid->abs.sb_idx, false);
4388         if (rc != ECORE_SUCCESS)
4389                 goto out;
4390
4391         address = BAR0_MAP_REG_USDM_RAM +
4392                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4393
4394         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4395                                 sizeof(struct ustorm_eth_queue_zone), timeset);
4396         if (rc != ECORE_SUCCESS)
4397                 goto out;
4398
4399  out:
4400         return rc;
4401 }
4402
4403 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
4404                                             struct ecore_ptt *p_ptt,
4405                                             u16 coalesce,
4406                                             struct ecore_queue_cid *p_cid)
4407 {
4408         struct xstorm_eth_queue_zone eth_qzone;
4409         u8 timeset, timer_res;
4410         u32 address;
4411         enum _ecore_status_t rc;
4412
4413         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4414         if (coalesce <= 0x7F) {
4415                 timer_res = 0;
4416         } else if (coalesce <= 0xFF) {
4417                 timer_res = 1;
4418         } else if (coalesce <= 0x1FF) {
4419                 timer_res = 2;
4420         } else {
4421                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4422                 return ECORE_INVAL;
4423         }
4424
4425         timeset = (u8)(coalesce >> timer_res);
4426
4427         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4428                                      p_cid->abs.sb_idx, true);
4429         if (rc != ECORE_SUCCESS)
4430                 goto out;
4431
4432         address = BAR0_MAP_REG_XSDM_RAM +
4433                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4434
4435         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4436                                 sizeof(struct xstorm_eth_queue_zone), timeset);
4437  out:
4438         return rc;
4439 }
4440
4441 /* Calculate final WFQ values for all vports and configure it.
4442  * After this configuration each vport must have
4443  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
4444  */
4445 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4446                                                struct ecore_ptt *p_ptt,
4447                                                u32 min_pf_rate)
4448 {
4449         struct init_qm_vport_params *vport_params;
4450         int i;
4451
4452         vport_params = p_hwfn->qm_info.qm_vport_params;
4453
4454         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4455                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4456
4457                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
4458                     min_pf_rate;
4459                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4460                                      vport_params[i].first_tx_pq_id,
4461                                      vport_params[i].vport_wfq);
4462         }
4463 }
4464
4465 static void
4466 ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn, u32 min_pf_rate)
4467 {
4468         int i;
4469
4470         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4471                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4472 }
4473
4474 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
4475                                              struct ecore_ptt *p_ptt,
4476                                              u32 min_pf_rate)
4477 {
4478         struct init_qm_vport_params *vport_params;
4479         int i;
4480
4481         vport_params = p_hwfn->qm_info.qm_vport_params;
4482
4483         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4484                 ecore_init_wfq_default_param(p_hwfn, min_pf_rate);
4485                 ecore_init_vport_wfq(p_hwfn, p_ptt,
4486                                      vport_params[i].first_tx_pq_id,
4487                                      vport_params[i].vport_wfq);
4488         }
4489 }
4490
4491 /* This function performs several validations for WFQ
4492  * configuration and required min rate for a given vport
4493  * 1. req_rate must be greater than one percent of min_pf_rate.
4494  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4495  *    rates to get less than one percent of min_pf_rate.
4496  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4497  */
4498 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
4499                                                  u16 vport_id, u32 req_rate,
4500                                                  u32 min_pf_rate)
4501 {
4502         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4503         int non_requested_count = 0, req_count = 0, i, num_vports;
4504
4505         num_vports = p_hwfn->qm_info.num_vports;
4506
4507 /* Accounting for the vports which are configured for WFQ explicitly */
4508
4509         for (i = 0; i < num_vports; i++) {
4510                 u32 tmp_speed;
4511
4512                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
4513                         req_count++;
4514                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4515                         total_req_min_rate += tmp_speed;
4516                 }
4517         }
4518
4519         /* Include current vport data as well */
4520         req_count++;
4521         total_req_min_rate += req_rate;
4522         non_requested_count = num_vports - req_count;
4523
4524         /* validate possible error cases */
4525         if (req_rate > min_pf_rate) {
4526                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4527                            "Vport [%d] - Requested rate[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4528                            vport_id, req_rate, min_pf_rate);
4529                 return ECORE_INVAL;
4530         }
4531
4532         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
4533                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4534                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4535                            vport_id, req_rate, min_pf_rate);
4536                 return ECORE_INVAL;
4537         }
4538
4539         /* TBD - for number of vports greater than 100 */
4540         if (num_vports > ECORE_WFQ_UNIT) {
4541                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4542                            "Number of vports is greater than %d\n",
4543                            ECORE_WFQ_UNIT);
4544                 return ECORE_INVAL;
4545         }
4546
4547         if (total_req_min_rate > min_pf_rate) {
4548                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4549                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4550                            total_req_min_rate, min_pf_rate);
4551                 return ECORE_INVAL;
4552         }
4553
4554         /* Data left for non requested vports */
4555         total_left_rate = min_pf_rate - total_req_min_rate;
4556         left_rate_per_vp = total_left_rate / non_requested_count;
4557
4558         /* validate if non requested get < 1% of min bw */
4559         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
4560                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4561                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4562                            left_rate_per_vp, min_pf_rate);
4563                 return ECORE_INVAL;
4564         }
4565
4566         /* now req_rate for given vport passes all scenarios.
4567          * assign final wfq rates to all vports.
4568          */
4569         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4570         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4571
4572         for (i = 0; i < num_vports; i++) {
4573                 if (p_hwfn->qm_info.wfq_data[i].configured)
4574                         continue;
4575
4576                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4577         }
4578
4579         return ECORE_SUCCESS;
4580 }
4581
4582 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
4583                                        struct ecore_ptt *p_ptt,
4584                                        u16 vp_id, u32 rate)
4585 {
4586         struct ecore_mcp_link_state *p_link;
4587         int rc = ECORE_SUCCESS;
4588
4589         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
4590
4591         if (!p_link->min_pf_rate) {
4592                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4593                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4594                 return rc;
4595         }
4596
4597         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4598
4599         if (rc == ECORE_SUCCESS)
4600                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4601                                                    p_link->min_pf_rate);
4602         else
4603                 DP_NOTICE(p_hwfn, false,
4604                           "Validation failed while configuring min rate\n");
4605
4606         return rc;
4607 }
4608
4609 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
4610                                                    struct ecore_ptt *p_ptt,
4611                                                    u32 min_pf_rate)
4612 {
4613         bool use_wfq = false;
4614         int rc = ECORE_SUCCESS;
4615         u16 i;
4616
4617         /* Validate all pre configured vports for wfq */
4618         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4619                 u32 rate;
4620
4621                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4622                         continue;
4623
4624                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4625                 use_wfq = true;
4626
4627                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4628                 if (rc != ECORE_SUCCESS) {
4629                         DP_NOTICE(p_hwfn, false,
4630                                   "WFQ validation failed while configuring min rate\n");
4631                         break;
4632                 }
4633         }
4634
4635         if (rc == ECORE_SUCCESS && use_wfq)
4636                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4637         else
4638                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4639
4640         return rc;
4641 }
4642
4643 /* Main API for ecore clients to configure vport min rate.
4644  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4645  * rate - Speed in Mbps needs to be assigned to a given vport.
4646  */
4647 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
4648 {
4649         int i, rc = ECORE_INVAL;
4650
4651         /* TBD - for multiple hardware functions - that is 100 gig */
4652         if (p_dev->num_hwfns > 1) {
4653                 DP_NOTICE(p_dev, false,
4654                           "WFQ configuration is not supported for this device\n");
4655                 return rc;
4656         }
4657
4658         for_each_hwfn(p_dev, i) {
4659                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4660                 struct ecore_ptt *p_ptt;
4661
4662                 p_ptt = ecore_ptt_acquire(p_hwfn);
4663                 if (!p_ptt)
4664                         return ECORE_TIMEOUT;
4665
4666                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4667
4668                 if (rc != ECORE_SUCCESS) {
4669                         ecore_ptt_release(p_hwfn, p_ptt);
4670                         return rc;
4671                 }
4672
4673                 ecore_ptt_release(p_hwfn, p_ptt);
4674         }
4675
4676         return rc;
4677 }
4678
4679 /* API to configure WFQ from mcp link change */
4680 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
4681                                            u32 min_pf_rate)
4682 {
4683         int i;
4684
4685         /* TBD - for multiple hardware functions - that is 100 gig */
4686         if (p_dev->num_hwfns > 1) {
4687                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
4688                            "WFQ configuration is not supported for this device\n");
4689                 return;
4690         }
4691
4692         for_each_hwfn(p_dev, i) {
4693                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4694
4695                 __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4696                                                         p_hwfn->p_dpc_ptt,
4697                                                         min_pf_rate);
4698         }
4699 }
4700
4701 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
4702                                        struct ecore_ptt *p_ptt,
4703                                        struct ecore_mcp_link_state *p_link,
4704                                        u8 max_bw)
4705 {
4706         int rc = ECORE_SUCCESS;
4707
4708         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4709
4710         if (!p_link->line_speed && (max_bw != 100))
4711                 return rc;
4712
4713         p_link->speed = (p_link->line_speed * max_bw) / 100;
4714         p_hwfn->qm_info.pf_rl = p_link->speed;
4715
4716         /* Since the limiter also affects Tx-switched traffic, we don't want it
4717          * to limit such traffic in case there's no actual limit.
4718          * In that case, set limit to imaginary high boundary.
4719          */
4720         if (max_bw == 100)
4721                 p_hwfn->qm_info.pf_rl = 100000;
4722
4723         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4724                               p_hwfn->qm_info.pf_rl);
4725
4726         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4727                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4728                    p_link->speed);
4729
4730         return rc;
4731 }
4732
4733 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4734 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
4735 {
4736         int i, rc = ECORE_INVAL;
4737
4738         if (max_bw < 1 || max_bw > 100) {
4739                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
4740                 return rc;
4741         }
4742
4743         for_each_hwfn(p_dev, i) {
4744                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4745                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4746                 struct ecore_mcp_link_state *p_link;
4747                 struct ecore_ptt *p_ptt;
4748
4749                 p_link = &p_lead->mcp_info->link_output;
4750
4751                 p_ptt = ecore_ptt_acquire(p_hwfn);
4752                 if (!p_ptt)
4753                         return ECORE_TIMEOUT;
4754
4755                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4756                                                         p_link, max_bw);
4757
4758                 ecore_ptt_release(p_hwfn, p_ptt);
4759
4760                 if (rc != ECORE_SUCCESS)
4761                         break;
4762         }
4763
4764         return rc;
4765 }
4766
4767 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
4768                                        struct ecore_ptt *p_ptt,
4769                                        struct ecore_mcp_link_state *p_link,
4770                                        u8 min_bw)
4771 {
4772         int rc = ECORE_SUCCESS;
4773
4774         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4775         p_hwfn->qm_info.pf_wfq = min_bw;
4776
4777         if (!p_link->line_speed)
4778                 return rc;
4779
4780         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4781
4782         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4783
4784         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4785                    "Configured MIN bandwidth to be %d Mb/sec\n",
4786                    p_link->min_pf_rate);
4787
4788         return rc;
4789 }
4790
4791 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4792 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
4793 {
4794         int i, rc = ECORE_INVAL;
4795
4796         if (min_bw < 1 || min_bw > 100) {
4797                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
4798                 return rc;
4799         }
4800
4801         for_each_hwfn(p_dev, i) {
4802                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4803                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
4804                 struct ecore_mcp_link_state *p_link;
4805                 struct ecore_ptt *p_ptt;
4806
4807                 p_link = &p_lead->mcp_info->link_output;
4808
4809                 p_ptt = ecore_ptt_acquire(p_hwfn);
4810                 if (!p_ptt)
4811                         return ECORE_TIMEOUT;
4812
4813                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4814                                                         p_link, min_bw);
4815                 if (rc != ECORE_SUCCESS) {
4816                         ecore_ptt_release(p_hwfn, p_ptt);
4817                         return rc;
4818                 }
4819
4820                 if (p_link->min_pf_rate) {
4821                         u32 min_rate = p_link->min_pf_rate;
4822
4823                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
4824                                                                      p_ptt,
4825                                                                      min_rate);
4826                 }
4827
4828                 ecore_ptt_release(p_hwfn, p_ptt);
4829         }
4830
4831         return rc;
4832 }
4833
4834 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
4835 {
4836         struct ecore_mcp_link_state *p_link;
4837
4838         p_link = &p_hwfn->mcp_info->link_output;
4839
4840         if (p_link->min_pf_rate)
4841                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4842                                                  p_link->min_pf_rate);
4843
4844         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
4845                     sizeof(*p_hwfn->qm_info.wfq_data) *
4846                     p_hwfn->qm_info.num_vports);
4847 }
4848
4849 int ecore_device_num_engines(struct ecore_dev *p_dev)
4850 {
4851         return ECORE_IS_BB(p_dev) ? 2 : 1;
4852 }
4853
4854 int ecore_device_num_ports(struct ecore_dev *p_dev)
4855 {
4856         /* in CMT always only one port */
4857         if (p_dev->num_hwfns > 1)
4858                 return 1;
4859
4860         return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
4861 }
4862
4863 void ecore_set_fw_mac_addr(__le16 *fw_msb,
4864                           __le16 *fw_mid,
4865                           __le16 *fw_lsb,
4866                           u8 *mac)
4867 {
4868         ((u8 *)fw_msb)[0] = mac[1];
4869         ((u8 *)fw_msb)[1] = mac[0];
4870         ((u8 *)fw_mid)[0] = mac[3];
4871         ((u8 *)fw_mid)[1] = mac[2];
4872         ((u8 *)fw_lsb)[0] = mac[5];
4873         ((u8 *)fw_lsb)[1] = mac[4];
4874 }