drivers/net/qede/base/ecore_dev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "reg_addr.h"
  11 #include "ecore_gtt_reg_addr.h"
  12 #include "ecore.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_status.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_init_ops.h"
  18 #include "ecore_int.h"
  19 #include "ecore_cxt.h"
  20 #include "ecore_spq.h"
  21 #include "ecore_init_fw_funcs.h"
  22 #include "ecore_sp_commands.h"
  23 #include "ecore_dev_api.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_mcp.h"
  27 #include "ecore_hw_defs.h"
  28 #include "mcp_public.h"
  29 #include "ecore_iro.h"
  30 #include "nvm_cfg.h"
  31 #include "ecore_dcbx.h"
  32 #include "ecore_l2.h"
  33
  34 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  35  * registers involved are not split and thus configuration is a race where
  36  * some of the PFs configuration might be lost.
  37  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  38  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  39  * there's more than a single compiled ecore component in system].
  40  */
  41 static osal_spinlock_t qm_lock;
  42 static bool qm_lock_init;
  43
  44 /******************** Doorbell Recovery *******************/
  45 /* The doorbell recovery mechanism consists of a list of entries which represent
  46  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  47  * entity needs to register with the mechanism and provide the parameters
  48  * describing it's doorbell, including a location where last used doorbell data
  49  * can be found. The doorbell execute function will traverse the list and
  50  * doorbell all of the registered entries.
  51  */
  52 struct ecore_db_recovery_entry {
  53         osal_list_entry_t       list_entry;
  54         void OSAL_IOMEM         *db_addr;
  55         void                    *db_data;
  56         enum ecore_db_rec_width db_width;
  57         enum ecore_db_rec_space db_space;
  58         u8                      hwfn_idx;
  59 };
  60
  61 /* display a single doorbell recovery entry */
  62 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  63                                 struct ecore_db_recovery_entry *db_entry,
  64                                 const char *action)
  65 {
  66         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  67                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  68                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  69                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  70                    db_entry->hwfn_idx);
  71 }
  72
  73 /* doorbell address sanity (address within doorbell bar range) */
  74 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  75                          void *db_data)
  76 {
  77         /* make sure doorbell address  is within the doorbell bar */
  78         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  79                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  80                 OSAL_WARN(true,
  81                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  82                           db_addr, p_dev->doorbells,
  83                           (u8 *)p_dev->doorbells + p_dev->db_size);
  84                 return false;
  85         }
  86
  87         /* make sure doorbell data pointer is not null */
  88         if (!db_data) {
  89                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  90                 return false;
  91         }
  92
  93         return true;
  94 }
  95
  96 /* find hwfn according to the doorbell address */
  97 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
  98                                           void OSAL_IOMEM *db_addr)
  99 {
 100         struct ecore_hwfn *p_hwfn;
 101
 102         /* In CMT doorbell bar is split down the middle between engine 0 and
 103          * enigne 1
 104          */
 105         if (ECORE_IS_CMT(p_dev))
 106                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 107                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 108         else
 109                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 110
 111         return p_hwfn;
 112 }
 113
 114 /* add a new entry to the doorbell recovery mechanism */
 115 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 116                                            void OSAL_IOMEM *db_addr,
 117                                            void *db_data,
 118                                            enum ecore_db_rec_width db_width,
 119                                            enum ecore_db_rec_space db_space)
 120 {
 121         struct ecore_db_recovery_entry *db_entry;
 122         struct ecore_hwfn *p_hwfn;
 123
 124         /* shortcircuit VFs, for now */
 125         if (IS_VF(p_dev)) {
 126                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 127                 return ECORE_SUCCESS;
 128         }
 129
 130         /* sanitize doorbell address */
 131         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 132                 return ECORE_INVAL;
 133
 134         /* obtain hwfn from doorbell address */
 135         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 136
 137         /* create entry */
 138         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 139         if (!db_entry) {
 140                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 141                 return ECORE_NOMEM;
 142         }
 143
 144         /* populate entry */
 145         db_entry->db_addr = db_addr;
 146         db_entry->db_data = db_data;
 147         db_entry->db_width = db_width;
 148         db_entry->db_space = db_space;
 149         db_entry->hwfn_idx = p_hwfn->my_id;
 150
 151         /* display */
 152         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 153
 154         /* protect the list */
 155         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 156         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 157                             &p_hwfn->db_recovery_info.list);
 158         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 159
 160         return ECORE_SUCCESS;
 161 }
 162
 163 /* remove an entry from the doorbell recovery mechanism */
 164 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 165                                            void OSAL_IOMEM *db_addr,
 166                                            void *db_data)
 167 {
 168         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 169         enum _ecore_status_t rc = ECORE_INVAL;
 170         struct ecore_hwfn *p_hwfn;
 171
 172         /* shortcircuit VFs, for now */
 173         if (IS_VF(p_dev)) {
 174                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 175                 return ECORE_SUCCESS;
 176         }
 177
 178         /* sanitize doorbell address */
 179         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 180                 return ECORE_INVAL;
 181
 182         /* obtain hwfn from doorbell address */
 183         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 184
 185         /* protect the list */
 186         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 187         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 188                                  &p_hwfn->db_recovery_info.list,
 189                                  list_entry,
 190                                  struct ecore_db_recovery_entry) {
 191                 /* search according to db_data addr since db_addr is not unique
 192                  * (roce)
 193                  */
 194                 if (db_entry->db_data == db_data) {
 195                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 196                                                    "Deleting");
 197                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 198                                                &p_hwfn->db_recovery_info.list);
 199                         rc = ECORE_SUCCESS;
 200                         break;
 201                 }
 202         }
 203
 204         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 205
 206         if (rc == ECORE_INVAL)
 207                 /*OSAL_WARN(true,*/
 208                 DP_NOTICE(p_hwfn, false,
 209                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 210                           db_data, db_addr);
 211         else
 212                 OSAL_FREE(p_dev, db_entry);
 213
 214         return rc;
 215 }
 216
 217 /* initialize the doorbell recovery mechanism */
 218 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 219 {
 220         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 221
 222         /* make sure db_size was set in p_dev */
 223         if (!p_hwfn->p_dev->db_size) {
 224                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 225                 return ECORE_INVAL;
 226         }
 227
 228         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 229 #ifdef CONFIG_ECORE_LOCK_ALLOC
 230         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock);
 231 #endif
 232         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 233         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 234
 235         return ECORE_SUCCESS;
 236 }
 237
 238 /* destroy the doorbell recovery mechanism */
 239 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 240 {
 241         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 242
 243         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 244         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 245                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 246                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 247                         db_entry = OSAL_LIST_FIRST_ENTRY(
 248                                                 &p_hwfn->db_recovery_info.list,
 249                                                 struct ecore_db_recovery_entry,
 250                                                 list_entry);
 251                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 252                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 253                                                &p_hwfn->db_recovery_info.list);
 254                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 255                 }
 256         }
 257 #ifdef CONFIG_ECORE_LOCK_ALLOC
 258         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 259 #endif
 260         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 261 }
 262
 263 /* print the content of the doorbell recovery mechanism */
 264 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 265 {
 266         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 267
 268         DP_NOTICE(p_hwfn, false,
 269                   "Dispalying doorbell recovery database. Counter was %d\n",
 270                   p_hwfn->db_recovery_info.db_recovery_counter);
 271
 272         /* protect the list */
 273         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 274         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 275                                  &p_hwfn->db_recovery_info.list,
 276                                  list_entry,
 277                                  struct ecore_db_recovery_entry) {
 278                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 279         }
 280
 281         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 282 }
 283
 284 /* ring the doorbell of a single doorbell recovery entry */
 285 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 286                             struct ecore_db_recovery_entry *db_entry,
 287                             enum ecore_db_rec_exec db_exec)
 288 {
 289         /* Print according to width */
 290         if (db_entry->db_width == DB_REC_WIDTH_32B)
 291                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 292                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 293                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 294         else
 295                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 296                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 297                            db_entry->db_addr,
 298                            *(unsigned long *)(db_entry->db_data));
 299
 300         /* Sanity */
 301         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 302                                  db_entry->db_data))
 303                 return;
 304
 305         /* Flush the write combined buffer. Since there are multiple doorbelling
 306          * entities using the same address, if we don't flush, a transaction
 307          * could be lost.
 308          */
 309         OSAL_WMB(p_hwfn->p_dev);
 310
 311         /* Ring the doorbell */
 312         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 313                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 314                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 315                                       *(u32 *)(db_entry->db_data));
 316                 else
 317                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 318                                         *(u64 *)(db_entry->db_data));
 319         }
 320
 321         /* Flush the write combined buffer. Next doorbell may come from a
 322          * different entity to the same address...
 323          */
 324         OSAL_WMB(p_hwfn->p_dev);
 325 }
 326
 327 /* traverse the doorbell recovery entry list and ring all the doorbells */
 328 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 329                                enum ecore_db_rec_exec db_exec)
 330 {
 331         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 332
 333         if (db_exec != DB_REC_ONCE) {
 334                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 335                           p_hwfn->db_recovery_info.db_recovery_counter);
 336
 337                 /* track amount of times recovery was executed */
 338                 p_hwfn->db_recovery_info.db_recovery_counter++;
 339         }
 340
 341         /* protect the list */
 342         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 343         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 344                                  &p_hwfn->db_recovery_info.list,
 345                                  list_entry,
 346                                  struct ecore_db_recovery_entry) {
 347                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 348                 if (db_exec == DB_REC_ONCE)
 349                         break;
 350         }
 351
 352         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 353 }
 354 /******************** Doorbell Recovery end ****************/
 355
 356 /* Configurable */
 357 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
 358                                          * load the driver. The number was
 359                                          * arbitrarily set.
 360                                          */
 361
 362 /* Derived */
 363 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
 364
 365 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
 366                              struct ecore_ptt *p_ptt,
 367                              enum BAR_ID bar_id)
 368 {
 369         u32 bar_reg = (bar_id == BAR_ID_0 ?
 370                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
 371         u32 val;
 372
 373         if (IS_VF(p_hwfn->p_dev))
 374                 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
 375
 376         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
 377         if (val)
 378                 return 1 << (val + 15);
 379
 380         /* The above registers were updated in the past only in CMT mode. Since
 381          * they were found to be useful MFW started updating them from 8.7.7.0.
 382          * In older MFW versions they are set to 0 which means disabled.
 383          */
 384         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
 385                 DP_INFO(p_hwfn,
 386                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
 387                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
 388         } else {
 389                 DP_INFO(p_hwfn,
 390                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
 391                 val = 512 * 1024;
 392         }
 393
 394         return val;
 395 }
 396
 397 void ecore_init_dp(struct ecore_dev *p_dev,
 398                    u32 dp_module, u8 dp_level, void *dp_ctx)
 399 {
 400         u32 i;
 401
 402         p_dev->dp_level = dp_level;
 403         p_dev->dp_module = dp_module;
 404         p_dev->dp_ctx = dp_ctx;
 405         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 406                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 407
 408                 p_hwfn->dp_level = dp_level;
 409                 p_hwfn->dp_module = dp_module;
 410                 p_hwfn->dp_ctx = dp_ctx;
 411         }
 412 }
 413
 414 void ecore_init_struct(struct ecore_dev *p_dev)
 415 {
 416         u8 i;
 417
 418         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 419                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 420
 421                 p_hwfn->p_dev = p_dev;
 422                 p_hwfn->my_id = i;
 423                 p_hwfn->b_active = false;
 424
 425 #ifdef CONFIG_ECORE_LOCK_ALLOC
 426                 OSAL_MUTEX_ALLOC(p_hwfn, &p_hwfn->dmae_info.mutex);
 427 #endif
 428                 OSAL_MUTEX_INIT(&p_hwfn->dmae_info.mutex);
 429         }
 430
 431         /* hwfn 0 is always active */
 432         p_dev->hwfns[0].b_active = true;
 433
 434         /* set the default cache alignment to 128 (may be overridden later) */
 435         p_dev->cache_shift = 7;
 436 }
 437
 438 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
 439 {
 440         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 441
 442         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
 443         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
 444         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
 445         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
 446 }
 447
 448 void ecore_resc_free(struct ecore_dev *p_dev)
 449 {
 450         int i;
 451
 452         if (IS_VF(p_dev)) {
 453                 for_each_hwfn(p_dev, i)
 454                         ecore_l2_free(&p_dev->hwfns[i]);
 455                 return;
 456         }
 457
 458         OSAL_FREE(p_dev, p_dev->fw_data);
 459
 460         OSAL_FREE(p_dev, p_dev->reset_stats);
 461
 462         for_each_hwfn(p_dev, i) {
 463                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 464
 465                 ecore_cxt_mngr_free(p_hwfn);
 466                 ecore_qm_info_free(p_hwfn);
 467                 ecore_spq_free(p_hwfn);
 468                 ecore_eq_free(p_hwfn);
 469                 ecore_consq_free(p_hwfn);
 470                 ecore_int_free(p_hwfn);
 471                 ecore_iov_free(p_hwfn);
 472                 ecore_l2_free(p_hwfn);
 473                 ecore_dmae_info_free(p_hwfn);
 474                 ecore_dcbx_info_free(p_hwfn);
 475                 /* @@@TBD Flush work-queue ? */
 476
 477                 /* destroy doorbell recovery mechanism */
 478                 ecore_db_recovery_teardown(p_hwfn);
 479         }
 480 }
 481
 482 /******************** QM initialization *******************/
 483
 484 /* bitmaps for indicating active traffic classes.
 485  * Special case for Arrowhead 4 port
 486  */
 487 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
 488 #define ACTIVE_TCS_BMAP 0x9f
 489 /* 0..3 actually used, OOO and high priority stuff all use 3 */
 490 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 491
 492 /* determines the physical queue flags for a given PF. */
 493 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
 494 {
 495         u32 flags;
 496
 497         /* common flags */
 498         flags = PQ_FLAGS_LB;
 499
 500         /* feature flags */
 501         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
 502                 flags |= PQ_FLAGS_VFS;
 503
 504         /* protocol flags */
 505         switch (p_hwfn->hw_info.personality) {
 506         case ECORE_PCI_ETH:
 507                 flags |= PQ_FLAGS_MCOS;
 508                 break;
 509         case ECORE_PCI_FCOE:
 510                 flags |= PQ_FLAGS_OFLD;
 511                 break;
 512         case ECORE_PCI_ISCSI:
 513                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 514                 break;
 515         case ECORE_PCI_ETH_ROCE:
 516                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD;
 517                 break;
 518         case ECORE_PCI_ETH_IWARP:
 519                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 520                          PQ_FLAGS_OFLD;
 521                 break;
 522         default:
 523                 DP_ERR(p_hwfn, "unknown personality %d\n",
 524                        p_hwfn->hw_info.personality);
 525                 return 0;
 526         }
 527         return flags;
 528 }
 529
 530 /* Getters for resource amounts necessary for qm initialization */
 531 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
 532 {
 533         return p_hwfn->hw_info.num_hw_tc;
 534 }
 535
 536 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
 537 {
 538         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
 539                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
 540 }
 541
 542 #define NUM_DEFAULT_RLS 1
 543
 544 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 545 {
 546         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 547
 548         /* @DPDK */
 549         /* num RLs can't exceed resource amount of rls or vports or the
 550          * dcqcn qps
 551          */
 552         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
 553                                      (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
 554
 555         /* make sure after we reserve the default and VF rls we'll have
 556          * something left
 557          */
 558         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
 559                 DP_NOTICE(p_hwfn, false,
 560                           "no rate limiters left for PF rate limiting"
 561                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
 562                 return 0;
 563         }
 564
 565         /* subtract rls necessary for VFs and one default one for the PF */
 566         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 567
 568         return num_pf_rls;
 569 }
 570
 571 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
 572 {
 573         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 574
 575         /* all pqs share the same vport (hence the 1 below), except for vfs
 576          * and pf_rl pqs
 577          */
 578         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 579                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 580                (!!(PQ_FLAGS_VFS & pq_flags)) *
 581                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
 582 }
 583
 584 /* calc amount of PQs according to the requested flags */
 585 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
 586 {
 587         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
 588
 589         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 590                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
 591                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 592                 ecore_init_qm_get_num_tcs(p_hwfn) +
 593                (!!(PQ_FLAGS_LB & pq_flags)) +
 594                (!!(PQ_FLAGS_OOO & pq_flags)) +
 595                (!!(PQ_FLAGS_ACK & pq_flags)) +
 596                (!!(PQ_FLAGS_OFLD & pq_flags)) +
 597                (!!(PQ_FLAGS_VFS & pq_flags)) *
 598                 ecore_init_qm_get_num_vfs(p_hwfn);
 599 }
 600
 601 /* initialize the top level QM params */
 602 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
 603 {
 604         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 605         bool four_port;
 606
 607         /* pq and vport bases for this PF */
 608         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
 609         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
 610
 611         /* rate limiting and weighted fair queueing are always enabled */
 612         qm_info->vport_rl_en = 1;
 613         qm_info->vport_wfq_en = 1;
 614
 615         /* TC config is different for AH 4 port */
 616         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 617
 618         /* in AH 4 port we have fewer TCs per port */
 619         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 620                                                      NUM_OF_PHYS_TCS;
 621
 622         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
 623          * 4 otherwise
 624          */
 625         if (!qm_info->ooo_tc)
 626                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 627                                               DCBX_TCP_OOO_TC;
 628 }
 629
 630 /* initialize qm vport params */
 631 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
 632 {
 633         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 634         u8 i;
 635
 636         /* all vports participate in weighted fair queueing */
 637         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
 638                 qm_info->qm_vport_params[i].vport_wfq = 1;
 639 }
 640
 641 /* initialize qm port params */
 642 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
 643 {
 644         /* Initialize qm port parameters */
 645         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
 646
 647         /* indicate how ooo and high pri traffic is dealt with */
 648         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 649                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
 650
 651         for (i = 0; i < num_ports; i++) {
 652                 struct init_qm_port_params *p_qm_port =
 653                         &p_hwfn->qm_info.qm_port_params[i];
 654
 655                 p_qm_port->active = 1;
 656                 p_qm_port->active_phys_tcs = active_phys_tcs;
 657                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
 658                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 659         }
 660 }
 661
 662 /* Reset the params which must be reset for qm init. QM init may be called as
 663  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 664  * params may be affected by the init but would simply recalculate to the same
 665  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 666  * affected as these amounts stay the same.
 667  */
 668 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
 669 {
 670         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 671
 672         qm_info->num_pqs = 0;
 673         qm_info->num_vports = 0;
 674         qm_info->num_pf_rls = 0;
 675         qm_info->num_vf_pqs = 0;
 676         qm_info->first_vf_pq = 0;
 677         qm_info->first_mcos_pq = 0;
 678         qm_info->first_rl_pq = 0;
 679 }
 680
 681 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
 682 {
 683         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 684
 685         qm_info->num_vports++;
 686
 687         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 688                 DP_ERR(p_hwfn,
 689                        "vport overflow! qm_info->num_vports %d,"
 690                        " qm_init_get_num_vports() %d\n",
 691                        qm_info->num_vports,
 692                        ecore_init_qm_get_num_vports(p_hwfn));
 693 }
 694
 695 /* initialize a single pq and manage qm_info resources accounting.
 696  * The pq_init_flags param determines whether the PQ is rate limited
 697  * (for VF or PF)
 698  * and whether a new vport is allocated to the pq or not (i.e. vport will be
 699  * shared)
 700  */
 701
 702 /* flags for pq init */
 703 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 704 #define PQ_INIT_PF_RL           (1 << 1)
 705 #define PQ_INIT_VF_RL           (1 << 2)
 706
 707 /* defines for pq init */
 708 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 709 #define PQ_INIT_DEFAULT_TC              0
 710 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 711
 712 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
 713                              struct ecore_qm_info *qm_info,
 714                              u8 tc, u32 pq_init_flags)
 715 {
 716         u16 pq_idx = qm_info->num_pqs, max_pq =
 717                                         ecore_init_qm_get_num_pqs(p_hwfn);
 718
 719         if (pq_idx > max_pq)
 720                 DP_ERR(p_hwfn,
 721                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 722
 723         /* init pq params */
 724         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 725                                                  qm_info->num_vports;
 726         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 727         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 728         qm_info->qm_pq_params[pq_idx].rl_valid =
 729                 (pq_init_flags & PQ_INIT_PF_RL ||
 730                  pq_init_flags & PQ_INIT_VF_RL);
 731
 732         /* qm params accounting */
 733         qm_info->num_pqs++;
 734         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 735                 qm_info->num_vports++;
 736
 737         if (pq_init_flags & PQ_INIT_PF_RL)
 738                 qm_info->num_pf_rls++;
 739
 740         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
 741                 DP_ERR(p_hwfn,
 742                        "vport overflow! qm_info->num_vports %d,"
 743                        " qm_init_get_num_vports() %d\n",
 744                        qm_info->num_vports,
 745                        ecore_init_qm_get_num_vports(p_hwfn));
 746
 747         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
 748                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
 749                        " qm_init_get_num_pf_rls() %d\n",
 750                        qm_info->num_pf_rls,
 751                        ecore_init_qm_get_num_pf_rls(p_hwfn));
 752 }
 753
 754 /* get pq index according to PQ_FLAGS */
 755 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
 756                                              u32 pq_flags)
 757 {
 758         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 759
 760         /* Can't have multiple flags set here */
 761         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
 762                                 sizeof(pq_flags)) > 1)
 763                 goto err;
 764
 765         switch (pq_flags) {
 766         case PQ_FLAGS_RLS:
 767                 return &qm_info->first_rl_pq;
 768         case PQ_FLAGS_MCOS:
 769                 return &qm_info->first_mcos_pq;
 770         case PQ_FLAGS_LB:
 771                 return &qm_info->pure_lb_pq;
 772         case PQ_FLAGS_OOO:
 773                 return &qm_info->ooo_pq;
 774         case PQ_FLAGS_ACK:
 775                 return &qm_info->pure_ack_pq;
 776         case PQ_FLAGS_OFLD:
 777                 return &qm_info->offload_pq;
 778         case PQ_FLAGS_VFS:
 779                 return &qm_info->first_vf_pq;
 780         default:
 781                 goto err;
 782         }
 783
 784 err:
 785         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 786         return OSAL_NULL;
 787 }
 788
 789 /* save pq index in qm info */
 790 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
 791                                   u32 pq_flags, u16 pq_val)
 792 {
 793         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 794
 795         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 796 }
 797
 798 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 799 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
 800 {
 801         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 802
 803         return *base_pq_idx + CM_TX_PQ_BASE;
 804 }
 805
 806 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
 807 {
 808         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
 809
 810         if (tc > max_tc)
 811                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 812
 813         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 814 }
 815
 816 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
 817 {
 818         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
 819
 820         if (vf > max_vf)
 821                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 822
 823         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 824 }
 825
 826 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 rl)
 827 {
 828         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 829
 830         if (rl > max_rl)
 831                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 832
 833         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 834 }
 835
 836 /* Functions for creating specific types of pqs */
 837 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
 838 {
 839         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 840
 841         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 842                 return;
 843
 844         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 845         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 846 }
 847
 848 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
 849 {
 850         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 851
 852         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 853                 return;
 854
 855         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 856         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 857 }
 858
 859 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
 860 {
 861         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 862
 863         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 864                 return;
 865
 866         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 867         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 868 }
 869
 870 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
 871 {
 872         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 873
 874         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 875                 return;
 876
 877         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 878         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 879 }
 880
 881 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
 882 {
 883         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 884         u8 tc_idx;
 885
 886         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 887                 return;
 888
 889         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 890         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 891                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 892 }
 893
 894 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
 895 {
 896         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 897         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 898
 899         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 900                 return;
 901
 902         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 903
 904         qm_info->num_vf_pqs = num_vfs;
 905         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 906                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
 907                                  PQ_INIT_VF_RL);
 908 }
 909
 910 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
 911 {
 912         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
 913         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 914
 915         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 916                 return;
 917
 918         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 919         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 920                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
 921                                  PQ_INIT_PF_RL);
 922 }
 923
 924 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
 925 {
 926         /* rate limited pqs, must come first (FW assumption) */
 927         ecore_init_qm_rl_pqs(p_hwfn);
 928
 929         /* pqs for multi cos */
 930         ecore_init_qm_mcos_pqs(p_hwfn);
 931
 932         /* pure loopback pq */
 933         ecore_init_qm_lb_pq(p_hwfn);
 934
 935         /* out of order pq */
 936         ecore_init_qm_ooo_pq(p_hwfn);
 937
 938         /* pure ack pq */
 939         ecore_init_qm_pure_ack_pq(p_hwfn);
 940
 941         /* pq for offloaded protocol */
 942         ecore_init_qm_offload_pq(p_hwfn);
 943
 944         /* done sharing vports */
 945         ecore_init_qm_advance_vport(p_hwfn);
 946
 947         /* pqs for vfs */
 948         ecore_init_qm_vf_pqs(p_hwfn);
 949 }
 950
 951 /* compare values of getters against resources amounts */
 952 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
 953 {
 954         if (ecore_init_qm_get_num_vports(p_hwfn) >
 955             RESC_NUM(p_hwfn, ECORE_VPORT)) {
 956                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 957                 return ECORE_INVAL;
 958         }
 959
 960         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
 961                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 962                 return ECORE_INVAL;
 963         }
 964
 965         return ECORE_SUCCESS;
 966 }
 967
 968 /*
 969  * Function for verbose printing of the qm initialization results
 970  */
 971 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
 972 {
 973         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
 974         struct init_qm_vport_params *vport;
 975         struct init_qm_port_params *port;
 976         struct init_qm_pq_params *pq;
 977         int i, tc;
 978
 979         /* top level params */
 980         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 981                    "qm init top level params: start_pq %d, start_vport %d,"
 982                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 983                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
 984                    qm_info->offload_pq, qm_info->pure_ack_pq);
 985         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 986                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
 987                    " num_vports %d, max_phys_tcs_per_port %d\n",
 988                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
 989                    qm_info->num_vf_pqs, qm_info->num_vports,
 990                    qm_info->max_phys_tcs_per_port);
 991         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 992                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
 993                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 994                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
 995                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
 996                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
 997
 998         /* port table */
 999         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
1000                 port = &qm_info->qm_port_params[i];
1001                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1002                            "port idx %d, active %d, active_phys_tcs %d,"
1003                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
1004                            " reserved %d\n",
1005                            i, port->active, port->active_phys_tcs,
1006                            port->num_pbf_cmd_lines, port->num_btb_blocks,
1007                            port->reserved);
1008         }
1009
1010         /* vport table */
1011         for (i = 0; i < qm_info->num_vports; i++) {
1012                 vport = &qm_info->qm_vport_params[i];
1013                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1014                            "vport idx %d, vport_rl %d, wfq %d,"
1015                            " first_tx_pq_id [ ",
1016                            qm_info->start_vport + i, vport->vport_rl,
1017                            vport->vport_wfq);
1018                 for (tc = 0; tc < NUM_OF_TCS; tc++)
1019                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
1020                                    vport->first_tx_pq_id[tc]);
1021                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
1022         }
1023
1024         /* pq table */
1025         for (i = 0; i < qm_info->num_pqs; i++) {
1026                 pq = &qm_info->qm_pq_params[i];
1027                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
1028                            "pq idx %d, vport_id %d, tc %d, wrr_grp %d,"
1029                            " rl_valid %d\n",
1030                            qm_info->start_pq + i, pq->vport_id, pq->tc_id,
1031                            pq->wrr_group, pq->rl_valid);
1032         }
1033 }
1034
1035 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
1036 {
1037         /* reset params required for init run */
1038         ecore_init_qm_reset_params(p_hwfn);
1039
1040         /* init QM top level params */
1041         ecore_init_qm_params(p_hwfn);
1042
1043         /* init QM port params */
1044         ecore_init_qm_port_params(p_hwfn);
1045
1046         /* init QM vport params */
1047         ecore_init_qm_vport_params(p_hwfn);
1048
1049         /* init QM physical queue params */
1050         ecore_init_qm_pq_params(p_hwfn);
1051
1052         /* display all that init */
1053         ecore_dp_init_qm_params(p_hwfn);
1054 }
1055
1056 /* This function reconfigures the QM pf on the fly.
1057  * For this purpose we:
1058  * 1. reconfigure the QM database
1059  * 2. set new values to runtime array
1060  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
1061  * 4. activate init tool in QM_PF stage
1062  * 5. send an sdm_qm_cmd through rbc interface to release the QM
1063  */
1064 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
1065                                      struct ecore_ptt *p_ptt)
1066 {
1067         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1068         bool b_rc;
1069         enum _ecore_status_t rc;
1070
1071         /* initialize ecore's qm data structure */
1072         ecore_init_qm_info(p_hwfn);
1073
1074         /* stop PF's qm queues */
1075         OSAL_SPIN_LOCK(&qm_lock);
1076         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
1077                                       qm_info->start_pq, qm_info->num_pqs);
1078         OSAL_SPIN_UNLOCK(&qm_lock);
1079         if (!b_rc)
1080                 return ECORE_INVAL;
1081
1082         /* clear the QM_PF runtime phase leftovers from previous init */
1083         ecore_init_clear_rt_data(p_hwfn);
1084
1085         /* prepare QM portion of runtime array */
1086         ecore_qm_init_pf(p_hwfn, p_ptt);
1087
1088         /* activate init tool on runtime array */
1089         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
1090                             p_hwfn->hw_info.hw_mode);
1091         if (rc != ECORE_SUCCESS)
1092                 return rc;
1093
1094         /* start PF's qm queues */
1095         OSAL_SPIN_LOCK(&qm_lock);
1096         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
1097                                       qm_info->start_pq, qm_info->num_pqs);
1098         OSAL_SPIN_UNLOCK(&qm_lock);
1099         if (!b_rc)
1100                 return ECORE_INVAL;
1101
1102         return ECORE_SUCCESS;
1103 }
1104
1105 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
1106 {
1107         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1108         enum _ecore_status_t rc;
1109
1110         rc = ecore_init_qm_sanity(p_hwfn);
1111         if (rc != ECORE_SUCCESS)
1112                 goto alloc_err;
1113
1114         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1115                                             sizeof(struct init_qm_pq_params) *
1116                                             ecore_init_qm_get_num_pqs(p_hwfn));
1117         if (!qm_info->qm_pq_params)
1118                 goto alloc_err;
1119
1120         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1121                                        sizeof(struct init_qm_vport_params) *
1122                                        ecore_init_qm_get_num_vports(p_hwfn));
1123         if (!qm_info->qm_vport_params)
1124                 goto alloc_err;
1125
1126         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1127                                       sizeof(struct init_qm_port_params) *
1128                                       p_hwfn->p_dev->num_ports_in_engine);
1129         if (!qm_info->qm_port_params)
1130                 goto alloc_err;
1131
1132         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1133                                         sizeof(struct ecore_wfq_data) *
1134                                         ecore_init_qm_get_num_vports(p_hwfn));
1135         if (!qm_info->wfq_data)
1136                 goto alloc_err;
1137
1138         return ECORE_SUCCESS;
1139
1140 alloc_err:
1141         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
1142         ecore_qm_info_free(p_hwfn);
1143         return ECORE_NOMEM;
1144 }
1145 /******************** End QM initialization ***************/
1146
1147 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
1148 {
1149         enum _ecore_status_t rc = ECORE_SUCCESS;
1150         int i;
1151
1152         if (IS_VF(p_dev)) {
1153                 for_each_hwfn(p_dev, i) {
1154                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
1155                         if (rc != ECORE_SUCCESS)
1156                                 return rc;
1157                 }
1158                 return rc;
1159         }
1160
1161         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1162                                      sizeof(*p_dev->fw_data));
1163         if (!p_dev->fw_data)
1164                 return ECORE_NOMEM;
1165
1166         for_each_hwfn(p_dev, i) {
1167                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1168                 u32 n_eqes, num_cons;
1169
1170                 /* initialize the doorbell recovery mechanism */
1171                 rc = ecore_db_recovery_setup(p_hwfn);
1172                 if (rc)
1173                         goto alloc_err;
1174
1175                 /* First allocate the context manager structure */
1176                 rc = ecore_cxt_mngr_alloc(p_hwfn);
1177                 if (rc)
1178                         goto alloc_err;
1179
1180                 /* Set the HW cid/tid numbers (in the context manager)
1181                  * Must be done prior to any further computations.
1182                  */
1183                 rc = ecore_cxt_set_pf_params(p_hwfn);
1184                 if (rc)
1185                         goto alloc_err;
1186
1187                 rc = ecore_alloc_qm_data(p_hwfn);
1188                 if (rc)
1189                         goto alloc_err;
1190
1191                 /* init qm info */
1192                 ecore_init_qm_info(p_hwfn);
1193
1194                 /* Compute the ILT client partition */
1195                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
1196                 if (rc)
1197                         goto alloc_err;
1198
1199                 /* CID map / ILT shadow table / T2
1200                  * The talbes sizes are determined by the computations above
1201                  */
1202                 rc = ecore_cxt_tables_alloc(p_hwfn);
1203                 if (rc)
1204                         goto alloc_err;
1205
1206                 /* SPQ, must follow ILT because initializes SPQ context */
1207                 rc = ecore_spq_alloc(p_hwfn);
1208                 if (rc)
1209                         goto alloc_err;
1210
1211                 /* SP status block allocation */
1212                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
1213                                                            RESERVED_PTT_DPC);
1214
1215                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1216                 if (rc)
1217                         goto alloc_err;
1218
1219                 rc = ecore_iov_alloc(p_hwfn);
1220                 if (rc)
1221                         goto alloc_err;
1222
1223                 /* EQ */
1224                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
1225                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
1226                         /* Calculate the EQ size
1227                          * ---------------------
1228                          * Each ICID may generate up to one event at a time i.e.
1229                          * the event must be handled/cleared before a new one
1230                          * can be generated. We calculate the sum of events per
1231                          * protocol and create an EQ deep enough to handle the
1232                          * worst case:
1233                          * - Core - according to SPQ.
1234                          * - RoCE - per QP there are a couple of ICIDs, one
1235                          *        responder and one requester, each can
1236                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
1237                          *        Each CQ can generate an EQE. There are 2 CQs
1238                          *        per QP => n_eqes_cq = 2 * n_qp.
1239                          *        Hence the RoCE total is 4 * n_qp or
1240                          *        2 * num_cons.
1241                          * - ENet - There can be up to two events per VF. One
1242                          *        for VF-PF channel and another for VF FLR
1243                          *        initial cleanup. The number of VFs is
1244                          *        bounded by MAX_NUM_VFS_BB, and is much
1245                          *        smaller than RoCE's so we avoid exact
1246                          *        calculation.
1247                          */
1248                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
1249                                 num_cons =
1250                                     ecore_cxt_get_proto_cid_count(
1251                                                 p_hwfn,
1252                                                 PROTOCOLID_ROCE,
1253                                                 OSAL_NULL);
1254                                 num_cons *= 2;
1255                         } else {
1256                                 num_cons = ecore_cxt_get_proto_cid_count(
1257                                                 p_hwfn,
1258                                                 PROTOCOLID_IWARP,
1259                                                 OSAL_NULL);
1260                         }
1261                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1262                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
1263                         num_cons =
1264                             ecore_cxt_get_proto_cid_count(p_hwfn,
1265                                                           PROTOCOLID_ISCSI,
1266                                                           OSAL_NULL);
1267                         n_eqes += 2 * num_cons;
1268                 }
1269
1270                 if (n_eqes > 0xFFFF) {
1271                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
1272                                        "The maximum of a u16 chain is 0x%x\n",
1273                                n_eqes, 0xFFFF);
1274                         goto alloc_no_mem;
1275                 }
1276
1277                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
1278                 if (rc)
1279                         goto alloc_err;
1280
1281                 rc = ecore_consq_alloc(p_hwfn);
1282                 if (rc)
1283                         goto alloc_err;
1284
1285                 rc = ecore_l2_alloc(p_hwfn);
1286                 if (rc != ECORE_SUCCESS)
1287                         goto alloc_err;
1288
1289                 /* DMA info initialization */
1290                 rc = ecore_dmae_info_alloc(p_hwfn);
1291                 if (rc) {
1292                         DP_NOTICE(p_hwfn, true,
1293                                   "Failed to allocate memory for dmae_info"
1294                                   " structure\n");
1295                         goto alloc_err;
1296                 }
1297
1298                 /* DCBX initialization */
1299                 rc = ecore_dcbx_info_alloc(p_hwfn);
1300                 if (rc) {
1301                         DP_NOTICE(p_hwfn, true,
1302                                   "Failed to allocate memory for dcbx structure\n");
1303                         goto alloc_err;
1304                 }
1305         }
1306
1307         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
1308                                          sizeof(*p_dev->reset_stats));
1309         if (!p_dev->reset_stats) {
1310                 DP_NOTICE(p_dev, true, "Failed to allocate reset statistics\n");
1311                 goto alloc_no_mem;
1312         }
1313
1314         return ECORE_SUCCESS;
1315
1316 alloc_no_mem:
1317         rc = ECORE_NOMEM;
1318 alloc_err:
1319         ecore_resc_free(p_dev);
1320         return rc;
1321 }
1322
1323 void ecore_resc_setup(struct ecore_dev *p_dev)
1324 {
1325         int i;
1326
1327         if (IS_VF(p_dev)) {
1328                 for_each_hwfn(p_dev, i)
1329                         ecore_l2_setup(&p_dev->hwfns[i]);
1330                 return;
1331         }
1332
1333         for_each_hwfn(p_dev, i) {
1334                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1335
1336                 ecore_cxt_mngr_setup(p_hwfn);
1337                 ecore_spq_setup(p_hwfn);
1338                 ecore_eq_setup(p_hwfn);
1339                 ecore_consq_setup(p_hwfn);
1340
1341                 /* Read shadow of current MFW mailbox */
1342                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1343                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
1344                             p_hwfn->mcp_info->mfw_mb_cur,
1345                             p_hwfn->mcp_info->mfw_mb_length);
1346
1347                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1348
1349                 ecore_l2_setup(p_hwfn);
1350                 ecore_iov_setup(p_hwfn);
1351         }
1352 }
1353
1354 #define FINAL_CLEANUP_POLL_CNT  (100)
1355 #define FINAL_CLEANUP_POLL_TIME (10)
1356 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
1357                                          struct ecore_ptt *p_ptt,
1358                                          u16 id, bool is_vf)
1359 {
1360         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1361         enum _ecore_status_t rc = ECORE_TIMEOUT;
1362
1363 #ifndef ASIC_ONLY
1364         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
1365             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1366                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
1367                 return ECORE_SUCCESS;
1368         }
1369 #endif
1370
1371         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1372             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1373
1374         if (is_vf)
1375                 id += 0x10;
1376
1377         command |= X_FINAL_CLEANUP_AGG_INT <<
1378             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1379         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1380         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1381         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1382
1383 /* Make sure notification is not set before initiating final cleanup */
1384
1385         if (REG_RD(p_hwfn, addr)) {
1386                 DP_NOTICE(p_hwfn, false,
1387                           "Unexpected; Found final cleanup notification");
1388                 DP_NOTICE(p_hwfn, false,
1389                           " before initiating final cleanup\n");
1390                 REG_WR(p_hwfn, addr, 0);
1391         }
1392
1393         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1394                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1395                    id, command);
1396
1397         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1398
1399         /* Poll until completion */
1400         while (!REG_RD(p_hwfn, addr) && count--)
1401                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
1402
1403         if (REG_RD(p_hwfn, addr))
1404                 rc = ECORE_SUCCESS;
1405         else
1406                 DP_NOTICE(p_hwfn, true,
1407                           "Failed to receive FW final cleanup notification\n");
1408
1409         /* Cleanup afterwards */
1410         REG_WR(p_hwfn, addr, 0);
1411
1412         return rc;
1413 }
1414
1415 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
1416 {
1417         int hw_mode = 0;
1418
1419         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
1420                 hw_mode |= 1 << MODE_BB;
1421         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
1422                 hw_mode |= 1 << MODE_K2;
1423         } else {
1424                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
1425                           p_hwfn->p_dev->type);
1426                 return ECORE_INVAL;
1427         }
1428
1429         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
1430         switch (p_hwfn->p_dev->num_ports_in_engine) {
1431         case 1:
1432                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1433                 break;
1434         case 2:
1435                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1436                 break;
1437         case 4:
1438                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1439                 break;
1440         default:
1441                 DP_NOTICE(p_hwfn, true,
1442                           "num_ports_in_engine = %d not supported\n",
1443                           p_hwfn->p_dev->num_ports_in_engine);
1444                 return ECORE_INVAL;
1445         }
1446
1447         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,
1448                           &p_hwfn->p_dev->mf_bits))
1449                 hw_mode |= 1 << MODE_MF_SD;
1450         else
1451                 hw_mode |= 1 << MODE_MF_SI;
1452
1453 #ifndef ASIC_ONLY
1454         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1455                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1456                         hw_mode |= 1 << MODE_FPGA;
1457                 } else {
1458                         if (p_hwfn->p_dev->b_is_emul_full)
1459                                 hw_mode |= 1 << MODE_EMUL_FULL;
1460                         else
1461                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
1462                 }
1463         } else
1464 #endif
1465                 hw_mode |= 1 << MODE_ASIC;
1466
1467         if (ECORE_IS_CMT(p_hwfn->p_dev))
1468                 hw_mode |= 1 << MODE_100G;
1469
1470         p_hwfn->hw_info.hw_mode = hw_mode;
1471
1472         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
1473                    "Configuring function for hw_mode: 0x%08x\n",
1474                    p_hwfn->hw_info.hw_mode);
1475
1476         return ECORE_SUCCESS;
1477 }
1478
1479 #ifndef ASIC_ONLY
1480 /* MFW-replacement initializations for non-ASIC */
1481 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
1482                                                struct ecore_ptt *p_ptt)
1483 {
1484         struct ecore_dev *p_dev = p_hwfn->p_dev;
1485         u32 pl_hv = 1;
1486         int i;
1487
1488         if (CHIP_REV_IS_EMUL(p_dev)) {
1489                 if (ECORE_IS_AH(p_dev))
1490                         pl_hv |= 0x600;
1491         }
1492
1493         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
1494
1495         if (CHIP_REV_IS_EMUL(p_dev) &&
1496             (ECORE_IS_AH(p_dev)))
1497                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
1498                          0x3ffffff);
1499
1500         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
1501         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
1502         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
1503                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
1504
1505         if (CHIP_REV_IS_EMUL(p_dev)) {
1506                 if (ECORE_IS_AH(p_dev)) {
1507                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
1508                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
1509                                  (p_dev->num_ports_in_engine >> 1));
1510
1511                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
1512                                  p_dev->num_ports_in_engine == 4 ? 0 : 3);
1513                 }
1514         }
1515
1516         /* Poll on RBC */
1517         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
1518         for (i = 0; i < 100; i++) {
1519                 OSAL_UDELAY(50);
1520                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
1521                         break;
1522         }
1523         if (i == 100)
1524                 DP_NOTICE(p_hwfn, true,
1525                           "RBC done failed to complete in PSWRQ2\n");
1526
1527         return ECORE_SUCCESS;
1528 }
1529 #endif
1530
1531 /* Init run time data for all PFs and their VFs on an engine.
1532  * TBD - for VFs - Once we have parent PF info for each VF in
1533  * shmem available as CAU requires knowledge of parent PF for each VF.
1534  */
1535 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
1536 {
1537         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1538         int i, igu_sb_id;
1539
1540         for_each_hwfn(p_dev, i) {
1541                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1542                 struct ecore_igu_info *p_igu_info;
1543                 struct ecore_igu_block *p_block;
1544                 struct cau_sb_entry sb_entry;
1545
1546                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1547
1548                 for (igu_sb_id = 0;
1549                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
1550                      igu_sb_id++) {
1551                         p_block = &p_igu_info->entry[igu_sb_id];
1552
1553                         if (!p_block->is_pf)
1554                                 continue;
1555
1556                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
1557                                                 p_block->function_id, 0, 0);
1558                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1559                                          sb_entry);
1560                 }
1561         }
1562 }
1563
1564 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
1565                                        struct ecore_ptt *p_ptt)
1566 {
1567         u32 val, wr_mbs, cache_line_size;
1568
1569         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1570         switch (val) {
1571         case 0:
1572                 wr_mbs = 128;
1573                 break;
1574         case 1:
1575                 wr_mbs = 256;
1576                 break;
1577         case 2:
1578                 wr_mbs = 512;
1579                 break;
1580         default:
1581                 DP_INFO(p_hwfn,
1582                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1583                         val);
1584                 return;
1585         }
1586
1587         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
1588         switch (cache_line_size) {
1589         case 32:
1590                 val = 0;
1591                 break;
1592         case 64:
1593                 val = 1;
1594                 break;
1595         case 128:
1596                 val = 2;
1597                 break;
1598         case 256:
1599                 val = 3;
1600                 break;
1601         default:
1602                 DP_INFO(p_hwfn,
1603                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1604                         cache_line_size);
1605         }
1606
1607         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
1608                 DP_INFO(p_hwfn,
1609                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1610                         OSAL_CACHE_LINE_SIZE, wr_mbs);
1611
1612         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1613         if (val > 0) {
1614                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1615                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1616         }
1617 }
1618
1619 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
1620                                                  struct ecore_ptt *p_ptt,
1621                                                  int hw_mode)
1622 {
1623         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1624         struct ecore_dev *p_dev = p_hwfn->p_dev;
1625         u8 vf_id, max_num_vfs;
1626         u16 num_pfs, pf_id;
1627         u32 concrete_fid;
1628         enum _ecore_status_t rc = ECORE_SUCCESS;
1629
1630         ecore_init_cau_rt_data(p_dev);
1631
1632         /* Program GTT windows */
1633         ecore_gtt_init(p_hwfn, p_ptt);
1634
1635 #ifndef ASIC_ONLY
1636         if (CHIP_REV_IS_EMUL(p_dev)) {
1637                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
1638                 if (rc != ECORE_SUCCESS)
1639                         return rc;
1640         }
1641 #endif
1642
1643         if (p_hwfn->mcp_info) {
1644                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1645                         qm_info->pf_rl_en = 1;
1646                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1647                         qm_info->pf_wfq_en = 1;
1648         }
1649
1650         ecore_qm_common_rt_init(p_hwfn,
1651                                 p_dev->num_ports_in_engine,
1652                                 qm_info->max_phys_tcs_per_port,
1653                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
1654                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
1655                                 qm_info->qm_port_params);
1656
1657         ecore_cxt_hw_init_common(p_hwfn);
1658
1659         ecore_init_cache_line_size(p_hwfn, p_ptt);
1660
1661         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1662         if (rc != ECORE_SUCCESS)
1663                 return rc;
1664
1665         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
1666          * need to decide with which value, maybe runtime
1667          */
1668         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1669         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1670
1671         if (ECORE_IS_BB(p_dev)) {
1672                 /* Workaround clears ROCE search for all functions to prevent
1673                  * involving non initialized function in processing ROCE packet.
1674                  */
1675                 num_pfs = NUM_OF_ENG_PFS(p_dev);
1676                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1677                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
1678                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1679                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1680                 }
1681                 /* pretend to original PF */
1682                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1683         }
1684
1685         /* Workaround for avoiding CCFC execution error when getting packets
1686          * with CRC errors, and allowing instead the invoking of the FW error
1687          * handler.
1688          * This is not done inside the init tool since it currently can't
1689          * perform a pretending to VFs.
1690          */
1691         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1692         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1693                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
1694                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
1695                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1696                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1697                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1698                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1699         }
1700         /* pretend to original PF */
1701         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1702
1703         return rc;
1704 }
1705
1706 #ifndef ASIC_ONLY
1707 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
1708 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
1709
1710 #define PMEG_IF_BYTE_COUNT      8
1711
1712 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
1713                              struct ecore_ptt *p_ptt,
1714                              u32 addr, u64 data, u8 reg_type, u8 port)
1715 {
1716         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1717                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
1718                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
1719                    (8 << PMEG_IF_BYTE_COUNT),
1720                    (reg_type << 25) | (addr << 8) | port,
1721                    (u32)((data >> 32) & 0xffffffff),
1722                    (u32)(data & 0xffffffff));
1723
1724         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
1725                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
1726                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
1727         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
1728                  (reg_type << 25) | (addr << 8) | port);
1729         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
1730         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
1731                  (data >> 32) & 0xffffffff);
1732 }
1733
1734 #define XLPORT_MODE_REG (0x20a)
1735 #define XLPORT_MAC_CONTROL (0x210)
1736 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
1737 #define XLPORT_ENABLE_REG (0x20b)
1738
1739 #define XLMAC_CTRL (0x600)
1740 #define XLMAC_MODE (0x601)
1741 #define XLMAC_RX_MAX_SIZE (0x608)
1742 #define XLMAC_TX_CTRL (0x604)
1743 #define XLMAC_PAUSE_CTRL (0x60d)
1744 #define XLMAC_PFC_CTRL (0x60e)
1745
1746 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
1747                                     struct ecore_ptt *p_ptt)
1748 {
1749         u8 loopback = 0, port = p_hwfn->port_id * 2;
1750
1751         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1752
1753         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
1754         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
1755                          port);
1756         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
1757         /* XLMAC: SOFT RESET */
1758         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
1759         /* XLMAC: Port Speed >= 10Gbps */
1760         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
1761         /* XLMAC: Max Size */
1762         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
1763         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
1764                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
1765                          0, port);
1766         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
1767         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
1768                          0x30ffffc000ULL, 0, port);
1769         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
1770                          port); /* XLMAC: TX_EN, RX_EN */
1771         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
1772         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
1773                          0x1003 | (loopback << 2), 0, port);
1774         /* Enabled Parallel PFC interface */
1775         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
1776
1777         /* XLPORT port enable */
1778         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
1779 }
1780
1781 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
1782                                        struct ecore_ptt *p_ptt)
1783 {
1784         u8 port = p_hwfn->port_id;
1785         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
1786
1787         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
1788
1789         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
1790                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
1791                  (port <<
1792                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
1793                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
1794
1795         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
1796                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
1797
1798         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
1799                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
1800
1801         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
1802                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
1803
1804         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
1805                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
1806
1807         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
1808                  (0xA <<
1809                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
1810                  (8 <<
1811                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
1812
1813         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
1814                  0xa853);
1815 }
1816
1817 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
1818                                  struct ecore_ptt *p_ptt)
1819 {
1820         if (ECORE_IS_AH(p_hwfn->p_dev))
1821                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
1822         else /* BB */
1823                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
1824 }
1825
1826 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
1827                                struct ecore_ptt *p_ptt,  u8 port)
1828 {
1829         int port_offset = port ? 0x800 : 0;
1830         u32 xmac_rxctrl = 0;
1831
1832         /* Reset of XMAC */
1833         /* FIXME: move to common start */
1834         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1835                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
1836         OSAL_MSLEEP(1);
1837         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1838                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
1839
1840         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
1841
1842         /* Set the number of ports on the Warp Core to 10G */
1843         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
1844
1845         /* Soft reset of XMAC */
1846         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
1847                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1848         OSAL_MSLEEP(1);
1849         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
1850                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
1851
1852         /* FIXME: move to common end */
1853         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
1854                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
1855
1856         /* Set Max packet size: initialize XMAC block register for port 0 */
1857         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
1858
1859         /* CRC append for Tx packets: init XMAC block register for port 1 */
1860         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
1861
1862         /* Enable TX and RX: initialize XMAC block register for port 1 */
1863         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
1864                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
1865         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
1866                                XMAC_REG_RX_CTRL_BB + port_offset);
1867         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
1868         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
1869 }
1870 #endif
1871
1872 static enum _ecore_status_t
1873 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
1874                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1875 {
1876         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1877         u32 min_dpis;
1878         u32 n_wids;
1879
1880         /* Calculate DPI size
1881          * ------------------
1882          * The PWM region contains Doorbell Pages. The first is reserverd for
1883          * the kernel for, e.g, L2. The others are free to be used by non-
1884          * trusted applications, typically from user space. Each page, called a
1885          * doorbell page is sectioned into windows that allow doorbells to be
1886          * issued in parallel by the kernel/application. The size of such a
1887          * window (a.k.a. WID) is 1kB.
1888          * Summary:
1889          *    1kB WID x N WIDS = DPI page size
1890          *    DPI page size x N DPIs = PWM region size
1891          * Notes:
1892          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
1893          * in order to ensure that two applications won't share the same page.
1894          * It also must contain at least one WID per CPU to allow parallelism.
1895          * It also must be a power of 2, since it is stored as a bit shift.
1896          *
1897          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
1898          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
1899          * containing 4 WIDs.
1900          */
1901         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
1902         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
1903         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
1904                         ~(OSAL_PAGE_SIZE - 1);
1905         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
1906         dpi_count = pwm_region_size / dpi_page_size;
1907
1908         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1909         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
1910
1911         /* Update hwfn */
1912         p_hwfn->dpi_size = dpi_page_size;
1913         p_hwfn->dpi_count = dpi_count;
1914
1915         /* Update registers */
1916         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1917
1918         if (dpi_count < min_dpis)
1919                 return ECORE_NORESOURCES;
1920
1921         return ECORE_SUCCESS;
1922 }
1923
1924 enum ECORE_ROCE_EDPM_MODE {
1925         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
1926         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
1927         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
1928 };
1929
1930 static enum _ecore_status_t
1931 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
1932                               struct ecore_ptt *p_ptt)
1933 {
1934         u32 pwm_regsize, norm_regsize;
1935         u32 non_pwm_conn, min_addr_reg1;
1936         u32 db_bar_size, n_cpus;
1937         u32 roce_edpm_mode;
1938         u32 pf_dems_shift;
1939         enum _ecore_status_t rc = ECORE_SUCCESS;
1940         u8 cond;
1941
1942         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1943         if (ECORE_IS_CMT(p_hwfn->p_dev))
1944                 db_bar_size /= 2;
1945
1946         /* Calculate doorbell regions
1947          * -----------------------------------
1948          * The doorbell BAR is made of two regions. The first is called normal
1949          * region and the second is called PWM region. In the normal region
1950          * each ICID has its own set of addresses so that writing to that
1951          * specific address identifies the ICID. In the Process Window Mode
1952          * region the ICID is given in the data written to the doorbell. The
1953          * above per PF register denotes the offset in the doorbell BAR in which
1954          * the PWM region begins.
1955          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
1956          * non-PWM connection. The calculation below computes the total non-PWM
1957          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
1958          * in units of 4,096 bytes.
1959          */
1960         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1961             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1962                                           OSAL_NULL) +
1963             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
1964         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
1965                                OSAL_PAGE_SIZE);
1966         min_addr_reg1 = norm_regsize / 4096;
1967         pwm_regsize = db_bar_size - norm_regsize;
1968
1969         /* Check that the normal and PWM sizes are valid */
1970         if (db_bar_size < norm_regsize) {
1971                 DP_ERR(p_hwfn->p_dev,
1972                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1973                        db_bar_size, norm_regsize);
1974                 return ECORE_NORESOURCES;
1975         }
1976         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
1977                 DP_ERR(p_hwfn->p_dev,
1978                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1979                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
1980                        norm_regsize);
1981                 return ECORE_NORESOURCES;
1982         }
1983
1984         /* Calculate number of DPIs */
1985         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1986         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
1987             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
1988                 /* Either EDPM is mandatory, or we are attempting to allocate a
1989                  * WID per CPU.
1990                  */
1991                 n_cpus = OSAL_NUM_CPUS();
1992                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1993         }
1994
1995         cond = ((rc != ECORE_SUCCESS) &&
1996                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
1997                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
1998         if (cond || p_hwfn->dcbx_no_edpm) {
1999                 /* Either EDPM is disabled from user configuration, or it is
2000                  * disabled via DCBx, or it is not mandatory and we failed to
2001                  * allocated a WID per CPU.
2002                  */
2003                 n_cpus = 1;
2004                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2005
2006                 /* If we entered this flow due to DCBX then the DPM register is
2007                  * already configured.
2008                  */
2009         }
2010
2011         DP_INFO(p_hwfn,
2012                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
2013                 norm_regsize, pwm_regsize);
2014         DP_INFO(p_hwfn,
2015                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
2016                 p_hwfn->dpi_size, p_hwfn->dpi_count,
2017                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
2018                 "disabled" : "enabled");
2019
2020         /* Check return codes from above calls */
2021         if (rc != ECORE_SUCCESS) {
2022                 DP_ERR(p_hwfn,
2023                        "Failed to allocate enough DPIs\n");
2024                 return ECORE_NORESOURCES;
2025         }
2026
2027         /* Update hwfn */
2028         p_hwfn->dpi_start_offset = norm_regsize;
2029
2030         /* Update registers */
2031         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2032         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
2033         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2034         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2035
2036         return ECORE_SUCCESS;
2037 }
2038
2039 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
2040                                                struct ecore_ptt *p_ptt,
2041                                                int hw_mode)
2042 {
2043         u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
2044         u32 val;
2045         enum _ecore_status_t rc = ECORE_SUCCESS;
2046         u8 i;
2047
2048         /* In CMT for non-RoCE packets - use connection based classification */
2049         val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
2050         for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
2051                 ppf_to_eng_sel[i] = val;
2052         STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
2053                          ppf_to_eng_sel);
2054
2055         /* In CMT the gate should be cleared by the 2nd hwfn */
2056         if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
2057                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2058
2059         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
2060                             hw_mode);
2061         if (rc != ECORE_SUCCESS)
2062                 return rc;
2063
2064         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2065
2066 #ifndef ASIC_ONLY
2067         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
2068                 return ECORE_SUCCESS;
2069
2070         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2071                 if (ECORE_IS_AH(p_hwfn->p_dev))
2072                         return ECORE_SUCCESS;
2073                 else if (ECORE_IS_BB(p_hwfn->p_dev))
2074                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
2075         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2076                 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
2077                         /* Activate OPTE in CMT */
2078                         u32 val;
2079
2080                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
2081                         val |= 0x10;
2082                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
2083                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
2084                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
2085                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
2086                         ecore_wr(p_hwfn, p_ptt,
2087                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
2088                         ecore_wr(p_hwfn, p_ptt,
2089                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
2090                         ecore_wr(p_hwfn, p_ptt,
2091                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
2092                                  0x55555555);
2093                 }
2094
2095                 ecore_emul_link_init(p_hwfn, p_ptt);
2096         } else {
2097                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
2098         }
2099 #endif
2100
2101         return rc;
2102 }
2103
2104 static enum _ecore_status_t
2105 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
2106                  struct ecore_ptt *p_ptt,
2107                  struct ecore_tunnel_info *p_tunn,
2108                  int hw_mode,
2109                  bool b_hw_start,
2110                  enum ecore_int_mode int_mode, bool allow_npar_tx_switch)
2111 {
2112         u8 rel_pf_id = p_hwfn->rel_pf_id;
2113         u32 prs_reg;
2114         enum _ecore_status_t rc = ECORE_SUCCESS;
2115         u16 ctrl;
2116         int pos;
2117
2118         if (p_hwfn->mcp_info) {
2119                 struct ecore_mcp_function_info *p_info;
2120
2121                 p_info = &p_hwfn->mcp_info->func_info;
2122                 if (p_info->bandwidth_min)
2123                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2124
2125                 /* Update rate limit once we'll actually have a link */
2126                 p_hwfn->qm_info.pf_rl = 100000;
2127         }
2128         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
2129
2130         ecore_int_igu_init_rt(p_hwfn);
2131
2132         /* Set VLAN in NIG if needed */
2133         if (hw_mode & (1 << MODE_MF_SD)) {
2134                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2135                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2136                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2137                              p_hwfn->hw_info.ovlan);
2138
2139                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2140                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2141                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2142                              1);
2143         }
2144
2145         /* Enable classification by MAC if needed */
2146         if (hw_mode & (1 << MODE_MF_SI)) {
2147                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2148                            "Configuring TAGMAC_CLS_TYPE\n");
2149                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
2150                              1);
2151         }
2152
2153         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
2154         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2155                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
2156         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2157                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
2158         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2159
2160         /* perform debug configuration when chip is out of reset */
2161         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
2162
2163         /* PF Init sequence */
2164         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2165         if (rc)
2166                 return rc;
2167
2168         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2169         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2170         if (rc)
2171                 return rc;
2172
2173         /* Pure runtime initializations - directly to the HW  */
2174         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2175
2176         /* PCI relaxed ordering causes a decrease in the performance on some
2177          * systems. Till a root cause is found, disable this attribute in the
2178          * PCI config space.
2179          */
2180         /* Not in use @DPDK
2181         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
2182         * if (!pos) {
2183         *       DP_NOTICE(p_hwfn, true,
2184         *                 "Failed to find the PCIe Cap\n");
2185         *       return ECORE_IO;
2186         * }
2187         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
2188         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
2189         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
2190         */
2191
2192         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2193         if (rc)
2194                 return rc;
2195         if (b_hw_start) {
2196                 /* enable interrupts */
2197                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);
2198                 if (rc != ECORE_SUCCESS)
2199                         return rc;
2200
2201                 /* send function start command */
2202                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2203                                        allow_npar_tx_switch);
2204                 if (rc) {
2205                         DP_NOTICE(p_hwfn, true,
2206                                   "Function start ramrod failed\n");
2207                 } else {
2208                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2209                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2210                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2211
2212                         if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
2213                                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
2214                                          (1 << 2));
2215                                 ecore_wr(p_hwfn, p_ptt,
2216                                     PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2217                                     0x100);
2218                         }
2219                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2220                                    "PRS_REG_SEARCH registers after start PFn\n");
2221                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
2222                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2223                                    "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
2224                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
2225                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2226                                    "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
2227                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
2228                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2229                                    "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
2230                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
2231                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2232                                    "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
2233                         prs_reg = ecore_rd(p_hwfn, p_ptt,
2234                                            PRS_REG_SEARCH_TCP_FIRST_FRAG);
2235                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2236                                    "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
2237                                    prs_reg);
2238                         prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
2239                         DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
2240                                    "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
2241                 }
2242         }
2243         return rc;
2244 }
2245
2246 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
2247                                                   struct ecore_ptt *p_ptt,
2248                                                   bool b_enable)
2249 {
2250         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2251
2252         /* Configure the PF's internal FID_enable for master transactions */
2253         ecore_wr(p_hwfn, p_ptt,
2254                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2255
2256         /* Wait until value is set - try for 1 second every 50us */
2257         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2258                 val = ecore_rd(p_hwfn, p_ptt,
2259                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2260                 if (val == set_val)
2261                         break;
2262
2263                 OSAL_UDELAY(50);
2264         }
2265
2266         if (val != set_val) {
2267                 DP_NOTICE(p_hwfn, true,
2268                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
2269                 return ECORE_UNKNOWN_ERROR;
2270         }
2271
2272         return ECORE_SUCCESS;
2273 }
2274
2275 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
2276                                   struct ecore_ptt *p_main_ptt)
2277 {
2278         /* Read shadow of current MFW mailbox */
2279         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
2280         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2281                     p_hwfn->mcp_info->mfw_mb_cur,
2282                     p_hwfn->mcp_info->mfw_mb_length);
2283 }
2284
2285 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
2286                                      struct ecore_ptt *p_ptt)
2287 {
2288         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2289                  1 << p_hwfn->abs_pf_id);
2290 }
2291
2292 static void
2293 ecore_fill_load_req_params(struct ecore_load_req_params *p_load_req,
2294                            struct ecore_drv_load_params *p_drv_load)
2295 {
2296         /* Make sure that if ecore-client didn't provide inputs, all the
2297          * expected defaults are indeed zero.
2298          */
2299         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
2300         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
2301         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
2302
2303         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
2304
2305         if (p_drv_load != OSAL_NULL) {
2306                 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2307                                        ECORE_DRV_ROLE_KDUMP :
2308                                        ECORE_DRV_ROLE_OS;
2309                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2310                 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2311                 p_load_req->override_force_load =
2312                         p_drv_load->override_force_load;
2313         }
2314 }
2315
2316 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
2317                                     struct ecore_hw_init_params *p_params)
2318 {
2319         if (p_params->p_tunn) {
2320                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2321                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2322         }
2323
2324         p_hwfn->b_int_enabled = 1;
2325
2326         return ECORE_SUCCESS;
2327 }
2328
2329 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
2330                                    struct ecore_hw_init_params *p_params)
2331 {
2332         struct ecore_load_req_params load_req_params;
2333         u32 load_code, resp, param, drv_mb_param;
2334         bool b_default_mtu = true;
2335         struct ecore_hwfn *p_hwfn;
2336         enum _ecore_status_t rc = ECORE_SUCCESS;
2337         int i;
2338
2339         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
2340                 DP_NOTICE(p_dev, false,
2341                           "MSI mode is not supported for CMT devices\n");
2342                 return ECORE_INVAL;
2343         }
2344
2345         if (IS_PF(p_dev)) {
2346                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
2347                 if (rc != ECORE_SUCCESS)
2348                         return rc;
2349         }
2350
2351         for_each_hwfn(p_dev, i) {
2352                 p_hwfn = &p_dev->hwfns[i];
2353
2354                 /* If management didn't provide a default, set one of our own */
2355                 if (!p_hwfn->hw_info.mtu) {
2356                         p_hwfn->hw_info.mtu = 1500;
2357                         b_default_mtu = false;
2358                 }
2359
2360                 if (IS_VF(p_dev)) {
2361                         ecore_vf_start(p_hwfn, p_params);
2362                         continue;
2363                 }
2364
2365                 rc = ecore_calc_hw_mode(p_hwfn);
2366                 if (rc != ECORE_SUCCESS)
2367                         return rc;
2368
2369                 ecore_fill_load_req_params(&load_req_params,
2370                                            p_params->p_drv_load_params);
2371                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
2372                                         &load_req_params);
2373                 if (rc != ECORE_SUCCESS) {
2374                         DP_NOTICE(p_hwfn, true,
2375                                   "Failed sending a LOAD_REQ command\n");
2376                         return rc;
2377                 }
2378
2379                 load_code = load_req_params.load_code;
2380                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2381                            "Load request was sent. Load code: 0x%x\n",
2382                            load_code);
2383
2384                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
2385
2386                 /* CQ75580:
2387                  * When coming back from hiberbate state, the registers from
2388                  * which shadow is read initially are not initialized. It turns
2389                  * out that these registers get initialized during the call to
2390                  * ecore_mcp_load_req request. So we need to reread them here
2391                  * to get the proper shadow register value.
2392                  * Note: This is a workaround for the missing MFW
2393                  * initialization. It may be removed once the implementation
2394                  * is done.
2395                  */
2396                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
2397
2398                 /* Only relevant for recovery:
2399                  * Clear the indication after the LOAD_REQ command is responded
2400                  * by the MFW.
2401                  */
2402                 p_dev->recov_in_prog = false;
2403
2404                 p_hwfn->first_on_engine = (load_code ==
2405                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
2406
2407                 if (!qm_lock_init) {
2408                         OSAL_SPIN_LOCK_INIT(&qm_lock);
2409                         qm_lock_init = true;
2410                 }
2411
2412                 /* Clean up chip from previous driver if such remains exist.
2413                  * This is not needed when the PF is the first one on the
2414                  * engine, since afterwards we are going to init the FW.
2415                  */
2416                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
2417                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
2418                                                  p_hwfn->rel_pf_id, false);
2419                         if (rc != ECORE_SUCCESS) {
2420                                 ecore_hw_err_notify(p_hwfn,
2421                                                     ECORE_HW_ERR_RAMROD_FAIL);
2422                                 goto load_err;
2423                         }
2424                 }
2425
2426                 /* Log and clean previous pglue_b errors if such exist */
2427                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
2428                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2429
2430                 /* Enable the PF's internal FID_enable in the PXP */
2431                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2432                                                   true);
2433                 if (rc != ECORE_SUCCESS)
2434                         goto load_err;
2435
2436                 switch (load_code) {
2437                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
2438                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
2439                                                   p_hwfn->hw_info.hw_mode);
2440                         if (rc != ECORE_SUCCESS)
2441                                 break;
2442                         /* Fall into */
2443                 case FW_MSG_CODE_DRV_LOAD_PORT:
2444                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
2445                                                 p_hwfn->hw_info.hw_mode);
2446                         if (rc != ECORE_SUCCESS)
2447                                 break;
2448                         /* Fall into */
2449                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
2450                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
2451                                               p_params->p_tunn,
2452                                               p_hwfn->hw_info.hw_mode,
2453                                               p_params->b_hw_start,
2454                                               p_params->int_mode,
2455                                               p_params->allow_npar_tx_switch);
2456                         break;
2457                 default:
2458                         DP_NOTICE(p_hwfn, false,
2459                                   "Unexpected load code [0x%08x]", load_code);
2460                         rc = ECORE_NOTIMPL;
2461                         break;
2462                 }
2463
2464                 if (rc != ECORE_SUCCESS) {
2465                         DP_NOTICE(p_hwfn, true,
2466                                   "init phase failed for loadcode 0x%x (rc %d)\n",
2467                                   load_code, rc);
2468                         goto load_err;
2469                 }
2470
2471                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2472                 if (rc != ECORE_SUCCESS)
2473                         return rc;
2474
2475                 /* send DCBX attention request command */
2476                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
2477                            "sending phony dcbx set command to trigger DCBx attention handling\n");
2478                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2479                                    DRV_MSG_CODE_SET_DCBX,
2480                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
2481                                    &param);
2482                 if (rc != ECORE_SUCCESS) {
2483                         DP_NOTICE(p_hwfn, true,
2484                                   "Failed to send DCBX attention request\n");
2485                         return rc;
2486                 }
2487
2488                 p_hwfn->hw_init_done = true;
2489         }
2490
2491         if (IS_PF(p_dev)) {
2492                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2493                 drv_mb_param = STORM_FW_VERSION;
2494                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
2495                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
2496                                    drv_mb_param, &resp, &param);
2497                 if (rc != ECORE_SUCCESS)
2498                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
2499
2500                 if (!b_default_mtu)
2501                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
2502                                                       p_hwfn->hw_info.mtu);
2503                 if (rc != ECORE_SUCCESS)
2504                         DP_INFO(p_hwfn, "Failed to update default mtu\n");
2505
2506                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
2507                                                       p_hwfn->p_main_ptt,
2508                                                 ECORE_OV_DRIVER_STATE_DISABLED);
2509                 if (rc != ECORE_SUCCESS)
2510                         DP_INFO(p_hwfn, "Failed to update driver state\n");
2511         }
2512
2513         return rc;
2514
2515 load_err:
2516         /* The MFW load lock should be released regardless of success or failure
2517          * of initialization.
2518          * TODO: replace this with an attempt to send cancel_load.
2519          */
2520         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
2521         return rc;
2522 }
2523
2524 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
2525 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
2526                                  struct ecore_hwfn *p_hwfn,
2527                                  struct ecore_ptt *p_ptt)
2528 {
2529         int i;
2530
2531         /* close timers */
2532         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
2533         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
2534         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
2535                                                                         i++) {
2536                 if ((!ecore_rd(p_hwfn, p_ptt,
2537                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
2538                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
2539                         break;
2540
2541                 /* Dependent on number of connection/tasks, possibly
2542                  * 1ms sleep is required between polls
2543                  */
2544                 OSAL_MSLEEP(1);
2545         }
2546
2547         if (i < ECORE_HW_STOP_RETRY_LIMIT)
2548                 return;
2549
2550         DP_NOTICE(p_hwfn, true, "Timers linear scans are not over"
2551                   " [Connection %02x Tasks %02x]\n",
2552                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
2553                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
2554 }
2555
2556 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
2557 {
2558         int j;
2559
2560         for_each_hwfn(p_dev, j) {
2561                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2562                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2563
2564                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2565         }
2566 }
2567
2568 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
2569                                                  struct ecore_ptt *p_ptt,
2570                                                  u32 addr, u32 expected_val)
2571 {
2572         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
2573
2574         if (val != expected_val) {
2575                 DP_NOTICE(p_hwfn, true,
2576                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
2577                           addr, val, expected_val);
2578                 return ECORE_UNKNOWN_ERROR;
2579         }
2580
2581         return ECORE_SUCCESS;
2582 }
2583
2584 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
2585 {
2586         struct ecore_hwfn *p_hwfn;
2587         struct ecore_ptt *p_ptt;
2588         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
2589         int j;
2590
2591         for_each_hwfn(p_dev, j) {
2592                 p_hwfn = &p_dev->hwfns[j];
2593                 p_ptt = p_hwfn->p_main_ptt;
2594
2595                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
2596
2597                 if (IS_VF(p_dev)) {
2598                         ecore_vf_pf_int_cleanup(p_hwfn);
2599                         rc = ecore_vf_pf_reset(p_hwfn);
2600                         if (rc != ECORE_SUCCESS) {
2601                                 DP_NOTICE(p_hwfn, true,
2602                                           "ecore_vf_pf_reset failed. rc = %d.\n",
2603                                           rc);
2604                                 rc2 = ECORE_UNKNOWN_ERROR;
2605                         }
2606                         continue;
2607                 }
2608
2609                 /* mark the hw as uninitialized... */
2610                 p_hwfn->hw_init_done = false;
2611
2612                 /* Send unload command to MCP */
2613                 if (!p_dev->recov_in_prog) {
2614                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
2615                         if (rc != ECORE_SUCCESS) {
2616                                 DP_NOTICE(p_hwfn, true,
2617                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2618                                           rc);
2619                                 rc2 = ECORE_UNKNOWN_ERROR;
2620                         }
2621                 }
2622
2623                 OSAL_DPC_SYNC(p_hwfn);
2624
2625                 /* After this point no MFW attentions are expected, e.g. prevent
2626                  * race between pf stop and dcbx pf update.
2627                  */
2628
2629                 rc = ecore_sp_pf_stop(p_hwfn);
2630                 if (rc != ECORE_SUCCESS) {
2631                         DP_NOTICE(p_hwfn, true,
2632                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2633                                   rc);
2634                         rc2 = ECORE_UNKNOWN_ERROR;
2635                 }
2636
2637                 /* perform debug action after PF stop was sent */
2638                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
2639
2640                 /* close NIG to BRB gate */
2641                 ecore_wr(p_hwfn, p_ptt,
2642                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2643
2644                 /* close parser */
2645                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2646                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2647                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2648                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2649                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2650
2651                 /* @@@TBD - clean transmission queues (5.b) */
2652                 /* @@@TBD - clean BTB (5.c) */
2653
2654                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
2655
2656                 /* @@@TBD - verify DMAE requests are done (8) */
2657
2658                 /* Disable Attention Generation */
2659                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
2660                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2661                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2662                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2663                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
2664                 if (rc != ECORE_SUCCESS) {
2665                         DP_NOTICE(p_hwfn, true,
2666                                   "Failed to return IGU CAM to default\n");
2667                         rc2 = ECORE_UNKNOWN_ERROR;
2668                 }
2669
2670                 /* Need to wait 1ms to guarantee SBs are cleared */
2671                 OSAL_MSLEEP(1);
2672
2673                 if (!p_dev->recov_in_prog) {
2674                         ecore_verify_reg_val(p_hwfn, p_ptt,
2675                                              QM_REG_USG_CNT_PF_TX, 0);
2676                         ecore_verify_reg_val(p_hwfn, p_ptt,
2677                                              QM_REG_USG_CNT_PF_OTHER, 0);
2678                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
2679                 }
2680
2681                 /* Disable PF in HW blocks */
2682                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2683                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2684
2685                 if (!p_dev->recov_in_prog) {
2686                         ecore_mcp_unload_done(p_hwfn, p_ptt);
2687                         if (rc != ECORE_SUCCESS) {
2688                                 DP_NOTICE(p_hwfn, true,
2689                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2690                                           rc);
2691                                 rc2 = ECORE_UNKNOWN_ERROR;
2692                         }
2693                 }
2694         } /* hwfn loop */
2695
2696         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
2697                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
2698                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
2699
2700                  /* Clear the PF's internal FID_enable in the PXP.
2701                   * In CMT this should only be done for first hw-function, and
2702                   * only after all transactions have stopped for all active
2703                   * hw-functions.
2704                   */
2705                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
2706                                                   false);
2707                 if (rc != ECORE_SUCCESS) {
2708                         DP_NOTICE(p_hwfn, true,
2709                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2710                                   rc);
2711                         rc2 = ECORE_UNKNOWN_ERROR;
2712                 }
2713         }
2714
2715         return rc2;
2716 }
2717
2718 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
2719 {
2720         int j;
2721
2722         for_each_hwfn(p_dev, j) {
2723                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
2724                 struct ecore_ptt *p_ptt;
2725
2726                 if (IS_VF(p_dev)) {
2727                         ecore_vf_pf_int_cleanup(p_hwfn);
2728                         continue;
2729                 }
2730                 p_ptt = ecore_ptt_acquire(p_hwfn);
2731                 if (!p_ptt)
2732                         return ECORE_AGAIN;
2733
2734                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
2735                            "Shutting down the fastpath\n");
2736
2737                 ecore_wr(p_hwfn, p_ptt,
2738                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2739
2740                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2741                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2742                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2743                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2744                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2745
2746                 /* @@@TBD - clean transmission queues (5.b) */
2747                 /* @@@TBD - clean BTB (5.c) */
2748
2749                 /* @@@TBD - verify DMAE requests are done (8) */
2750
2751                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2752                 /* Need to wait 1ms to guarantee SBs are cleared */
2753                 OSAL_MSLEEP(1);
2754                 ecore_ptt_release(p_hwfn, p_ptt);
2755         }
2756
2757         return ECORE_SUCCESS;
2758 }
2759
2760 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
2761 {
2762         struct ecore_ptt *p_ptt;
2763
2764         if (IS_VF(p_hwfn->p_dev))
2765                 return ECORE_SUCCESS;
2766
2767         p_ptt = ecore_ptt_acquire(p_hwfn);
2768         if (!p_ptt)
2769                 return ECORE_AGAIN;
2770
2771         /* If roce info is allocated it means roce is initialized and should
2772          * be enabled in searcher.
2773          */
2774         if (p_hwfn->p_rdma_info) {
2775                 if (p_hwfn->b_rdma_enabled_in_prs)
2776                         ecore_wr(p_hwfn, p_ptt,
2777                                  p_hwfn->rdma_prs_search_reg, 0x1);
2778                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
2779         }
2780
2781         /* Re-open incoming traffic */
2782         ecore_wr(p_hwfn, p_ptt,
2783                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2784         ecore_ptt_release(p_hwfn, p_ptt);
2785
2786         return ECORE_SUCCESS;
2787 }
2788
2789 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2790 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
2791 {
2792         ecore_ptt_pool_free(p_hwfn);
2793         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
2794 }
2795
2796 /* Setup bar access */
2797 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
2798 {
2799         /* clear indirect access */
2800         if (ECORE_IS_AH(p_hwfn->p_dev)) {
2801                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2802                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
2803                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2804                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
2805                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2806                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
2807                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2808                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
2809         } else {
2810                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2811                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2812                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2813                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2814                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2815                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2816                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2817                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2818         }
2819
2820         /* Clean previous pglue_b errors if such exist */
2821         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
2822
2823         /* enable internal target-read */
2824         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
2825                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2826 }
2827
2828 static void get_function_id(struct ecore_hwfn *p_hwfn)
2829 {
2830         /* ME Register */
2831         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
2832                                                   PXP_PF_ME_OPAQUE_ADDR);
2833
2834         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2835
2836         /* Bits 16-19 from the ME registers are the pf_num */
2837         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2838         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2839                                       PXP_CONCRETE_FID_PFID);
2840         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2841                                     PXP_CONCRETE_FID_PORT);
2842
2843         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2844                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2845                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2846 }
2847
2848 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
2849 {
2850         u32 *feat_num = p_hwfn->hw_info.feat_num;
2851         struct ecore_sb_cnt_info sb_cnt;
2852         u32 non_l2_sbs = 0;
2853
2854         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
2855         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
2856
2857         /* L2 Queues require each: 1 status block. 1 L2 queue */
2858         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
2859                 /* Start by allocating VF queues, then PF's */
2860                 feat_num[ECORE_VF_L2_QUE] =
2861                         OSAL_MIN_T(u32,
2862                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
2863                                    sb_cnt.iov_cnt);
2864                 feat_num[ECORE_PF_L2_QUE] =
2865                         OSAL_MIN_T(u32,
2866                                    sb_cnt.cnt - non_l2_sbs,
2867                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
2868                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
2869         }
2870
2871         if (ECORE_IS_FCOE_PERSONALITY(p_hwfn))
2872                 feat_num[ECORE_FCOE_CQ] =
2873                         OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2874                                                              ECORE_CMDQS_CQS));
2875
2876         if (ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
2877                 feat_num[ECORE_ISCSI_CQ] =
2878                         OSAL_MIN_T(u32, sb_cnt.cnt, RESC_NUM(p_hwfn,
2879                                                              ECORE_CMDQS_CQS));
2880
2881         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
2882                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
2883                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
2884                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
2885                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
2886                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
2887                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
2888                    (int)sb_cnt.cnt);
2889 }
2890
2891 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
2892 {
2893         switch (res_id) {
2894         case ECORE_L2_QUEUE:
2895                 return "L2_QUEUE";
2896         case ECORE_VPORT:
2897                 return "VPORT";
2898         case ECORE_RSS_ENG:
2899                 return "RSS_ENG";
2900         case ECORE_PQ:
2901                 return "PQ";
2902         case ECORE_RL:
2903                 return "RL";
2904         case ECORE_MAC:
2905                 return "MAC";
2906         case ECORE_VLAN:
2907                 return "VLAN";
2908         case ECORE_RDMA_CNQ_RAM:
2909                 return "RDMA_CNQ_RAM";
2910         case ECORE_ILT:
2911                 return "ILT";
2912         case ECORE_LL2_QUEUE:
2913                 return "LL2_QUEUE";
2914         case ECORE_CMDQS_CQS:
2915                 return "CMDQS_CQS";
2916         case ECORE_RDMA_STATS_QUEUE:
2917                 return "RDMA_STATS_QUEUE";
2918         case ECORE_BDQ:
2919                 return "BDQ";
2920         case ECORE_SB:
2921                 return "SB";
2922         default:
2923                 return "UNKNOWN_RESOURCE";
2924         }
2925 }
2926
2927 static enum _ecore_status_t
2928 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2929                               struct ecore_ptt *p_ptt,
2930                               enum ecore_resources res_id,
2931                               u32 resc_max_val,
2932                               u32 *p_mcp_resp)
2933 {
2934         enum _ecore_status_t rc;
2935
2936         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2937                                         resc_max_val, p_mcp_resp);
2938         if (rc != ECORE_SUCCESS) {
2939                 DP_NOTICE(p_hwfn, true,
2940                           "MFW response failure for a max value setting of resource %d [%s]\n",
2941                           res_id, ecore_hw_get_resc_name(res_id));
2942                 return rc;
2943         }
2944
2945         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2946                 DP_INFO(p_hwfn,
2947                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2948                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
2949
2950         return ECORE_SUCCESS;
2951 }
2952
2953 static enum _ecore_status_t
2954 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
2955                             struct ecore_ptt *p_ptt)
2956 {
2957         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
2958         u32 resc_max_val, mcp_resp;
2959         u8 res_id;
2960         enum _ecore_status_t rc;
2961
2962         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
2963                 /* @DPDK */
2964                 switch (res_id) {
2965                 case ECORE_LL2_QUEUE:
2966                 case ECORE_RDMA_CNQ_RAM:
2967                 case ECORE_RDMA_STATS_QUEUE:
2968                 case ECORE_BDQ:
2969                         resc_max_val = 0;
2970                         break;
2971                 default:
2972                         continue;
2973                 }
2974
2975                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2976                                                    resc_max_val, &mcp_resp);
2977                 if (rc != ECORE_SUCCESS)
2978                         return rc;
2979
2980                 /* There's no point to continue to the next resource if the
2981                  * command is not supported by the MFW.
2982                  * We do continue if the command is supported but the resource
2983                  * is unknown to the MFW. Such a resource will be later
2984                  * configured with the default allocation values.
2985                  */
2986                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2987                         return ECORE_NOTIMPL;
2988         }
2989
2990         return ECORE_SUCCESS;
2991 }
2992
2993 static
2994 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
2995                                             enum ecore_resources res_id,
2996                                             u32 *p_resc_num, u32 *p_resc_start)
2997 {
2998         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2999         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3000
3001         switch (res_id) {
3002         case ECORE_L2_QUEUE:
3003                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
3004                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
3005                 break;
3006         case ECORE_VPORT:
3007                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3008                                  MAX_NUM_VPORTS_BB) / num_funcs;
3009                 break;
3010         case ECORE_RSS_ENG:
3011                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
3012                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
3013                 break;
3014         case ECORE_PQ:
3015                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
3016                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
3017                 break;
3018         case ECORE_RL:
3019                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
3020                 break;
3021         case ECORE_MAC:
3022         case ECORE_VLAN:
3023                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3024                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3025                 break;
3026         case ECORE_ILT:
3027                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
3028                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
3029                 break;
3030         case ECORE_LL2_QUEUE:
3031                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
3032                 break;
3033         case ECORE_RDMA_CNQ_RAM:
3034         case ECORE_CMDQS_CQS:
3035                 /* CNQ/CMDQS are the same resource */
3036                 /* @DPDK */
3037                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
3038                 break;
3039         case ECORE_RDMA_STATS_QUEUE:
3040                 /* @DPDK */
3041                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
3042                                  MAX_NUM_VPORTS_BB) / num_funcs;
3043                 break;
3044         case ECORE_BDQ:
3045                 /* @DPDK */
3046                 *p_resc_num = 0;
3047                 break;
3048         default:
3049                 break;
3050         }
3051
3052
3053         switch (res_id) {
3054         case ECORE_BDQ:
3055                 if (!*p_resc_num)
3056                         *p_resc_start = 0;
3057                 break;
3058         case ECORE_SB:
3059                 /* Since we want its value to reflect whether MFW supports
3060                  * the new scheme, have a default of 0.
3061                  */
3062                 *p_resc_num = 0;
3063                 break;
3064         default:
3065                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3066                 break;
3067         }
3068
3069         return ECORE_SUCCESS;
3070 }
3071
3072 static enum _ecore_status_t
3073 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
3074                          bool drv_resc_alloc)
3075 {
3076         u32 dflt_resc_num = 0, dflt_resc_start = 0;
3077         u32 mcp_resp, *p_resc_num, *p_resc_start;
3078         enum _ecore_status_t rc;
3079
3080         p_resc_num = &RESC_NUM(p_hwfn, res_id);
3081         p_resc_start = &RESC_START(p_hwfn, res_id);
3082
3083         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3084                                     &dflt_resc_start);
3085         if (rc != ECORE_SUCCESS) {
3086                 DP_ERR(p_hwfn,
3087                        "Failed to get default amount for resource %d [%s]\n",
3088                         res_id, ecore_hw_get_resc_name(res_id));
3089                 return rc;
3090         }
3091
3092 #ifndef ASIC_ONLY
3093         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3094                 *p_resc_num = dflt_resc_num;
3095                 *p_resc_start = dflt_resc_start;
3096                 goto out;
3097         }
3098 #endif
3099
3100         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3101                                      &mcp_resp, p_resc_num, p_resc_start);
3102         if (rc != ECORE_SUCCESS) {
3103                 DP_NOTICE(p_hwfn, true,
3104                           "MFW response failure for an allocation request for"
3105                           " resource %d [%s]\n",
3106                           res_id, ecore_hw_get_resc_name(res_id));
3107                 return rc;
3108         }
3109
3110         /* Default driver values are applied in the following cases:
3111          * - The resource allocation MB command is not supported by the MFW
3112          * - There is an internal error in the MFW while processing the request
3113          * - The resource ID is unknown to the MFW
3114          */
3115         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3116                 DP_INFO(p_hwfn,
3117                         "Failed to receive allocation info for resource %d [%s]."
3118                         " mcp_resp = 0x%x. Applying default values"
3119                         " [%d,%d].\n",
3120                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
3121                         dflt_resc_num, dflt_resc_start);
3122
3123                 *p_resc_num = dflt_resc_num;
3124                 *p_resc_start = dflt_resc_start;
3125                 goto out;
3126         }
3127
3128         if ((*p_resc_num != dflt_resc_num ||
3129              *p_resc_start != dflt_resc_start) &&
3130             res_id != ECORE_SB) {
3131                 DP_INFO(p_hwfn,
3132                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
3133                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
3134                         *p_resc_start, dflt_resc_num, dflt_resc_start,
3135                         drv_resc_alloc ? " - Applying default values" : "");
3136                 if (drv_resc_alloc) {
3137                         *p_resc_num = dflt_resc_num;
3138                         *p_resc_start = dflt_resc_start;
3139                 }
3140         }
3141 out:
3142         return ECORE_SUCCESS;
3143 }
3144
3145 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
3146                                                    bool drv_resc_alloc)
3147 {
3148         enum _ecore_status_t rc;
3149         u8 res_id;
3150
3151         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
3152                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
3153                 if (rc != ECORE_SUCCESS)
3154                         return rc;
3155         }
3156
3157         return ECORE_SUCCESS;
3158 }
3159
3160 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
3161                                               struct ecore_ptt *p_ptt,
3162                                               bool drv_resc_alloc)
3163 {
3164         struct ecore_resc_unlock_params resc_unlock_params;
3165         struct ecore_resc_lock_params resc_lock_params;
3166         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
3167         u8 res_id;
3168         enum _ecore_status_t rc;
3169 #ifndef ASIC_ONLY
3170         u32 *resc_start = p_hwfn->hw_info.resc_start;
3171         u32 *resc_num = p_hwfn->hw_info.resc_num;
3172         /* For AH, an equal share of the ILT lines between the maximal number of
3173          * PFs is not enough for RoCE. This would be solved by the future
3174          * resource allocation scheme, but isn't currently present for
3175          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
3176          * to work - the BB number of ILT lines divided by its max PFs number.
3177          */
3178         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
3179 #endif
3180
3181         /* Setting the max values of the soft resources and the following
3182          * resources allocation queries should be atomic. Since several PFs can
3183          * run in parallel - a resource lock is needed.
3184          * If either the resource lock or resource set value commands are not
3185          * supported - skip the the max values setting, release the lock if
3186          * needed, and proceed to the queries. Other failures, including a
3187          * failure to acquire the lock, will cause this function to fail.
3188          * Old drivers that don't acquire the lock can run in parallel, and
3189          * their allocation values won't be affected by the updated max values.
3190          */
3191         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3192                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
3193
3194         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3195         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3196                 return rc;
3197         } else if (rc == ECORE_NOTIMPL) {
3198                 DP_INFO(p_hwfn,
3199                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3200         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
3201                 DP_NOTICE(p_hwfn, false,
3202                           "Failed to acquire the resource lock for the resource allocation commands\n");
3203                 rc = ECORE_BUSY;
3204                 goto unlock_and_exit;
3205         } else {
3206                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
3207                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
3208                         DP_NOTICE(p_hwfn, false,
3209                                   "Failed to set the max values of the soft resources\n");
3210                         goto unlock_and_exit;
3211                 } else if (rc == ECORE_NOTIMPL) {
3212                         DP_INFO(p_hwfn,
3213                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3214                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3215                                                    &resc_unlock_params);
3216                         if (rc != ECORE_SUCCESS)
3217                                 DP_INFO(p_hwfn,
3218                                         "Failed to release the resource lock for the resource allocation commands\n");
3219                 }
3220         }
3221
3222         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
3223         if (rc != ECORE_SUCCESS)
3224                 goto unlock_and_exit;
3225
3226         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3227                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3228                                            &resc_unlock_params);
3229                 if (rc != ECORE_SUCCESS)
3230                         DP_INFO(p_hwfn,
3231                                 "Failed to release the resource lock for the resource allocation commands\n");
3232         }
3233
3234 #ifndef ASIC_ONLY
3235         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
3236                 /* Reduced build contains less PQs */
3237                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
3238                         resc_num[ECORE_PQ] = 32;
3239                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
3240                             p_hwfn->enabled_func_idx;
3241                 }
3242
3243                 /* For AH emulation, since we have a possible maximal number of
3244                  * 16 enabled PFs, in case there are not enough ILT lines -
3245                  * allocate only first PF as RoCE and have all the other ETH
3246                  * only with less ILT lines.
3247                  */
3248                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
3249                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
3250                                                          resc_num[ECORE_ILT],
3251                                                          roce_min_ilt_lines);
3252         }
3253
3254         /* Correct the common ILT calculation if PF0 has more */
3255         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
3256             p_hwfn->p_dev->b_is_emul_full &&
3257             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
3258                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
3259                     resc_num[ECORE_ILT];
3260 #endif
3261
3262         /* Sanity for ILT */
3263         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3264             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3265                 DP_NOTICE(p_hwfn, true,
3266                           "Can't assign ILT pages [%08x,...,%08x]\n",
3267                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
3268                                                                   ECORE_ILT) -
3269                           1);
3270                 return ECORE_INVAL;
3271         }
3272
3273         /* This will also learn the number of SBs from MFW */
3274         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
3275                 return ECORE_INVAL;
3276
3277         ecore_hw_set_feat(p_hwfn);
3278
3279         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3280                    "The numbers for each resource are:\n");
3281         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
3282                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
3283                            ecore_hw_get_resc_name(res_id),
3284                            RESC_NUM(p_hwfn, res_id),
3285                            RESC_START(p_hwfn, res_id));
3286
3287         return ECORE_SUCCESS;
3288
3289 unlock_and_exit:
3290         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3291                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
3292                                       &resc_unlock_params);
3293         return rc;
3294 }
3295
3296 static enum _ecore_status_t
3297 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
3298                       struct ecore_ptt *p_ptt,
3299                       struct ecore_hw_prepare_params *p_params)
3300 {
3301         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
3302         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3303         struct ecore_mcp_link_capabilities *p_caps;
3304         struct ecore_mcp_link_params *link;
3305         enum _ecore_status_t rc;
3306
3307         /* Read global nvm_cfg address */
3308         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3309
3310         /* Verify MCP has initialized it */
3311         if (!nvm_cfg_addr) {
3312                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
3313                 if (p_params->b_relaxed_probe)
3314                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
3315                 return ECORE_INVAL;
3316         }
3317
3318 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
3319
3320         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
3321
3322         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3323                    OFFSETOF(struct nvm_cfg1, glob) +
3324                    OFFSETOF(struct nvm_cfg1_glob, core_cfg);
3325
3326         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
3327
3328         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
3329                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
3330         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
3331                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
3332                 break;
3333         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
3334                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
3335                 break;
3336         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
3337                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
3338                 break;
3339         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
3340                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
3341                 break;
3342         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
3343                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
3344                 break;
3345         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
3346                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
3347                 break;
3348         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
3349                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
3350                 break;
3351         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
3352                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
3353                 break;
3354         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
3355                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
3356                 break;
3357         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
3358                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
3359                 break;
3360         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
3361                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
3362                 break;
3363         default:
3364                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
3365                           core_cfg);
3366                 break;
3367         }
3368
3369         /* Read DCBX configuration */
3370         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3371                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3372         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
3373                              port_cfg_addr +
3374                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
3375         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
3376                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
3377         switch (dcbx_mode) {
3378         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
3379                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
3380                 break;
3381         case NVM_CFG1_PORT_DCBX_MODE_CEE:
3382                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
3383                 break;
3384         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
3385                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
3386                 break;
3387         default:
3388                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
3389         }
3390
3391         /* Read default link configuration */
3392         link = &p_hwfn->mcp_info->link_input;
3393         p_caps = &p_hwfn->mcp_info->link_capabilities;
3394         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3395             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
3396         link_temp = ecore_rd(p_hwfn, p_ptt,
3397                              port_cfg_addr +
3398                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
3399         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
3400         link->speed.advertised_speeds = link_temp;
3401         p_caps->speed_capabilities = link->speed.advertised_speeds;
3402
3403         link_temp = ecore_rd(p_hwfn, p_ptt,
3404                                  port_cfg_addr +
3405                                  OFFSETOF(struct nvm_cfg1_port, link_settings));
3406         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
3407                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
3408         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
3409                 link->speed.autoneg = true;
3410                 break;
3411         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
3412                 link->speed.forced_speed = 1000;
3413                 break;
3414         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
3415                 link->speed.forced_speed = 10000;
3416                 break;
3417         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
3418                 link->speed.forced_speed = 25000;
3419                 break;
3420         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
3421                 link->speed.forced_speed = 40000;
3422                 break;
3423         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
3424                 link->speed.forced_speed = 50000;
3425                 break;
3426         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
3427                 link->speed.forced_speed = 100000;
3428                 break;
3429         default:
3430                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
3431         }
3432
3433         p_caps->default_speed = link->speed.forced_speed;
3434         p_caps->default_speed_autoneg = link->speed.autoneg;
3435
3436         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
3437         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
3438         link->pause.autoneg = !!(link_temp &
3439                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
3440         link->pause.forced_rx = !!(link_temp &
3441                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
3442         link->pause.forced_tx = !!(link_temp &
3443                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
3444         link->loopback_mode = 0;
3445
3446         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
3447                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
3448                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
3449                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
3450                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
3451                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
3452                 link->eee.enable = true;
3453                 switch (link_temp) {
3454                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
3455                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
3456                         link->eee.enable = false;
3457                         break;
3458                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
3459                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
3460                         break;
3461                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
3462                         p_caps->eee_lpi_timer =
3463                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
3464                         break;
3465                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
3466                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
3467                         break;
3468                 }
3469
3470                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
3471                 link->eee.tx_lpi_enable = link->eee.enable;
3472                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
3473         } else {
3474                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
3475         }
3476
3477         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
3478                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
3479                    link->speed.forced_speed, link->speed.advertised_speeds,
3480                    link->speed.autoneg, link->pause.autoneg,
3481                    p_caps->default_eee, p_caps->eee_lpi_timer);
3482
3483         /* Read Multi-function information from shmem */
3484         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3485                    OFFSETOF(struct nvm_cfg1, glob) +
3486                    OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
3487
3488         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
3489
3490         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
3491             NVM_CFG1_GLOB_MF_MODE_OFFSET;
3492
3493         switch (mf_mode) {
3494         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3495                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
3496                 break;
3497         case NVM_CFG1_GLOB_MF_MODE_UFP:
3498                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3499                                          1 << ECORE_MF_UFP_SPECIFIC |
3500                                          1 << ECORE_MF_8021Q_TAGGING;
3501                 break;
3502         case NVM_CFG1_GLOB_MF_MODE_BD:
3503                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
3504                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3505                                          1 << ECORE_MF_8021AD_TAGGING;
3506                 break;
3507         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3508                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3509                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3510                                          1 << ECORE_MF_LL2_NON_UNICAST |
3511                                          1 << ECORE_MF_INTER_PF_SWITCH |
3512                                          1 << ECORE_MF_DISABLE_ARFS;
3513                 break;
3514         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3515                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
3516                                          1 << ECORE_MF_LLH_PROTO_CLSS |
3517                                          1 << ECORE_MF_LL2_NON_UNICAST;
3518                 if (ECORE_IS_BB(p_hwfn->p_dev))
3519                         p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
3520                 break;
3521         }
3522         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
3523                 p_hwfn->p_dev->mf_bits);
3524
3525         if (ECORE_IS_CMT(p_hwfn->p_dev))
3526                 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
3527
3528         /* It's funny since we have another switch, but it's easier
3529          * to throw this away in linux this way. Long term, it might be
3530          * better to have have getters for needed ECORE_MF_* fields,
3531          * convert client code and eliminate this.
3532          */
3533         switch (mf_mode) {
3534         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
3535         case NVM_CFG1_GLOB_MF_MODE_BD:
3536                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
3537                 break;
3538         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
3539                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
3540                 break;
3541         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
3542                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
3543                 break;
3544         case NVM_CFG1_GLOB_MF_MODE_UFP:
3545                 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
3546                 break;
3547         }
3548
3549         /* Read Multi-function information from shmem */
3550         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
3551                    OFFSETOF(struct nvm_cfg1, glob) +
3552                    OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
3553
3554         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
3555         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
3556                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
3557                                 &p_hwfn->hw_info.device_capabilities);
3558         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
3559                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
3560                                 &p_hwfn->hw_info.device_capabilities);
3561         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
3562                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
3563                                 &p_hwfn->hw_info.device_capabilities);
3564         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
3565                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
3566                                 &p_hwfn->hw_info.device_capabilities);
3567         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
3568                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
3569                                 &p_hwfn->hw_info.device_capabilities);
3570
3571         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
3572         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3573                 rc = ECORE_SUCCESS;
3574                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3575         }
3576
3577         return rc;
3578 }
3579
3580 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
3581                                 struct ecore_ptt *p_ptt)
3582 {
3583         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
3584         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
3585         struct ecore_dev *p_dev = p_hwfn->p_dev;
3586
3587         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
3588
3589         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
3590          * in the other bits are selected.
3591          * Bits 1-15 are for functions 1-15, respectively, and their value is
3592          * '0' only for enabled functions (function 0 always exists and
3593          * enabled).
3594          * In case of CMT in BB, only the "even" functions are enabled, and thus
3595          * the number of functions for both hwfns is learnt from the same bits.
3596          */
3597         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
3598                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
3599                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
3600         } else { /* E5 */
3601                 reg_function_hide = 0;
3602         }
3603
3604         if (reg_function_hide & 0x1) {
3605                 if (ECORE_IS_BB(p_dev)) {
3606                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
3607                                 num_funcs = 0;
3608                                 eng_mask = 0xaaaa;
3609                         } else {
3610                                 num_funcs = 1;
3611                                 eng_mask = 0x5554;
3612                         }
3613                 } else {
3614                         num_funcs = 1;
3615                         eng_mask = 0xfffe;
3616                 }
3617
3618                 /* Get the number of the enabled functions on the engine */
3619                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
3620                 while (tmp) {
3621                         if (tmp & 0x1)
3622                                 num_funcs++;
3623                         tmp >>= 0x1;
3624                 }
3625
3626                 /* Get the PF index within the enabled functions */
3627                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
3628                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
3629                 while (tmp) {
3630                         if (tmp & 0x1)
3631                                 enabled_func_idx--;
3632                         tmp >>= 0x1;
3633                 }
3634         }
3635
3636         p_hwfn->num_funcs_on_engine = num_funcs;
3637         p_hwfn->enabled_func_idx = enabled_func_idx;
3638
3639 #ifndef ASIC_ONLY
3640         if (CHIP_REV_IS_FPGA(p_dev)) {
3641                 DP_NOTICE(p_hwfn, false,
3642                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
3643                 p_hwfn->num_funcs_on_engine = 4;
3644         }
3645 #endif
3646
3647         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
3648                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
3649                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
3650                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
3651 }
3652
3653 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
3654                                       struct ecore_ptt *p_ptt)
3655 {
3656         struct ecore_dev *p_dev = p_hwfn->p_dev;
3657         u32 port_mode;
3658
3659 #ifndef ASIC_ONLY
3660         /* Read the port mode */
3661         if (CHIP_REV_IS_FPGA(p_dev))
3662                 port_mode = 4;
3663         else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
3664                 /* In CMT on emulation, assume 1 port */
3665                 port_mode = 1;
3666         else
3667 #endif
3668         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
3669
3670         if (port_mode < 3) {
3671                 p_dev->num_ports_in_engine = 1;
3672         } else if (port_mode <= 5) {
3673                 p_dev->num_ports_in_engine = 2;
3674         } else {
3675                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
3676                           p_dev->num_ports_in_engine);
3677
3678                 /* Default num_ports_in_engine to something */
3679                 p_dev->num_ports_in_engine = 1;
3680         }
3681 }
3682
3683 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
3684                                          struct ecore_ptt *p_ptt)
3685 {
3686         struct ecore_dev *p_dev = p_hwfn->p_dev;
3687         u32 port;
3688         int i;
3689
3690         p_dev->num_ports_in_engine = 0;
3691
3692 #ifndef ASIC_ONLY
3693         if (CHIP_REV_IS_EMUL(p_dev)) {
3694                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3695                 switch ((port & 0xf000) >> 12) {
3696                 case 1:
3697                         p_dev->num_ports_in_engine = 1;
3698                         break;
3699                 case 3:
3700                         p_dev->num_ports_in_engine = 2;
3701                         break;
3702                 case 0xf:
3703                         p_dev->num_ports_in_engine = 4;
3704                         break;
3705                 default:
3706                         DP_NOTICE(p_hwfn, false,
3707                                   "Unknown port mode in ECO_RESERVED %08x\n",
3708                                   port);
3709                 }
3710         } else
3711 #endif
3712                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
3713                         port = ecore_rd(p_hwfn, p_ptt,
3714                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
3715                                         (i * 4));
3716                         if (port & 1)
3717                                 p_dev->num_ports_in_engine++;
3718                 }
3719
3720         if (!p_dev->num_ports_in_engine) {
3721                 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
3722
3723                 /* Default num_ports_in_engine to something */
3724                 p_dev->num_ports_in_engine = 1;
3725         }
3726 }
3727
3728 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
3729                                    struct ecore_ptt *p_ptt)
3730 {
3731         struct ecore_dev *p_dev = p_hwfn->p_dev;
3732
3733         /* Determine the number of ports per engine */
3734         if (ECORE_IS_BB(p_dev))
3735                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
3736         else
3737                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
3738
3739         /* Get the total number of ports of the device */
3740         if (ECORE_IS_CMT(p_dev)) {
3741                 /* In CMT there is always only one port */
3742                 p_dev->num_ports = 1;
3743 #ifndef ASIC_ONLY
3744         } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
3745                 p_dev->num_ports = p_dev->num_ports_in_engine *
3746                                    ecore_device_num_engines(p_dev);
3747 #endif
3748         } else {
3749                 u32 addr, global_offsize, global_addr;
3750
3751                 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
3752                                             PUBLIC_GLOBAL);
3753                 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
3754                 global_addr = SECTION_ADDR(global_offsize, 0);
3755                 addr = global_addr + OFFSETOF(struct public_global, max_ports);
3756                 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
3757         }
3758 }
3759
3760 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
3761                                    struct ecore_ptt *p_ptt)
3762 {
3763         struct ecore_mcp_link_capabilities *p_caps;
3764         u32 eee_status;
3765
3766         p_caps = &p_hwfn->mcp_info->link_capabilities;
3767         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
3768                 return;
3769
3770         p_caps->eee_speed_caps = 0;
3771         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
3772                               OFFSETOF(struct public_port, eee_status));
3773         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
3774                         EEE_SUPPORTED_SPEED_OFFSET;
3775         if (eee_status & EEE_1G_SUPPORTED)
3776                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
3777         if (eee_status & EEE_10G_ADV)
3778                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
3779 }
3780
3781 static enum _ecore_status_t
3782 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3783                   enum ecore_pci_personality personality,
3784                   struct ecore_hw_prepare_params *p_params)
3785 {
3786         bool drv_resc_alloc = p_params->drv_resc_alloc;
3787         enum _ecore_status_t rc;
3788
3789         /* Since all information is common, only first hwfns should do this */
3790         if (IS_LEAD_HWFN(p_hwfn)) {
3791                 rc = ecore_iov_hw_info(p_hwfn);
3792                 if (rc != ECORE_SUCCESS) {
3793                         if (p_params->b_relaxed_probe)
3794                                 p_params->p_relaxed_res =
3795                                                 ECORE_HW_PREPARE_BAD_IOV;
3796                         else
3797                                 return rc;
3798                 }
3799         }
3800
3801         if (IS_LEAD_HWFN(p_hwfn))
3802                 ecore_hw_info_port_num(p_hwfn, p_ptt);
3803
3804         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
3805
3806 #ifndef ASIC_ONLY
3807         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
3808 #endif
3809         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
3810         if (rc != ECORE_SUCCESS)
3811                 return rc;
3812 #ifndef ASIC_ONLY
3813         }
3814 #endif
3815
3816         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
3817         if (rc != ECORE_SUCCESS) {
3818                 if (p_params->b_relaxed_probe)
3819                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
3820                 else
3821                         return rc;
3822         }
3823
3824 #ifndef ASIC_ONLY
3825         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
3826 #endif
3827                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
3828                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
3829 #ifndef ASIC_ONLY
3830         } else {
3831                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
3832
3833                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
3834                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
3835         }
3836 #endif
3837
3838         if (ecore_mcp_is_init(p_hwfn)) {
3839                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
3840                         p_hwfn->hw_info.ovlan =
3841                             p_hwfn->mcp_info->func_info.ovlan;
3842
3843                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
3844
3845                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
3846
3847                 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
3848         }
3849
3850         if (personality != ECORE_PCI_DEFAULT) {
3851                 p_hwfn->hw_info.personality = personality;
3852         } else if (ecore_mcp_is_init(p_hwfn)) {
3853                 enum ecore_pci_personality protocol;
3854
3855                 protocol = p_hwfn->mcp_info->func_info.protocol;
3856                 p_hwfn->hw_info.personality = protocol;
3857         }
3858
3859 #ifndef ASIC_ONLY
3860         /* To overcome ILT lack for emulation, until at least until we'll have
3861          * a definite answer from system about it, allow only PF0 to be RoCE.
3862          */
3863         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
3864                 if (!p_hwfn->rel_pf_id)
3865                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
3866                 else
3867                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
3868         }
3869 #endif
3870
3871         /* although in BB some constellations may support more than 4 tcs,
3872          * that can result in performance penalty in some cases. 4
3873          * represents a good tradeoff between performance and flexibility.
3874          */
3875         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3876
3877         /* start out with a single active tc. This can be increased either
3878          * by dcbx negotiation or by upper layer driver
3879          */
3880         p_hwfn->hw_info.num_active_tc = 1;
3881
3882         ecore_get_num_funcs(p_hwfn, p_ptt);
3883
3884         if (ecore_mcp_is_init(p_hwfn))
3885                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3886
3887         /* In case of forcing the driver's default resource allocation, calling
3888          * ecore_hw_get_resc() should come after initializing the personality
3889          * and after getting the number of functions, since the calculation of
3890          * the resources/features depends on them.
3891          * This order is not harmful if not forcing.
3892          */
3893         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
3894         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
3895                 rc = ECORE_SUCCESS;
3896                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
3897         }
3898
3899         return rc;
3900 }
3901
3902 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
3903                                                struct ecore_ptt *p_ptt)
3904 {
3905         struct ecore_dev *p_dev = p_hwfn->p_dev;
3906         u16 device_id_mask;
3907         u32 tmp;
3908
3909         /* Read Vendor Id / Device Id */
3910         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
3911                                   &p_dev->vendor_id);
3912         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
3913                                   &p_dev->device_id);
3914
3915         /* Determine type */
3916         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
3917         switch (device_id_mask) {
3918         case ECORE_DEV_ID_MASK_BB:
3919                 p_dev->type = ECORE_DEV_TYPE_BB;
3920                 break;
3921         case ECORE_DEV_ID_MASK_AH:
3922                 p_dev->type = ECORE_DEV_TYPE_AH;
3923                 break;
3924         default:
3925                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
3926                           p_dev->device_id);
3927                 return ECORE_ABORTED;
3928         }
3929
3930         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3931         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
3932         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3933         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
3934
3935         /* Learn number of HW-functions */
3936         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3937
3938         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3939                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
3940                 p_dev->num_hwfns = 2;
3941         } else {
3942                 p_dev->num_hwfns = 1;
3943         }
3944
3945 #ifndef ASIC_ONLY
3946         if (CHIP_REV_IS_EMUL(p_dev)) {
3947                 /* For some reason we have problems with this register
3948                  * in B0 emulation; Simply assume no CMT
3949                  */
3950                 DP_NOTICE(p_dev->hwfns, false,
3951                           "device on emul - assume no CMT\n");
3952                 p_dev->num_hwfns = 1;
3953         }
3954 #endif
3955
3956         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
3957         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
3958         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3959         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
3960
3961         DP_INFO(p_dev->hwfns,
3962                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
3963                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
3964                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
3965                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
3966                 p_dev->chip_metal);
3967
3968         if (ECORE_IS_BB_A0(p_dev)) {
3969                 DP_NOTICE(p_dev->hwfns, false,
3970                           "The chip type/rev (BB A0) is not supported!\n");
3971                 return ECORE_ABORTED;
3972         }
3973 #ifndef ASIC_ONLY
3974         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
3975                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
3976
3977         if (CHIP_REV_IS_EMUL(p_dev)) {
3978                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
3979                 if (tmp & (1 << 29)) {
3980                         DP_NOTICE(p_hwfn, false,
3981                                   "Emulation: Running on a FULL build\n");
3982                         p_dev->b_is_emul_full = true;
3983                 } else {
3984                         DP_NOTICE(p_hwfn, false,
3985                                   "Emulation: Running on a REDUCED build\n");
3986                 }
3987         }
3988 #endif
3989
3990         return ECORE_SUCCESS;
3991 }
3992
3993 #ifndef LINUX_REMOVE
3994 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
3995 {
3996         int j;
3997
3998         if (IS_VF(p_dev))
3999                 return;
4000
4001         for_each_hwfn(p_dev, j) {
4002                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4003
4004                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4005                            "Mark hw/fw uninitialized\n");
4006
4007                 p_hwfn->hw_init_done = false;
4008
4009                 ecore_ptt_invalidate(p_hwfn);
4010         }
4011 }
4012 #endif
4013
4014 static enum _ecore_status_t
4015 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,
4016                         void OSAL_IOMEM * p_regview,
4017                         void OSAL_IOMEM * p_doorbells,
4018                         struct ecore_hw_prepare_params *p_params)
4019 {
4020         struct ecore_mdump_retain_data mdump_retain;
4021         struct ecore_dev *p_dev = p_hwfn->p_dev;
4022         struct ecore_mdump_info mdump_info;
4023         enum _ecore_status_t rc = ECORE_SUCCESS;
4024
4025         /* Split PCI bars evenly between hwfns */
4026         p_hwfn->regview = p_regview;
4027         p_hwfn->doorbells = p_doorbells;
4028
4029         if (IS_VF(p_dev))
4030                 return ecore_vf_hw_prepare(p_hwfn);
4031
4032         /* Validate that chip access is feasible */
4033         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4034                 DP_ERR(p_hwfn,
4035                        "Reading the ME register returns all Fs; Preventing further chip access\n");
4036                 if (p_params->b_relaxed_probe)
4037                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
4038                 return ECORE_INVAL;
4039         }
4040
4041         get_function_id(p_hwfn);
4042
4043         /* Allocate PTT pool */
4044         rc = ecore_ptt_pool_alloc(p_hwfn);
4045         if (rc) {
4046                 DP_NOTICE(p_hwfn, true, "Failed to prepare hwfn's hw\n");
4047                 if (p_params->b_relaxed_probe)
4048                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4049                 goto err0;
4050         }
4051
4052         /* Allocate the main PTT */
4053         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4054
4055         /* First hwfn learns basic information, e.g., number of hwfns */
4056         if (!p_hwfn->my_id) {
4057                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4058                 if (rc != ECORE_SUCCESS) {
4059                         if (p_params->b_relaxed_probe)
4060                                 p_params->p_relaxed_res =
4061                                         ECORE_HW_PREPARE_FAILED_DEV;
4062                         goto err1;
4063                 }
4064         }
4065
4066         ecore_hw_hwfn_prepare(p_hwfn);
4067
4068         /* Initialize MCP structure */
4069         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4070         if (rc) {
4071                 DP_NOTICE(p_hwfn, true, "Failed initializing mcp command\n");
4072                 if (p_params->b_relaxed_probe)
4073                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4074                 goto err1;
4075         }
4076
4077         /* Read the device configuration information from the HW and SHMEM */
4078         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
4079                                p_params->personality, p_params);
4080         if (rc) {
4081                 DP_NOTICE(p_hwfn, true, "Failed to get HW information\n");
4082                 goto err2;
4083         }
4084
4085         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
4086          * called, since among others it sets the ports number in an engine.
4087          */
4088         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
4089             !p_dev->recov_in_prog) {
4090                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4091                 if (rc != ECORE_SUCCESS)
4092                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
4093         }
4094
4095         /* Check if mdump logs/data are present and update the epoch value */
4096         if (IS_LEAD_HWFN(p_hwfn)) {
4097 #ifndef ASIC_ONLY
4098                 if (!CHIP_REV_IS_EMUL(p_dev)) {
4099 #endif
4100                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
4101                                               &mdump_info);
4102                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
4103                         DP_NOTICE(p_hwfn, false,
4104                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
4105
4106                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
4107                                                 &mdump_retain);
4108                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
4109                         DP_NOTICE(p_hwfn, false,
4110                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
4111                                   mdump_retain.epoch, mdump_retain.pf,
4112                                   mdump_retain.status);
4113
4114                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
4115                                            p_params->epoch);
4116 #ifndef ASIC_ONLY
4117                 }
4118 #endif
4119         }
4120
4121         /* Allocate the init RT array and initialize the init-ops engine */
4122         rc = ecore_init_alloc(p_hwfn);
4123         if (rc) {
4124                 DP_NOTICE(p_hwfn, true, "Failed to allocate the init array\n");
4125                 if (p_params->b_relaxed_probe)
4126                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
4127                 goto err2;
4128         }
4129 #ifndef ASIC_ONLY
4130         if (CHIP_REV_IS_FPGA(p_dev)) {
4131                 DP_NOTICE(p_hwfn, false,
4132                           "FPGA: workaround; Prevent DMAE parities\n");
4133                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
4134                          7);
4135
4136                 DP_NOTICE(p_hwfn, false,
4137                           "FPGA: workaround: Set VF bar0 size\n");
4138                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4139                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
4140         }
4141 #endif
4142
4143         return rc;
4144 err2:
4145         if (IS_LEAD_HWFN(p_hwfn))
4146                 ecore_iov_free_hw_info(p_dev);
4147         ecore_mcp_free(p_hwfn);
4148 err1:
4149         ecore_hw_hwfn_free(p_hwfn);
4150 err0:
4151         return rc;
4152 }
4153
4154 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
4155                                       struct ecore_hw_prepare_params *p_params)
4156 {
4157         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4158         enum _ecore_status_t rc;
4159
4160         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
4161         p_dev->allow_mdump = p_params->allow_mdump;
4162
4163         if (p_params->b_relaxed_probe)
4164                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
4165
4166         /* Store the precompiled init data ptrs */
4167         if (IS_PF(p_dev))
4168                 ecore_init_iro_array(p_dev);
4169
4170         /* Initialize the first hwfn - will learn number of hwfns */
4171         rc = ecore_hw_prepare_single(p_hwfn,
4172                                      p_dev->regview,
4173                                      p_dev->doorbells, p_params);
4174         if (rc != ECORE_SUCCESS)
4175                 return rc;
4176
4177         p_params->personality = p_hwfn->hw_info.personality;
4178
4179         /* initilalize 2nd hwfn if necessary */
4180         if (ECORE_IS_CMT(p_dev)) {
4181                 void OSAL_IOMEM *p_regview, *p_doorbell;
4182                 u8 OSAL_IOMEM *addr;
4183
4184                 /* adjust bar offset for second engine */
4185                 addr = (u8 OSAL_IOMEM *)p_dev->regview +
4186                                         ecore_hw_bar_size(p_hwfn,
4187                                                           p_hwfn->p_main_ptt,
4188                                                           BAR_ID_0) / 2;
4189                 p_regview = (void OSAL_IOMEM *)addr;
4190
4191                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells +
4192                                         ecore_hw_bar_size(p_hwfn,
4193                                                           p_hwfn->p_main_ptt,
4194                                                           BAR_ID_1) / 2;
4195                 p_doorbell = (void OSAL_IOMEM *)addr;
4196
4197                 /* prepare second hw function */
4198                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
4199                                              p_doorbell, p_params);
4200
4201                 /* in case of error, need to free the previously
4202                  * initiliazed hwfn 0.
4203                  */
4204                 if (rc != ECORE_SUCCESS) {
4205                         if (p_params->b_relaxed_probe)
4206                                 p_params->p_relaxed_res =
4207                                                 ECORE_HW_PREPARE_FAILED_ENG2;
4208
4209                         if (IS_PF(p_dev)) {
4210                                 ecore_init_free(p_hwfn);
4211                                 ecore_mcp_free(p_hwfn);
4212                                 ecore_hw_hwfn_free(p_hwfn);
4213                         } else {
4214                                 DP_NOTICE(p_dev, true,
4215                                           "What do we need to free when VF hwfn1 init fails\n");
4216                         }
4217                         return rc;
4218                 }
4219         }
4220
4221         return rc;
4222 }
4223
4224 void ecore_hw_remove(struct ecore_dev *p_dev)
4225 {
4226         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
4227         int i;
4228
4229         if (IS_PF(p_dev))
4230                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4231                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
4232
4233         for_each_hwfn(p_dev, i) {
4234                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
4235
4236                 if (IS_VF(p_dev)) {
4237                         ecore_vf_pf_release(p_hwfn);
4238                         continue;
4239                 }
4240
4241                 ecore_init_free(p_hwfn);
4242                 ecore_hw_hwfn_free(p_hwfn);
4243                 ecore_mcp_free(p_hwfn);
4244
4245 #ifdef CONFIG_ECORE_LOCK_ALLOC
4246                 OSAL_MUTEX_DEALLOC(&p_hwfn->dmae_info.mutex);
4247 #endif
4248         }
4249
4250         ecore_iov_free_hw_info(p_dev);
4251 }
4252
4253 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
4254                                       struct ecore_chain *p_chain)
4255 {
4256         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
4257         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4258         struct ecore_chain_next *p_next;
4259         u32 size, i;
4260
4261         if (!p_virt)
4262                 return;
4263
4264         size = p_chain->elem_size * p_chain->usable_per_page;
4265
4266         for (i = 0; i < p_chain->page_cnt; i++) {
4267                 if (!p_virt)
4268                         break;
4269
4270                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
4271                 p_virt_next = p_next->next_virt;
4272                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4273
4274                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
4275                                        ECORE_CHAIN_PAGE_SIZE);
4276
4277                 p_virt = p_virt_next;
4278                 p_phys = p_phys_next;
4279         }
4280 }
4281
4282 static void ecore_chain_free_single(struct ecore_dev *p_dev,
4283                                     struct ecore_chain *p_chain)
4284 {
4285         if (!p_chain->p_virt_addr)
4286                 return;
4287
4288         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
4289                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
4290 }
4291
4292 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
4293                                  struct ecore_chain *p_chain)
4294 {
4295         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4296         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
4297         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4298
4299         if (!pp_virt_addr_tbl)
4300                 return;
4301
4302         if (!p_pbl_virt)
4303                 goto out;
4304
4305         for (i = 0; i < page_cnt; i++) {
4306                 if (!pp_virt_addr_tbl[i])
4307                         break;
4308
4309                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
4310                                        *(dma_addr_t *)p_pbl_virt,
4311                                        ECORE_CHAIN_PAGE_SIZE);
4312
4313                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4314         }
4315
4316         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4317
4318         if (!p_chain->b_external_pbl)
4319                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
4320                                        p_chain->pbl_sp.p_phys_table, pbl_size);
4321 out:
4322         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
4323 }
4324
4325 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4326 {
4327         switch (p_chain->mode) {
4328         case ECORE_CHAIN_MODE_NEXT_PTR:
4329                 ecore_chain_free_next_ptr(p_dev, p_chain);
4330                 break;
4331         case ECORE_CHAIN_MODE_SINGLE:
4332                 ecore_chain_free_single(p_dev, p_chain);
4333                 break;
4334         case ECORE_CHAIN_MODE_PBL:
4335                 ecore_chain_free_pbl(p_dev, p_chain);
4336                 break;
4337         }
4338 }
4339
4340 static enum _ecore_status_t
4341 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
4342                                enum ecore_chain_cnt_type cnt_type,
4343                                osal_size_t elem_size, u32 page_cnt)
4344 {
4345         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4346
4347         /* The actual chain size can be larger than the maximal possible value
4348          * after rounding up the requested elements number to pages, and after
4349          * taking into acount the unusuable elements (next-ptr elements).
4350          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4351          * size/capacity fields are of a u32 type.
4352          */
4353         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
4354              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
4355             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
4356              chain_size > ECORE_U32_MAX)) {
4357                 DP_NOTICE(p_dev, true,
4358                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
4359                           (unsigned long)chain_size);
4360                 return ECORE_INVAL;
4361         }
4362
4363         return ECORE_SUCCESS;
4364 }
4365
4366 static enum _ecore_status_t
4367 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4368 {
4369         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
4370         dma_addr_t p_phys = 0;
4371         u32 i;
4372
4373         for (i = 0; i < p_chain->page_cnt; i++) {
4374                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4375                                                  ECORE_CHAIN_PAGE_SIZE);
4376                 if (!p_virt) {
4377                         DP_NOTICE(p_dev, true,
4378                                   "Failed to allocate chain memory\n");
4379                         return ECORE_NOMEM;
4380                 }
4381
4382                 if (i == 0) {
4383                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4384                         ecore_chain_reset(p_chain);
4385                 } else {
4386                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4387                                                        p_virt, p_phys);
4388                 }
4389
4390                 p_virt_prev = p_virt;
4391         }
4392         /* Last page's next element should point to the beginning of the
4393          * chain.
4394          */
4395         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4396                                        p_chain->p_virt_addr,
4397                                        p_chain->p_phys_addr);
4398
4399         return ECORE_SUCCESS;
4400 }
4401
4402 static enum _ecore_status_t
4403 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
4404 {
4405         dma_addr_t p_phys = 0;
4406         void *p_virt = OSAL_NULL;
4407
4408         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
4409         if (!p_virt) {
4410                 DP_NOTICE(p_dev, true, "Failed to allocate chain memory\n");
4411                 return ECORE_NOMEM;
4412         }
4413
4414         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4415         ecore_chain_reset(p_chain);
4416
4417         return ECORE_SUCCESS;
4418 }
4419
4420 static enum _ecore_status_t
4421 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
4422                       struct ecore_chain *p_chain,
4423                       struct ecore_chain_ext_pbl *ext_pbl)
4424 {
4425         u32 page_cnt = p_chain->page_cnt, size, i;
4426         dma_addr_t p_phys = 0, p_pbl_phys = 0;
4427         void **pp_virt_addr_tbl = OSAL_NULL;
4428         u8 *p_pbl_virt = OSAL_NULL;
4429         void *p_virt = OSAL_NULL;
4430
4431         size = page_cnt * sizeof(*pp_virt_addr_tbl);
4432         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
4433         if (!pp_virt_addr_tbl) {
4434                 DP_NOTICE(p_dev, true,
4435                           "Failed to allocate memory for the chain virtual addresses table\n");
4436                 return ECORE_NOMEM;
4437         }
4438
4439         /* The allocation of the PBL table is done with its full size, since it
4440          * is expected to be successive.
4441          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
4442          * failure, since pp_virt_addr_tbl was previously allocated, and it
4443          * should be saved to allow its freeing during the error flow.
4444          */
4445         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
4446
4447         if (ext_pbl == OSAL_NULL) {
4448                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
4449         } else {
4450                 p_pbl_virt = ext_pbl->p_pbl_virt;
4451                 p_pbl_phys = ext_pbl->p_pbl_phys;
4452                 p_chain->b_external_pbl = true;
4453         }
4454
4455         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4456                                  pp_virt_addr_tbl);
4457         if (!p_pbl_virt) {
4458                 DP_NOTICE(p_dev, true, "Failed to allocate chain pbl memory\n");
4459                 return ECORE_NOMEM;
4460         }
4461
4462         for (i = 0; i < page_cnt; i++) {
4463                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
4464                                                  ECORE_CHAIN_PAGE_SIZE);
4465                 if (!p_virt) {
4466                         DP_NOTICE(p_dev, true,
4467                                   "Failed to allocate chain memory\n");
4468                         return ECORE_NOMEM;
4469                 }
4470
4471                 if (i == 0) {
4472                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
4473                         ecore_chain_reset(p_chain);
4474                 }
4475
4476                 /* Fill the PBL table with the physical address of the page */
4477                 *(dma_addr_t *)p_pbl_virt = p_phys;
4478                 /* Keep the virtual address of the page */
4479                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4480
4481                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
4482         }
4483
4484         return ECORE_SUCCESS;
4485 }
4486
4487 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
4488                                        enum ecore_chain_use_mode intended_use,
4489                                        enum ecore_chain_mode mode,
4490                                        enum ecore_chain_cnt_type cnt_type,
4491                                        u32 num_elems, osal_size_t elem_size,
4492                                        struct ecore_chain *p_chain,
4493                                        struct ecore_chain_ext_pbl *ext_pbl)
4494 {
4495         u32 page_cnt;
4496         enum _ecore_status_t rc = ECORE_SUCCESS;
4497
4498         if (mode == ECORE_CHAIN_MODE_SINGLE)
4499                 page_cnt = 1;
4500         else
4501                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4502
4503         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
4504                                             page_cnt);
4505         if (rc) {
4506                 DP_NOTICE(p_dev, true,
4507                           "Cannot allocate a chain with the given arguments:\n"
4508                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4509                           intended_use, mode, cnt_type, num_elems, elem_size);
4510                 return rc;
4511         }
4512
4513         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
4514                                 mode, cnt_type, p_dev->dp_ctx);
4515
4516         switch (mode) {
4517         case ECORE_CHAIN_MODE_NEXT_PTR:
4518                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
4519                 break;
4520         case ECORE_CHAIN_MODE_SINGLE:
4521                 rc = ecore_chain_alloc_single(p_dev, p_chain);
4522                 break;
4523         case ECORE_CHAIN_MODE_PBL:
4524                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
4525                 break;
4526         }
4527         if (rc)
4528                 goto nomem;
4529
4530         return ECORE_SUCCESS;
4531
4532 nomem:
4533         ecore_chain_free(p_dev, p_chain);
4534         return rc;
4535 }
4536
4537 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
4538                                        u16 src_id, u16 *dst_id)
4539 {
4540         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
4541                 u16 min, max;
4542
4543                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
4544                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
4545                 DP_NOTICE(p_hwfn, true,
4546                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4547                           src_id, min, max);
4548
4549                 return ECORE_INVAL;
4550         }
4551
4552         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
4553
4554         return ECORE_SUCCESS;
4555 }
4556
4557 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
4558                                     u8 src_id, u8 *dst_id)
4559 {
4560         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
4561                 u8 min, max;
4562
4563                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
4564                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
4565                 DP_NOTICE(p_hwfn, true,
4566                           "vport id [%d] is not valid, available indices [%d - %d]\n",
4567                           src_id, min, max);
4568
4569                 return ECORE_INVAL;
4570         }
4571
4572         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
4573
4574         return ECORE_SUCCESS;
4575 }
4576
4577 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
4578                                       u8 src_id, u8 *dst_id)
4579 {
4580         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
4581                 u8 min, max;
4582
4583                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
4584                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
4585                 DP_NOTICE(p_hwfn, true,
4586                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4587                           src_id, min, max);
4588
4589                 return ECORE_INVAL;
4590         }
4591
4592         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
4593
4594         return ECORE_SUCCESS;
4595 }
4596
4597 static enum _ecore_status_t
4598 ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4599                                struct ecore_ptt *p_ptt, u32 high, u32 low,
4600                                u32 *p_entry_num)
4601 {
4602         u32 en;
4603         int i;
4604
4605         /* Find a free entry and utilize it */
4606         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4607                 en = ecore_rd(p_hwfn, p_ptt,
4608                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4609                               i * sizeof(u32));
4610                 if (en)
4611                         continue;
4612                 ecore_wr(p_hwfn, p_ptt,
4613                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4614                          2 * i * sizeof(u32), low);
4615                 ecore_wr(p_hwfn, p_ptt,
4616                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4617                          (2 * i + 1) * sizeof(u32), high);
4618                 ecore_wr(p_hwfn, p_ptt,
4619                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4620                          i * sizeof(u32), 0);
4621                 ecore_wr(p_hwfn, p_ptt,
4622                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4623                          i * sizeof(u32), 0);
4624                 ecore_wr(p_hwfn, p_ptt,
4625                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4626                          i * sizeof(u32), 1);
4627                 break;
4628         }
4629
4630         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4631                 return ECORE_NORESOURCES;
4632
4633         *p_entry_num = i;
4634
4635         return ECORE_SUCCESS;
4636 }
4637
4638 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
4639                                           struct ecore_ptt *p_ptt, u8 *p_filter)
4640 {
4641         u32 high, low, entry_num;
4642         enum _ecore_status_t rc = ECORE_SUCCESS;
4643
4644         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4645                            &p_hwfn->p_dev->mf_bits))
4646                 return ECORE_SUCCESS;
4647
4648         high = p_filter[1] | (p_filter[0] << 8);
4649         low = p_filter[5] | (p_filter[4] << 8) |
4650               (p_filter[3] << 16) | (p_filter[2] << 24);
4651
4652         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4653                 rc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,
4654                                                     &entry_num);
4655         if (rc != ECORE_SUCCESS) {
4656                 DP_NOTICE(p_hwfn, false,
4657                           "Failed to find an empty LLH filter to utilize\n");
4658                 return rc;
4659         }
4660
4661         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4662                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\n",
4663                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4664                    p_filter[4], p_filter[5], entry_num);
4665
4666         return rc;
4667 }
4668
4669 static enum _ecore_status_t
4670 ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4671                                   struct ecore_ptt *p_ptt, u32 high, u32 low,
4672                                   u32 *p_entry_num)
4673 {
4674         int i;
4675
4676         /* Find the entry and clean it */
4677         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4678                 if (ecore_rd(p_hwfn, p_ptt,
4679                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4680                              2 * i * sizeof(u32)) != low)
4681                         continue;
4682                 if (ecore_rd(p_hwfn, p_ptt,
4683                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4684                              (2 * i + 1) * sizeof(u32)) != high)
4685                         continue;
4686
4687                 ecore_wr(p_hwfn, p_ptt,
4688                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4689                 ecore_wr(p_hwfn, p_ptt,
4690                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4691                          2 * i * sizeof(u32), 0);
4692                 ecore_wr(p_hwfn, p_ptt,
4693                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4694                          (2 * i + 1) * sizeof(u32), 0);
4695                 break;
4696         }
4697
4698         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4699                 return ECORE_INVAL;
4700
4701         *p_entry_num = i;
4702
4703         return ECORE_SUCCESS;
4704 }
4705
4706 void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
4707                              struct ecore_ptt *p_ptt, u8 *p_filter)
4708 {
4709         u32 high, low, entry_num;
4710         enum _ecore_status_t rc = ECORE_SUCCESS;
4711
4712         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
4713                            &p_hwfn->p_dev->mf_bits))
4714                 return;
4715
4716         high = p_filter[1] | (p_filter[0] << 8);
4717         low = p_filter[5] | (p_filter[4] << 8) |
4718               (p_filter[3] << 16) | (p_filter[2] << 24);
4719
4720         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4721                 rc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,
4722                                                        low, &entry_num);
4723         if (rc != ECORE_SUCCESS) {
4724                 DP_NOTICE(p_hwfn, false,
4725                           "Tried to remove a non-configured filter\n");
4726                 return;
4727         }
4728
4729
4730         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4731                    "MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\n",
4732                    p_filter[0], p_filter[1], p_filter[2], p_filter[3],
4733                    p_filter[4], p_filter[5], entry_num);
4734 }
4735
4736 static enum _ecore_status_t
4737 ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4738                                     struct ecore_ptt *p_ptt,
4739                                     enum ecore_llh_port_filter_type_t type,
4740                                     u32 high, u32 low, u32 *p_entry_num)
4741 {
4742         u32 en;
4743         int i;
4744
4745         /* Find a free entry and utilize it */
4746         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4747                 en = ecore_rd(p_hwfn, p_ptt,
4748                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4749                               i * sizeof(u32));
4750                 if (en)
4751                         continue;
4752                 ecore_wr(p_hwfn, p_ptt,
4753                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4754                          2 * i * sizeof(u32), low);
4755                 ecore_wr(p_hwfn, p_ptt,
4756                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4757                          (2 * i + 1) * sizeof(u32), high);
4758                 ecore_wr(p_hwfn, p_ptt,
4759                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4760                          i * sizeof(u32), 1);
4761                 ecore_wr(p_hwfn, p_ptt,
4762                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4763                          i * sizeof(u32), 1 << type);
4764                 ecore_wr(p_hwfn, p_ptt,
4765                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);
4766                 break;
4767         }
4768
4769         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4770                 return ECORE_NORESOURCES;
4771
4772         *p_entry_num = i;
4773
4774         return ECORE_SUCCESS;
4775 }
4776
4777 enum _ecore_status_t
4778 ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
4779                               struct ecore_ptt *p_ptt,
4780                               u16 source_port_or_eth_type,
4781                               u16 dest_port,
4782                               enum ecore_llh_port_filter_type_t type)
4783 {
4784         u32 high, low, entry_num;
4785         enum _ecore_status_t rc = ECORE_SUCCESS;
4786
4787         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4788                            &p_hwfn->p_dev->mf_bits))
4789                 return rc;
4790
4791         high = 0;
4792         low = 0;
4793
4794         switch (type) {
4795         case ECORE_LLH_FILTER_ETHERTYPE:
4796                 high = source_port_or_eth_type;
4797                 break;
4798         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4799         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4800                 low = source_port_or_eth_type << 16;
4801                 break;
4802         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4803         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4804                 low = dest_port;
4805                 break;
4806         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4807         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4808                 low = (source_port_or_eth_type << 16) | dest_port;
4809                 break;
4810         default:
4811                 DP_NOTICE(p_hwfn, true,
4812                           "Non valid LLH protocol filter type %d\n", type);
4813                 return ECORE_INVAL;
4814         }
4815
4816         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4817                 rc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4818                                                          high, low, &entry_num);
4819         if (rc != ECORE_SUCCESS) {
4820                 DP_NOTICE(p_hwfn, false,
4821                           "Failed to find an empty LLH filter to utilize\n");
4822                 return rc;
4823         }
4824         switch (type) {
4825         case ECORE_LLH_FILTER_ETHERTYPE:
4826                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4827                            "ETH type %x is added at %d\n",
4828                            source_port_or_eth_type, entry_num);
4829                 break;
4830         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4831                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4832                            "TCP src port %x is added at %d\n",
4833                            source_port_or_eth_type, entry_num);
4834                 break;
4835         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4836                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4837                            "UDP src port %x is added at %d\n",
4838                            source_port_or_eth_type, entry_num);
4839                 break;
4840         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4841                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4842                            "TCP dst port %x is added at %d\n", dest_port,
4843                            entry_num);
4844                 break;
4845         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4846                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4847                            "UDP dst port %x is added at %d\n", dest_port,
4848                            entry_num);
4849                 break;
4850         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4851                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4852                            "TCP src/dst ports %x/%x are added at %d\n",
4853                            source_port_or_eth_type, dest_port, entry_num);
4854                 break;
4855         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4856                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4857                            "UDP src/dst ports %x/%x are added at %d\n",
4858                            source_port_or_eth_type, dest_port, entry_num);
4859                 break;
4860         }
4861
4862         return rc;
4863 }
4864
4865 static enum _ecore_status_t
4866 ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,
4867                                        struct ecore_ptt *p_ptt,
4868                                        enum ecore_llh_port_filter_type_t type,
4869                                        u32 high, u32 low, u32 *p_entry_num)
4870 {
4871         int i;
4872
4873         /* Find the entry and clean it */
4874         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4875                 if (!ecore_rd(p_hwfn, p_ptt,
4876                               NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +
4877                               i * sizeof(u32)))
4878                         continue;
4879                 if (!ecore_rd(p_hwfn, p_ptt,
4880                               NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4881                               i * sizeof(u32)))
4882                         continue;
4883                 if (!(ecore_rd(p_hwfn, p_ptt,
4884                                NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4885                                i * sizeof(u32)) & (1 << type)))
4886                         continue;
4887                 if (ecore_rd(p_hwfn, p_ptt,
4888                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4889                              2 * i * sizeof(u32)) != low)
4890                         continue;
4891                 if (ecore_rd(p_hwfn, p_ptt,
4892                              NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4893                              (2 * i + 1) * sizeof(u32)) != high)
4894                         continue;
4895
4896                 ecore_wr(p_hwfn, p_ptt,
4897                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);
4898                 ecore_wr(p_hwfn, p_ptt,
4899                          NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +
4900                          i * sizeof(u32), 0);
4901                 ecore_wr(p_hwfn, p_ptt,
4902                          NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +
4903                          i * sizeof(u32), 0);
4904                 ecore_wr(p_hwfn, p_ptt,
4905                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4906                          2 * i * sizeof(u32), 0);
4907                 ecore_wr(p_hwfn, p_ptt,
4908                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4909                          (2 * i + 1) * sizeof(u32), 0);
4910                 break;
4911         }
4912
4913         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
4914                 return ECORE_INVAL;
4915
4916         *p_entry_num = i;
4917
4918         return ECORE_SUCCESS;
4919 }
4920
4921 void
4922 ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
4923                                  struct ecore_ptt *p_ptt,
4924                                  u16 source_port_or_eth_type,
4925                                  u16 dest_port,
4926                                  enum ecore_llh_port_filter_type_t type)
4927 {
4928         u32 high, low, entry_num;
4929         enum _ecore_status_t rc = ECORE_SUCCESS;
4930
4931         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
4932                            &p_hwfn->p_dev->mf_bits))
4933                 return;
4934
4935         high = 0;
4936         low = 0;
4937
4938         switch (type) {
4939         case ECORE_LLH_FILTER_ETHERTYPE:
4940                 high = source_port_or_eth_type;
4941                 break;
4942         case ECORE_LLH_FILTER_TCP_SRC_PORT:
4943         case ECORE_LLH_FILTER_UDP_SRC_PORT:
4944                 low = source_port_or_eth_type << 16;
4945                 break;
4946         case ECORE_LLH_FILTER_TCP_DEST_PORT:
4947         case ECORE_LLH_FILTER_UDP_DEST_PORT:
4948                 low = dest_port;
4949                 break;
4950         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
4951         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
4952                 low = (source_port_or_eth_type << 16) | dest_port;
4953                 break;
4954         default:
4955                 DP_NOTICE(p_hwfn, true,
4956                           "Non valid LLH protocol filter type %d\n", type);
4957                 return;
4958         }
4959
4960         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
4961                 rc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,
4962                                                             high, low,
4963                                                             &entry_num);
4964         if (rc != ECORE_SUCCESS) {
4965                 DP_NOTICE(p_hwfn, false,
4966                           "Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\n",
4967                           type, source_port_or_eth_type, dest_port);
4968                 return;
4969         }
4970
4971         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
4972                    "Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\n",
4973                    type, source_port_or_eth_type, dest_port, entry_num);
4974 }
4975
4976 static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,
4977                                               struct ecore_ptt *p_ptt)
4978 {
4979         int i;
4980
4981         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
4982                 return;
4983
4984         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
4985                 ecore_wr(p_hwfn, p_ptt,
4986                          NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +
4987                          i * sizeof(u32), 0);
4988                 ecore_wr(p_hwfn, p_ptt,
4989                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4990                          2 * i * sizeof(u32), 0);
4991                 ecore_wr(p_hwfn, p_ptt,
4992                          NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +
4993                          (2 * i + 1) * sizeof(u32), 0);
4994         }
4995 }
4996
4997 void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
4998                              struct ecore_ptt *p_ptt)
4999 {
5000         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,
5001                            &p_hwfn->p_dev->mf_bits) &&
5002             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,
5003                            &p_hwfn->p_dev->mf_bits))
5004                 return;
5005
5006         if (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))
5007                 ecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);
5008 }
5009
5010 enum _ecore_status_t
5011 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
5012                                   struct ecore_ptt *p_ptt)
5013 {
5014         if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
5015                 ecore_wr(p_hwfn, p_ptt,
5016                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
5017                          1 << p_hwfn->abs_pf_id / 2);
5018                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
5019                 return ECORE_SUCCESS;
5020         }
5021
5022         DP_NOTICE(p_hwfn, false,
5023                   "This function can't be set as default\n");
5024         return ECORE_INVAL;
5025 }
5026
5027 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
5028                                                struct ecore_ptt *p_ptt,
5029                                                u32 hw_addr, void *p_eth_qzone,
5030                                                osal_size_t eth_qzone_size,
5031                                                u8 timeset)
5032 {
5033         struct coalescing_timeset *p_coal_timeset;
5034
5035         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
5036                 DP_NOTICE(p_hwfn, true,
5037                           "Coalescing configuration not enabled\n");
5038                 return ECORE_INVAL;
5039         }
5040
5041         p_coal_timeset = p_eth_qzone;
5042         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
5043         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5044         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5045         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5046
5047         return ECORE_SUCCESS;
5048 }
5049
5050 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
5051                                               u16 rx_coal, u16 tx_coal,
5052                                               void *p_handle)
5053 {
5054         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
5055         enum _ecore_status_t rc = ECORE_SUCCESS;
5056         struct ecore_ptt *p_ptt;
5057
5058         /* TODO - Configuring a single queue's coalescing but
5059          * claiming all queues are abiding same configuration
5060          * for PF and VF both.
5061          */
5062
5063         if (IS_VF(p_hwfn->p_dev))
5064                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
5065                                                 tx_coal, p_cid);
5066
5067         p_ptt = ecore_ptt_acquire(p_hwfn);
5068         if (!p_ptt)
5069                 return ECORE_AGAIN;
5070
5071         if (rx_coal) {
5072                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5073                 if (rc)
5074                         goto out;
5075                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
5076         }
5077
5078         if (tx_coal) {
5079                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5080                 if (rc)
5081                         goto out;
5082                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
5083         }
5084 out:
5085         ecore_ptt_release(p_hwfn, p_ptt);
5086
5087         return rc;
5088 }
5089
5090 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
5091                                             struct ecore_ptt *p_ptt,
5092                                             u16 coalesce,
5093                                             struct ecore_queue_cid *p_cid)
5094 {
5095         struct ustorm_eth_queue_zone eth_qzone;
5096         u8 timeset, timer_res;
5097         u32 address;
5098         enum _ecore_status_t rc;
5099
5100         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5101         if (coalesce <= 0x7F) {
5102                 timer_res = 0;
5103         } else if (coalesce <= 0xFF) {
5104                 timer_res = 1;
5105         } else if (coalesce <= 0x1FF) {
5106                 timer_res = 2;
5107         } else {
5108                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5109                 return ECORE_INVAL;
5110         }
5111         timeset = (u8)(coalesce >> timer_res);
5112
5113         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5114                                      p_cid->sb_igu_id, false);
5115         if (rc != ECORE_SUCCESS)
5116                 goto out;
5117
5118         address = BAR0_MAP_REG_USDM_RAM +
5119                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5120
5121         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5122                                 sizeof(struct ustorm_eth_queue_zone), timeset);
5123         if (rc != ECORE_SUCCESS)
5124                 goto out;
5125
5126 out:
5127         return rc;
5128 }
5129
5130 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
5131                                             struct ecore_ptt *p_ptt,
5132                                             u16 coalesce,
5133                                             struct ecore_queue_cid *p_cid)
5134 {
5135         struct xstorm_eth_queue_zone eth_qzone;
5136         u8 timeset, timer_res;
5137         u32 address;
5138         enum _ecore_status_t rc;
5139
5140         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5141         if (coalesce <= 0x7F) {
5142                 timer_res = 0;
5143         } else if (coalesce <= 0xFF) {
5144                 timer_res = 1;
5145         } else if (coalesce <= 0x1FF) {
5146                 timer_res = 2;
5147         } else {
5148                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5149                 return ECORE_INVAL;
5150         }
5151
5152         timeset = (u8)(coalesce >> timer_res);
5153
5154         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5155                                      p_cid->sb_igu_id, true);
5156         if (rc != ECORE_SUCCESS)
5157                 goto out;
5158
5159         address = BAR0_MAP_REG_XSDM_RAM +
5160                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5161
5162         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
5163                                 sizeof(struct xstorm_eth_queue_zone), timeset);
5164 out:
5165         return rc;
5166 }
5167
5168 /* Calculate final WFQ values for all vports and configure it.
5169  * After this configuration each vport must have
5170  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
5171  */
5172 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5173                                                struct ecore_ptt *p_ptt,
5174                                                u32 min_pf_rate)
5175 {
5176         struct init_qm_vport_params *vport_params;
5177         int i;
5178
5179         vport_params = p_hwfn->qm_info.qm_vport_params;
5180
5181         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5182                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5183
5184                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
5185                     min_pf_rate;
5186                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5187                                      vport_params[i].first_tx_pq_id,
5188                                      vport_params[i].vport_wfq);
5189         }
5190 }
5191
5192 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
5193 {
5194         int i;
5195
5196         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5197                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
5198 }
5199
5200 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
5201                                              struct ecore_ptt *p_ptt)
5202 {
5203         struct init_qm_vport_params *vport_params;
5204         int i;
5205
5206         vport_params = p_hwfn->qm_info.qm_vport_params;
5207
5208         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5209                 ecore_init_wfq_default_param(p_hwfn);
5210                 ecore_init_vport_wfq(p_hwfn, p_ptt,
5211                                      vport_params[i].first_tx_pq_id,
5212                                      vport_params[i].vport_wfq);
5213         }
5214 }
5215
5216 /* This function performs several validations for WFQ
5217  * configuration and required min rate for a given vport
5218  * 1. req_rate must be greater than one percent of min_pf_rate.
5219  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5220  *    rates to get less than one percent of min_pf_rate.
5221  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5222  */
5223 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
5224                                                  u16 vport_id, u32 req_rate,
5225                                                  u32 min_pf_rate)
5226 {
5227         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5228         int non_requested_count = 0, req_count = 0, i, num_vports;
5229
5230         num_vports = p_hwfn->qm_info.num_vports;
5231
5232 /* Accounting for the vports which are configured for WFQ explicitly */
5233
5234         for (i = 0; i < num_vports; i++) {
5235                 u32 tmp_speed;
5236
5237                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
5238                         req_count++;
5239                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5240                         total_req_min_rate += tmp_speed;
5241                 }
5242         }
5243
5244         /* Include current vport data as well */
5245         req_count++;
5246         total_req_min_rate += req_rate;
5247         non_requested_count = num_vports - req_count;
5248
5249         /* validate possible error cases */
5250         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
5251                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5252                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5253                            vport_id, req_rate, min_pf_rate);
5254                 return ECORE_INVAL;
5255         }
5256
5257         /* TBD - for number of vports greater than 100 */
5258         if (num_vports > ECORE_WFQ_UNIT) {
5259                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5260                            "Number of vports is greater than %d\n",
5261                            ECORE_WFQ_UNIT);
5262                 return ECORE_INVAL;
5263         }
5264
5265         if (total_req_min_rate > min_pf_rate) {
5266                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5267                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5268                            total_req_min_rate, min_pf_rate);
5269                 return ECORE_INVAL;
5270         }
5271
5272         /* Data left for non requested vports */
5273         total_left_rate = min_pf_rate - total_req_min_rate;
5274         left_rate_per_vp = total_left_rate / non_requested_count;
5275
5276         /* validate if non requested get < 1% of min bw */
5277         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
5278                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5279                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5280                            left_rate_per_vp, min_pf_rate);
5281                 return ECORE_INVAL;
5282         }
5283
5284         /* now req_rate for given vport passes all scenarios.
5285          * assign final wfq rates to all vports.
5286          */
5287         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5288         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5289
5290         for (i = 0; i < num_vports; i++) {
5291                 if (p_hwfn->qm_info.wfq_data[i].configured)
5292                         continue;
5293
5294                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5295         }
5296
5297         return ECORE_SUCCESS;
5298 }
5299
5300 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
5301                                        struct ecore_ptt *p_ptt,
5302                                        u16 vp_id, u32 rate)
5303 {
5304         struct ecore_mcp_link_state *p_link;
5305         int rc = ECORE_SUCCESS;
5306
5307         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
5308
5309         if (!p_link->min_pf_rate) {
5310                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5311                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5312                 return rc;
5313         }
5314
5315         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5316
5317         if (rc == ECORE_SUCCESS)
5318                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5319                                                    p_link->min_pf_rate);
5320         else
5321                 DP_NOTICE(p_hwfn, false,
5322                           "Validation failed while configuring min rate\n");
5323
5324         return rc;
5325 }
5326
5327 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
5328                                                    struct ecore_ptt *p_ptt,
5329                                                    u32 min_pf_rate)
5330 {
5331         bool use_wfq = false;
5332         int rc = ECORE_SUCCESS;
5333         u16 i;
5334
5335         /* Validate all pre configured vports for wfq */
5336         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5337                 u32 rate;
5338
5339                 if (!p_hwfn->qm_info.wfq_data[i].configured)
5340                         continue;
5341
5342                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5343                 use_wfq = true;
5344
5345                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5346                 if (rc != ECORE_SUCCESS) {
5347                         DP_NOTICE(p_hwfn, false,
5348                                   "WFQ validation failed while configuring min rate\n");
5349                         break;
5350                 }
5351         }
5352
5353         if (rc == ECORE_SUCCESS && use_wfq)
5354                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5355         else
5356                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5357
5358         return rc;
5359 }
5360
5361 /* Main API for ecore clients to configure vport min rate.
5362  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5363  * rate - Speed in Mbps needs to be assigned to a given vport.
5364  */
5365 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
5366 {
5367         int i, rc = ECORE_INVAL;
5368
5369         /* TBD - for multiple hardware functions - that is 100 gig */
5370         if (ECORE_IS_CMT(p_dev)) {
5371                 DP_NOTICE(p_dev, false,
5372                           "WFQ configuration is not supported for this device\n");
5373                 return rc;
5374         }
5375
5376         for_each_hwfn(p_dev, i) {
5377                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5378                 struct ecore_ptt *p_ptt;
5379
5380                 p_ptt = ecore_ptt_acquire(p_hwfn);
5381                 if (!p_ptt)
5382                         return ECORE_TIMEOUT;
5383
5384                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5385
5386                 if (rc != ECORE_SUCCESS) {
5387                         ecore_ptt_release(p_hwfn, p_ptt);
5388                         return rc;
5389                 }
5390
5391                 ecore_ptt_release(p_hwfn, p_ptt);
5392         }
5393
5394         return rc;
5395 }
5396
5397 /* API to configure WFQ from mcp link change */
5398 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
5399                                            struct ecore_ptt *p_ptt,
5400                                            u32 min_pf_rate)
5401 {
5402         int i;
5403
5404         /* TBD - for multiple hardware functions - that is 100 gig */
5405         if (ECORE_IS_CMT(p_dev)) {
5406                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
5407                            "WFQ configuration is not supported for this device\n");
5408                 return;
5409         }
5410
5411         for_each_hwfn(p_dev, i) {
5412                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5413
5414                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5415                                                         min_pf_rate);
5416         }
5417 }
5418
5419 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
5420                                        struct ecore_ptt *p_ptt,
5421                                        struct ecore_mcp_link_state *p_link,
5422                                        u8 max_bw)
5423 {
5424         int rc = ECORE_SUCCESS;
5425
5426         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5427
5428         if (!p_link->line_speed && (max_bw != 100))
5429                 return rc;
5430
5431         p_link->speed = (p_link->line_speed * max_bw) / 100;
5432         p_hwfn->qm_info.pf_rl = p_link->speed;
5433
5434         /* Since the limiter also affects Tx-switched traffic, we don't want it
5435          * to limit such traffic in case there's no actual limit.
5436          * In that case, set limit to imaginary high boundary.
5437          */
5438         if (max_bw == 100)
5439                 p_hwfn->qm_info.pf_rl = 100000;
5440
5441         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5442                               p_hwfn->qm_info.pf_rl);
5443
5444         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5445                    "Configured MAX bandwidth to be %08x Mb/sec\n",
5446                    p_link->speed);
5447
5448         return rc;
5449 }
5450
5451 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5452 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
5453 {
5454         int i, rc = ECORE_INVAL;
5455
5456         if (max_bw < 1 || max_bw > 100) {
5457                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
5458                 return rc;
5459         }
5460
5461         for_each_hwfn(p_dev, i) {
5462                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5463                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5464                 struct ecore_mcp_link_state *p_link;
5465                 struct ecore_ptt *p_ptt;
5466
5467                 p_link = &p_lead->mcp_info->link_output;
5468
5469                 p_ptt = ecore_ptt_acquire(p_hwfn);
5470                 if (!p_ptt)
5471                         return ECORE_TIMEOUT;
5472
5473                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5474                                                         p_link, max_bw);
5475
5476                 ecore_ptt_release(p_hwfn, p_ptt);
5477
5478                 if (rc != ECORE_SUCCESS)
5479                         break;
5480         }
5481
5482         return rc;
5483 }
5484
5485 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
5486                                        struct ecore_ptt *p_ptt,
5487                                        struct ecore_mcp_link_state *p_link,
5488                                        u8 min_bw)
5489 {
5490         int rc = ECORE_SUCCESS;
5491
5492         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5493         p_hwfn->qm_info.pf_wfq = min_bw;
5494
5495         if (!p_link->line_speed)
5496                 return rc;
5497
5498         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5499
5500         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5501
5502         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
5503                    "Configured MIN bandwidth to be %d Mb/sec\n",
5504                    p_link->min_pf_rate);
5505
5506         return rc;
5507 }
5508
5509 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5510 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
5511 {
5512         int i, rc = ECORE_INVAL;
5513
5514         if (min_bw < 1 || min_bw > 100) {
5515                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
5516                 return rc;
5517         }
5518
5519         for_each_hwfn(p_dev, i) {
5520                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5521                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
5522                 struct ecore_mcp_link_state *p_link;
5523                 struct ecore_ptt *p_ptt;
5524
5525                 p_link = &p_lead->mcp_info->link_output;
5526
5527                 p_ptt = ecore_ptt_acquire(p_hwfn);
5528                 if (!p_ptt)
5529                         return ECORE_TIMEOUT;
5530
5531                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5532                                                         p_link, min_bw);
5533                 if (rc != ECORE_SUCCESS) {
5534                         ecore_ptt_release(p_hwfn, p_ptt);
5535                         return rc;
5536                 }
5537
5538                 if (p_link->min_pf_rate) {
5539                         u32 min_rate = p_link->min_pf_rate;
5540
5541                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
5542                                                                      p_ptt,
5543                                                                      min_rate);
5544                 }
5545
5546                 ecore_ptt_release(p_hwfn, p_ptt);
5547         }
5548
5549         return rc;
5550 }
5551
5552 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
5553 {
5554         struct ecore_mcp_link_state *p_link;
5555
5556         p_link = &p_hwfn->mcp_info->link_output;
5557
5558         if (p_link->min_pf_rate)
5559                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
5560
5561         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
5562                     sizeof(*p_hwfn->qm_info.wfq_data) *
5563                     p_hwfn->qm_info.num_vports);
5564 }
5565
5566 int ecore_device_num_engines(struct ecore_dev *p_dev)
5567 {
5568         return ECORE_IS_BB(p_dev) ? 2 : 1;
5569 }
5570
5571 int ecore_device_num_ports(struct ecore_dev *p_dev)
5572 {
5573         return p_dev->num_ports;
5574 }
5575
5576 void ecore_set_fw_mac_addr(__le16 *fw_msb,
5577                           __le16 *fw_mid,
5578                           __le16 *fw_lsb,
5579                           u8 *mac)
5580 {
5581         ((u8 *)fw_msb)[0] = mac[1];
5582         ((u8 *)fw_msb)[1] = mac[0];
5583         ((u8 *)fw_mid)[0] = mac[3];
5584         ((u8 *)fw_mid)[1] = mac[2];
5585         ((u8 *)fw_lsb)[0] = mac[5];
5586         ((u8 *)fw_lsb)[1] = mac[4];
5587 }