drivers/net/qede/base/ecore_dev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "bcm_osal.h"
   8 #include "reg_addr.h"
   9 #include "ecore_gtt_reg_addr.h"
  10 #include "ecore.h"
  11 #include "ecore_chain.h"
  12 #include "ecore_status.h"
  13 #include "ecore_hw.h"
  14 #include "ecore_rt_defs.h"
  15 #include "ecore_init_ops.h"
  16 #include "ecore_int.h"
  17 #include "ecore_cxt.h"
  18 #include "ecore_spq.h"
  19 #include "ecore_init_fw_funcs.h"
  20 #include "ecore_sp_commands.h"
  21 #include "ecore_dev_api.h"
  22 #include "ecore_sriov.h"
  23 #include "ecore_vf.h"
  24 #include "ecore_mcp.h"
  25 #include "ecore_hw_defs.h"
  26 #include "mcp_public.h"
  27 #include "ecore_iro.h"
  28 #include "nvm_cfg.h"
  29 #include "ecore_dcbx.h"
  30 #include "ecore_l2.h"
  31
  32 /* TODO - there's a bug in DCBx re-configuration flows in MF, as the QM
  33  * registers involved are not split and thus configuration is a race where
  34  * some of the PFs configuration might be lost.
  35  * Eventually, this needs to move into a MFW-covered HW-lock as arbitration
  36  * mechanism as this doesn't cover some cases [E.g., PDA or scenarios where
  37  * there's more than a single compiled ecore component in system].
  38  */
  39 static osal_spinlock_t qm_lock;
  40 static u32 qm_lock_ref_cnt;
  41
  42 /******************** Doorbell Recovery *******************/
  43 /* The doorbell recovery mechanism consists of a list of entries which represent
  44  * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
  45  * entity needs to register with the mechanism and provide the parameters
  46  * describing it's doorbell, including a location where last used doorbell data
  47  * can be found. The doorbell execute function will traverse the list and
  48  * doorbell all of the registered entries.
  49  */
  50 struct ecore_db_recovery_entry {
  51         osal_list_entry_t       list_entry;
  52         void OSAL_IOMEM         *db_addr;
  53         void                    *db_data;
  54         enum ecore_db_rec_width db_width;
  55         enum ecore_db_rec_space db_space;
  56         u8                      hwfn_idx;
  57 };
  58
  59 /* display a single doorbell recovery entry */
  60 void ecore_db_recovery_dp_entry(struct ecore_hwfn *p_hwfn,
  61                                 struct ecore_db_recovery_entry *db_entry,
  62                                 const char *action)
  63 {
  64         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
  65                    action, db_entry, db_entry->db_addr, db_entry->db_data,
  66                    db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
  67                    db_entry->db_space == DB_REC_USER ? "user" : "kernel",
  68                    db_entry->hwfn_idx);
  69 }
  70
  71 /* doorbell address sanity (address within doorbell bar range) */
  72 bool ecore_db_rec_sanity(struct ecore_dev *p_dev, void OSAL_IOMEM *db_addr,
  73                          void *db_data)
  74 {
  75         /* make sure doorbell address  is within the doorbell bar */
  76         if (db_addr < p_dev->doorbells || (u8 *)db_addr >
  77                         (u8 *)p_dev->doorbells + p_dev->db_size) {
  78                 OSAL_WARN(true,
  79                           "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
  80                           db_addr, p_dev->doorbells,
  81                           (u8 *)p_dev->doorbells + p_dev->db_size);
  82                 return false;
  83         }
  84
  85         /* make sure doorbell data pointer is not null */
  86         if (!db_data) {
  87                 OSAL_WARN(true, "Illegal doorbell data pointer: %p", db_data);
  88                 return false;
  89         }
  90
  91         return true;
  92 }
  93
  94 /* find hwfn according to the doorbell address */
  95 struct ecore_hwfn *ecore_db_rec_find_hwfn(struct ecore_dev *p_dev,
  96                                           void OSAL_IOMEM *db_addr)
  97 {
  98         struct ecore_hwfn *p_hwfn;
  99
 100         /* In CMT doorbell bar is split down the middle between engine 0 and
 101          * enigne 1
 102          */
 103         if (ECORE_IS_CMT(p_dev))
 104                 p_hwfn = db_addr < p_dev->hwfns[1].doorbells ?
 105                         &p_dev->hwfns[0] : &p_dev->hwfns[1];
 106         else
 107                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
 108
 109         return p_hwfn;
 110 }
 111
 112 /* add a new entry to the doorbell recovery mechanism */
 113 enum _ecore_status_t ecore_db_recovery_add(struct ecore_dev *p_dev,
 114                                            void OSAL_IOMEM *db_addr,
 115                                            void *db_data,
 116                                            enum ecore_db_rec_width db_width,
 117                                            enum ecore_db_rec_space db_space)
 118 {
 119         struct ecore_db_recovery_entry *db_entry;
 120         struct ecore_hwfn *p_hwfn;
 121
 122         /* shortcircuit VFs, for now */
 123         if (IS_VF(p_dev)) {
 124                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 125                 return ECORE_SUCCESS;
 126         }
 127
 128         /* sanitize doorbell address */
 129         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 130                 return ECORE_INVAL;
 131
 132         /* obtain hwfn from doorbell address */
 133         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 134
 135         /* create entry */
 136         db_entry = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*db_entry));
 137         if (!db_entry) {
 138                 DP_NOTICE(p_dev, false, "Failed to allocate a db recovery entry\n");
 139                 return ECORE_NOMEM;
 140         }
 141
 142         /* populate entry */
 143         db_entry->db_addr = db_addr;
 144         db_entry->db_data = db_data;
 145         db_entry->db_width = db_width;
 146         db_entry->db_space = db_space;
 147         db_entry->hwfn_idx = p_hwfn->my_id;
 148
 149         /* display */
 150         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
 151
 152         /* protect the list */
 153         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 154         OSAL_LIST_PUSH_TAIL(&db_entry->list_entry,
 155                             &p_hwfn->db_recovery_info.list);
 156         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 157
 158         return ECORE_SUCCESS;
 159 }
 160
 161 /* remove an entry from the doorbell recovery mechanism */
 162 enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
 163                                            void OSAL_IOMEM *db_addr,
 164                                            void *db_data)
 165 {
 166         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 167         enum _ecore_status_t rc = ECORE_INVAL;
 168         struct ecore_hwfn *p_hwfn;
 169
 170         /* shortcircuit VFs, for now */
 171         if (IS_VF(p_dev)) {
 172                 DP_VERBOSE(p_dev, ECORE_MSG_IOV, "db recovery - skipping VF doorbell\n");
 173                 return ECORE_SUCCESS;
 174         }
 175
 176         /* sanitize doorbell address */
 177         if (!ecore_db_rec_sanity(p_dev, db_addr, db_data))
 178                 return ECORE_INVAL;
 179
 180         /* obtain hwfn from doorbell address */
 181         p_hwfn = ecore_db_rec_find_hwfn(p_dev, db_addr);
 182
 183         /* protect the list */
 184         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 185         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 186                                  &p_hwfn->db_recovery_info.list,
 187                                  list_entry,
 188                                  struct ecore_db_recovery_entry) {
 189                 /* search according to db_data addr since db_addr is not unique
 190                  * (roce)
 191                  */
 192                 if (db_entry->db_data == db_data) {
 193                         ecore_db_recovery_dp_entry(p_hwfn, db_entry,
 194                                                    "Deleting");
 195                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 196                                                &p_hwfn->db_recovery_info.list);
 197                         rc = ECORE_SUCCESS;
 198                         break;
 199                 }
 200         }
 201
 202         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 203
 204         if (rc == ECORE_INVAL)
 205                 /*OSAL_WARN(true,*/
 206                 DP_NOTICE(p_hwfn, false,
 207                           "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
 208                           db_data, db_addr);
 209         else
 210                 OSAL_FREE(p_dev, db_entry);
 211
 212         return rc;
 213 }
 214
 215 /* initialize the doorbell recovery mechanism */
 216 enum _ecore_status_t ecore_db_recovery_setup(struct ecore_hwfn *p_hwfn)
 217 {
 218         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Setting up db recovery\n");
 219
 220         /* make sure db_size was set in p_dev */
 221         if (!p_hwfn->p_dev->db_size) {
 222                 DP_ERR(p_hwfn->p_dev, "db_size not set\n");
 223                 return ECORE_INVAL;
 224         }
 225
 226         OSAL_LIST_INIT(&p_hwfn->db_recovery_info.list);
 227 #ifdef CONFIG_ECORE_LOCK_ALLOC
 228         if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->db_recovery_info.lock))
 229                 return ECORE_NOMEM;
 230 #endif
 231         OSAL_SPIN_LOCK_INIT(&p_hwfn->db_recovery_info.lock);
 232         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 233
 234         return ECORE_SUCCESS;
 235 }
 236
 237 /* destroy the doorbell recovery mechanism */
 238 void ecore_db_recovery_teardown(struct ecore_hwfn *p_hwfn)
 239 {
 240         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 241
 242         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "Tearing down db recovery\n");
 243         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 244                 DP_VERBOSE(p_hwfn, false, "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
 245                 while (!OSAL_LIST_IS_EMPTY(&p_hwfn->db_recovery_info.list)) {
 246                         db_entry = OSAL_LIST_FIRST_ENTRY(
 247                                                 &p_hwfn->db_recovery_info.list,
 248                                                 struct ecore_db_recovery_entry,
 249                                                 list_entry);
 250                         ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
 251                         OSAL_LIST_REMOVE_ENTRY(&db_entry->list_entry,
 252                                                &p_hwfn->db_recovery_info.list);
 253                         OSAL_FREE(p_hwfn->p_dev, db_entry);
 254                 }
 255         }
 256 #ifdef CONFIG_ECORE_LOCK_ALLOC
 257         OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->db_recovery_info.lock);
 258 #endif
 259         p_hwfn->db_recovery_info.db_recovery_counter = 0;
 260 }
 261
 262 /* print the content of the doorbell recovery mechanism */
 263 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn)
 264 {
 265         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 266
 267         DP_NOTICE(p_hwfn, false,
 268                   "Dispalying doorbell recovery database. Counter was %d\n",
 269                   p_hwfn->db_recovery_info.db_recovery_counter);
 270
 271         /* protect the list */
 272         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 273         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 274                                  &p_hwfn->db_recovery_info.list,
 275                                  list_entry,
 276                                  struct ecore_db_recovery_entry) {
 277                 ecore_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
 278         }
 279
 280         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 281 }
 282
 283 /* ring the doorbell of a single doorbell recovery entry */
 284 void ecore_db_recovery_ring(struct ecore_hwfn *p_hwfn,
 285                             struct ecore_db_recovery_entry *db_entry,
 286                             enum ecore_db_rec_exec db_exec)
 287 {
 288         /* Print according to width */
 289         if (db_entry->db_width == DB_REC_WIDTH_32B)
 290                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %x\n",
 291                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 292                            db_entry->db_addr, *(u32 *)db_entry->db_data);
 293         else
 294                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "%s doorbell address %p data %lx\n",
 295                            db_exec == DB_REC_DRY_RUN ? "would have rung" : "ringing",
 296                            db_entry->db_addr,
 297                            *(unsigned long *)(db_entry->db_data));
 298
 299         /* Sanity */
 300         if (!ecore_db_rec_sanity(p_hwfn->p_dev, db_entry->db_addr,
 301                                  db_entry->db_data))
 302                 return;
 303
 304         /* Flush the write combined buffer. Since there are multiple doorbelling
 305          * entities using the same address, if we don't flush, a transaction
 306          * could be lost.
 307          */
 308         OSAL_WMB(p_hwfn->p_dev);
 309
 310         /* Ring the doorbell */
 311         if (db_exec == DB_REC_REAL_DEAL || db_exec == DB_REC_ONCE) {
 312                 if (db_entry->db_width == DB_REC_WIDTH_32B)
 313                         DIRECT_REG_WR(p_hwfn, db_entry->db_addr,
 314                                       *(u32 *)(db_entry->db_data));
 315                 else
 316                         DIRECT_REG_WR64(p_hwfn, db_entry->db_addr,
 317                                         *(u64 *)(db_entry->db_data));
 318         }
 319
 320         /* Flush the write combined buffer. Next doorbell may come from a
 321          * different entity to the same address...
 322          */
 323         OSAL_WMB(p_hwfn->p_dev);
 324 }
 325
 326 /* traverse the doorbell recovery entry list and ring all the doorbells */
 327 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
 328                                enum ecore_db_rec_exec db_exec)
 329 {
 330         struct ecore_db_recovery_entry *db_entry = OSAL_NULL;
 331
 332         if (db_exec != DB_REC_ONCE) {
 333                 DP_NOTICE(p_hwfn, false, "Executing doorbell recovery. Counter was %d\n",
 334                           p_hwfn->db_recovery_info.db_recovery_counter);
 335
 336                 /* track amount of times recovery was executed */
 337                 p_hwfn->db_recovery_info.db_recovery_counter++;
 338         }
 339
 340         /* protect the list */
 341         OSAL_SPIN_LOCK(&p_hwfn->db_recovery_info.lock);
 342         OSAL_LIST_FOR_EACH_ENTRY(db_entry,
 343                                  &p_hwfn->db_recovery_info.list,
 344                                  list_entry,
 345                                  struct ecore_db_recovery_entry) {
 346                 ecore_db_recovery_ring(p_hwfn, db_entry, db_exec);
 347                 if (db_exec == DB_REC_ONCE)
 348                         break;
 349         }
 350
 351         OSAL_SPIN_UNLOCK(&p_hwfn->db_recovery_info.lock);
 352 }
 353 /******************** Doorbell Recovery end ****************/
 354
 355 /********************************** NIG LLH ***********************************/
 356
 357 enum ecore_llh_filter_type {
 358         ECORE_LLH_FILTER_TYPE_MAC,
 359         ECORE_LLH_FILTER_TYPE_PROTOCOL,
 360 };
 361
 362 struct ecore_llh_mac_filter {
 363         u8 addr[ETH_ALEN];
 364 };
 365
 366 struct ecore_llh_protocol_filter {
 367         enum ecore_llh_prot_filter_type_t type;
 368         u16 source_port_or_eth_type;
 369         u16 dest_port;
 370 };
 371
 372 union ecore_llh_filter {
 373         struct ecore_llh_mac_filter mac;
 374         struct ecore_llh_protocol_filter protocol;
 375 };
 376
 377 struct ecore_llh_filter_info {
 378         bool b_enabled;
 379         u32 ref_cnt;
 380         enum ecore_llh_filter_type type;
 381         union ecore_llh_filter filter;
 382 };
 383
 384 struct ecore_llh_info {
 385         /* Number of LLH filters banks */
 386         u8 num_ppfid;
 387
 388 #define MAX_NUM_PPFID   8
 389         u8 ppfid_array[MAX_NUM_PPFID];
 390
 391         /* Array of filters arrays:
 392          * "num_ppfid" elements of filters banks, where each is an array of
 393          * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
 394          */
 395         struct ecore_llh_filter_info **pp_filters;
 396 };
 397
 398 static void ecore_llh_free(struct ecore_dev *p_dev)
 399 {
 400         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 401         u32 i;
 402
 403         if (p_llh_info != OSAL_NULL) {
 404                 if (p_llh_info->pp_filters != OSAL_NULL) {
 405                         for (i = 0; i < p_llh_info->num_ppfid; i++)
 406                                 OSAL_FREE(p_dev, p_llh_info->pp_filters[i]);
 407                 }
 408
 409                 OSAL_FREE(p_dev, p_llh_info->pp_filters);
 410         }
 411
 412         OSAL_FREE(p_dev, p_llh_info);
 413         p_dev->p_llh_info = OSAL_NULL;
 414 }
 415
 416 static enum _ecore_status_t ecore_llh_alloc(struct ecore_dev *p_dev)
 417 {
 418         struct ecore_llh_info *p_llh_info;
 419         u32 size;
 420         u8 i;
 421
 422         p_llh_info = OSAL_ZALLOC(p_dev, GFP_KERNEL, sizeof(*p_llh_info));
 423         if (!p_llh_info)
 424                 return ECORE_NOMEM;
 425         p_dev->p_llh_info = p_llh_info;
 426
 427         for (i = 0; i < MAX_NUM_PPFID; i++) {
 428                 if (!(p_dev->ppfid_bitmap & (0x1 << i)))
 429                         continue;
 430
 431                 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
 432                 DP_VERBOSE(p_dev, ECORE_MSG_SP, "ppfid_array[%d] = %hhd\n",
 433                            p_llh_info->num_ppfid, i);
 434                 p_llh_info->num_ppfid++;
 435         }
 436
 437         size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
 438         p_llh_info->pp_filters = OSAL_ZALLOC(p_dev, GFP_KERNEL, size);
 439         if (!p_llh_info->pp_filters)
 440                 return ECORE_NOMEM;
 441
 442         size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
 443                sizeof(**p_llh_info->pp_filters);
 444         for (i = 0; i < p_llh_info->num_ppfid; i++) {
 445                 p_llh_info->pp_filters[i] = OSAL_ZALLOC(p_dev, GFP_KERNEL,
 446                                                         size);
 447                 if (!p_llh_info->pp_filters[i])
 448                         return ECORE_NOMEM;
 449         }
 450
 451         return ECORE_SUCCESS;
 452 }
 453
 454 static enum _ecore_status_t ecore_llh_shadow_sanity(struct ecore_dev *p_dev,
 455                                                     u8 ppfid, u8 filter_idx,
 456                                                     const char *action)
 457 {
 458         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 459
 460         if (ppfid >= p_llh_info->num_ppfid) {
 461                 DP_NOTICE(p_dev, false,
 462                           "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
 463                           action, ppfid, p_llh_info->num_ppfid);
 464                 return ECORE_INVAL;
 465         }
 466
 467         if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
 468                 DP_NOTICE(p_dev, false,
 469                           "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
 470                           action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
 471                 return ECORE_INVAL;
 472         }
 473
 474         return ECORE_SUCCESS;
 475 }
 476
 477 #define ECORE_LLH_INVALID_FILTER_IDX    0xff
 478
 479 static enum _ecore_status_t
 480 ecore_llh_shadow_search_filter(struct ecore_dev *p_dev, u8 ppfid,
 481                                union ecore_llh_filter *p_filter,
 482                                u8 *p_filter_idx)
 483 {
 484         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 485         struct ecore_llh_filter_info *p_filters;
 486         enum _ecore_status_t rc;
 487         u8 i;
 488
 489         rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "search");
 490         if (rc != ECORE_SUCCESS)
 491                 return rc;
 492
 493         *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
 494
 495         p_filters = p_llh_info->pp_filters[ppfid];
 496         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
 497                 if (!OSAL_MEMCMP(p_filter, &p_filters[i].filter,
 498                                  sizeof(*p_filter))) {
 499                         *p_filter_idx = i;
 500                         break;
 501                 }
 502         }
 503
 504         return ECORE_SUCCESS;
 505 }
 506
 507 static enum _ecore_status_t
 508 ecore_llh_shadow_get_free_idx(struct ecore_dev *p_dev, u8 ppfid,
 509                               u8 *p_filter_idx)
 510 {
 511         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 512         struct ecore_llh_filter_info *p_filters;
 513         enum _ecore_status_t rc;
 514         u8 i;
 515
 516         rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "get_free_idx");
 517         if (rc != ECORE_SUCCESS)
 518                 return rc;
 519
 520         *p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;
 521
 522         p_filters = p_llh_info->pp_filters[ppfid];
 523         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
 524                 if (!p_filters[i].b_enabled) {
 525                         *p_filter_idx = i;
 526                         break;
 527                 }
 528         }
 529
 530         return ECORE_SUCCESS;
 531 }
 532
 533 static enum _ecore_status_t
 534 __ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid, u8 filter_idx,
 535                               enum ecore_llh_filter_type type,
 536                               union ecore_llh_filter *p_filter, u32 *p_ref_cnt)
 537 {
 538         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 539         struct ecore_llh_filter_info *p_filters;
 540         enum _ecore_status_t rc;
 541
 542         rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "add");
 543         if (rc != ECORE_SUCCESS)
 544                 return rc;
 545
 546         p_filters = p_llh_info->pp_filters[ppfid];
 547         if (!p_filters[filter_idx].ref_cnt) {
 548                 p_filters[filter_idx].b_enabled = true;
 549                 p_filters[filter_idx].type = type;
 550                 OSAL_MEMCPY(&p_filters[filter_idx].filter, p_filter,
 551                             sizeof(p_filters[filter_idx].filter));
 552         }
 553
 554         *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
 555
 556         return ECORE_SUCCESS;
 557 }
 558
 559 static enum _ecore_status_t
 560 ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid,
 561                             enum ecore_llh_filter_type type,
 562                             union ecore_llh_filter *p_filter,
 563                             u8 *p_filter_idx, u32 *p_ref_cnt)
 564 {
 565         enum _ecore_status_t rc;
 566
 567         /* Check if the same filter already exist */
 568         rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
 569                                             p_filter_idx);
 570         if (rc != ECORE_SUCCESS)
 571                 return rc;
 572
 573         /* Find a new entry in case of a new filter */
 574         if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
 575                 rc = ecore_llh_shadow_get_free_idx(p_dev, ppfid, p_filter_idx);
 576                 if (rc != ECORE_SUCCESS)
 577                         return rc;
 578         }
 579
 580         /* No free entry was found */
 581         if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
 582                 DP_NOTICE(p_dev, false,
 583                           "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
 584                           ppfid);
 585                 return ECORE_NORESOURCES;
 586         }
 587
 588         return __ecore_llh_shadow_add_filter(p_dev, ppfid, *p_filter_idx, type,
 589                                              p_filter, p_ref_cnt);
 590 }
 591
 592 static enum _ecore_status_t
 593 __ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
 594                                  u8 filter_idx, u32 *p_ref_cnt)
 595 {
 596         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 597         struct ecore_llh_filter_info *p_filters;
 598         enum _ecore_status_t rc;
 599
 600         rc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, "remove");
 601         if (rc != ECORE_SUCCESS)
 602                 return rc;
 603
 604         p_filters = p_llh_info->pp_filters[ppfid];
 605         if (!p_filters[filter_idx].ref_cnt) {
 606                 DP_NOTICE(p_dev, false,
 607                           "LLH shadow: trying to remove a filter with ref_cnt=0\n");
 608                 return ECORE_INVAL;
 609         }
 610
 611         *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
 612         if (!p_filters[filter_idx].ref_cnt)
 613                 OSAL_MEM_ZERO(&p_filters[filter_idx],
 614                               sizeof(p_filters[filter_idx]));
 615
 616         return ECORE_SUCCESS;
 617 }
 618
 619 static enum _ecore_status_t
 620 ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,
 621                                union ecore_llh_filter *p_filter,
 622                                u8 *p_filter_idx, u32 *p_ref_cnt)
 623 {
 624         enum _ecore_status_t rc;
 625
 626         rc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,
 627                                             p_filter_idx);
 628         if (rc != ECORE_SUCCESS)
 629                 return rc;
 630
 631         /* No matching filter was found */
 632         if (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {
 633                 DP_NOTICE(p_dev, false,
 634                           "Failed to find a filter in the LLH shadow\n");
 635                 return ECORE_INVAL;
 636         }
 637
 638         return __ecore_llh_shadow_remove_filter(p_dev, ppfid, *p_filter_idx,
 639                                                 p_ref_cnt);
 640 }
 641
 642 static enum _ecore_status_t
 643 ecore_llh_shadow_remove_all_filters(struct ecore_dev *p_dev, u8 ppfid)
 644 {
 645         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 646         struct ecore_llh_filter_info *p_filters;
 647         enum _ecore_status_t rc;
 648
 649         rc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, "remove_all");
 650         if (rc != ECORE_SUCCESS)
 651                 return rc;
 652
 653         p_filters = p_llh_info->pp_filters[ppfid];
 654         OSAL_MEM_ZERO(p_filters,
 655                       NIG_REG_LLH_FUNC_FILTER_EN_SIZE * sizeof(*p_filters));
 656
 657         return ECORE_SUCCESS;
 658 }
 659
 660 static enum _ecore_status_t ecore_abs_ppfid(struct ecore_dev *p_dev,
 661                                             u8 rel_ppfid, u8 *p_abs_ppfid)
 662 {
 663         struct ecore_llh_info *p_llh_info = p_dev->p_llh_info;
 664         u8 ppfids = p_llh_info->num_ppfid - 1;
 665
 666         if (rel_ppfid >= p_llh_info->num_ppfid) {
 667                 DP_NOTICE(p_dev, false,
 668                           "rel_ppfid %d is not valid, available indices are 0..%hhd\n",
 669                           rel_ppfid, ppfids);
 670                 return ECORE_INVAL;
 671         }
 672
 673         *p_abs_ppfid = p_llh_info->ppfid_array[rel_ppfid];
 674
 675         return ECORE_SUCCESS;
 676 }
 677
 678 static enum _ecore_status_t
 679 __ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 680 {
 681         struct ecore_dev *p_dev = p_hwfn->p_dev;
 682         enum ecore_eng eng;
 683         u8 ppfid;
 684         enum _ecore_status_t rc;
 685
 686         rc = ecore_mcp_get_engine_config(p_hwfn, p_ptt);
 687         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
 688                 DP_NOTICE(p_hwfn, false,
 689                           "Failed to get the engine affinity configuration\n");
 690                 return rc;
 691         }
 692
 693         /* RoCE PF is bound to a single engine */
 694         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 695                 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
 696                 rc = ecore_llh_set_roce_affinity(p_dev, eng);
 697                 if (rc != ECORE_SUCCESS) {
 698                         DP_NOTICE(p_dev, false,
 699                                   "Failed to set the RoCE engine affinity\n");
 700                         return rc;
 701                 }
 702
 703                 DP_VERBOSE(p_dev, ECORE_MSG_SP,
 704                            "LLH: Set the engine affinity of RoCE packets as %d\n",
 705                            eng);
 706         }
 707
 708         /* Storage PF is bound to a single engine while L2 PF uses both */
 709         if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
 710             ECORE_IS_ISCSI_PERSONALITY(p_hwfn))
 711                 eng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;
 712         else /* L2_PERSONALITY */
 713                 eng = ECORE_BOTH_ENG;
 714
 715         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
 716                 rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
 717                 if (rc != ECORE_SUCCESS) {
 718                         DP_NOTICE(p_dev, false,
 719                                   "Failed to set the engine affinity of ppfid %d\n",
 720                                   ppfid);
 721                         return rc;
 722                 }
 723         }
 724
 725         DP_VERBOSE(p_dev, ECORE_MSG_SP,
 726                    "LLH: Set the engine affinity of non-RoCE packets as %d\n",
 727                    eng);
 728
 729         return ECORE_SUCCESS;
 730 }
 731
 732 static enum _ecore_status_t
 733 ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 734                            bool avoid_eng_affin)
 735 {
 736         struct ecore_dev *p_dev = p_hwfn->p_dev;
 737         enum _ecore_status_t rc;
 738
 739         /* Backwards compatible mode:
 740          * - RoCE packets     - Use engine 0.
 741          * - Non-RoCE packets - Use connection based classification for L2 PFs,
 742          *                      and engine 0 otherwise.
 743          */
 744         if (avoid_eng_affin) {
 745                 enum ecore_eng eng;
 746                 u8 ppfid;
 747
 748                 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
 749                         eng = ECORE_ENG0;
 750                         rc = ecore_llh_set_roce_affinity(p_dev, eng);
 751                         if (rc != ECORE_SUCCESS) {
 752                                 DP_NOTICE(p_dev, false,
 753                                           "Failed to set the RoCE engine affinity\n");
 754                                 return rc;
 755                         }
 756
 757                         DP_VERBOSE(p_dev, ECORE_MSG_SP,
 758                                    "LLH [backwards compatible mode]: Set the engine affinity of RoCE packets as %d\n",
 759                                    eng);
 760                 }
 761
 762                 eng = (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
 763                        ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) ? ECORE_ENG0
 764                                                            : ECORE_BOTH_ENG;
 765                 for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
 766                         rc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);
 767                         if (rc != ECORE_SUCCESS) {
 768                                 DP_NOTICE(p_dev, false,
 769                                           "Failed to set the engine affinity of ppfid %d\n",
 770                                           ppfid);
 771                                 return rc;
 772                         }
 773                 }
 774
 775                 DP_VERBOSE(p_dev, ECORE_MSG_SP,
 776                            "LLH [backwards compatible mode]: Set the engine affinity of non-RoCE packets as %d\n",
 777                            eng);
 778
 779                 return ECORE_SUCCESS;
 780         }
 781
 782         return __ecore_llh_set_engine_affin(p_hwfn, p_ptt);
 783 }
 784
 785 static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn,
 786                                                  struct ecore_ptt *p_ptt,
 787                                                  bool avoid_eng_affin)
 788 {
 789         struct ecore_dev *p_dev = p_hwfn->p_dev;
 790         u8 ppfid, abs_ppfid;
 791         enum _ecore_status_t rc;
 792
 793         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
 794                 u32 addr;
 795
 796                 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
 797                 if (rc != ECORE_SUCCESS)
 798                         return rc;
 799
 800                 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
 801                 ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
 802         }
 803
 804         if (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
 805             !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {
 806                 rc = ecore_llh_add_mac_filter(p_dev, 0,
 807                                               p_hwfn->hw_info.hw_mac_addr);
 808                 if (rc != ECORE_SUCCESS)
 809                         DP_NOTICE(p_dev, false,
 810                                   "Failed to add an LLH filter with the primary MAC\n");
 811         }
 812
 813         if (ECORE_IS_CMT(p_dev)) {
 814                 rc = ecore_llh_set_engine_affin(p_hwfn, p_ptt, avoid_eng_affin);
 815                 if (rc != ECORE_SUCCESS)
 816                         return rc;
 817         }
 818
 819         return ECORE_SUCCESS;
 820 }
 821
 822 u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev)
 823 {
 824         return p_dev->p_llh_info->num_ppfid;
 825 }
 826
 827 enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev)
 828 {
 829         return p_dev->l2_affin_hint ? ECORE_ENG1 : ECORE_ENG0;
 830 }
 831
 832 /* TBD - should be removed when these definitions are available in reg_addr.h */
 833 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK             0x3
 834 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT            0
 835 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK         0x3
 836 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT        2
 837
 838 enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev,
 839                                                   u8 ppfid, enum ecore_eng eng)
 840 {
 841         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
 842         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
 843         u32 addr, val, eng_sel;
 844         enum _ecore_status_t rc = ECORE_SUCCESS;
 845         u8 abs_ppfid;
 846
 847         if (p_ptt == OSAL_NULL)
 848                 return ECORE_AGAIN;
 849
 850         if (!ECORE_IS_CMT(p_dev))
 851                 goto out;
 852
 853         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
 854         if (rc != ECORE_SUCCESS)
 855                 goto out;
 856
 857         switch (eng) {
 858         case ECORE_ENG0:
 859                 eng_sel = 0;
 860                 break;
 861         case ECORE_ENG1:
 862                 eng_sel = 1;
 863                 break;
 864         case ECORE_BOTH_ENG:
 865                 eng_sel = 2;
 866                 break;
 867         default:
 868                 DP_NOTICE(p_dev, false,
 869                           "Invalid affinity value for ppfid [%d]\n", eng);
 870                 rc = ECORE_INVAL;
 871                 goto out;
 872         }
 873
 874         addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
 875         val = ecore_rd(p_hwfn, p_ptt, addr);
 876         SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
 877         ecore_wr(p_hwfn, p_ptt, addr, val);
 878
 879         /* The iWARP affinity is set as the affinity of ppfid 0 */
 880         if (!ppfid && ECORE_IS_IWARP_PERSONALITY(p_hwfn))
 881                 p_dev->iwarp_affin = (eng == ECORE_ENG1) ? 1 : 0;
 882 out:
 883         ecore_ptt_release(p_hwfn, p_ptt);
 884
 885         return rc;
 886 }
 887
 888 enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,
 889                                                  enum ecore_eng eng)
 890 {
 891         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
 892         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
 893         u32 addr, val, eng_sel;
 894         enum _ecore_status_t rc = ECORE_SUCCESS;
 895         u8 ppfid, abs_ppfid;
 896
 897         if (p_ptt == OSAL_NULL)
 898                 return ECORE_AGAIN;
 899
 900         if (!ECORE_IS_CMT(p_dev))
 901                 goto out;
 902
 903         switch (eng) {
 904         case ECORE_ENG0:
 905                 eng_sel = 0;
 906                 break;
 907         case ECORE_ENG1:
 908                 eng_sel = 1;
 909                 break;
 910         case ECORE_BOTH_ENG:
 911                 eng_sel = 2;
 912                 ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
 913                          0xf /* QP bit 15 */);
 914                 break;
 915         default:
 916                 DP_NOTICE(p_dev, false,
 917                           "Invalid affinity value for RoCE [%d]\n", eng);
 918                 rc = ECORE_INVAL;
 919                 goto out;
 920         }
 921
 922         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
 923                 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
 924                 if (rc != ECORE_SUCCESS)
 925                         goto out;
 926
 927                 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
 928                 val = ecore_rd(p_hwfn, p_ptt, addr);
 929                 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
 930                 ecore_wr(p_hwfn, p_ptt, addr, val);
 931         }
 932 out:
 933         ecore_ptt_release(p_hwfn, p_ptt);
 934
 935         return rc;
 936 }
 937
 938 struct ecore_llh_filter_e4_details {
 939         u64 value;
 940         u32 mode;
 941         u32 protocol_type;
 942         u32 hdr_sel;
 943         u32 enable;
 944 };
 945
 946 static enum _ecore_status_t
 947 ecore_llh_access_filter_e4(struct ecore_hwfn *p_hwfn,
 948                            struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx,
 949                            struct ecore_llh_filter_e4_details *p_details,
 950                            bool b_write_access)
 951 {
 952         u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
 953         struct ecore_dmae_params params;
 954         enum _ecore_status_t rc;
 955         u32 addr;
 956
 957         /* The NIG/LLH registers that are accessed in this function have only 16
 958          * rows which are exposed to a PF. I.e. only the 16 filters of its
 959          * default ppfid
 960          * Accessing filters of other ppfids requires pretending to other PFs,
 961          * and thus the usage of the ecore_ppfid_rd/wr() functions.
 962          */
 963
 964         /* Filter enable - should be done first when removing a filter */
 965         if (b_write_access && !p_details->enable) {
 966                 addr = NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + filter_idx * 0x4;
 967                 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
 968                                p_details->enable);
 969         }
 970
 971         /* Filter value */
 972         addr = NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 2 * filter_idx * 0x4;
 973         OSAL_MEMSET(&params, 0, sizeof(params));
 974
 975         if (b_write_access) {
 976                 params.flags = ECORE_DMAE_FLAG_PF_DST;
 977                 params.dst_pfid = pfid;
 978                 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
 979                                          (u64)(osal_uintptr_t)&p_details->value,
 980                                          addr, 2 /* size_in_dwords */, &params);
 981         } else {
 982                 params.flags = ECORE_DMAE_FLAG_PF_SRC |
 983                                ECORE_DMAE_FLAG_COMPLETION_DST;
 984                 params.src_pfid = pfid;
 985                 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, addr,
 986                                          (u64)(osal_uintptr_t)&p_details->value,
 987                                          2 /* size_in_dwords */, &params);
 988         }
 989
 990         if (rc != ECORE_SUCCESS)
 991                 return rc;
 992
 993         /* Filter mode */
 994         addr = NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + filter_idx * 0x4;
 995         if (b_write_access)
 996                 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, p_details->mode);
 997         else
 998                 p_details->mode = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
 999                                                  addr);
1000
1001         /* Filter protocol type */
1002         addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + filter_idx * 0x4;
1003         if (b_write_access)
1004                 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1005                                p_details->protocol_type);
1006         else
1007                 p_details->protocol_type = ecore_ppfid_rd(p_hwfn, p_ptt,
1008                                                           abs_ppfid, addr);
1009
1010         /* Filter header select */
1011         addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 + filter_idx * 0x4;
1012         if (b_write_access)
1013                 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1014                                p_details->hdr_sel);
1015         else
1016                 p_details->hdr_sel = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,
1017                                                     addr);
1018
1019         /* Filter enable - should be done last when adding a filter */
1020         if (!b_write_access || p_details->enable) {
1021                 addr = NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + filter_idx * 0x4;
1022                 if (b_write_access)
1023                         ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,
1024                                        p_details->enable);
1025                 else
1026                         p_details->enable = ecore_ppfid_rd(p_hwfn, p_ptt,
1027                                                            abs_ppfid, addr);
1028         }
1029
1030         return ECORE_SUCCESS;
1031 }
1032
1033 static enum _ecore_status_t
1034 ecore_llh_add_filter_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1035                         u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type,
1036                         u32 high, u32 low)
1037 {
1038         struct ecore_llh_filter_e4_details filter_details;
1039
1040         filter_details.enable = 1;
1041         filter_details.value = ((u64)high << 32) | low;
1042         filter_details.hdr_sel =
1043                 OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
1044                 1 : /* inner/encapsulated header */
1045                 0;  /* outer/tunnel header */
1046         filter_details.protocol_type = filter_prot_type;
1047         filter_details.mode = filter_prot_type ?
1048                               1 : /* protocol-based classification */
1049                               0;  /* MAC-address based classification */
1050
1051         return ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1052                                           &filter_details,
1053                                           true /* write access */);
1054 }
1055
1056 static enum _ecore_status_t
1057 ecore_llh_remove_filter_e4(struct ecore_hwfn *p_hwfn,
1058                            struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
1059 {
1060         struct ecore_llh_filter_e4_details filter_details;
1061
1062         OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1063
1064         return ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1065                                           &filter_details,
1066                                           true /* write access */);
1067 }
1068
1069 static enum _ecore_status_t
1070 ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1071                      u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type, u32 high,
1072                      u32 low)
1073 {
1074         return ecore_llh_add_filter_e4(p_hwfn, p_ptt, abs_ppfid,
1075                                        filter_idx, filter_prot_type,
1076                                        high, low);
1077 }
1078
1079 static enum _ecore_status_t
1080 ecore_llh_remove_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1081                         u8 abs_ppfid, u8 filter_idx)
1082 {
1083         return ecore_llh_remove_filter_e4(p_hwfn, p_ptt, abs_ppfid,
1084                                           filter_idx);
1085 }
1086
1087 enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1088                                               u8 mac_addr[ETH_ALEN])
1089 {
1090         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1091         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1092         union ecore_llh_filter filter;
1093         u8 filter_idx, abs_ppfid;
1094         u32 high, low, ref_cnt;
1095         enum _ecore_status_t rc = ECORE_SUCCESS;
1096
1097         if (p_ptt == OSAL_NULL)
1098                 return ECORE_AGAIN;
1099
1100         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1101                 goto out;
1102
1103         OSAL_MEM_ZERO(&filter, sizeof(filter));
1104         OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1105         rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1106                                          ECORE_LLH_FILTER_TYPE_MAC,
1107                                          &filter, &filter_idx, &ref_cnt);
1108         if (rc != ECORE_SUCCESS)
1109                 goto err;
1110
1111         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1112         if (rc != ECORE_SUCCESS)
1113                 goto err;
1114
1115         /* Configure the LLH only in case of a new the filter */
1116         if (ref_cnt == 1) {
1117                 high = mac_addr[1] | (mac_addr[0] << 8);
1118                 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1119                       (mac_addr[2] << 24);
1120                 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1121                                           0, high, low);
1122                 if (rc != ECORE_SUCCESS)
1123                         goto err;
1124         }
1125
1126         DP_VERBOSE(p_dev, ECORE_MSG_SP,
1127                    "LLH: Added MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1128                    mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1129                    mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1130                    ref_cnt);
1131
1132         goto out;
1133
1134 err:
1135         DP_NOTICE(p_dev, false,
1136                   "LLH: Failed to add MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd\n",
1137                   mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1138                   mac_addr[4], mac_addr[5], ppfid);
1139 out:
1140         ecore_ptt_release(p_hwfn, p_ptt);
1141
1142         return rc;
1143 }
1144
1145 static enum _ecore_status_t
1146 ecore_llh_protocol_filter_stringify(struct ecore_dev *p_dev,
1147                                     enum ecore_llh_prot_filter_type_t type,
1148                                     u16 source_port_or_eth_type, u16 dest_port,
1149                                     char *str, osal_size_t str_len)
1150 {
1151         switch (type) {
1152         case ECORE_LLH_FILTER_ETHERTYPE:
1153                 OSAL_SNPRINTF(str, str_len, "Ethertype 0x%04x",
1154                               source_port_or_eth_type);
1155                 break;
1156         case ECORE_LLH_FILTER_TCP_SRC_PORT:
1157                 OSAL_SNPRINTF(str, str_len, "TCP src port 0x%04x",
1158                               source_port_or_eth_type);
1159                 break;
1160         case ECORE_LLH_FILTER_UDP_SRC_PORT:
1161                 OSAL_SNPRINTF(str, str_len, "UDP src port 0x%04x",
1162                               source_port_or_eth_type);
1163                 break;
1164         case ECORE_LLH_FILTER_TCP_DEST_PORT:
1165                 OSAL_SNPRINTF(str, str_len, "TCP dst port 0x%04x", dest_port);
1166                 break;
1167         case ECORE_LLH_FILTER_UDP_DEST_PORT:
1168                 OSAL_SNPRINTF(str, str_len, "UDP dst port 0x%04x", dest_port);
1169                 break;
1170         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1171                 OSAL_SNPRINTF(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1172                               source_port_or_eth_type, dest_port);
1173                 break;
1174         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1175                 OSAL_SNPRINTF(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1176                               source_port_or_eth_type, dest_port);
1177                 break;
1178         default:
1179                 DP_NOTICE(p_dev, true,
1180                           "Non valid LLH protocol filter type %d\n", type);
1181                 return ECORE_INVAL;
1182         }
1183
1184         return ECORE_SUCCESS;
1185 }
1186
1187 static enum _ecore_status_t
1188 ecore_llh_protocol_filter_to_hilo(struct ecore_dev *p_dev,
1189                                   enum ecore_llh_prot_filter_type_t type,
1190                                   u16 source_port_or_eth_type, u16 dest_port,
1191                                   u32 *p_high, u32 *p_low)
1192 {
1193         *p_high = 0;
1194         *p_low = 0;
1195
1196         switch (type) {
1197         case ECORE_LLH_FILTER_ETHERTYPE:
1198                 *p_high = source_port_or_eth_type;
1199                 break;
1200         case ECORE_LLH_FILTER_TCP_SRC_PORT:
1201         case ECORE_LLH_FILTER_UDP_SRC_PORT:
1202                 *p_low = source_port_or_eth_type << 16;
1203                 break;
1204         case ECORE_LLH_FILTER_TCP_DEST_PORT:
1205         case ECORE_LLH_FILTER_UDP_DEST_PORT:
1206                 *p_low = dest_port;
1207                 break;
1208         case ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1209         case ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1210                 *p_low = (source_port_or_eth_type << 16) | dest_port;
1211                 break;
1212         default:
1213                 DP_NOTICE(p_dev, true,
1214                           "Non valid LLH protocol filter type %d\n", type);
1215                 return ECORE_INVAL;
1216         }
1217
1218         return ECORE_SUCCESS;
1219 }
1220
1221 enum _ecore_status_t
1222 ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1223                               enum ecore_llh_prot_filter_type_t type,
1224                               u16 source_port_or_eth_type, u16 dest_port)
1225 {
1226         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1227         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1228         u8 filter_idx, abs_ppfid, type_bitmap;
1229         char str[32];
1230         union ecore_llh_filter filter;
1231         u32 high, low, ref_cnt;
1232         enum _ecore_status_t rc = ECORE_SUCCESS;
1233
1234         if (p_ptt == OSAL_NULL)
1235                 return ECORE_AGAIN;
1236
1237         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1238                 goto out;
1239
1240         rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1241                                                  source_port_or_eth_type,
1242                                                  dest_port, str, sizeof(str));
1243         if (rc != ECORE_SUCCESS)
1244                 goto err;
1245
1246         OSAL_MEM_ZERO(&filter, sizeof(filter));
1247         filter.protocol.type = type;
1248         filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1249         filter.protocol.dest_port = dest_port;
1250         rc = ecore_llh_shadow_add_filter(p_dev, ppfid,
1251                                          ECORE_LLH_FILTER_TYPE_PROTOCOL,
1252                                          &filter, &filter_idx, &ref_cnt);
1253         if (rc != ECORE_SUCCESS)
1254                 goto err;
1255
1256         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1257         if (rc != ECORE_SUCCESS)
1258                 goto err;
1259
1260         /* Configure the LLH only in case of a new the filter */
1261         if (ref_cnt == 1) {
1262                 rc = ecore_llh_protocol_filter_to_hilo(p_dev, type,
1263                                                        source_port_or_eth_type,
1264                                                        dest_port, &high, &low);
1265                 if (rc != ECORE_SUCCESS)
1266                         goto err;
1267
1268                 type_bitmap = 0x1 << type;
1269                 rc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1270                                           type_bitmap, high, low);
1271                 if (rc != ECORE_SUCCESS)
1272                         goto err;
1273         }
1274
1275         DP_VERBOSE(p_dev, ECORE_MSG_SP,
1276                    "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1277                    str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1278
1279         goto out;
1280
1281 err:
1282         DP_NOTICE(p_hwfn, false,
1283                   "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1284                   str, ppfid);
1285 out:
1286         ecore_ptt_release(p_hwfn, p_ptt);
1287
1288         return rc;
1289 }
1290
1291 void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
1292                                  u8 mac_addr[ETH_ALEN])
1293 {
1294         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1295         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1296         union ecore_llh_filter filter;
1297         u8 filter_idx, abs_ppfid;
1298         enum _ecore_status_t rc = ECORE_SUCCESS;
1299         u32 ref_cnt;
1300
1301         if (p_ptt == OSAL_NULL)
1302                 return;
1303
1304         if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1305                 goto out;
1306
1307         OSAL_MEM_ZERO(&filter, sizeof(filter));
1308         OSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);
1309         rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1310                                             &ref_cnt);
1311         if (rc != ECORE_SUCCESS)
1312                 goto err;
1313
1314         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1315         if (rc != ECORE_SUCCESS)
1316                 goto err;
1317
1318         /* Remove from the LLH in case the filter is not in use */
1319         if (!ref_cnt) {
1320                 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1321                                              filter_idx);
1322                 if (rc != ECORE_SUCCESS)
1323                         goto err;
1324         }
1325
1326         DP_VERBOSE(p_dev, ECORE_MSG_SP,
1327                    "LLH: Removed MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1328                    mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1329                    mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,
1330                    ref_cnt);
1331
1332         goto out;
1333
1334 err:
1335         DP_NOTICE(p_dev, false,
1336                   "LLH: Failed to remove MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd\n",
1337                   mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],
1338                   mac_addr[4], mac_addr[5], ppfid);
1339 out:
1340         ecore_ptt_release(p_hwfn, p_ptt);
1341 }
1342
1343 void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
1344                                       enum ecore_llh_prot_filter_type_t type,
1345                                       u16 source_port_or_eth_type,
1346                                       u16 dest_port)
1347 {
1348         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1349         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1350         u8 filter_idx, abs_ppfid;
1351         char str[32];
1352         union ecore_llh_filter filter;
1353         enum _ecore_status_t rc = ECORE_SUCCESS;
1354         u32 ref_cnt;
1355
1356         if (p_ptt == OSAL_NULL)
1357                 return;
1358
1359         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
1360                 goto out;
1361
1362         rc = ecore_llh_protocol_filter_stringify(p_dev, type,
1363                                                  source_port_or_eth_type,
1364                                                  dest_port, str, sizeof(str));
1365         if (rc != ECORE_SUCCESS)
1366                 goto err;
1367
1368         OSAL_MEM_ZERO(&filter, sizeof(filter));
1369         filter.protocol.type = type;
1370         filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1371         filter.protocol.dest_port = dest_port;
1372         rc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,
1373                                             &ref_cnt);
1374         if (rc != ECORE_SUCCESS)
1375                 goto err;
1376
1377         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1378         if (rc != ECORE_SUCCESS)
1379                 goto err;
1380
1381         /* Remove from the LLH in case the filter is not in use */
1382         if (!ref_cnt) {
1383                 rc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1384                                              filter_idx);
1385                 if (rc != ECORE_SUCCESS)
1386                         goto err;
1387         }
1388
1389         DP_VERBOSE(p_dev, ECORE_MSG_SP,
1390                    "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1391                    str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1392
1393         goto out;
1394
1395 err:
1396         DP_NOTICE(p_dev, false,
1397                   "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1398                   str, ppfid);
1399 out:
1400         ecore_ptt_release(p_hwfn, p_ptt);
1401 }
1402
1403 void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid)
1404 {
1405         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1406         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1407         u8 filter_idx, abs_ppfid;
1408         enum _ecore_status_t rc = ECORE_SUCCESS;
1409
1410         if (p_ptt == OSAL_NULL)
1411                 return;
1412
1413         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1414             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1415                 goto out;
1416
1417         rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1418         if (rc != ECORE_SUCCESS)
1419                 goto out;
1420
1421         rc = ecore_llh_shadow_remove_all_filters(p_dev, ppfid);
1422         if (rc != ECORE_SUCCESS)
1423                 goto out;
1424
1425         for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1426              filter_idx++) {
1427                 rc = ecore_llh_remove_filter_e4(p_hwfn, p_ptt,
1428                                                 abs_ppfid, filter_idx);
1429                 if (rc != ECORE_SUCCESS)
1430                         goto out;
1431         }
1432 out:
1433         ecore_ptt_release(p_hwfn, p_ptt);
1434 }
1435
1436 void ecore_llh_clear_all_filters(struct ecore_dev *p_dev)
1437 {
1438         u8 ppfid;
1439
1440         if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
1441             !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
1442                 return;
1443
1444         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)
1445                 ecore_llh_clear_ppfid_filters(p_dev, ppfid);
1446 }
1447
1448 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
1449                                          struct ecore_ptt *p_ptt, u32 addr,
1450                                          u32 val)
1451 {
1452         struct ecore_dev *p_dev = p_hwfn->p_dev;
1453         u8 ppfid, abs_ppfid;
1454         enum _ecore_status_t rc;
1455
1456         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1457                 rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
1458                 if (rc != ECORE_SUCCESS)
1459                         return rc;
1460
1461                 ecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, val);
1462         }
1463
1464         return ECORE_SUCCESS;
1465 }
1466
1467 static enum _ecore_status_t
1468 ecore_llh_dump_ppfid_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1469                         u8 ppfid)
1470 {
1471         struct ecore_llh_filter_e4_details filter_details;
1472         u8 abs_ppfid, filter_idx;
1473         u32 addr;
1474         enum _ecore_status_t rc;
1475
1476         rc = ecore_abs_ppfid(p_hwfn->p_dev, ppfid, &abs_ppfid);
1477         if (rc != ECORE_SUCCESS)
1478                 return rc;
1479
1480         addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
1481         DP_NOTICE(p_hwfn, false,
1482                   "[rel_pf_id %hhd, ppfid={rel %hhd, abs %hhd}, engine_sel 0x%x]\n",
1483                   p_hwfn->rel_pf_id, ppfid, abs_ppfid,
1484                   ecore_rd(p_hwfn, p_ptt, addr));
1485
1486         for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
1487              filter_idx++) {
1488                 OSAL_MEMSET(&filter_details, 0, sizeof(filter_details));
1489                 rc =  ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid,
1490                                                  filter_idx, &filter_details,
1491                                                  false /* read access */);
1492                 if (rc != ECORE_SUCCESS)
1493                         return rc;
1494
1495                 DP_NOTICE(p_hwfn, false,
1496                           "filter %2hhd: enable %d, value 0x%016lx, mode %d, protocol_type 0x%x, hdr_sel 0x%x\n",
1497                           filter_idx, filter_details.enable,
1498                           (unsigned long)filter_details.value,
1499                           filter_details.mode,
1500                           filter_details.protocol_type, filter_details.hdr_sel);
1501         }
1502
1503         return ECORE_SUCCESS;
1504 }
1505
1506 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid)
1507 {
1508         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
1509         struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
1510         enum _ecore_status_t rc;
1511
1512         if (p_ptt == OSAL_NULL)
1513                 return ECORE_AGAIN;
1514
1515         rc = ecore_llh_dump_ppfid_e4(p_hwfn, p_ptt, ppfid);
1516
1517         ecore_ptt_release(p_hwfn, p_ptt);
1518
1519         return rc;
1520 }
1521
1522 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev)
1523 {
1524         u8 ppfid;
1525         enum _ecore_status_t rc;
1526
1527         for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {
1528                 rc = ecore_llh_dump_ppfid(p_dev, ppfid);
1529                 if (rc != ECORE_SUCCESS)
1530                         return rc;
1531         }
1532
1533         return ECORE_SUCCESS;
1534 }
1535
1536 /******************************* NIG LLH - End ********************************/
1537
1538 /* Configurable */
1539 #define ECORE_MIN_DPIS          (4)     /* The minimal num of DPIs required to
1540                                          * load the driver. The number was
1541                                          * arbitrarily set.
1542                                          */
1543
1544 /* Derived */
1545 #define ECORE_MIN_PWM_REGION    (ECORE_WID_SIZE * ECORE_MIN_DPIS)
1546
1547 static u32 ecore_hw_bar_size(struct ecore_hwfn *p_hwfn,
1548                              struct ecore_ptt *p_ptt,
1549                              enum BAR_ID bar_id)
1550 {
1551         u32 bar_reg = (bar_id == BAR_ID_0 ?
1552                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1553         u32 val;
1554
1555         if (IS_VF(p_hwfn->p_dev))
1556                 return ecore_vf_hw_bar_size(p_hwfn, bar_id);
1557
1558         val = ecore_rd(p_hwfn, p_ptt, bar_reg);
1559         if (val)
1560                 return 1 << (val + 15);
1561
1562         /* The above registers were updated in the past only in CMT mode. Since
1563          * they were found to be useful MFW started updating them from 8.7.7.0.
1564          * In older MFW versions they are set to 0 which means disabled.
1565          */
1566         if (ECORE_IS_CMT(p_hwfn->p_dev)) {
1567                 DP_INFO(p_hwfn,
1568                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1569                 val = BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1570         } else {
1571                 DP_INFO(p_hwfn,
1572                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1573                 val = 512 * 1024;
1574         }
1575
1576         return val;
1577 }
1578
1579 void ecore_init_dp(struct ecore_dev *p_dev,
1580                    u32 dp_module, u8 dp_level, void *dp_ctx)
1581 {
1582         u32 i;
1583
1584         p_dev->dp_level = dp_level;
1585         p_dev->dp_module = dp_module;
1586         p_dev->dp_ctx = dp_ctx;
1587         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1588                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1589
1590                 p_hwfn->dp_level = dp_level;
1591                 p_hwfn->dp_module = dp_module;
1592                 p_hwfn->dp_ctx = dp_ctx;
1593         }
1594 }
1595
1596 enum _ecore_status_t ecore_init_struct(struct ecore_dev *p_dev)
1597 {
1598         u8 i;
1599
1600         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1601                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1602
1603                 p_hwfn->p_dev = p_dev;
1604                 p_hwfn->my_id = i;
1605                 p_hwfn->b_active = false;
1606
1607 #ifdef CONFIG_ECORE_LOCK_ALLOC
1608                 if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_hwfn->dmae_info.lock))
1609                         goto handle_err;
1610 #endif
1611                 OSAL_SPIN_LOCK_INIT(&p_hwfn->dmae_info.lock);
1612         }
1613
1614         /* hwfn 0 is always active */
1615         p_dev->hwfns[0].b_active = true;
1616
1617         /* set the default cache alignment to 128 (may be overridden later) */
1618         p_dev->cache_shift = 7;
1619         return ECORE_SUCCESS;
1620 #ifdef CONFIG_ECORE_LOCK_ALLOC
1621 handle_err:
1622         while (--i) {
1623                 struct ecore_hwfn *p_hwfn = OSAL_NULL;
1624
1625                 p_hwfn = &p_dev->hwfns[i];
1626                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
1627         }
1628         return ECORE_NOMEM;
1629 #endif
1630 }
1631
1632 static void ecore_qm_info_free(struct ecore_hwfn *p_hwfn)
1633 {
1634         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1635
1636         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_pq_params);
1637         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_vport_params);
1638         OSAL_FREE(p_hwfn->p_dev, qm_info->qm_port_params);
1639         OSAL_FREE(p_hwfn->p_dev, qm_info->wfq_data);
1640 }
1641
1642 static void ecore_dbg_user_data_free(struct ecore_hwfn *p_hwfn)
1643 {
1644         OSAL_FREE(p_hwfn->p_dev, p_hwfn->dbg_user_info);
1645         p_hwfn->dbg_user_info = OSAL_NULL;
1646 }
1647
1648 void ecore_resc_free(struct ecore_dev *p_dev)
1649 {
1650         int i;
1651
1652         if (IS_VF(p_dev)) {
1653                 for_each_hwfn(p_dev, i)
1654                         ecore_l2_free(&p_dev->hwfns[i]);
1655                 return;
1656         }
1657
1658         OSAL_FREE(p_dev, p_dev->fw_data);
1659
1660         OSAL_FREE(p_dev, p_dev->reset_stats);
1661
1662         ecore_llh_free(p_dev);
1663
1664         for_each_hwfn(p_dev, i) {
1665                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1666
1667                 ecore_cxt_mngr_free(p_hwfn);
1668                 ecore_qm_info_free(p_hwfn);
1669                 ecore_spq_free(p_hwfn);
1670                 ecore_eq_free(p_hwfn);
1671                 ecore_consq_free(p_hwfn);
1672                 ecore_int_free(p_hwfn);
1673                 ecore_iov_free(p_hwfn);
1674                 ecore_l2_free(p_hwfn);
1675                 ecore_dmae_info_free(p_hwfn);
1676                 ecore_dcbx_info_free(p_hwfn);
1677                 ecore_dbg_user_data_free(p_hwfn);
1678                 /* @@@TBD Flush work-queue ? */
1679
1680                 /* destroy doorbell recovery mechanism */
1681                 ecore_db_recovery_teardown(p_hwfn);
1682         }
1683 }
1684
1685 /******************** QM initialization *******************/
1686
1687 /* bitmaps for indicating active traffic classes.
1688  * Special case for Arrowhead 4 port
1689  */
1690 /* 0..3 actualy used, 4 serves OOO, 7 serves high priority stuff (e.g. DCQCN) */
1691 #define ACTIVE_TCS_BMAP 0x9f
1692 /* 0..3 actually used, OOO and high priority stuff all use 3 */
1693 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1694
1695 /* determines the physical queue flags for a given PF. */
1696 static u32 ecore_get_pq_flags(struct ecore_hwfn *p_hwfn)
1697 {
1698         u32 flags;
1699
1700         /* common flags */
1701         flags = PQ_FLAGS_LB;
1702
1703         /* feature flags */
1704         if (IS_ECORE_SRIOV(p_hwfn->p_dev))
1705                 flags |= PQ_FLAGS_VFS;
1706         if (IS_ECORE_PACING(p_hwfn))
1707                 flags |= PQ_FLAGS_RLS;
1708
1709         /* protocol flags */
1710         switch (p_hwfn->hw_info.personality) {
1711         case ECORE_PCI_ETH:
1712                 if (!IS_ECORE_PACING(p_hwfn))
1713                         flags |= PQ_FLAGS_MCOS;
1714                 break;
1715         case ECORE_PCI_FCOE:
1716                 flags |= PQ_FLAGS_OFLD;
1717                 break;
1718         case ECORE_PCI_ISCSI:
1719                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1720                 break;
1721         case ECORE_PCI_ETH_ROCE:
1722                 flags |= PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1723                 if (!IS_ECORE_PACING(p_hwfn))
1724                         flags |= PQ_FLAGS_MCOS;
1725                 break;
1726         case ECORE_PCI_ETH_IWARP:
1727                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1728                 if (!IS_ECORE_PACING(p_hwfn))
1729                         flags |= PQ_FLAGS_MCOS;
1730                 break;
1731         default:
1732                 DP_ERR(p_hwfn, "unknown personality %d\n",
1733                        p_hwfn->hw_info.personality);
1734                 return 0;
1735         }
1736         return flags;
1737 }
1738
1739 /* Getters for resource amounts necessary for qm initialization */
1740 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn)
1741 {
1742         return p_hwfn->hw_info.num_hw_tc;
1743 }
1744
1745 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn)
1746 {
1747         return IS_ECORE_SRIOV(p_hwfn->p_dev) ?
1748                         p_hwfn->p_dev->p_iov_info->total_vfs : 0;
1749 }
1750
1751 #define NUM_DEFAULT_RLS 1
1752
1753 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
1754 {
1755         u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
1756
1757         /* num RLs can't exceed resource amount of rls or vports or the
1758          * dcqcn qps
1759          */
1760         num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
1761                                      RESC_NUM(p_hwfn, ECORE_VPORT));
1762
1763         /* make sure after we reserve the default and VF rls we'll have
1764          * something left
1765          */
1766         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) {
1767                 DP_NOTICE(p_hwfn, false,
1768                           "no rate limiters left for PF rate limiting"
1769                           " [num_pf_rls %d num_vfs %d]\n", num_pf_rls, num_vfs);
1770                 return 0;
1771         }
1772
1773         /* subtract rls necessary for VFs and one default one for the PF */
1774         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1775
1776         return num_pf_rls;
1777 }
1778
1779 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn)
1780 {
1781         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1782
1783         /* all pqs share the same vport (hence the 1 below), except for vfs
1784          * and pf_rl pqs
1785          */
1786         return (!!(PQ_FLAGS_RLS & pq_flags)) *
1787                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
1788                (!!(PQ_FLAGS_VFS & pq_flags)) *
1789                 ecore_init_qm_get_num_vfs(p_hwfn) + 1;
1790 }
1791
1792 /* calc amount of PQs according to the requested flags */
1793 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn)
1794 {
1795         u32 pq_flags = ecore_get_pq_flags(p_hwfn);
1796
1797         return (!!(PQ_FLAGS_RLS & pq_flags)) *
1798                 ecore_init_qm_get_num_pf_rls(p_hwfn) +
1799                (!!(PQ_FLAGS_MCOS & pq_flags)) *
1800                 ecore_init_qm_get_num_tcs(p_hwfn) +
1801                (!!(PQ_FLAGS_LB & pq_flags)) +
1802                (!!(PQ_FLAGS_OOO & pq_flags)) +
1803                (!!(PQ_FLAGS_ACK & pq_flags)) +
1804                (!!(PQ_FLAGS_OFLD & pq_flags)) +
1805                (!!(PQ_FLAGS_VFS & pq_flags)) *
1806                 ecore_init_qm_get_num_vfs(p_hwfn);
1807 }
1808
1809 /* initialize the top level QM params */
1810 static void ecore_init_qm_params(struct ecore_hwfn *p_hwfn)
1811 {
1812         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1813         bool four_port;
1814
1815         /* pq and vport bases for this PF */
1816         qm_info->start_pq = (u16)RESC_START(p_hwfn, ECORE_PQ);
1817         qm_info->start_vport = (u8)RESC_START(p_hwfn, ECORE_VPORT);
1818
1819         /* rate limiting and weighted fair queueing are always enabled */
1820         qm_info->vport_rl_en = 1;
1821         qm_info->vport_wfq_en = 1;
1822
1823         /* TC config is different for AH 4 port */
1824         four_port = p_hwfn->p_dev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1825
1826         /* in AH 4 port we have fewer TCs per port */
1827         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1828                                                      NUM_OF_PHYS_TCS;
1829
1830         /* unless MFW indicated otherwise, ooo_tc should be 3 for AH 4 port and
1831          * 4 otherwise
1832          */
1833         if (!qm_info->ooo_tc)
1834                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1835                                               DCBX_TCP_OOO_TC;
1836 }
1837
1838 /* initialize qm vport params */
1839 static void ecore_init_qm_vport_params(struct ecore_hwfn *p_hwfn)
1840 {
1841         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1842         u8 i;
1843
1844         /* all vports participate in weighted fair queueing */
1845         for (i = 0; i < ecore_init_qm_get_num_vports(p_hwfn); i++)
1846                 qm_info->qm_vport_params[i].vport_wfq = 1;
1847 }
1848
1849 /* initialize qm port params */
1850 static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
1851 {
1852         /* Initialize qm port parameters */
1853         u8 i, active_phys_tcs, num_ports = p_hwfn->p_dev->num_ports_in_engine;
1854
1855         /* indicate how ooo and high pri traffic is dealt with */
1856         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1857                 ACTIVE_TCS_BMAP_4PORT_K2 : ACTIVE_TCS_BMAP;
1858
1859         for (i = 0; i < num_ports; i++) {
1860                 struct init_qm_port_params *p_qm_port =
1861                         &p_hwfn->qm_info.qm_port_params[i];
1862
1863                 p_qm_port->active = 1;
1864                 p_qm_port->active_phys_tcs = active_phys_tcs;
1865                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
1866                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
1867         }
1868 }
1869
1870 /* Reset the params which must be reset for qm init. QM init may be called as
1871  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1872  * params may be affected by the init but would simply recalculate to the same
1873  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1874  * affected as these amounts stay the same.
1875  */
1876 static void ecore_init_qm_reset_params(struct ecore_hwfn *p_hwfn)
1877 {
1878         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1879
1880         qm_info->num_pqs = 0;
1881         qm_info->num_vports = 0;
1882         qm_info->num_pf_rls = 0;
1883         qm_info->num_vf_pqs = 0;
1884         qm_info->first_vf_pq = 0;
1885         qm_info->first_mcos_pq = 0;
1886         qm_info->first_rl_pq = 0;
1887 }
1888
1889 static void ecore_init_qm_advance_vport(struct ecore_hwfn *p_hwfn)
1890 {
1891         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1892
1893         qm_info->num_vports++;
1894
1895         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1896                 DP_ERR(p_hwfn,
1897                        "vport overflow! qm_info->num_vports %d,"
1898                        " qm_init_get_num_vports() %d\n",
1899                        qm_info->num_vports,
1900                        ecore_init_qm_get_num_vports(p_hwfn));
1901 }
1902
1903 /* initialize a single pq and manage qm_info resources accounting.
1904  * The pq_init_flags param determines whether the PQ is rate limited
1905  * (for VF or PF)
1906  * and whether a new vport is allocated to the pq or not (i.e. vport will be
1907  * shared)
1908  */
1909
1910 /* flags for pq init */
1911 #define PQ_INIT_SHARE_VPORT     (1 << 0)
1912 #define PQ_INIT_PF_RL           (1 << 1)
1913 #define PQ_INIT_VF_RL           (1 << 2)
1914
1915 /* defines for pq init */
1916 #define PQ_INIT_DEFAULT_WRR_GROUP       1
1917 #define PQ_INIT_DEFAULT_TC              0
1918 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
1919
1920 static void ecore_init_qm_pq(struct ecore_hwfn *p_hwfn,
1921                              struct ecore_qm_info *qm_info,
1922                              u8 tc, u32 pq_init_flags)
1923 {
1924         u16 pq_idx = qm_info->num_pqs, max_pq =
1925                                         ecore_init_qm_get_num_pqs(p_hwfn);
1926
1927         if (pq_idx > max_pq)
1928                 DP_ERR(p_hwfn,
1929                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1930
1931         /* init pq params */
1932         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1933         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1934                                                  qm_info->num_vports;
1935         qm_info->qm_pq_params[pq_idx].tc_id = tc;
1936         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1937         qm_info->qm_pq_params[pq_idx].rl_valid =
1938                 (pq_init_flags & PQ_INIT_PF_RL ||
1939                  pq_init_flags & PQ_INIT_VF_RL);
1940
1941         /* qm params accounting */
1942         qm_info->num_pqs++;
1943         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1944                 qm_info->num_vports++;
1945
1946         if (pq_init_flags & PQ_INIT_PF_RL)
1947                 qm_info->num_pf_rls++;
1948
1949         if (qm_info->num_vports > ecore_init_qm_get_num_vports(p_hwfn))
1950                 DP_ERR(p_hwfn,
1951                        "vport overflow! qm_info->num_vports %d,"
1952                        " qm_init_get_num_vports() %d\n",
1953                        qm_info->num_vports,
1954                        ecore_init_qm_get_num_vports(p_hwfn));
1955
1956         if (qm_info->num_pf_rls > ecore_init_qm_get_num_pf_rls(p_hwfn))
1957                 DP_ERR(p_hwfn, "rl overflow! qm_info->num_pf_rls %d,"
1958                        " qm_init_get_num_pf_rls() %d\n",
1959                        qm_info->num_pf_rls,
1960                        ecore_init_qm_get_num_pf_rls(p_hwfn));
1961 }
1962
1963 /* get pq index according to PQ_FLAGS */
1964 static u16 *ecore_init_qm_get_idx_from_flags(struct ecore_hwfn *p_hwfn,
1965                                              u32 pq_flags)
1966 {
1967         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1968
1969         /* Can't have multiple flags set here */
1970         if (OSAL_BITMAP_WEIGHT((unsigned long *)&pq_flags,
1971                                 sizeof(pq_flags)) > 1)
1972                 goto err;
1973
1974         switch (pq_flags) {
1975         case PQ_FLAGS_RLS:
1976                 return &qm_info->first_rl_pq;
1977         case PQ_FLAGS_MCOS:
1978                 return &qm_info->first_mcos_pq;
1979         case PQ_FLAGS_LB:
1980                 return &qm_info->pure_lb_pq;
1981         case PQ_FLAGS_OOO:
1982                 return &qm_info->ooo_pq;
1983         case PQ_FLAGS_ACK:
1984                 return &qm_info->pure_ack_pq;
1985         case PQ_FLAGS_OFLD:
1986                 return &qm_info->offload_pq;
1987         case PQ_FLAGS_VFS:
1988                 return &qm_info->first_vf_pq;
1989         default:
1990                 goto err;
1991         }
1992
1993 err:
1994         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
1995         return OSAL_NULL;
1996 }
1997
1998 /* save pq index in qm info */
1999 static void ecore_init_qm_set_idx(struct ecore_hwfn *p_hwfn,
2000                                   u32 pq_flags, u16 pq_val)
2001 {
2002         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
2003
2004         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
2005 }
2006
2007 /* get tx pq index, with the PQ TX base already set (ready for context init) */
2008 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags)
2009 {
2010         u16 *base_pq_idx = ecore_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
2011
2012         return *base_pq_idx + CM_TX_PQ_BASE;
2013 }
2014
2015 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
2016 {
2017         u8 max_tc = ecore_init_qm_get_num_tcs(p_hwfn);
2018
2019         if (tc > max_tc)
2020                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
2021
2022         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
2023 }
2024
2025 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
2026 {
2027         u16 max_vf = ecore_init_qm_get_num_vfs(p_hwfn);
2028
2029         if (vf > max_vf)
2030                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
2031
2032         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
2033 }
2034
2035 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
2036 {
2037         u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
2038
2039         /* for rate limiters, it is okay to use the modulo behavior - no
2040          * DP_ERR
2041          */
2042         return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + (rl % max_rl);
2043 }
2044
2045 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
2046 {
2047         u16 start_pq, pq, qm_pq_idx;
2048
2049         pq = ecore_get_cm_pq_idx_rl(p_hwfn, rl);
2050         start_pq = p_hwfn->qm_info.start_pq;
2051         qm_pq_idx = pq - start_pq - CM_TX_PQ_BASE;
2052
2053         if (qm_pq_idx > p_hwfn->qm_info.num_pqs) {
2054                 DP_ERR(p_hwfn,
2055                        "qm_pq_idx %d must be smaller than %d\n",
2056                         qm_pq_idx, p_hwfn->qm_info.num_pqs);
2057         }
2058
2059         return p_hwfn->qm_info.qm_pq_params[qm_pq_idx].vport_id;
2060 }
2061
2062 /* Functions for creating specific types of pqs */
2063 static void ecore_init_qm_lb_pq(struct ecore_hwfn *p_hwfn)
2064 {
2065         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2066
2067         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
2068                 return;
2069
2070         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
2071         ecore_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
2072 }
2073
2074 static void ecore_init_qm_ooo_pq(struct ecore_hwfn *p_hwfn)
2075 {
2076         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2077
2078         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
2079                 return;
2080
2081         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
2082         ecore_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
2083 }
2084
2085 static void ecore_init_qm_pure_ack_pq(struct ecore_hwfn *p_hwfn)
2086 {
2087         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2088
2089         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
2090                 return;
2091
2092         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
2093         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2094 }
2095
2096 static void ecore_init_qm_offload_pq(struct ecore_hwfn *p_hwfn)
2097 {
2098         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2099
2100         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
2101                 return;
2102
2103         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
2104         ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
2105 }
2106
2107 static void ecore_init_qm_mcos_pqs(struct ecore_hwfn *p_hwfn)
2108 {
2109         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2110         u8 tc_idx;
2111
2112         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
2113                 return;
2114
2115         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
2116         for (tc_idx = 0; tc_idx < ecore_init_qm_get_num_tcs(p_hwfn); tc_idx++)
2117                 ecore_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
2118 }
2119
2120 static void ecore_init_qm_vf_pqs(struct ecore_hwfn *p_hwfn)
2121 {
2122         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2123         u16 vf_idx, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
2124
2125         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
2126                 return;
2127
2128         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
2129
2130         qm_info->num_vf_pqs = num_vfs;
2131         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
2132                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_DEFAULT_TC,
2133                                  PQ_INIT_VF_RL);
2134 }
2135
2136 static void ecore_init_qm_rl_pqs(struct ecore_hwfn *p_hwfn)
2137 {
2138         u16 pf_rls_idx, num_pf_rls = ecore_init_qm_get_num_pf_rls(p_hwfn);
2139         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2140
2141         if (!(ecore_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
2142                 return;
2143
2144         ecore_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
2145         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
2146                 ecore_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC,
2147                                  PQ_INIT_PF_RL);
2148 }
2149
2150 static void ecore_init_qm_pq_params(struct ecore_hwfn *p_hwfn)
2151 {
2152         /* rate limited pqs, must come first (FW assumption) */
2153         ecore_init_qm_rl_pqs(p_hwfn);
2154
2155         /* pqs for multi cos */
2156         ecore_init_qm_mcos_pqs(p_hwfn);
2157
2158         /* pure loopback pq */
2159         ecore_init_qm_lb_pq(p_hwfn);
2160
2161         /* out of order pq */
2162         ecore_init_qm_ooo_pq(p_hwfn);
2163
2164         /* pure ack pq */
2165         ecore_init_qm_pure_ack_pq(p_hwfn);
2166
2167         /* pq for offloaded protocol */
2168         ecore_init_qm_offload_pq(p_hwfn);
2169
2170         /* done sharing vports */
2171         ecore_init_qm_advance_vport(p_hwfn);
2172
2173         /* pqs for vfs */
2174         ecore_init_qm_vf_pqs(p_hwfn);
2175 }
2176
2177 /* compare values of getters against resources amounts */
2178 static enum _ecore_status_t ecore_init_qm_sanity(struct ecore_hwfn *p_hwfn)
2179 {
2180         if (ecore_init_qm_get_num_vports(p_hwfn) >
2181             RESC_NUM(p_hwfn, ECORE_VPORT)) {
2182                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
2183                 return ECORE_INVAL;
2184         }
2185
2186         if (ecore_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, ECORE_PQ)) {
2187                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
2188                 return ECORE_INVAL;
2189         }
2190
2191         return ECORE_SUCCESS;
2192 }
2193
2194 /*
2195  * Function for verbose printing of the qm initialization results
2196  */
2197 static void ecore_dp_init_qm_params(struct ecore_hwfn *p_hwfn)
2198 {
2199         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2200         struct init_qm_vport_params *vport;
2201         struct init_qm_port_params *port;
2202         struct init_qm_pq_params *pq;
2203         int i, tc;
2204
2205         /* top level params */
2206         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2207                    "qm init top level params: start_pq %d, start_vport %d,"
2208                    " pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
2209                    qm_info->start_pq, qm_info->start_vport, qm_info->pure_lb_pq,
2210                    qm_info->offload_pq, qm_info->pure_ack_pq);
2211         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2212                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d,"
2213                    " num_vports %d, max_phys_tcs_per_port %d\n",
2214                    qm_info->ooo_pq, qm_info->first_vf_pq, qm_info->num_pqs,
2215                    qm_info->num_vf_pqs, qm_info->num_vports,
2216                    qm_info->max_phys_tcs_per_port);
2217         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2218                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d,"
2219                    " pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2220                    qm_info->pf_rl_en, qm_info->pf_wfq_en, qm_info->vport_rl_en,
2221                    qm_info->vport_wfq_en, qm_info->pf_wfq, qm_info->pf_rl,
2222                    qm_info->num_pf_rls, ecore_get_pq_flags(p_hwfn));
2223
2224         /* port table */
2225         for (i = 0; i < p_hwfn->p_dev->num_ports_in_engine; i++) {
2226                 port = &qm_info->qm_port_params[i];
2227                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2228                            "port idx %d, active %d, active_phys_tcs %d,"
2229                            " num_pbf_cmd_lines %d, num_btb_blocks %d,"
2230                            " reserved %d\n",
2231                            i, port->active, port->active_phys_tcs,
2232                            port->num_pbf_cmd_lines, port->num_btb_blocks,
2233                            port->reserved);
2234         }
2235
2236         /* vport table */
2237         for (i = 0; i < qm_info->num_vports; i++) {
2238                 vport = &qm_info->qm_vport_params[i];
2239                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2240                            "vport idx %d, vport_rl %d, wfq %d,"
2241                            " first_tx_pq_id [ ",
2242                            qm_info->start_vport + i, vport->vport_rl,
2243                            vport->vport_wfq);
2244                 for (tc = 0; tc < NUM_OF_TCS; tc++)
2245                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "%d ",
2246                                    vport->first_tx_pq_id[tc]);
2247                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "]\n");
2248         }
2249
2250         /* pq table */
2251         for (i = 0; i < qm_info->num_pqs; i++) {
2252                 pq = &qm_info->qm_pq_params[i];
2253                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
2254                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
2255                            qm_info->start_pq + i, pq->port_id, pq->vport_id,
2256                            pq->tc_id, pq->wrr_group, pq->rl_valid);
2257         }
2258 }
2259
2260 static void ecore_init_qm_info(struct ecore_hwfn *p_hwfn)
2261 {
2262         /* reset params required for init run */
2263         ecore_init_qm_reset_params(p_hwfn);
2264
2265         /* init QM top level params */
2266         ecore_init_qm_params(p_hwfn);
2267
2268         /* init QM port params */
2269         ecore_init_qm_port_params(p_hwfn);
2270
2271         /* init QM vport params */
2272         ecore_init_qm_vport_params(p_hwfn);
2273
2274         /* init QM physical queue params */
2275         ecore_init_qm_pq_params(p_hwfn);
2276
2277         /* display all that init */
2278         ecore_dp_init_qm_params(p_hwfn);
2279 }
2280
2281 /* This function reconfigures the QM pf on the fly.
2282  * For this purpose we:
2283  * 1. reconfigure the QM database
2284  * 2. set new values to runtime array
2285  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2286  * 4. activate init tool in QM_PF stage
2287  * 5. send an sdm_qm_cmd through rbc interface to release the QM
2288  */
2289 enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
2290                                      struct ecore_ptt *p_ptt)
2291 {
2292         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2293         bool b_rc;
2294         enum _ecore_status_t rc;
2295
2296         /* initialize ecore's qm data structure */
2297         ecore_init_qm_info(p_hwfn);
2298
2299         /* stop PF's qm queues */
2300         OSAL_SPIN_LOCK(&qm_lock);
2301         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2302                                       qm_info->start_pq, qm_info->num_pqs);
2303         OSAL_SPIN_UNLOCK(&qm_lock);
2304         if (!b_rc)
2305                 return ECORE_INVAL;
2306
2307         /* clear the QM_PF runtime phase leftovers from previous init */
2308         ecore_init_clear_rt_data(p_hwfn);
2309
2310         /* prepare QM portion of runtime array */
2311         ecore_qm_init_pf(p_hwfn, p_ptt, false);
2312
2313         /* activate init tool on runtime array */
2314         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2315                             p_hwfn->hw_info.hw_mode);
2316         if (rc != ECORE_SUCCESS)
2317                 return rc;
2318
2319         /* start PF's qm queues */
2320         OSAL_SPIN_LOCK(&qm_lock);
2321         b_rc = ecore_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2322                                       qm_info->start_pq, qm_info->num_pqs);
2323         OSAL_SPIN_UNLOCK(&qm_lock);
2324         if (!b_rc)
2325                 return ECORE_INVAL;
2326
2327         return ECORE_SUCCESS;
2328 }
2329
2330 static enum _ecore_status_t ecore_alloc_qm_data(struct ecore_hwfn *p_hwfn)
2331 {
2332         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2333         enum _ecore_status_t rc;
2334
2335         rc = ecore_init_qm_sanity(p_hwfn);
2336         if (rc != ECORE_SUCCESS)
2337                 goto alloc_err;
2338
2339         qm_info->qm_pq_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2340                                             sizeof(struct init_qm_pq_params) *
2341                                             ecore_init_qm_get_num_pqs(p_hwfn));
2342         if (!qm_info->qm_pq_params)
2343                 goto alloc_err;
2344
2345         qm_info->qm_vport_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2346                                        sizeof(struct init_qm_vport_params) *
2347                                        ecore_init_qm_get_num_vports(p_hwfn));
2348         if (!qm_info->qm_vport_params)
2349                 goto alloc_err;
2350
2351         qm_info->qm_port_params = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2352                                       sizeof(struct init_qm_port_params) *
2353                                       p_hwfn->p_dev->num_ports_in_engine);
2354         if (!qm_info->qm_port_params)
2355                 goto alloc_err;
2356
2357         qm_info->wfq_data = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
2358                                         sizeof(struct ecore_wfq_data) *
2359                                         ecore_init_qm_get_num_vports(p_hwfn));
2360         if (!qm_info->wfq_data)
2361                 goto alloc_err;
2362
2363         return ECORE_SUCCESS;
2364
2365 alloc_err:
2366         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for QM params\n");
2367         ecore_qm_info_free(p_hwfn);
2368         return ECORE_NOMEM;
2369 }
2370 /******************** End QM initialization ***************/
2371
2372 enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
2373 {
2374         enum _ecore_status_t rc = ECORE_SUCCESS;
2375         int i;
2376
2377         if (IS_VF(p_dev)) {
2378                 for_each_hwfn(p_dev, i) {
2379                         rc = ecore_l2_alloc(&p_dev->hwfns[i]);
2380                         if (rc != ECORE_SUCCESS)
2381                                 return rc;
2382                 }
2383                 return rc;
2384         }
2385
2386         p_dev->fw_data = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2387                                      sizeof(*p_dev->fw_data));
2388         if (!p_dev->fw_data)
2389                 return ECORE_NOMEM;
2390
2391         for_each_hwfn(p_dev, i) {
2392                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2393                 u32 n_eqes, num_cons;
2394
2395                 /* initialize the doorbell recovery mechanism */
2396                 rc = ecore_db_recovery_setup(p_hwfn);
2397                 if (rc)
2398                         goto alloc_err;
2399
2400                 /* First allocate the context manager structure */
2401                 rc = ecore_cxt_mngr_alloc(p_hwfn);
2402                 if (rc)
2403                         goto alloc_err;
2404
2405                 /* Set the HW cid/tid numbers (in the context manager)
2406                  * Must be done prior to any further computations.
2407                  */
2408                 rc = ecore_cxt_set_pf_params(p_hwfn);
2409                 if (rc)
2410                         goto alloc_err;
2411
2412                 rc = ecore_alloc_qm_data(p_hwfn);
2413                 if (rc)
2414                         goto alloc_err;
2415
2416                 /* init qm info */
2417                 ecore_init_qm_info(p_hwfn);
2418
2419                 /* Compute the ILT client partition */
2420                 rc = ecore_cxt_cfg_ilt_compute(p_hwfn);
2421                 if (rc)
2422                         goto alloc_err;
2423
2424                 /* CID map / ILT shadow table / T2
2425                  * The talbes sizes are determined by the computations above
2426                  */
2427                 rc = ecore_cxt_tables_alloc(p_hwfn);
2428                 if (rc)
2429                         goto alloc_err;
2430
2431                 /* SPQ, must follow ILT because initializes SPQ context */
2432                 rc = ecore_spq_alloc(p_hwfn);
2433                 if (rc)
2434                         goto alloc_err;
2435
2436                 /* SP status block allocation */
2437                 p_hwfn->p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
2438                                                            RESERVED_PTT_DPC);
2439
2440                 rc = ecore_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2441                 if (rc)
2442                         goto alloc_err;
2443
2444                 rc = ecore_iov_alloc(p_hwfn);
2445                 if (rc)
2446                         goto alloc_err;
2447
2448                 /* EQ */
2449                 n_eqes = ecore_chain_get_capacity(&p_hwfn->p_spq->chain);
2450                 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) {
2451                         /* Calculate the EQ size
2452                          * ---------------------
2453                          * Each ICID may generate up to one event at a time i.e.
2454                          * the event must be handled/cleared before a new one
2455                          * can be generated. We calculate the sum of events per
2456                          * protocol and create an EQ deep enough to handle the
2457                          * worst case:
2458                          * - Core - according to SPQ.
2459                          * - RoCE - per QP there are a couple of ICIDs, one
2460                          *        responder and one requester, each can
2461                          *        generate an EQE => n_eqes_qp = 2 * n_qp.
2462                          *        Each CQ can generate an EQE. There are 2 CQs
2463                          *        per QP => n_eqes_cq = 2 * n_qp.
2464                          *        Hence the RoCE total is 4 * n_qp or
2465                          *        2 * num_cons.
2466                          * - ENet - There can be up to two events per VF. One
2467                          *        for VF-PF channel and another for VF FLR
2468                          *        initial cleanup. The number of VFs is
2469                          *        bounded by MAX_NUM_VFS_BB, and is much
2470                          *        smaller than RoCE's so we avoid exact
2471                          *        calculation.
2472                          */
2473                         if (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {
2474                                 num_cons =
2475                                     ecore_cxt_get_proto_cid_count(
2476                                                 p_hwfn,
2477                                                 PROTOCOLID_ROCE,
2478                                                 OSAL_NULL);
2479                                 num_cons *= 2;
2480                         } else {
2481                                 num_cons = ecore_cxt_get_proto_cid_count(
2482                                                 p_hwfn,
2483                                                 PROTOCOLID_IWARP,
2484                                                 OSAL_NULL);
2485                         }
2486                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
2487                 } else if (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) {
2488                         num_cons =
2489                             ecore_cxt_get_proto_cid_count(p_hwfn,
2490                                                           PROTOCOLID_ISCSI,
2491                                                           OSAL_NULL);
2492                         n_eqes += 2 * num_cons;
2493                 }
2494
2495                 if (n_eqes > 0xFFFF) {
2496                         DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
2497                                        "The maximum of a u16 chain is 0x%x\n",
2498                                n_eqes, 0xFFFF);
2499                         goto alloc_no_mem;
2500                 }
2501
2502                 rc = ecore_eq_alloc(p_hwfn, (u16)n_eqes);
2503                 if (rc)
2504                         goto alloc_err;
2505
2506                 rc = ecore_consq_alloc(p_hwfn);
2507                 if (rc)
2508                         goto alloc_err;
2509
2510                 rc = ecore_l2_alloc(p_hwfn);
2511                 if (rc != ECORE_SUCCESS)
2512                         goto alloc_err;
2513
2514                 /* DMA info initialization */
2515                 rc = ecore_dmae_info_alloc(p_hwfn);
2516                 if (rc) {
2517                         DP_NOTICE(p_hwfn, false, "Failed to allocate memory for dmae_info structure\n");
2518                         goto alloc_err;
2519                 }
2520
2521                 /* DCBX initialization */
2522                 rc = ecore_dcbx_info_alloc(p_hwfn);
2523                 if (rc) {
2524                         DP_NOTICE(p_hwfn, false,
2525                                   "Failed to allocate memory for dcbx structure\n");
2526                         goto alloc_err;
2527                 }
2528
2529                 rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
2530                 if (rc) {
2531                         DP_NOTICE(p_hwfn, false,
2532                                   "Failed to allocate dbg user info structure\n");
2533                         goto alloc_err;
2534                 }
2535         } /* hwfn loop */
2536
2537         rc = ecore_llh_alloc(p_dev);
2538         if (rc != ECORE_SUCCESS) {
2539                 DP_NOTICE(p_dev, true,
2540                           "Failed to allocate memory for the llh_info structure\n");
2541                 goto alloc_err;
2542         }
2543
2544         p_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,
2545                                          sizeof(*p_dev->reset_stats));
2546         if (!p_dev->reset_stats) {
2547                 DP_NOTICE(p_dev, false, "Failed to allocate reset statistics\n");
2548                 goto alloc_no_mem;
2549         }
2550
2551         return ECORE_SUCCESS;
2552
2553 alloc_no_mem:
2554         rc = ECORE_NOMEM;
2555 alloc_err:
2556         ecore_resc_free(p_dev);
2557         return rc;
2558 }
2559
2560 void ecore_resc_setup(struct ecore_dev *p_dev)
2561 {
2562         int i;
2563
2564         if (IS_VF(p_dev)) {
2565                 for_each_hwfn(p_dev, i)
2566                         ecore_l2_setup(&p_dev->hwfns[i]);
2567                 return;
2568         }
2569
2570         for_each_hwfn(p_dev, i) {
2571                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2572
2573                 ecore_cxt_mngr_setup(p_hwfn);
2574                 ecore_spq_setup(p_hwfn);
2575                 ecore_eq_setup(p_hwfn);
2576                 ecore_consq_setup(p_hwfn);
2577
2578                 /* Read shadow of current MFW mailbox */
2579                 ecore_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2580                 OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
2581                             p_hwfn->mcp_info->mfw_mb_cur,
2582                             p_hwfn->mcp_info->mfw_mb_length);
2583
2584                 ecore_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2585
2586                 ecore_l2_setup(p_hwfn);
2587                 ecore_iov_setup(p_hwfn);
2588         }
2589 }
2590
2591 #define FINAL_CLEANUP_POLL_CNT  (100)
2592 #define FINAL_CLEANUP_POLL_TIME (10)
2593 enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
2594                                          struct ecore_ptt *p_ptt,
2595                                          u16 id, bool is_vf)
2596 {
2597         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2598         enum _ecore_status_t rc = ECORE_TIMEOUT;
2599
2600 #ifndef ASIC_ONLY
2601         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev) ||
2602             CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2603                 DP_INFO(p_hwfn, "Skipping final cleanup for non-ASIC\n");
2604                 return ECORE_SUCCESS;
2605         }
2606 #endif
2607
2608         addr = GTT_BAR0_MAP_REG_USDM_RAM +
2609             USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2610
2611         if (is_vf)
2612                 id += 0x10;
2613
2614         command |= X_FINAL_CLEANUP_AGG_INT <<
2615             SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2616         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2617         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2618         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2619
2620 /* Make sure notification is not set before initiating final cleanup */
2621
2622         if (REG_RD(p_hwfn, addr)) {
2623                 DP_NOTICE(p_hwfn, false,
2624                           "Unexpected; Found final cleanup notification");
2625                 DP_NOTICE(p_hwfn, false,
2626                           " before initiating final cleanup\n");
2627                 REG_WR(p_hwfn, addr, 0);
2628         }
2629
2630         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2631                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2632                    id, command);
2633
2634         ecore_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2635
2636         /* Poll until completion */
2637         while (!REG_RD(p_hwfn, addr) && count--)
2638                 OSAL_MSLEEP(FINAL_CLEANUP_POLL_TIME);
2639
2640         if (REG_RD(p_hwfn, addr))
2641                 rc = ECORE_SUCCESS;
2642         else
2643                 DP_NOTICE(p_hwfn, true,
2644                           "Failed to receive FW final cleanup notification\n");
2645
2646         /* Cleanup afterwards */
2647         REG_WR(p_hwfn, addr, 0);
2648
2649         return rc;
2650 }
2651
2652 static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
2653 {
2654         int hw_mode = 0;
2655
2656         if (ECORE_IS_BB_B0(p_hwfn->p_dev)) {
2657                 hw_mode |= 1 << MODE_BB;
2658         } else if (ECORE_IS_AH(p_hwfn->p_dev)) {
2659                 hw_mode |= 1 << MODE_K2;
2660         } else {
2661                 DP_NOTICE(p_hwfn, true, "Unknown chip type %#x\n",
2662                           p_hwfn->p_dev->type);
2663                 return ECORE_INVAL;
2664         }
2665
2666         /* Ports per engine is based on the values in CNIG_REG_NW_PORT_MODE */
2667         switch (p_hwfn->p_dev->num_ports_in_engine) {
2668         case 1:
2669                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2670                 break;
2671         case 2:
2672                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2673                 break;
2674         case 4:
2675                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2676                 break;
2677         default:
2678                 DP_NOTICE(p_hwfn, true,
2679                           "num_ports_in_engine = %d not supported\n",
2680                           p_hwfn->p_dev->num_ports_in_engine);
2681                 return ECORE_INVAL;
2682         }
2683
2684         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
2685                 hw_mode |= 1 << MODE_MF_SD;
2686         else
2687                 hw_mode |= 1 << MODE_MF_SI;
2688
2689 #ifndef ASIC_ONLY
2690         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2691                 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
2692                         hw_mode |= 1 << MODE_FPGA;
2693                 } else {
2694                         if (p_hwfn->p_dev->b_is_emul_full)
2695                                 hw_mode |= 1 << MODE_EMUL_FULL;
2696                         else
2697                                 hw_mode |= 1 << MODE_EMUL_REDUCED;
2698                 }
2699         } else
2700 #endif
2701                 hw_mode |= 1 << MODE_ASIC;
2702
2703         if (ECORE_IS_CMT(p_hwfn->p_dev))
2704                 hw_mode |= 1 << MODE_100G;
2705
2706         p_hwfn->hw_info.hw_mode = hw_mode;
2707
2708         DP_VERBOSE(p_hwfn, (ECORE_MSG_PROBE | ECORE_MSG_IFUP),
2709                    "Configuring function for hw_mode: 0x%08x\n",
2710                    p_hwfn->hw_info.hw_mode);
2711
2712         return ECORE_SUCCESS;
2713 }
2714
2715 #ifndef ASIC_ONLY
2716 /* MFW-replacement initializations for non-ASIC */
2717 static enum _ecore_status_t ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
2718                                                struct ecore_ptt *p_ptt)
2719 {
2720         struct ecore_dev *p_dev = p_hwfn->p_dev;
2721         u32 pl_hv = 1;
2722         int i;
2723
2724         if (CHIP_REV_IS_EMUL(p_dev)) {
2725                 if (ECORE_IS_AH(p_dev))
2726                         pl_hv |= 0x600;
2727         }
2728
2729         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV + 4, pl_hv);
2730
2731         if (CHIP_REV_IS_EMUL(p_dev) &&
2732             (ECORE_IS_AH(p_dev)))
2733                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2_K2_E5,
2734                          0x3ffffff);
2735
2736         /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
2737         /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
2738         if (!CHIP_REV_IS_EMUL(p_dev) || ECORE_IS_BB(p_dev))
2739                 ecore_wr(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB, 4);
2740
2741         if (CHIP_REV_IS_EMUL(p_dev)) {
2742                 if (ECORE_IS_AH(p_dev)) {
2743                         /* 2 for 4-port, 1 for 2-port, 0 for 1-port */
2744                         ecore_wr(p_hwfn, p_ptt, MISC_REG_PORT_MODE,
2745                                  (p_dev->num_ports_in_engine >> 1));
2746
2747                         ecore_wr(p_hwfn, p_ptt, MISC_REG_BLOCK_256B_EN,
2748                                  p_dev->num_ports_in_engine == 4 ? 0 : 3);
2749                 }
2750         }
2751
2752         /* Poll on RBC */
2753         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_RBC_DONE, 1);
2754         for (i = 0; i < 100; i++) {
2755                 OSAL_UDELAY(50);
2756                 if (ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_CFG_DONE) == 1)
2757                         break;
2758         }
2759         if (i == 100)
2760                 DP_NOTICE(p_hwfn, true,
2761                           "RBC done failed to complete in PSWRQ2\n");
2762
2763         return ECORE_SUCCESS;
2764 }
2765 #endif
2766
2767 /* Init run time data for all PFs and their VFs on an engine.
2768  * TBD - for VFs - Once we have parent PF info for each VF in
2769  * shmem available as CAU requires knowledge of parent PF for each VF.
2770  */
2771 static void ecore_init_cau_rt_data(struct ecore_dev *p_dev)
2772 {
2773         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2774         int i, igu_sb_id;
2775
2776         for_each_hwfn(p_dev, i) {
2777                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
2778                 struct ecore_igu_info *p_igu_info;
2779                 struct ecore_igu_block *p_block;
2780                 struct cau_sb_entry sb_entry;
2781
2782                 p_igu_info = p_hwfn->hw_info.p_igu_info;
2783
2784                 for (igu_sb_id = 0;
2785                      igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_dev);
2786                      igu_sb_id++) {
2787                         p_block = &p_igu_info->entry[igu_sb_id];
2788
2789                         if (!p_block->is_pf)
2790                                 continue;
2791
2792                         ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
2793                                                 p_block->function_id, 0, 0);
2794                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2795                                          sb_entry);
2796                 }
2797         }
2798 }
2799
2800 static void ecore_init_cache_line_size(struct ecore_hwfn *p_hwfn,
2801                                        struct ecore_ptt *p_ptt)
2802 {
2803         u32 val, wr_mbs, cache_line_size;
2804
2805         val = ecore_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2806         switch (val) {
2807         case 0:
2808                 wr_mbs = 128;
2809                 break;
2810         case 1:
2811                 wr_mbs = 256;
2812                 break;
2813         case 2:
2814                 wr_mbs = 512;
2815                 break;
2816         default:
2817                 DP_INFO(p_hwfn,
2818                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2819                         val);
2820                 return;
2821         }
2822
2823         cache_line_size = OSAL_MIN_T(u32, OSAL_CACHE_LINE_SIZE, wr_mbs);
2824         switch (cache_line_size) {
2825         case 32:
2826                 val = 0;
2827                 break;
2828         case 64:
2829                 val = 1;
2830                 break;
2831         case 128:
2832                 val = 2;
2833                 break;
2834         case 256:
2835                 val = 3;
2836                 break;
2837         default:
2838                 DP_INFO(p_hwfn,
2839                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2840                         cache_line_size);
2841         }
2842
2843         if (wr_mbs < OSAL_CACHE_LINE_SIZE)
2844                 DP_INFO(p_hwfn,
2845                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2846                         OSAL_CACHE_LINE_SIZE, wr_mbs);
2847
2848         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2849         if (val > 0) {
2850                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2851                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2852         }
2853 }
2854
2855 static enum _ecore_status_t ecore_hw_init_common(struct ecore_hwfn *p_hwfn,
2856                                                  struct ecore_ptt *p_ptt,
2857                                                  int hw_mode)
2858 {
2859         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
2860         struct ecore_dev *p_dev = p_hwfn->p_dev;
2861         u8 vf_id, max_num_vfs;
2862         u16 num_pfs, pf_id;
2863         u32 concrete_fid;
2864         enum _ecore_status_t rc = ECORE_SUCCESS;
2865
2866         ecore_init_cau_rt_data(p_dev);
2867
2868         /* Program GTT windows */
2869         ecore_gtt_init(p_hwfn, p_ptt);
2870
2871 #ifndef ASIC_ONLY
2872         if (CHIP_REV_IS_EMUL(p_dev)) {
2873                 rc = ecore_hw_init_chip(p_hwfn, p_ptt);
2874                 if (rc != ECORE_SUCCESS)
2875                         return rc;
2876         }
2877 #endif
2878
2879         if (p_hwfn->mcp_info) {
2880                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2881                         qm_info->pf_rl_en = 1;
2882                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2883                         qm_info->pf_wfq_en = 1;
2884         }
2885
2886         ecore_qm_common_rt_init(p_hwfn,
2887                                 p_dev->num_ports_in_engine,
2888                                 qm_info->max_phys_tcs_per_port,
2889                                 qm_info->pf_rl_en, qm_info->pf_wfq_en,
2890                                 qm_info->vport_rl_en, qm_info->vport_wfq_en,
2891                                 qm_info->qm_port_params);
2892
2893         ecore_cxt_hw_init_common(p_hwfn);
2894
2895         ecore_init_cache_line_size(p_hwfn, p_ptt);
2896
2897         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ECORE_PATH_ID(p_hwfn),
2898                             hw_mode);
2899         if (rc != ECORE_SUCCESS)
2900                 return rc;
2901
2902         /* @@TBD MichalK - should add VALIDATE_VFID to init tool...
2903          * need to decide with which value, maybe runtime
2904          */
2905         ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2906         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2907
2908         if (ECORE_IS_BB(p_dev)) {
2909                 /* Workaround clears ROCE search for all functions to prevent
2910                  * involving non initialized function in processing ROCE packet.
2911                  */
2912                 num_pfs = NUM_OF_ENG_PFS(p_dev);
2913                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2914                         ecore_fid_pretend(p_hwfn, p_ptt, pf_id);
2915                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2916                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2917                 }
2918                 /* pretend to original PF */
2919                 ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2920         }
2921
2922         /* Workaround for avoiding CCFC execution error when getting packets
2923          * with CRC errors, and allowing instead the invoking of the FW error
2924          * handler.
2925          * This is not done inside the init tool since it currently can't
2926          * perform a pretending to VFs.
2927          */
2928         max_num_vfs = ECORE_IS_AH(p_dev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
2929         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2930                 concrete_fid = ecore_vfid_to_concrete(p_hwfn, vf_id);
2931                 ecore_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
2932                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2933                 ecore_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2934                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2935                 ecore_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2936         }
2937         /* pretend to original PF */
2938         ecore_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2939
2940         return rc;
2941 }
2942
2943 #ifndef ASIC_ONLY
2944 #define MISC_REG_RESET_REG_2_XMAC_BIT (1 << 4)
2945 #define MISC_REG_RESET_REG_2_XMAC_SOFT_BIT (1 << 5)
2946
2947 #define PMEG_IF_BYTE_COUNT      8
2948
2949 static void ecore_wr_nw_port(struct ecore_hwfn *p_hwfn,
2950                              struct ecore_ptt *p_ptt,
2951                              u32 addr, u64 data, u8 reg_type, u8 port)
2952 {
2953         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2954                    "CMD: %08x, ADDR: 0x%08x, DATA: %08x:%08x\n",
2955                    ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) |
2956                    (8 << PMEG_IF_BYTE_COUNT),
2957                    (reg_type << 25) | (addr << 8) | port,
2958                    (u32)((data >> 32) & 0xffffffff),
2959                    (u32)(data & 0xffffffff));
2960
2961         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB,
2962                  (ecore_rd(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_CMD_BB) &
2963                   0xffff00fe) | (8 << PMEG_IF_BYTE_COUNT));
2964         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_ADDR_BB,
2965                  (reg_type << 25) | (addr << 8) | port);
2966         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB, data & 0xffffffff);
2967         ecore_wr(p_hwfn, p_ptt, CNIG_REG_PMEG_IF_WRDATA_BB,
2968                  (data >> 32) & 0xffffffff);
2969 }
2970
2971 #define XLPORT_MODE_REG (0x20a)
2972 #define XLPORT_MAC_CONTROL (0x210)
2973 #define XLPORT_FLOW_CONTROL_CONFIG (0x207)
2974 #define XLPORT_ENABLE_REG (0x20b)
2975
2976 #define XLMAC_CTRL (0x600)
2977 #define XLMAC_MODE (0x601)
2978 #define XLMAC_RX_MAX_SIZE (0x608)
2979 #define XLMAC_TX_CTRL (0x604)
2980 #define XLMAC_PAUSE_CTRL (0x60d)
2981 #define XLMAC_PFC_CTRL (0x60e)
2982
2983 static void ecore_emul_link_init_bb(struct ecore_hwfn *p_hwfn,
2984                                     struct ecore_ptt *p_ptt)
2985 {
2986         u8 loopback = 0, port = p_hwfn->port_id * 2;
2987
2988         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
2989
2990         /* XLPORT MAC MODE *//* 0 Quad, 4 Single... */
2991         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MODE_REG, (0x4 << 4) | 0x4, 1,
2992                          port);
2993         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_MAC_CONTROL, 0, 1, port);
2994         /* XLMAC: SOFT RESET */
2995         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x40, 0, port);
2996         /* XLMAC: Port Speed >= 10Gbps */
2997         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_MODE, 0x40, 0, port);
2998         /* XLMAC: Max Size */
2999         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_RX_MAX_SIZE, 0x3fff, 0, port);
3000         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_TX_CTRL,
3001                          0x01000000800ULL | (0xa << 12) | ((u64)1 << 38),
3002                          0, port);
3003         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PAUSE_CTRL, 0x7c000, 0, port);
3004         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_PFC_CTRL,
3005                          0x30ffffc000ULL, 0, port);
3006         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL, 0x3 | (loopback << 2), 0,
3007                          port); /* XLMAC: TX_EN, RX_EN */
3008         /* XLMAC: TX_EN, RX_EN, SW_LINK_STATUS */
3009         ecore_wr_nw_port(p_hwfn, p_ptt, XLMAC_CTRL,
3010                          0x1003 | (loopback << 2), 0, port);
3011         /* Enabled Parallel PFC interface */
3012         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_FLOW_CONTROL_CONFIG, 1, 0, port);
3013
3014         /* XLPORT port enable */
3015         ecore_wr_nw_port(p_hwfn, p_ptt, XLPORT_ENABLE_REG, 0xf, 1, port);
3016 }
3017
3018 static void ecore_emul_link_init_ah_e5(struct ecore_hwfn *p_hwfn,
3019                                        struct ecore_ptt *p_ptt)
3020 {
3021         u8 port = p_hwfn->port_id;
3022         u32 mac_base = NWM_REG_MAC0_K2_E5 + (port << 2) * NWM_REG_MAC0_SIZE;
3023
3024         DP_INFO(p_hwfn->p_dev, "Configurating Emulation Link %02x\n", port);
3025
3026         ecore_wr(p_hwfn, p_ptt, CNIG_REG_NIG_PORT0_CONF_K2_E5 + (port << 2),
3027                  (1 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT) |
3028                  (port <<
3029                   CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT) |
3030                  (0 << CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT));
3031
3032         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_XIF_MODE_K2_E5,
3033                  1 << ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT);
3034
3035         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_FRM_LENGTH_K2_E5,
3036                  9018 << ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT);
3037
3038         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_IPG_LENGTH_K2_E5,
3039                  0xc << ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT);
3040
3041         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5,
3042                  8 << ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT);
3043
3044         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5,
3045                  (0xA <<
3046                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT) |
3047                  (8 <<
3048                   ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT));
3049
3050         ecore_wr(p_hwfn, p_ptt, mac_base + ETH_MAC_REG_COMMAND_CONFIG_K2_E5,
3051                  0xa853);
3052 }
3053
3054 static void ecore_emul_link_init(struct ecore_hwfn *p_hwfn,
3055                                  struct ecore_ptt *p_ptt)
3056 {
3057         if (ECORE_IS_AH(p_hwfn->p_dev))
3058                 ecore_emul_link_init_ah_e5(p_hwfn, p_ptt);
3059         else /* BB */
3060                 ecore_emul_link_init_bb(p_hwfn, p_ptt);
3061 }
3062
3063 static void ecore_link_init_bb(struct ecore_hwfn *p_hwfn,
3064                                struct ecore_ptt *p_ptt,  u8 port)
3065 {
3066         int port_offset = port ? 0x800 : 0;
3067         u32 xmac_rxctrl = 0;
3068
3069         /* Reset of XMAC */
3070         /* FIXME: move to common start */
3071         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3072                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Clear */
3073         OSAL_MSLEEP(1);
3074         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3075                  MISC_REG_RESET_REG_2_XMAC_BIT);        /* Set */
3076
3077         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_CORE_PORT_MODE_BB, 1);
3078
3079         /* Set the number of ports on the Warp Core to 10G */
3080         ecore_wr(p_hwfn, p_ptt, MISC_REG_XMAC_PHY_PORT_MODE_BB, 3);
3081
3082         /* Soft reset of XMAC */
3083         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + 2 * sizeof(u32),
3084                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3085         OSAL_MSLEEP(1);
3086         ecore_wr(p_hwfn, p_ptt, MISC_REG_RESET_PL_PDA_VAUX + sizeof(u32),
3087                  MISC_REG_RESET_REG_2_XMAC_SOFT_BIT);
3088
3089         /* FIXME: move to common end */
3090         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
3091                 ecore_wr(p_hwfn, p_ptt, XMAC_REG_MODE_BB + port_offset, 0x20);
3092
3093         /* Set Max packet size: initialize XMAC block register for port 0 */
3094         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_MAX_SIZE_BB + port_offset, 0x2710);
3095
3096         /* CRC append for Tx packets: init XMAC block register for port 1 */
3097         ecore_wr(p_hwfn, p_ptt, XMAC_REG_TX_CTRL_LO_BB + port_offset, 0xC800);
3098
3099         /* Enable TX and RX: initialize XMAC block register for port 1 */
3100         ecore_wr(p_hwfn, p_ptt, XMAC_REG_CTRL_BB + port_offset,
3101                  XMAC_REG_CTRL_TX_EN_BB | XMAC_REG_CTRL_RX_EN_BB);
3102         xmac_rxctrl = ecore_rd(p_hwfn, p_ptt,
3103                                XMAC_REG_RX_CTRL_BB + port_offset);
3104         xmac_rxctrl |= XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB;
3105         ecore_wr(p_hwfn, p_ptt, XMAC_REG_RX_CTRL_BB + port_offset, xmac_rxctrl);
3106 }
3107 #endif
3108
3109 static enum _ecore_status_t
3110 ecore_hw_init_dpi_size(struct ecore_hwfn *p_hwfn,
3111                        struct ecore_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
3112 {
3113         u32 dpi_bit_shift, dpi_count, dpi_page_size;
3114         u32 min_dpis;
3115         u32 n_wids;
3116
3117         /* Calculate DPI size
3118          * ------------------
3119          * The PWM region contains Doorbell Pages. The first is reserverd for
3120          * the kernel for, e.g, L2. The others are free to be used by non-
3121          * trusted applications, typically from user space. Each page, called a
3122          * doorbell page is sectioned into windows that allow doorbells to be
3123          * issued in parallel by the kernel/application. The size of such a
3124          * window (a.k.a. WID) is 1kB.
3125          * Summary:
3126          *    1kB WID x N WIDS = DPI page size
3127          *    DPI page size x N DPIs = PWM region size
3128          * Notes:
3129          * The size of the DPI page size must be in multiples of OSAL_PAGE_SIZE
3130          * in order to ensure that two applications won't share the same page.
3131          * It also must contain at least one WID per CPU to allow parallelism.
3132          * It also must be a power of 2, since it is stored as a bit shift.
3133          *
3134          * The DPI page size is stored in a register as 'dpi_bit_shift' so that
3135          * 0 is 4kB, 1 is 8kB and etc. Hence the minimum size is 4,096
3136          * containing 4 WIDs.
3137          */
3138         n_wids = OSAL_MAX_T(u32, ECORE_MIN_WIDS, n_cpus);
3139         dpi_page_size = ECORE_WID_SIZE * OSAL_ROUNDUP_POW_OF_TWO(n_wids);
3140         dpi_page_size = (dpi_page_size + OSAL_PAGE_SIZE - 1) &
3141                         ~(OSAL_PAGE_SIZE - 1);
3142         dpi_bit_shift = OSAL_LOG2(dpi_page_size / 4096);
3143         dpi_count = pwm_region_size / dpi_page_size;
3144
3145         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
3146         min_dpis = OSAL_MAX_T(u32, ECORE_MIN_DPIS, min_dpis);
3147
3148         /* Update hwfn */
3149         p_hwfn->dpi_size = dpi_page_size;
3150         p_hwfn->dpi_count = dpi_count;
3151
3152         /* Update registers */
3153         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
3154
3155         if (dpi_count < min_dpis)
3156                 return ECORE_NORESOURCES;
3157
3158         return ECORE_SUCCESS;
3159 }
3160
3161 enum ECORE_ROCE_EDPM_MODE {
3162         ECORE_ROCE_EDPM_MODE_ENABLE = 0,
3163         ECORE_ROCE_EDPM_MODE_FORCE_ON = 1,
3164         ECORE_ROCE_EDPM_MODE_DISABLE = 2,
3165 };
3166
3167 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn)
3168 {
3169         if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
3170                 return false;
3171
3172         return true;
3173 }
3174
3175 static enum _ecore_status_t
3176 ecore_hw_init_pf_doorbell_bar(struct ecore_hwfn *p_hwfn,
3177                               struct ecore_ptt *p_ptt)
3178 {
3179         u32 pwm_regsize, norm_regsize;
3180         u32 non_pwm_conn, min_addr_reg1;
3181         u32 db_bar_size, n_cpus;
3182         u32 roce_edpm_mode;
3183         u32 pf_dems_shift;
3184         enum _ecore_status_t rc = ECORE_SUCCESS;
3185         u8 cond;
3186
3187         db_bar_size = ecore_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
3188         if (ECORE_IS_CMT(p_hwfn->p_dev))
3189                 db_bar_size /= 2;
3190
3191         /* Calculate doorbell regions
3192          * -----------------------------------
3193          * The doorbell BAR is made of two regions. The first is called normal
3194          * region and the second is called PWM region. In the normal region
3195          * each ICID has its own set of addresses so that writing to that
3196          * specific address identifies the ICID. In the Process Window Mode
3197          * region the ICID is given in the data written to the doorbell. The
3198          * above per PF register denotes the offset in the doorbell BAR in which
3199          * the PWM region begins.
3200          * The normal region has ECORE_PF_DEMS_SIZE bytes per ICID, that is per
3201          * non-PWM connection. The calculation below computes the total non-PWM
3202          * connections. The DORQ_REG_PF_MIN_ADDR_REG1 register is
3203          * in units of 4,096 bytes.
3204          */
3205         non_pwm_conn = ecore_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
3206             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
3207                                           OSAL_NULL) +
3208             ecore_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, OSAL_NULL);
3209         norm_regsize = ROUNDUP(ECORE_PF_DEMS_SIZE * non_pwm_conn,
3210                                OSAL_PAGE_SIZE);
3211         min_addr_reg1 = norm_regsize / 4096;
3212         pwm_regsize = db_bar_size - norm_regsize;
3213
3214         /* Check that the normal and PWM sizes are valid */
3215         if (db_bar_size < norm_regsize) {
3216                 DP_ERR(p_hwfn->p_dev,
3217                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
3218                        db_bar_size, norm_regsize);
3219                 return ECORE_NORESOURCES;
3220         }
3221         if (pwm_regsize < ECORE_MIN_PWM_REGION) {
3222                 DP_ERR(p_hwfn->p_dev,
3223                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
3224                        pwm_regsize, ECORE_MIN_PWM_REGION, db_bar_size,
3225                        norm_regsize);
3226                 return ECORE_NORESOURCES;
3227         }
3228
3229         /* Calculate number of DPIs */
3230         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
3231         if ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE) ||
3232             ((roce_edpm_mode == ECORE_ROCE_EDPM_MODE_FORCE_ON))) {
3233                 /* Either EDPM is mandatory, or we are attempting to allocate a
3234                  * WID per CPU.
3235                  */
3236                 n_cpus = OSAL_NUM_CPUS();
3237                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3238         }
3239
3240         cond = ((rc != ECORE_SUCCESS) &&
3241                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_ENABLE)) ||
3242                 (roce_edpm_mode == ECORE_ROCE_EDPM_MODE_DISABLE);
3243         if (cond || p_hwfn->dcbx_no_edpm) {
3244                 /* Either EDPM is disabled from user configuration, or it is
3245                  * disabled via DCBx, or it is not mandatory and we failed to
3246                  * allocated a WID per CPU.
3247                  */
3248                 n_cpus = 1;
3249                 rc = ecore_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
3250
3251                 /* If we entered this flow due to DCBX then the DPM register is
3252                  * already configured.
3253                  */
3254         }
3255
3256         DP_INFO(p_hwfn,
3257                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d",
3258                 norm_regsize, pwm_regsize);
3259         DP_INFO(p_hwfn,
3260                 " dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
3261                 p_hwfn->dpi_size, p_hwfn->dpi_count,
3262                 (!ecore_edpm_enabled(p_hwfn)) ?
3263                 "disabled" : "enabled");
3264
3265         /* Check return codes from above calls */
3266         if (rc != ECORE_SUCCESS) {
3267                 DP_ERR(p_hwfn,
3268                        "Failed to allocate enough DPIs\n");
3269                 return ECORE_NORESOURCES;
3270         }
3271
3272         /* Update hwfn */
3273         p_hwfn->dpi_start_offset = norm_regsize;
3274
3275         /* Update registers */
3276         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
3277         pf_dems_shift = OSAL_LOG2(ECORE_PF_DEMS_SIZE / 4);
3278         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
3279         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
3280
3281         return ECORE_SUCCESS;
3282 }
3283
3284 static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
3285                                                struct ecore_ptt *p_ptt,
3286                                                int hw_mode)
3287 {
3288         enum _ecore_status_t rc = ECORE_SUCCESS;
3289
3290         /* In CMT the gate should be cleared by the 2nd hwfn */
3291         if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
3292                 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
3293
3294         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
3295                             hw_mode);
3296         if (rc != ECORE_SUCCESS)
3297                 return rc;
3298
3299         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
3300
3301 #ifndef ASIC_ONLY
3302         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev))
3303                 return ECORE_SUCCESS;
3304
3305         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
3306                 if (ECORE_IS_AH(p_hwfn->p_dev))
3307                         return ECORE_SUCCESS;
3308                 else if (ECORE_IS_BB(p_hwfn->p_dev))
3309                         ecore_link_init_bb(p_hwfn, p_ptt, p_hwfn->port_id);
3310         } else if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
3311                 if (ECORE_IS_CMT(p_hwfn->p_dev)) {
3312                         /* Activate OPTE in CMT */
3313                         u32 val;
3314
3315                         val = ecore_rd(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV);
3316                         val |= 0x10;
3317                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV, val);
3318                         ecore_wr(p_hwfn, p_ptt, MISC_REG_CLK_100G_MODE, 1);
3319                         ecore_wr(p_hwfn, p_ptt, MISCS_REG_CLK_100G_MODE, 1);
3320                         ecore_wr(p_hwfn, p_ptt, MISC_REG_OPTE_MODE, 1);
3321                         ecore_wr(p_hwfn, p_ptt,
3322                                  NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH, 1);
3323                         ecore_wr(p_hwfn, p_ptt,
3324                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL, 0x55555555);
3325                         ecore_wr(p_hwfn, p_ptt,
3326                                  NIG_REG_LLH_ENG_CLS_ENG_ID_TBL + 0x4,
3327                                  0x55555555);
3328                 }
3329
3330                 ecore_emul_link_init(p_hwfn, p_ptt);
3331         } else {
3332                 DP_INFO(p_hwfn->p_dev, "link is not being configured\n");
3333         }
3334 #endif
3335
3336         return rc;
3337 }
3338
3339 static enum _ecore_status_t
3340 ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3341                  int hw_mode, struct ecore_hw_init_params *p_params)
3342 {
3343         u8 rel_pf_id = p_hwfn->rel_pf_id;
3344         u32 prs_reg;
3345         enum _ecore_status_t rc = ECORE_SUCCESS;
3346         u16 ctrl;
3347         int pos;
3348
3349         if (p_hwfn->mcp_info) {
3350                 struct ecore_mcp_function_info *p_info;
3351
3352                 p_info = &p_hwfn->mcp_info->func_info;
3353                 if (p_info->bandwidth_min)
3354                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
3355
3356                 /* Update rate limit once we'll actually have a link */
3357                 p_hwfn->qm_info.pf_rl = 100000;
3358         }
3359         ecore_cxt_hw_init_pf(p_hwfn, p_ptt);
3360
3361         ecore_int_igu_init_rt(p_hwfn);
3362
3363         /* Set VLAN in NIG if needed */
3364         if (hw_mode & (1 << MODE_MF_SD)) {
3365                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "Configuring LLH_FUNC_TAG\n");
3366                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
3367                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
3368                              p_hwfn->hw_info.ovlan);
3369
3370                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3371                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
3372                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
3373                              1);
3374         }
3375
3376         /* Enable classification by MAC if needed */
3377         if (hw_mode & (1 << MODE_MF_SI)) {
3378                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
3379                            "Configuring TAGMAC_CLS_TYPE\n");
3380                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET,
3381                              1);
3382         }
3383
3384         /* Protocl Configuration  - @@@TBD - should we set 0 otherwise? */
3385         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
3386                      (p_hwfn->hw_info.personality == ECORE_PCI_ISCSI) ? 1 : 0);
3387         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
3388                      (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) ? 1 : 0);
3389         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
3390
3391         /* perform debug configuration when chip is out of reset */
3392         OSAL_BEFORE_PF_START((void *)p_hwfn->p_dev, p_hwfn->my_id);
3393
3394         /* Sanity check before the PF init sequence that uses DMAE */
3395         rc = ecore_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
3396         if (rc)
3397                 return rc;
3398
3399         /* PF Init sequence */
3400         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
3401         if (rc)
3402                 return rc;
3403
3404         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
3405         rc = ecore_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
3406         if (rc)
3407                 return rc;
3408
3409         /* Pure runtime initializations - directly to the HW  */
3410         ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
3411
3412         /* PCI relaxed ordering causes a decrease in the performance on some
3413          * systems. Till a root cause is found, disable this attribute in the
3414          * PCI config space.
3415          */
3416         /* Not in use @DPDK
3417         * pos = OSAL_PCI_FIND_CAPABILITY(p_hwfn->p_dev, PCI_CAP_ID_EXP);
3418         * if (!pos) {
3419         *       DP_NOTICE(p_hwfn, true,
3420         *                 "Failed to find the PCIe Cap\n");
3421         *       return ECORE_IO;
3422         * }
3423         * OSAL_PCI_READ_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
3424         * ctrl &= ~PCI_EXP_DEVCTL_RELAX_EN;
3425         * OSAL_PCI_WRITE_CONFIG_WORD(p_hwfn->p_dev, pos + PCI_EXP_DEVCTL, ctrl);
3426         */
3427
3428         rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
3429         if (rc != ECORE_SUCCESS)
3430                 return rc;
3431
3432         /* Use the leading hwfn since in CMT only NIG #0 is operational */
3433         if (IS_LEAD_HWFN(p_hwfn)) {
3434                 rc = ecore_llh_hw_init_pf(p_hwfn, p_ptt,
3435                                         p_params->avoid_eng_affin);
3436                 if (rc)
3437                         return rc;
3438         }
3439
3440         if (p_params->b_hw_start) {
3441                 /* enable interrupts */
3442                 rc = ecore_int_igu_enable(p_hwfn, p_ptt, p_params->int_mode);
3443                 if (rc != ECORE_SUCCESS)
3444                         return rc;
3445
3446                 /* send function start command */
3447                 rc = ecore_sp_pf_start(p_hwfn, p_ptt, p_params->p_tunn,
3448                                        p_params->allow_npar_tx_switch);
3449                 if (rc) {
3450                         DP_NOTICE(p_hwfn, true,
3451                                   "Function start ramrod failed\n");
3452                 } else {
3453                         return rc;
3454                 }
3455                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3456                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3457                                 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3458
3459                 if (p_hwfn->hw_info.personality == ECORE_PCI_FCOE) {
3460                         ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1,
3461                                         (1 << 2));
3462                         ecore_wr(p_hwfn, p_ptt,
3463                                  PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
3464                                  0x100);
3465                 }
3466                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3467                                 "PRS_REG_SEARCH registers after start PFn\n");
3468                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP);
3469                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3470                                 "PRS_REG_SEARCH_TCP: %x\n", prs_reg);
3471                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP);
3472                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3473                                 "PRS_REG_SEARCH_UDP: %x\n", prs_reg);
3474                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE);
3475                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3476                                 "PRS_REG_SEARCH_FCOE: %x\n", prs_reg);
3477                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE);
3478                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3479                                 "PRS_REG_SEARCH_ROCE: %x\n", prs_reg);
3480                 prs_reg = ecore_rd(p_hwfn, p_ptt,
3481                                 PRS_REG_SEARCH_TCP_FIRST_FRAG);
3482                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3483                                 "PRS_REG_SEARCH_TCP_FIRST_FRAG: %x\n",
3484                                 prs_reg);
3485                 prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
3486                 DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
3487                                 "PRS_REG_SEARCH_TAG1: %x\n", prs_reg);
3488         }
3489         return ECORE_SUCCESS;
3490 }
3491
3492 enum _ecore_status_t ecore_pglueb_set_pfid_enable(struct ecore_hwfn *p_hwfn,
3493                                                   struct ecore_ptt *p_ptt,
3494                                                   bool b_enable)
3495 {
3496         u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
3497
3498         /* Configure the PF's internal FID_enable for master transactions */
3499         ecore_wr(p_hwfn, p_ptt,
3500                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
3501
3502         /* Wait until value is set - try for 1 second every 50us */
3503         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
3504                 val = ecore_rd(p_hwfn, p_ptt,
3505                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
3506                 if (val == set_val)
3507                         break;
3508
3509                 OSAL_UDELAY(50);
3510         }
3511
3512         if (val != set_val) {
3513                 DP_NOTICE(p_hwfn, true,
3514                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
3515                 return ECORE_UNKNOWN_ERROR;
3516         }
3517
3518         return ECORE_SUCCESS;
3519 }
3520
3521 static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
3522                                   struct ecore_ptt *p_main_ptt)
3523 {
3524         /* Read shadow of current MFW mailbox */
3525         ecore_mcp_read_mb(p_hwfn, p_main_ptt);
3526         OSAL_MEMCPY(p_hwfn->mcp_info->mfw_mb_shadow,
3527                     p_hwfn->mcp_info->mfw_mb_cur,
3528                     p_hwfn->mcp_info->mfw_mb_length);
3529 }
3530
3531 static void ecore_pglueb_clear_err(struct ecore_hwfn *p_hwfn,
3532                                    struct ecore_ptt *p_ptt)
3533 {
3534         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
3535                  1 << p_hwfn->abs_pf_id);
3536 }
3537
3538 static enum _ecore_status_t
3539 ecore_fill_load_req_params(struct ecore_hwfn *p_hwfn,
3540                            struct ecore_load_req_params *p_load_req,
3541                            struct ecore_drv_load_params *p_drv_load)
3542 {
3543         /* Make sure that if ecore-client didn't provide inputs, all the
3544          * expected defaults are indeed zero.
3545          */
3546         OSAL_BUILD_BUG_ON(ECORE_DRV_ROLE_OS != 0);
3547         OSAL_BUILD_BUG_ON(ECORE_LOAD_REQ_LOCK_TO_DEFAULT != 0);
3548         OSAL_BUILD_BUG_ON(ECORE_OVERRIDE_FORCE_LOAD_NONE != 0);
3549
3550         OSAL_MEM_ZERO(p_load_req, sizeof(*p_load_req));
3551
3552         if (p_drv_load == OSAL_NULL)
3553                 goto out;
3554
3555         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
3556                                ECORE_DRV_ROLE_KDUMP :
3557                                ECORE_DRV_ROLE_OS;
3558         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
3559         p_load_req->override_force_load = p_drv_load->override_force_load;
3560
3561         /* Old MFW versions don't support timeout values other than default and
3562          * none, so these values are replaced according to the fall-back action.
3563          */
3564
3565         if (p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT ||
3566             p_drv_load->mfw_timeout_val == ECORE_LOAD_REQ_LOCK_TO_NONE ||
3567             (p_hwfn->mcp_info->capabilities &
3568              FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO)) {
3569                 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
3570                 goto out;
3571         }
3572
3573         switch (p_drv_load->mfw_timeout_fallback) {
3574         case ECORE_TO_FALLBACK_TO_NONE:
3575                 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_NONE;
3576                 break;
3577         case ECORE_TO_FALLBACK_TO_DEFAULT:
3578                 p_load_req->timeout_val = ECORE_LOAD_REQ_LOCK_TO_DEFAULT;
3579                 break;
3580         case ECORE_TO_FALLBACK_FAIL_LOAD:
3581                 DP_NOTICE(p_hwfn, false,
3582                           "Received %d as a value for MFW timeout while the MFW supports only default [%d] or none [%d]. Abort.\n",
3583                           p_drv_load->mfw_timeout_val,
3584                           ECORE_LOAD_REQ_LOCK_TO_DEFAULT,
3585                           ECORE_LOAD_REQ_LOCK_TO_NONE);
3586                 return ECORE_ABORTED;
3587         }
3588
3589         DP_INFO(p_hwfn,
3590                 "Modified the MFW timeout value from %d to %s [%d] due to lack of MFW support\n",
3591                 p_drv_load->mfw_timeout_val,
3592                 (p_load_req->timeout_val == ECORE_LOAD_REQ_LOCK_TO_DEFAULT) ?
3593                 "default" : "none",
3594                 p_load_req->timeout_val);
3595 out:
3596         return ECORE_SUCCESS;
3597 }
3598
3599 enum _ecore_status_t ecore_vf_start(struct ecore_hwfn *p_hwfn,
3600                                     struct ecore_hw_init_params *p_params)
3601 {
3602         if (p_params->p_tunn) {
3603                 ecore_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
3604                 ecore_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
3605         }
3606
3607         p_hwfn->b_int_enabled = 1;
3608
3609         return ECORE_SUCCESS;
3610 }
3611
3612 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
3613                                    struct ecore_hw_init_params *p_params)
3614 {
3615         struct ecore_load_req_params load_req_params;
3616         u32 load_code, resp, param, drv_mb_param;
3617         bool b_default_mtu = true;
3618         struct ecore_hwfn *p_hwfn;
3619         enum _ecore_status_t rc = ECORE_SUCCESS;
3620         u16 ether_type;
3621         int i;
3622
3623         if ((p_params->int_mode == ECORE_INT_MODE_MSI) && ECORE_IS_CMT(p_dev)) {
3624                 DP_NOTICE(p_dev, false,
3625                           "MSI mode is not supported for CMT devices\n");
3626                 return ECORE_INVAL;
3627         }
3628
3629         if (IS_PF(p_dev)) {
3630                 rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
3631                 if (rc != ECORE_SUCCESS)
3632                         return rc;
3633         }
3634
3635         for_each_hwfn(p_dev, i) {
3636                 p_hwfn = &p_dev->hwfns[i];
3637
3638                 /* If management didn't provide a default, set one of our own */
3639                 if (!p_hwfn->hw_info.mtu) {
3640                         p_hwfn->hw_info.mtu = 1500;
3641                         b_default_mtu = false;
3642                 }
3643
3644                 if (IS_VF(p_dev)) {
3645                         ecore_vf_start(p_hwfn, p_params);
3646                         continue;
3647                 }
3648
3649                 rc = ecore_calc_hw_mode(p_hwfn);
3650                 if (rc != ECORE_SUCCESS)
3651                         return rc;
3652
3653                 if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
3654                                                    &p_dev->mf_bits) ||
3655                                      OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
3656                                                    &p_dev->mf_bits))) {
3657                         if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
3658                                           &p_dev->mf_bits))
3659                                 ether_type = ETHER_TYPE_VLAN;
3660                         else
3661                                 ether_type = ETHER_TYPE_QINQ;
3662                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3663                                      ether_type);
3664                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3665                                      ether_type);
3666                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3667                                      ether_type);
3668                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3669                                      ether_type);
3670                 }
3671
3672                 ecore_set_spq_block_timeout(p_hwfn, p_params->spq_timeout_ms);
3673
3674                 rc = ecore_fill_load_req_params(p_hwfn, &load_req_params,
3675                                                 p_params->p_drv_load_params);
3676                 if (rc != ECORE_SUCCESS)
3677                         return rc;
3678
3679                 rc = ecore_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3680                                         &load_req_params);
3681                 if (rc != ECORE_SUCCESS) {
3682                         DP_NOTICE(p_hwfn, false,
3683                                   "Failed sending a LOAD_REQ command\n");
3684                         return rc;
3685                 }
3686
3687                 load_code = load_req_params.load_code;
3688                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3689                            "Load request was sent. Load code: 0x%x\n",
3690                            load_code);
3691
3692                 ecore_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3693
3694                 /* CQ75580:
3695                  * When coming back from hiberbate state, the registers from
3696                  * which shadow is read initially are not initialized. It turns
3697                  * out that these registers get initialized during the call to
3698                  * ecore_mcp_load_req request. So we need to reread them here
3699                  * to get the proper shadow register value.
3700                  * Note: This is a workaround for the missing MFW
3701                  * initialization. It may be removed once the implementation
3702                  * is done.
3703                  */
3704                 ecore_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3705
3706                 /* Only relevant for recovery:
3707                  * Clear the indication after the LOAD_REQ command is responded
3708                  * by the MFW.
3709                  */
3710                 p_dev->recov_in_prog = false;
3711
3712                 p_hwfn->first_on_engine = (load_code ==
3713                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
3714
3715                 if (!qm_lock_ref_cnt) {
3716 #ifdef CONFIG_ECORE_LOCK_ALLOC
3717                         rc = OSAL_SPIN_LOCK_ALLOC(p_hwfn, &qm_lock);
3718                         if (rc) {
3719                                 DP_ERR(p_hwfn, "qm_lock allocation failed\n");
3720                                 goto qm_lock_fail;
3721                         }
3722 #endif
3723                         OSAL_SPIN_LOCK_INIT(&qm_lock);
3724                 }
3725                 ++qm_lock_ref_cnt;
3726
3727                 /* Clean up chip from previous driver if such remains exist.
3728                  * This is not needed when the PF is the first one on the
3729                  * engine, since afterwards we are going to init the FW.
3730                  */
3731                 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3732                         rc = ecore_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3733                                                  p_hwfn->rel_pf_id, false);
3734                         if (rc != ECORE_SUCCESS) {
3735                                 ecore_hw_err_notify(p_hwfn,
3736                                                     ECORE_HW_ERR_RAMROD_FAIL);
3737                                 goto load_err;
3738                         }
3739                 }
3740
3741                 /* Log and clear previous pglue_b errors if such exist */
3742                 ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
3743
3744                 /* Enable the PF's internal FID_enable in the PXP */
3745                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3746                                                   true);
3747                 if (rc != ECORE_SUCCESS)
3748                         goto load_err;
3749
3750                 /* Clear the pglue_b was_error indication.
3751                  * In E4 it must be done after the BME and the internal
3752                  * FID_enable for the PF are set, since VDMs may cause the
3753                  * indication to be set again.
3754                  */
3755                 ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3756
3757                 switch (load_code) {
3758                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3759                         rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3760                                                   p_hwfn->hw_info.hw_mode);
3761                         if (rc != ECORE_SUCCESS)
3762                                 break;
3763                         /* Fall into */
3764                 case FW_MSG_CODE_DRV_LOAD_PORT:
3765                         rc = ecore_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3766                                                 p_hwfn->hw_info.hw_mode);
3767                         if (rc != ECORE_SUCCESS)
3768                                 break;
3769                         /* Fall into */
3770                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3771                         rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3772                                               p_hwfn->hw_info.hw_mode,
3773                                               p_params);
3774                         break;
3775                 default:
3776                         DP_NOTICE(p_hwfn, false,
3777                                   "Unexpected load code [0x%08x]", load_code);
3778                         rc = ECORE_NOTIMPL;
3779                         break;
3780                 }
3781
3782                 if (rc != ECORE_SUCCESS) {
3783                         DP_NOTICE(p_hwfn, false,
3784                                   "init phase failed for loadcode 0x%x (rc %d)\n",
3785                                   load_code, rc);
3786                         goto load_err;
3787                 }
3788
3789                 rc = ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3790                 if (rc != ECORE_SUCCESS) {
3791                         DP_NOTICE(p_hwfn, false,
3792                                   "Sending load done failed, rc = %d\n", rc);
3793                         if (rc == ECORE_NOMEM) {
3794                                 DP_NOTICE(p_hwfn, false,
3795                                           "Sending load done was failed due to memory allocation failure\n");
3796                                 goto load_err;
3797                         }
3798                         return rc;
3799                 }
3800
3801                 /* send DCBX attention request command */
3802                 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
3803                            "sending phony dcbx set command to trigger DCBx attention handling\n");
3804                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3805                                    DRV_MSG_CODE_SET_DCBX,
3806                                    1 << DRV_MB_PARAM_DCBX_NOTIFY_OFFSET, &resp,
3807                                    &param);
3808                 if (rc != ECORE_SUCCESS) {
3809                         DP_NOTICE(p_hwfn, false,
3810                                   "Failed to send DCBX attention request\n");
3811                         return rc;
3812                 }
3813
3814                 p_hwfn->hw_init_done = true;
3815         }
3816
3817         if (IS_PF(p_dev)) {
3818                 /* Get pre-negotiated values for stag, bandwidth etc. */
3819                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3820                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3821                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3822                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3823                                    DRV_MSG_CODE_GET_OEM_UPDATES,
3824                                    1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3825                                    &resp, &param);
3826                 if (rc != ECORE_SUCCESS)
3827                         DP_NOTICE(p_hwfn, false,
3828                                   "Failed to send GET_OEM_UPDATES attention request\n");
3829         }
3830
3831         if (IS_PF(p_dev)) {
3832                 /* Get pre-negotiated values for stag, bandwidth etc. */
3833                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3834                 DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
3835                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3836                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3837                                    DRV_MSG_CODE_GET_OEM_UPDATES,
3838                                    1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
3839                                    &resp, &param);
3840                 if (rc != ECORE_SUCCESS)
3841                         DP_NOTICE(p_hwfn, false,
3842                                   "Failed to send GET_OEM_UPDATES attention request\n");
3843         }
3844
3845         if (IS_PF(p_dev)) {
3846                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
3847                 drv_mb_param = STORM_FW_VERSION;
3848                 rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3849                                    DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3850                                    drv_mb_param, &resp, &param);
3851                 if (rc != ECORE_SUCCESS)
3852                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
3853
3854                 if (!b_default_mtu) {
3855                         rc = ecore_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3856                                                       p_hwfn->hw_info.mtu);
3857                         if (rc != ECORE_SUCCESS)
3858                                 DP_INFO(p_hwfn, "Failed to update default mtu\n");
3859                 }
3860
3861                 rc = ecore_mcp_ov_update_driver_state(p_hwfn,
3862                                                       p_hwfn->p_main_ptt,
3863                                                 ECORE_OV_DRIVER_STATE_DISABLED);
3864                 if (rc != ECORE_SUCCESS)
3865                         DP_INFO(p_hwfn, "Failed to update driver state\n");
3866
3867                 rc = ecore_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3868                                                  ECORE_OV_ESWITCH_NONE);
3869                 if (rc != ECORE_SUCCESS)
3870                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3871         }
3872
3873         return rc;
3874
3875 load_err:
3876         --qm_lock_ref_cnt;
3877 #ifdef CONFIG_ECORE_LOCK_ALLOC
3878         if (!qm_lock_ref_cnt)
3879                 OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
3880 qm_lock_fail:
3881 #endif
3882         /* The MFW load lock should be released regardless of success or failure
3883          * of initialization.
3884          * TODO: replace this with an attempt to send cancel_load.
3885          */
3886         ecore_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3887         return rc;
3888 }
3889
3890 #define ECORE_HW_STOP_RETRY_LIMIT       (10)
3891 static void ecore_hw_timers_stop(struct ecore_dev *p_dev,
3892                                  struct ecore_hwfn *p_hwfn,
3893                                  struct ecore_ptt *p_ptt)
3894 {
3895         int i;
3896
3897         /* close timers */
3898         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3899         ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3900         for (i = 0; i < ECORE_HW_STOP_RETRY_LIMIT && !p_dev->recov_in_prog;
3901                                                                         i++) {
3902                 if ((!ecore_rd(p_hwfn, p_ptt,
3903                                TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3904                     (!ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3905                         break;
3906
3907                 /* Dependent on number of connection/tasks, possibly
3908                  * 1ms sleep is required between polls
3909                  */
3910                 OSAL_MSLEEP(1);
3911         }
3912
3913         if (i < ECORE_HW_STOP_RETRY_LIMIT)
3914                 return;
3915
3916         DP_NOTICE(p_hwfn, false,
3917                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3918                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3919                   (u8)ecore_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3920 }
3921
3922 void ecore_hw_timers_stop_all(struct ecore_dev *p_dev)
3923 {
3924         int j;
3925
3926         for_each_hwfn(p_dev, j) {
3927                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
3928                 struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3929
3930                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
3931         }
3932 }
3933
3934 static enum _ecore_status_t ecore_verify_reg_val(struct ecore_hwfn *p_hwfn,
3935                                                  struct ecore_ptt *p_ptt,
3936                                                  u32 addr, u32 expected_val)
3937 {
3938         u32 val = ecore_rd(p_hwfn, p_ptt, addr);
3939
3940         if (val != expected_val) {
3941                 DP_NOTICE(p_hwfn, true,
3942                           "Value at address 0x%08x is 0x%08x while the expected value is 0x%08x\n",
3943                           addr, val, expected_val);
3944                 return ECORE_UNKNOWN_ERROR;
3945         }
3946
3947         return ECORE_SUCCESS;
3948 }
3949
3950 enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
3951 {
3952         struct ecore_hwfn *p_hwfn;
3953         struct ecore_ptt *p_ptt;
3954         enum _ecore_status_t rc, rc2 = ECORE_SUCCESS;
3955         int j;
3956
3957         for_each_hwfn(p_dev, j) {
3958                 p_hwfn = &p_dev->hwfns[j];
3959                 p_ptt = p_hwfn->p_main_ptt;
3960
3961                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN, "Stopping hw/fw\n");
3962
3963                 if (IS_VF(p_dev)) {
3964                         ecore_vf_pf_int_cleanup(p_hwfn);
3965                         rc = ecore_vf_pf_reset(p_hwfn);
3966                         if (rc != ECORE_SUCCESS) {
3967                                 DP_NOTICE(p_hwfn, true,
3968                                           "ecore_vf_pf_reset failed. rc = %d.\n",
3969                                           rc);
3970                                 rc2 = ECORE_UNKNOWN_ERROR;
3971                         }
3972                         continue;
3973                 }
3974
3975                 /* mark the hw as uninitialized... */
3976                 p_hwfn->hw_init_done = false;
3977
3978                 /* Send unload command to MCP */
3979                 if (!p_dev->recov_in_prog) {
3980                         rc = ecore_mcp_unload_req(p_hwfn, p_ptt);
3981                         if (rc != ECORE_SUCCESS) {
3982                                 DP_NOTICE(p_hwfn, false,
3983                                           "Failed sending a UNLOAD_REQ command. rc = %d.\n",
3984                                           rc);
3985                                 rc2 = ECORE_UNKNOWN_ERROR;
3986                         }
3987                 }
3988
3989                 OSAL_DPC_SYNC(p_hwfn);
3990
3991                 /* After this point no MFW attentions are expected, e.g. prevent
3992                  * race between pf stop and dcbx pf update.
3993                  */
3994
3995                 rc = ecore_sp_pf_stop(p_hwfn);
3996                 if (rc != ECORE_SUCCESS) {
3997                         DP_NOTICE(p_hwfn, false,
3998                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
3999                                   rc);
4000                         rc2 = ECORE_UNKNOWN_ERROR;
4001                 }
4002
4003                 OSAL_DPC_SYNC(p_hwfn);
4004
4005                 /* After this point we don't expect the FW to send us async
4006                  * events
4007                  */
4008
4009                 /* perform debug action after PF stop was sent */
4010                 OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
4011
4012                 /* close NIG to BRB gate */
4013                 ecore_wr(p_hwfn, p_ptt,
4014                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4015
4016                 /* close parser */
4017                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4018                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4019                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4020                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4021                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4022
4023                 /* @@@TBD - clean transmission queues (5.b) */
4024                 /* @@@TBD - clean BTB (5.c) */
4025
4026                 ecore_hw_timers_stop(p_dev, p_hwfn, p_ptt);
4027
4028                 /* @@@TBD - verify DMAE requests are done (8) */
4029
4030                 /* Disable Attention Generation */
4031                 ecore_int_igu_disable_int(p_hwfn, p_ptt);
4032                 ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
4033                 ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
4034                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
4035                 rc = ecore_int_igu_reset_cam_default(p_hwfn, p_ptt);
4036                 if (rc != ECORE_SUCCESS) {
4037                         DP_NOTICE(p_hwfn, true,
4038                                   "Failed to return IGU CAM to default\n");
4039                         rc2 = ECORE_UNKNOWN_ERROR;
4040                 }
4041
4042                 /* Need to wait 1ms to guarantee SBs are cleared */
4043                 OSAL_MSLEEP(1);
4044
4045                 if (IS_LEAD_HWFN(p_hwfn) &&
4046                     OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
4047                     !ECORE_IS_FCOE_PERSONALITY(p_hwfn))
4048                         ecore_llh_remove_mac_filter(p_dev, 0,
4049                                                    p_hwfn->hw_info.hw_mac_addr);
4050
4051                 if (!p_dev->recov_in_prog) {
4052                         ecore_verify_reg_val(p_hwfn, p_ptt,
4053                                              QM_REG_USG_CNT_PF_TX, 0);
4054                         ecore_verify_reg_val(p_hwfn, p_ptt,
4055                                              QM_REG_USG_CNT_PF_OTHER, 0);
4056                         /* @@@TBD - assert on incorrect xCFC values (10.b) */
4057                 }
4058
4059                 /* Disable PF in HW blocks */
4060                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
4061                 ecore_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
4062
4063                 --qm_lock_ref_cnt;
4064 #ifdef CONFIG_ECORE_LOCK_ALLOC
4065                 if (!qm_lock_ref_cnt)
4066                         OSAL_SPIN_LOCK_DEALLOC(&qm_lock);
4067 #endif
4068
4069                 if (!p_dev->recov_in_prog) {
4070                         rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4071                         if (rc == ECORE_NOMEM) {
4072                                 DP_NOTICE(p_hwfn, false,
4073                                          "Failed sending an UNLOAD_DONE command due to a memory allocation failure. Resending.\n");
4074                                 rc = ecore_mcp_unload_done(p_hwfn, p_ptt);
4075                         }
4076                         if (rc != ECORE_SUCCESS) {
4077                                 DP_NOTICE(p_hwfn, false,
4078                                           "Failed sending a UNLOAD_DONE command. rc = %d.\n",
4079                                           rc);
4080                                 rc2 = ECORE_UNKNOWN_ERROR;
4081                         }
4082                 }
4083         } /* hwfn loop */
4084
4085         if (IS_PF(p_dev) && !p_dev->recov_in_prog) {
4086                 p_hwfn = ECORE_LEADING_HWFN(p_dev);
4087                 p_ptt = ECORE_LEADING_HWFN(p_dev)->p_main_ptt;
4088
4089                  /* Clear the PF's internal FID_enable in the PXP.
4090                   * In CMT this should only be done for first hw-function, and
4091                   * only after all transactions have stopped for all active
4092                   * hw-functions.
4093                   */
4094                 rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
4095                                                   false);
4096                 if (rc != ECORE_SUCCESS) {
4097                         DP_NOTICE(p_hwfn, true,
4098                                   "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
4099                                   rc);
4100                         rc2 = ECORE_UNKNOWN_ERROR;
4101                 }
4102         }
4103
4104         return rc2;
4105 }
4106
4107 enum _ecore_status_t ecore_hw_stop_fastpath(struct ecore_dev *p_dev)
4108 {
4109         int j;
4110
4111         for_each_hwfn(p_dev, j) {
4112                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
4113                 struct ecore_ptt *p_ptt;
4114
4115                 if (IS_VF(p_dev)) {
4116                         ecore_vf_pf_int_cleanup(p_hwfn);
4117                         continue;
4118                 }
4119                 p_ptt = ecore_ptt_acquire(p_hwfn);
4120                 if (!p_ptt)
4121                         return ECORE_AGAIN;
4122
4123                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
4124                            "Shutting down the fastpath\n");
4125
4126                 ecore_wr(p_hwfn, p_ptt,
4127                          NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
4128
4129                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
4130                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
4131                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
4132                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
4133                 ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
4134
4135                 /* @@@TBD - clean transmission queues (5.b) */
4136                 /* @@@TBD - clean BTB (5.c) */
4137
4138                 /* @@@TBD - verify DMAE requests are done (8) */
4139
4140                 ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
4141                 /* Need to wait 1ms to guarantee SBs are cleared */
4142                 OSAL_MSLEEP(1);
4143                 ecore_ptt_release(p_hwfn, p_ptt);
4144         }
4145
4146         return ECORE_SUCCESS;
4147 }
4148
4149 enum _ecore_status_t ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn)
4150 {
4151         struct ecore_ptt *p_ptt;
4152
4153         if (IS_VF(p_hwfn->p_dev))
4154                 return ECORE_SUCCESS;
4155
4156         p_ptt = ecore_ptt_acquire(p_hwfn);
4157         if (!p_ptt)
4158                 return ECORE_AGAIN;
4159
4160         /* If roce info is allocated it means roce is initialized and should
4161          * be enabled in searcher.
4162          */
4163         if (p_hwfn->p_rdma_info) {
4164                 if (p_hwfn->b_rdma_enabled_in_prs)
4165                         ecore_wr(p_hwfn, p_ptt,
4166                                  p_hwfn->rdma_prs_search_reg, 0x1);
4167                 ecore_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x1);
4168         }
4169
4170         /* Re-open incoming traffic */
4171         ecore_wr(p_hwfn, p_ptt,
4172                  NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
4173         ecore_ptt_release(p_hwfn, p_ptt);
4174
4175         return ECORE_SUCCESS;
4176 }
4177
4178 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
4179 static void ecore_hw_hwfn_free(struct ecore_hwfn *p_hwfn)
4180 {
4181         ecore_ptt_pool_free(p_hwfn);
4182         OSAL_FREE(p_hwfn->p_dev, p_hwfn->hw_info.p_igu_info);
4183 }
4184
4185 /* Setup bar access */
4186 static void ecore_hw_hwfn_prepare(struct ecore_hwfn *p_hwfn)
4187 {
4188         /* clear indirect access */
4189         if (ECORE_IS_AH(p_hwfn->p_dev)) {
4190                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4191                          PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5, 0);
4192                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4193                          PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5, 0);
4194                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4195                          PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5, 0);
4196                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4197                          PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5, 0);
4198         } else {
4199                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4200                          PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
4201                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4202                          PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
4203                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4204                          PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
4205                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4206                          PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
4207         }
4208
4209         /* Clean previous pglue_b errors if such exist */
4210         ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
4211
4212         /* enable internal target-read */
4213         ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
4214                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
4215 }
4216
4217 static void get_function_id(struct ecore_hwfn *p_hwfn)
4218 {
4219         /* ME Register */
4220         p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
4221                                                   PXP_PF_ME_OPAQUE_ADDR);
4222
4223         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
4224
4225         /* Bits 16-19 from the ME registers are the pf_num */
4226         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
4227         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4228                                       PXP_CONCRETE_FID_PFID);
4229         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
4230                                     PXP_CONCRETE_FID_PORT);
4231
4232         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4233                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
4234                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
4235 }
4236
4237 static void ecore_hw_set_feat(struct ecore_hwfn *p_hwfn)
4238 {
4239         u32 *feat_num = p_hwfn->hw_info.feat_num;
4240         struct ecore_sb_cnt_info sb_cnt;
4241         u32 non_l2_sbs = 0;
4242
4243         OSAL_MEM_ZERO(&sb_cnt, sizeof(sb_cnt));
4244         ecore_int_get_num_sbs(p_hwfn, &sb_cnt);
4245
4246         /* L2 Queues require each: 1 status block. 1 L2 queue */
4247         if (ECORE_IS_L2_PERSONALITY(p_hwfn)) {
4248                 /* Start by allocating VF queues, then PF's */
4249                 feat_num[ECORE_VF_L2_QUE] =
4250                         OSAL_MIN_T(u32,
4251                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE),
4252                                    sb_cnt.iov_cnt);
4253                 feat_num[ECORE_PF_L2_QUE] =
4254                         OSAL_MIN_T(u32,
4255                                    sb_cnt.cnt - non_l2_sbs,
4256                                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE) -
4257                                    FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE));
4258         }
4259
4260         if (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||
4261             ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) {
4262                 u32 *p_storage_feat = ECORE_IS_FCOE_PERSONALITY(p_hwfn) ?
4263                                       &feat_num[ECORE_FCOE_CQ] :
4264                                       &feat_num[ECORE_ISCSI_CQ];
4265                 u32 limit = sb_cnt.cnt;
4266
4267                 /* The number of queues should not exceed the number of FP SBs.
4268                  * In storage target, the queues are divided into pairs of a CQ
4269                  * and a CmdQ, and each pair uses a single SB. The limit in
4270                  * this case should allow a max ratio of 2:1 instead of 1:1.
4271                  */
4272                 if (p_hwfn->p_dev->b_is_target)
4273                         limit *= 2;
4274                 *p_storage_feat = OSAL_MIN_T(u32, limit,
4275                                              RESC_NUM(p_hwfn, ECORE_CMDQS_CQS));
4276
4277                 /* @DPDK */
4278                 /* The size of "cq_cmdq_sb_num_arr" in the fcoe/iscsi init
4279                  * ramrod is limited to "NUM_OF_GLOBAL_QUEUES / 2".
4280                  */
4281                 *p_storage_feat = OSAL_MIN_T(u32, *p_storage_feat,
4282                                              (NUM_OF_GLOBAL_QUEUES / 2));
4283         }
4284
4285         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4286                    "#PF_L2_QUEUE=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #FCOE_CQ=%d #ISCSI_CQ=%d #SB=%d\n",
4287                    (int)FEAT_NUM(p_hwfn, ECORE_PF_L2_QUE),
4288                    (int)FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE),
4289                    (int)FEAT_NUM(p_hwfn, ECORE_RDMA_CNQ),
4290                    (int)FEAT_NUM(p_hwfn, ECORE_FCOE_CQ),
4291                    (int)FEAT_NUM(p_hwfn, ECORE_ISCSI_CQ),
4292                    (int)sb_cnt.cnt);
4293 }
4294
4295 const char *ecore_hw_get_resc_name(enum ecore_resources res_id)
4296 {
4297         switch (res_id) {
4298         case ECORE_L2_QUEUE:
4299                 return "L2_QUEUE";
4300         case ECORE_VPORT:
4301                 return "VPORT";
4302         case ECORE_RSS_ENG:
4303                 return "RSS_ENG";
4304         case ECORE_PQ:
4305                 return "PQ";
4306         case ECORE_RL:
4307                 return "RL";
4308         case ECORE_MAC:
4309                 return "MAC";
4310         case ECORE_VLAN:
4311                 return "VLAN";
4312         case ECORE_RDMA_CNQ_RAM:
4313                 return "RDMA_CNQ_RAM";
4314         case ECORE_ILT:
4315                 return "ILT";
4316         case ECORE_LL2_QUEUE:
4317                 return "LL2_QUEUE";
4318         case ECORE_CMDQS_CQS:
4319                 return "CMDQS_CQS";
4320         case ECORE_RDMA_STATS_QUEUE:
4321                 return "RDMA_STATS_QUEUE";
4322         case ECORE_BDQ:
4323                 return "BDQ";
4324         case ECORE_SB:
4325                 return "SB";
4326         default:
4327                 return "UNKNOWN_RESOURCE";
4328         }
4329 }
4330
4331 static enum _ecore_status_t
4332 __ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4333                               struct ecore_ptt *p_ptt,
4334                               enum ecore_resources res_id,
4335                               u32 resc_max_val,
4336                               u32 *p_mcp_resp)
4337 {
4338         enum _ecore_status_t rc;
4339
4340         rc = ecore_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
4341                                         resc_max_val, p_mcp_resp);
4342         if (rc != ECORE_SUCCESS) {
4343                 DP_NOTICE(p_hwfn, false,
4344                           "MFW response failure for a max value setting of resource %d [%s]\n",
4345                           res_id, ecore_hw_get_resc_name(res_id));
4346                 return rc;
4347         }
4348
4349         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
4350                 DP_INFO(p_hwfn,
4351                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
4352                         res_id, ecore_hw_get_resc_name(res_id), *p_mcp_resp);
4353
4354         return ECORE_SUCCESS;
4355 }
4356
4357 static enum _ecore_status_t
4358 ecore_hw_set_soft_resc_size(struct ecore_hwfn *p_hwfn,
4359                             struct ecore_ptt *p_ptt)
4360 {
4361         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
4362         u32 resc_max_val, mcp_resp;
4363         u8 res_id;
4364         enum _ecore_status_t rc;
4365
4366         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4367                 /* @DPDK */
4368                 switch (res_id) {
4369                 case ECORE_LL2_QUEUE:
4370                 case ECORE_RDMA_CNQ_RAM:
4371                 case ECORE_RDMA_STATS_QUEUE:
4372                 case ECORE_BDQ:
4373                         resc_max_val = 0;
4374                         break;
4375                 default:
4376                         continue;
4377                 }
4378
4379                 rc = __ecore_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
4380                                                    resc_max_val, &mcp_resp);
4381                 if (rc != ECORE_SUCCESS)
4382                         return rc;
4383
4384                 /* There's no point to continue to the next resource if the
4385                  * command is not supported by the MFW.
4386                  * We do continue if the command is supported but the resource
4387                  * is unknown to the MFW. Such a resource will be later
4388                  * configured with the default allocation values.
4389                  */
4390                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
4391                         return ECORE_NOTIMPL;
4392         }
4393
4394         return ECORE_SUCCESS;
4395 }
4396
4397 static
4398 enum _ecore_status_t ecore_hw_get_dflt_resc(struct ecore_hwfn *p_hwfn,
4399                                             enum ecore_resources res_id,
4400                                             u32 *p_resc_num, u32 *p_resc_start)
4401 {
4402         u8 num_funcs = p_hwfn->num_funcs_on_engine;
4403         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
4404
4405         switch (res_id) {
4406         case ECORE_L2_QUEUE:
4407                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
4408                                  MAX_NUM_L2_QUEUES_BB) / num_funcs;
4409                 break;
4410         case ECORE_VPORT:
4411                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
4412                                  MAX_NUM_VPORTS_BB) / num_funcs;
4413                 break;
4414         case ECORE_RSS_ENG:
4415                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
4416                                  ETH_RSS_ENGINE_NUM_BB) / num_funcs;
4417                 break;
4418         case ECORE_PQ:
4419                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
4420                                  MAX_QM_TX_QUEUES_BB) / num_funcs;
4421                 break;
4422         case ECORE_RL:
4423                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
4424                 break;
4425         case ECORE_MAC:
4426         case ECORE_VLAN:
4427                 /* Each VFC resource can accommodate both a MAC and a VLAN */
4428                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
4429                 break;
4430         case ECORE_ILT:
4431                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
4432                                  PXP_NUM_ILT_RECORDS_BB) / num_funcs;
4433                 break;
4434         case ECORE_LL2_QUEUE:
4435                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
4436                 break;
4437         case ECORE_RDMA_CNQ_RAM:
4438         case ECORE_CMDQS_CQS:
4439                 /* CNQ/CMDQS are the same resource */
4440                 /* @DPDK */
4441                 *p_resc_num = (NUM_OF_GLOBAL_QUEUES / 2) / num_funcs;
4442                 break;
4443         case ECORE_RDMA_STATS_QUEUE:
4444                 /* @DPDK */
4445                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
4446                                  MAX_NUM_VPORTS_BB) / num_funcs;
4447                 break;
4448         case ECORE_BDQ:
4449                 /* @DPDK */
4450                 *p_resc_num = 0;
4451                 break;
4452         default:
4453                 break;
4454         }
4455
4456
4457         switch (res_id) {
4458         case ECORE_BDQ:
4459                 if (!*p_resc_num)
4460                         *p_resc_start = 0;
4461                 break;
4462         case ECORE_SB:
4463                 /* Since we want its value to reflect whether MFW supports
4464                  * the new scheme, have a default of 0.
4465                  */
4466                 *p_resc_num = 0;
4467                 break;
4468         default:
4469                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
4470                 break;
4471         }
4472
4473         return ECORE_SUCCESS;
4474 }
4475
4476 static enum _ecore_status_t
4477 __ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn, enum ecore_resources res_id,
4478                          bool drv_resc_alloc)
4479 {
4480         u32 dflt_resc_num = 0, dflt_resc_start = 0;
4481         u32 mcp_resp, *p_resc_num, *p_resc_start;
4482         enum _ecore_status_t rc;
4483
4484         p_resc_num = &RESC_NUM(p_hwfn, res_id);
4485         p_resc_start = &RESC_START(p_hwfn, res_id);
4486
4487         rc = ecore_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
4488                                     &dflt_resc_start);
4489         if (rc != ECORE_SUCCESS) {
4490                 DP_ERR(p_hwfn,
4491                        "Failed to get default amount for resource %d [%s]\n",
4492                         res_id, ecore_hw_get_resc_name(res_id));
4493                 return rc;
4494         }
4495
4496 #ifndef ASIC_ONLY
4497         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
4498                 *p_resc_num = dflt_resc_num;
4499                 *p_resc_start = dflt_resc_start;
4500                 goto out;
4501         }
4502 #endif
4503
4504         rc = ecore_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
4505                                      &mcp_resp, p_resc_num, p_resc_start);
4506         if (rc != ECORE_SUCCESS) {
4507                 DP_NOTICE(p_hwfn, true,
4508                           "MFW response failure for an allocation request for"
4509                           " resource %d [%s]\n",
4510                           res_id, ecore_hw_get_resc_name(res_id));
4511                 return rc;
4512         }
4513
4514         /* Default driver values are applied in the following cases:
4515          * - The resource allocation MB command is not supported by the MFW
4516          * - There is an internal error in the MFW while processing the request
4517          * - The resource ID is unknown to the MFW
4518          */
4519         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
4520                 DP_INFO(p_hwfn,
4521                         "Failed to receive allocation info for resource %d [%s]."
4522                         " mcp_resp = 0x%x. Applying default values"
4523                         " [%d,%d].\n",
4524                         res_id, ecore_hw_get_resc_name(res_id), mcp_resp,
4525                         dflt_resc_num, dflt_resc_start);
4526
4527                 *p_resc_num = dflt_resc_num;
4528                 *p_resc_start = dflt_resc_start;
4529                 goto out;
4530         }
4531
4532         if ((*p_resc_num != dflt_resc_num ||
4533              *p_resc_start != dflt_resc_start) &&
4534             res_id != ECORE_SB) {
4535                 DP_INFO(p_hwfn,
4536                         "MFW allocation for resource %d [%s] differs from default values [%d,%d vs. %d,%d]%s\n",
4537                         res_id, ecore_hw_get_resc_name(res_id), *p_resc_num,
4538                         *p_resc_start, dflt_resc_num, dflt_resc_start,
4539                         drv_resc_alloc ? " - Applying default values" : "");
4540                 if (drv_resc_alloc) {
4541                         *p_resc_num = dflt_resc_num;
4542                         *p_resc_start = dflt_resc_start;
4543                 }
4544         }
4545 out:
4546         return ECORE_SUCCESS;
4547 }
4548
4549 static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,
4550                                                    bool drv_resc_alloc)
4551 {
4552         enum _ecore_status_t rc;
4553         u8 res_id;
4554
4555         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++) {
4556                 rc = __ecore_hw_set_resc_info(p_hwfn, res_id, drv_resc_alloc);
4557                 if (rc != ECORE_SUCCESS)
4558                         return rc;
4559         }
4560
4561         return ECORE_SUCCESS;
4562 }
4563
4564 #define ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS 0xaa
4565 #define ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS 0x55
4566 #define ECORE_NONUSED_PPFID_MASK_AH_4P          0xf0
4567
4568 static enum _ecore_status_t ecore_hw_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,
4569                                                       struct ecore_ptt *p_ptt)
4570 {
4571         u8 native_ppfid_idx = ECORE_PPFID_BY_PFID(p_hwfn), new_bitmap;
4572         struct ecore_dev *p_dev = p_hwfn->p_dev;
4573         enum _ecore_status_t rc;
4574
4575         rc = ecore_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
4576         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL)
4577                 return rc;
4578         else if (rc == ECORE_NOTIMPL)
4579                 p_dev->ppfid_bitmap = 0x1 << native_ppfid_idx;
4580
4581         /* 4-ports mode has limitations that should be enforced:
4582          * - BB: the MFW can access only PPFIDs which their corresponding PFIDs
4583          *       belong to this certain port.
4584          * - AH/E5: only 4 PPFIDs per port are available.
4585          */
4586         if (ecore_device_num_ports(p_dev) == 4) {
4587                 u8 mask;
4588
4589                 if (ECORE_IS_BB(p_dev))
4590                         mask = MFW_PORT(p_hwfn) > 1 ?
4591                                ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS :
4592                                ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS;
4593                 else
4594                         mask = ECORE_NONUSED_PPFID_MASK_AH_4P;
4595
4596                 if (p_dev->ppfid_bitmap & mask) {
4597                         new_bitmap = p_dev->ppfid_bitmap & ~mask;
4598                         DP_INFO(p_hwfn,
4599                                 "Fix the PPFID bitmap for 4-ports mode: 0x%hhx -> 0x%hhx\n",
4600                                 p_dev->ppfid_bitmap, new_bitmap);
4601                         p_dev->ppfid_bitmap = new_bitmap;
4602                 }
4603         }
4604
4605         /* The native PPFID is expected to be part of the allocated bitmap */
4606         if (!(p_dev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
4607                 new_bitmap = 0x1 << native_ppfid_idx;
4608                 DP_INFO(p_hwfn,
4609                         "Fix the PPFID bitmap to inculde the native PPFID: %hhd -> 0x%hhx\n",
4610                         p_dev->ppfid_bitmap, new_bitmap);
4611                 p_dev->ppfid_bitmap = new_bitmap;
4612         }
4613
4614         return ECORE_SUCCESS;
4615 }
4616
4617 static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,
4618                                               struct ecore_ptt *p_ptt,
4619                                               bool drv_resc_alloc)
4620 {
4621         struct ecore_resc_unlock_params resc_unlock_params;
4622         struct ecore_resc_lock_params resc_lock_params;
4623         bool b_ah = ECORE_IS_AH(p_hwfn->p_dev);
4624         u8 res_id;
4625         enum _ecore_status_t rc;
4626 #ifndef ASIC_ONLY
4627         u32 *resc_start = p_hwfn->hw_info.resc_start;
4628         u32 *resc_num = p_hwfn->hw_info.resc_num;
4629         /* For AH, an equal share of the ILT lines between the maximal number of
4630          * PFs is not enough for RoCE. This would be solved by the future
4631          * resource allocation scheme, but isn't currently present for
4632          * FPGA/emulation. For now we keep a number that is sufficient for RoCE
4633          * to work - the BB number of ILT lines divided by its max PFs number.
4634          */
4635         u32 roce_min_ilt_lines = PXP_NUM_ILT_RECORDS_BB / MAX_NUM_PFS_BB;
4636 #endif
4637
4638         /* Setting the max values of the soft resources and the following
4639          * resources allocation queries should be atomic. Since several PFs can
4640          * run in parallel - a resource lock is needed.
4641          * If either the resource lock or resource set value commands are not
4642          * supported - skip the max values setting, release the lock if
4643          * needed, and proceed to the queries. Other failures, including a
4644          * failure to acquire the lock, will cause this function to fail.
4645          * Old drivers that don't acquire the lock can run in parallel, and
4646          * their allocation values won't be affected by the updated max values.
4647          */
4648         ecore_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
4649                                          ECORE_RESC_LOCK_RESC_ALLOC, false);
4650
4651         rc = ecore_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
4652         if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4653                 return rc;
4654         } else if (rc == ECORE_NOTIMPL) {
4655                 DP_INFO(p_hwfn,
4656                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
4657         } else if (rc == ECORE_SUCCESS && !resc_lock_params.b_granted) {
4658                 DP_NOTICE(p_hwfn, false,
4659                           "Failed to acquire the resource lock for the resource allocation commands\n");
4660                 rc = ECORE_BUSY;
4661                 goto unlock_and_exit;
4662         } else {
4663                 rc = ecore_hw_set_soft_resc_size(p_hwfn, p_ptt);
4664                 if (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {
4665                         DP_NOTICE(p_hwfn, false,
4666                                   "Failed to set the max values of the soft resources\n");
4667                         goto unlock_and_exit;
4668                 } else if (rc == ECORE_NOTIMPL) {
4669                         DP_INFO(p_hwfn,
4670                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
4671                         rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4672                                                    &resc_unlock_params);
4673                         if (rc != ECORE_SUCCESS)
4674                                 DP_INFO(p_hwfn,
4675                                         "Failed to release the resource lock for the resource allocation commands\n");
4676                 }
4677         }
4678
4679         rc = ecore_hw_set_resc_info(p_hwfn, drv_resc_alloc);
4680         if (rc != ECORE_SUCCESS)
4681                 goto unlock_and_exit;
4682
4683         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
4684                 rc = ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4685                                            &resc_unlock_params);
4686                 if (rc != ECORE_SUCCESS)
4687                         DP_INFO(p_hwfn,
4688                                 "Failed to release the resource lock for the resource allocation commands\n");
4689         }
4690
4691         /* PPFID bitmap */
4692         if (IS_LEAD_HWFN(p_hwfn)) {
4693                 rc = ecore_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
4694                 if (rc != ECORE_SUCCESS)
4695                         return rc;
4696         }
4697
4698 #ifndef ASIC_ONLY
4699         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
4700                 /* Reduced build contains less PQs */
4701                 if (!(p_hwfn->p_dev->b_is_emul_full)) {
4702                         resc_num[ECORE_PQ] = 32;
4703                         resc_start[ECORE_PQ] = resc_num[ECORE_PQ] *
4704                             p_hwfn->enabled_func_idx;
4705                 }
4706
4707                 /* For AH emulation, since we have a possible maximal number of
4708                  * 16 enabled PFs, in case there are not enough ILT lines -
4709                  * allocate only first PF as RoCE and have all the other ETH
4710                  * only with less ILT lines.
4711                  */
4712                 if (!p_hwfn->rel_pf_id && p_hwfn->p_dev->b_is_emul_full)
4713                         resc_num[ECORE_ILT] = OSAL_MAX_T(u32,
4714                                                          resc_num[ECORE_ILT],
4715                                                          roce_min_ilt_lines);
4716         }
4717
4718         /* Correct the common ILT calculation if PF0 has more */
4719         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev) &&
4720             p_hwfn->p_dev->b_is_emul_full &&
4721             p_hwfn->rel_pf_id && resc_num[ECORE_ILT] < roce_min_ilt_lines)
4722                 resc_start[ECORE_ILT] += roce_min_ilt_lines -
4723                     resc_num[ECORE_ILT];
4724 #endif
4725
4726         /* Sanity for ILT */
4727         if ((b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
4728             (!b_ah && (RESC_END(p_hwfn, ECORE_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
4729                 DP_NOTICE(p_hwfn, true,
4730                           "Can't assign ILT pages [%08x,...,%08x]\n",
4731                           RESC_START(p_hwfn, ECORE_ILT), RESC_END(p_hwfn,
4732                                                                   ECORE_ILT) -
4733                           1);
4734                 return ECORE_INVAL;
4735         }
4736
4737         /* This will also learn the number of SBs from MFW */
4738         if (ecore_int_igu_reset_cam(p_hwfn, p_ptt))
4739                 return ECORE_INVAL;
4740
4741         ecore_hw_set_feat(p_hwfn);
4742
4743         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
4744                    "The numbers for each resource are:\n");
4745         for (res_id = 0; res_id < ECORE_MAX_RESC; res_id++)
4746                 DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE, "%s = %d start = %d\n",
4747                            ecore_hw_get_resc_name(res_id),
4748                            RESC_NUM(p_hwfn, res_id),
4749                            RESC_START(p_hwfn, res_id));
4750
4751         return ECORE_SUCCESS;
4752
4753 unlock_and_exit:
4754         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
4755                 ecore_mcp_resc_unlock(p_hwfn, p_ptt,
4756                                       &resc_unlock_params);
4757         return rc;
4758 }
4759
4760 static enum _ecore_status_t
4761 ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
4762                       struct ecore_ptt *p_ptt,
4763                       struct ecore_hw_prepare_params *p_params)
4764 {
4765         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg, dcbx_mode;
4766         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
4767         struct ecore_mcp_link_capabilities *p_caps;
4768         struct ecore_mcp_link_params *link;
4769         enum _ecore_status_t rc;
4770
4771         /* Read global nvm_cfg address */
4772         nvm_cfg_addr = ecore_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
4773
4774         /* Verify MCP has initialized it */
4775         if (!nvm_cfg_addr) {
4776                 DP_NOTICE(p_hwfn, false, "Shared memory not initialized\n");
4777                 if (p_params->b_relaxed_probe)
4778                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_NVM;
4779                 return ECORE_INVAL;
4780         }
4781
4782 /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
4783
4784         nvm_cfg1_offset = ecore_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
4785
4786         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4787                    OFFSETOF(struct nvm_cfg1, glob) +
4788                    OFFSETOF(struct nvm_cfg1_glob, core_cfg);
4789
4790         core_cfg = ecore_rd(p_hwfn, p_ptt, addr);
4791
4792         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
4793                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
4794         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
4795                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X40G;
4796                 break;
4797         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4798                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X50G;
4799                 break;
4800         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4801                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X100G;
4802                 break;
4803         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4804                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_F;
4805                 break;
4806         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4807                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X10G_E;
4808                 break;
4809         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4810                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X20G;
4811                 break;
4812         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4813                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X40G;
4814                 break;
4815         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4816                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X25G;
4817                 break;
4818         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4819                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_2X10G;
4820                 break;
4821         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4822                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_1X25G;
4823                 break;
4824         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4825                 p_hwfn->hw_info.port_mode = ECORE_PORT_MODE_DE_4X25G;
4826                 break;
4827         default:
4828                 DP_NOTICE(p_hwfn, true, "Unknown port mode in 0x%08x\n",
4829                           core_cfg);
4830                 break;
4831         }
4832
4833         /* Read DCBX configuration */
4834         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4835                         OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4836         dcbx_mode = ecore_rd(p_hwfn, p_ptt,
4837                              port_cfg_addr +
4838                              OFFSETOF(struct nvm_cfg1_port, generic_cont0));
4839         dcbx_mode = (dcbx_mode & NVM_CFG1_PORT_DCBX_MODE_MASK)
4840                 >> NVM_CFG1_PORT_DCBX_MODE_OFFSET;
4841         switch (dcbx_mode) {
4842         case NVM_CFG1_PORT_DCBX_MODE_DYNAMIC:
4843                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DYNAMIC;
4844                 break;
4845         case NVM_CFG1_PORT_DCBX_MODE_CEE:
4846                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_CEE;
4847                 break;
4848         case NVM_CFG1_PORT_DCBX_MODE_IEEE:
4849                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_IEEE;
4850                 break;
4851         default:
4852                 p_hwfn->hw_info.dcbx_mode = ECORE_DCBX_VERSION_DISABLED;
4853         }
4854
4855         /* Read default link configuration */
4856         link = &p_hwfn->mcp_info->link_input;
4857         p_caps = &p_hwfn->mcp_info->link_capabilities;
4858         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4859             OFFSETOF(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4860         link_temp = ecore_rd(p_hwfn, p_ptt,
4861                              port_cfg_addr +
4862                              OFFSETOF(struct nvm_cfg1_port, speed_cap_mask));
4863         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4864         link->speed.advertised_speeds = link_temp;
4865         p_caps->speed_capabilities = link->speed.advertised_speeds;
4866
4867         link_temp = ecore_rd(p_hwfn, p_ptt,
4868                                  port_cfg_addr +
4869                                  OFFSETOF(struct nvm_cfg1_port, link_settings));
4870         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
4871                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
4872         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
4873                 link->speed.autoneg = true;
4874                 break;
4875         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
4876                 link->speed.forced_speed = 1000;
4877                 break;
4878         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
4879                 link->speed.forced_speed = 10000;
4880                 break;
4881         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
4882                 link->speed.forced_speed = 25000;
4883                 break;
4884         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
4885                 link->speed.forced_speed = 40000;
4886                 break;
4887         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
4888                 link->speed.forced_speed = 50000;
4889                 break;
4890         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
4891                 link->speed.forced_speed = 100000;
4892                 break;
4893         default:
4894                 DP_NOTICE(p_hwfn, true, "Unknown Speed in 0x%08x\n", link_temp);
4895         }
4896
4897         p_caps->default_speed = link->speed.forced_speed;
4898         p_caps->default_speed_autoneg = link->speed.autoneg;
4899
4900         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
4901         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
4902         link->pause.autoneg = !!(link_temp &
4903                                   NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
4904         link->pause.forced_rx = !!(link_temp &
4905                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
4906         link->pause.forced_tx = !!(link_temp &
4907                                     NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
4908         link->loopback_mode = 0;
4909
4910         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
4911                 link_temp = ecore_rd(p_hwfn, p_ptt, port_cfg_addr +
4912                                      OFFSETOF(struct nvm_cfg1_port, ext_phy));
4913                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
4914                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
4915                 p_caps->default_eee = ECORE_MCP_EEE_ENABLED;
4916                 link->eee.enable = true;
4917                 switch (link_temp) {
4918                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
4919                         p_caps->default_eee = ECORE_MCP_EEE_DISABLED;
4920                         link->eee.enable = false;
4921                         break;
4922                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
4923                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
4924                         break;
4925                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
4926                         p_caps->eee_lpi_timer =
4927                                 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
4928                         break;
4929                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
4930                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
4931                         break;
4932                 }
4933
4934                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
4935                 link->eee.tx_lpi_enable = link->eee.enable;
4936                 link->eee.adv_caps = ECORE_EEE_1G_ADV | ECORE_EEE_10G_ADV;
4937         } else {
4938                 p_caps->default_eee = ECORE_MCP_EEE_UNSUPPORTED;
4939         }
4940
4941         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
4942                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n EEE: %02x [%08x usec]",
4943                    link->speed.forced_speed, link->speed.advertised_speeds,
4944                    link->speed.autoneg, link->pause.autoneg,
4945                    p_caps->default_eee, p_caps->eee_lpi_timer);
4946
4947         /* Read Multi-function information from shmem */
4948         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4949                    OFFSETOF(struct nvm_cfg1, glob) +
4950                    OFFSETOF(struct nvm_cfg1_glob, generic_cont0);
4951
4952         generic_cont0 = ecore_rd(p_hwfn, p_ptt, addr);
4953
4954         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
4955             NVM_CFG1_GLOB_MF_MODE_OFFSET;
4956
4957         switch (mf_mode) {
4958         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
4959                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS;
4960                 break;
4961         case NVM_CFG1_GLOB_MF_MODE_UFP:
4962                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
4963                                          1 << ECORE_MF_UFP_SPECIFIC |
4964                                          1 << ECORE_MF_8021Q_TAGGING;
4965                 break;
4966         case NVM_CFG1_GLOB_MF_MODE_BD:
4967                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
4968                                          1 << ECORE_MF_LLH_PROTO_CLSS |
4969                                          1 << ECORE_MF_8021AD_TAGGING |
4970                                          1 << ECORE_MF_FIP_SPECIAL;
4971                 break;
4972         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
4973                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
4974                                          1 << ECORE_MF_LLH_PROTO_CLSS |
4975                                          1 << ECORE_MF_LL2_NON_UNICAST |
4976                                          1 << ECORE_MF_INTER_PF_SWITCH |
4977                                          1 << ECORE_MF_DISABLE_ARFS;
4978                 break;
4979         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
4980                 p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
4981                                          1 << ECORE_MF_LLH_PROTO_CLSS |
4982                                          1 << ECORE_MF_LL2_NON_UNICAST;
4983                 if (ECORE_IS_BB(p_hwfn->p_dev))
4984                         p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
4985                 break;
4986         }
4987         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4988                 p_hwfn->p_dev->mf_bits);
4989
4990         if (ECORE_IS_CMT(p_hwfn->p_dev))
4991                 p_hwfn->p_dev->mf_bits |= (1 << ECORE_MF_DISABLE_ARFS);
4992
4993         /* It's funny since we have another switch, but it's easier
4994          * to throw this away in linux this way. Long term, it might be
4995          * better to have have getters for needed ECORE_MF_* fields,
4996          * convert client code and eliminate this.
4997          */
4998         switch (mf_mode) {
4999         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
5000         case NVM_CFG1_GLOB_MF_MODE_BD:
5001                 p_hwfn->p_dev->mf_mode = ECORE_MF_OVLAN;
5002                 break;
5003         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
5004                 p_hwfn->p_dev->mf_mode = ECORE_MF_NPAR;
5005                 break;
5006         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
5007                 p_hwfn->p_dev->mf_mode = ECORE_MF_DEFAULT;
5008                 break;
5009         case NVM_CFG1_GLOB_MF_MODE_UFP:
5010                 p_hwfn->p_dev->mf_mode = ECORE_MF_UFP;
5011                 break;
5012         }
5013
5014         /* Read Multi-function information from shmem */
5015         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
5016                    OFFSETOF(struct nvm_cfg1, glob) +
5017                    OFFSETOF(struct nvm_cfg1_glob, device_capabilities);
5018
5019         device_capabilities = ecore_rd(p_hwfn, p_ptt, addr);
5020         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
5021                 OSAL_SET_BIT(ECORE_DEV_CAP_ETH,
5022                                 &p_hwfn->hw_info.device_capabilities);
5023         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
5024                 OSAL_SET_BIT(ECORE_DEV_CAP_FCOE,
5025                                 &p_hwfn->hw_info.device_capabilities);
5026         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
5027                 OSAL_SET_BIT(ECORE_DEV_CAP_ISCSI,
5028                                 &p_hwfn->hw_info.device_capabilities);
5029         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
5030                 OSAL_SET_BIT(ECORE_DEV_CAP_ROCE,
5031                                 &p_hwfn->hw_info.device_capabilities);
5032         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP)
5033                 OSAL_SET_BIT(ECORE_DEV_CAP_IWARP,
5034                                 &p_hwfn->hw_info.device_capabilities);
5035
5036         rc = ecore_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
5037         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5038                 rc = ECORE_SUCCESS;
5039                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5040         }
5041
5042         return rc;
5043 }
5044
5045 static void ecore_get_num_funcs(struct ecore_hwfn *p_hwfn,
5046                                 struct ecore_ptt *p_ptt)
5047 {
5048         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
5049         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
5050         struct ecore_dev *p_dev = p_hwfn->p_dev;
5051
5052         num_funcs = ECORE_IS_AH(p_dev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
5053
5054         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
5055          * in the other bits are selected.
5056          * Bits 1-15 are for functions 1-15, respectively, and their value is
5057          * '0' only for enabled functions (function 0 always exists and
5058          * enabled).
5059          * In case of CMT in BB, only the "even" functions are enabled, and thus
5060          * the number of functions for both hwfns is learnt from the same bits.
5061          */
5062         if (ECORE_IS_BB(p_dev) || ECORE_IS_AH(p_dev)) {
5063                 reg_function_hide = ecore_rd(p_hwfn, p_ptt,
5064                                              MISCS_REG_FUNCTION_HIDE_BB_K2);
5065         } else { /* E5 */
5066                 reg_function_hide = 0;
5067         }
5068
5069         if (reg_function_hide & 0x1) {
5070                 if (ECORE_IS_BB(p_dev)) {
5071                         if (ECORE_PATH_ID(p_hwfn) && !ECORE_IS_CMT(p_dev)) {
5072                                 num_funcs = 0;
5073                                 eng_mask = 0xaaaa;
5074                         } else {
5075                                 num_funcs = 1;
5076                                 eng_mask = 0x5554;
5077                         }
5078                 } else {
5079                         num_funcs = 1;
5080                         eng_mask = 0xfffe;
5081                 }
5082
5083                 /* Get the number of the enabled functions on the engine */
5084                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
5085                 while (tmp) {
5086                         if (tmp & 0x1)
5087                                 num_funcs++;
5088                         tmp >>= 0x1;
5089                 }
5090
5091                 /* Get the PF index within the enabled functions */
5092                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
5093                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
5094                 while (tmp) {
5095                         if (tmp & 0x1)
5096                                 enabled_func_idx--;
5097                         tmp >>= 0x1;
5098                 }
5099         }
5100
5101         p_hwfn->num_funcs_on_engine = num_funcs;
5102         p_hwfn->enabled_func_idx = enabled_func_idx;
5103
5104 #ifndef ASIC_ONLY
5105         if (CHIP_REV_IS_FPGA(p_dev)) {
5106                 DP_NOTICE(p_hwfn, false,
5107                           "FPGA: Limit number of PFs to 4 [would affect resource allocation, needed for IOV]\n");
5108                 p_hwfn->num_funcs_on_engine = 4;
5109         }
5110 #endif
5111
5112         DP_VERBOSE(p_hwfn, ECORE_MSG_PROBE,
5113                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
5114                    p_hwfn->rel_pf_id, p_hwfn->abs_pf_id,
5115                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
5116 }
5117
5118 static void ecore_hw_info_port_num_bb(struct ecore_hwfn *p_hwfn,
5119                                       struct ecore_ptt *p_ptt)
5120 {
5121         struct ecore_dev *p_dev = p_hwfn->p_dev;
5122         u32 port_mode;
5123
5124 #ifndef ASIC_ONLY
5125         /* Read the port mode */
5126         if (CHIP_REV_IS_FPGA(p_dev))
5127                 port_mode = 4;
5128         else if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_CMT(p_dev))
5129                 /* In CMT on emulation, assume 1 port */
5130                 port_mode = 1;
5131         else
5132 #endif
5133         port_mode = ecore_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
5134
5135         if (port_mode < 3) {
5136                 p_dev->num_ports_in_engine = 1;
5137         } else if (port_mode <= 5) {
5138                 p_dev->num_ports_in_engine = 2;
5139         } else {
5140                 DP_NOTICE(p_hwfn, true, "PORT MODE: %d not supported\n",
5141                           p_dev->num_ports_in_engine);
5142
5143                 /* Default num_ports_in_engine to something */
5144                 p_dev->num_ports_in_engine = 1;
5145         }
5146 }
5147
5148 static void ecore_hw_info_port_num_ah_e5(struct ecore_hwfn *p_hwfn,
5149                                          struct ecore_ptt *p_ptt)
5150 {
5151         struct ecore_dev *p_dev = p_hwfn->p_dev;
5152         u32 port;
5153         int i;
5154
5155         p_dev->num_ports_in_engine = 0;
5156
5157 #ifndef ASIC_ONLY
5158         if (CHIP_REV_IS_EMUL(p_dev)) {
5159                 port = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5160                 switch ((port & 0xf000) >> 12) {
5161                 case 1:
5162                         p_dev->num_ports_in_engine = 1;
5163                         break;
5164                 case 3:
5165                         p_dev->num_ports_in_engine = 2;
5166                         break;
5167                 case 0xf:
5168                         p_dev->num_ports_in_engine = 4;
5169                         break;
5170                 default:
5171                         DP_NOTICE(p_hwfn, false,
5172                                   "Unknown port mode in ECO_RESERVED %08x\n",
5173                                   port);
5174                 }
5175         } else
5176 #endif
5177                 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
5178                         port = ecore_rd(p_hwfn, p_ptt,
5179                                         CNIG_REG_NIG_PORT0_CONF_K2_E5 +
5180                                         (i * 4));
5181                         if (port & 1)
5182                                 p_dev->num_ports_in_engine++;
5183                 }
5184
5185         if (!p_dev->num_ports_in_engine) {
5186                 DP_NOTICE(p_hwfn, true, "All NIG ports are inactive\n");
5187
5188                 /* Default num_ports_in_engine to something */
5189                 p_dev->num_ports_in_engine = 1;
5190         }
5191 }
5192
5193 static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
5194                                    struct ecore_ptt *p_ptt)
5195 {
5196         struct ecore_dev *p_dev = p_hwfn->p_dev;
5197
5198         /* Determine the number of ports per engine */
5199         if (ECORE_IS_BB(p_dev))
5200                 ecore_hw_info_port_num_bb(p_hwfn, p_ptt);
5201         else
5202                 ecore_hw_info_port_num_ah_e5(p_hwfn, p_ptt);
5203
5204         /* Get the total number of ports of the device */
5205         if (ECORE_IS_CMT(p_dev)) {
5206                 /* In CMT there is always only one port */
5207                 p_dev->num_ports = 1;
5208 #ifndef ASIC_ONLY
5209         } else if (CHIP_REV_IS_EMUL(p_dev) || CHIP_REV_IS_TEDIBEAR(p_dev)) {
5210                 p_dev->num_ports = p_dev->num_ports_in_engine *
5211                                    ecore_device_num_engines(p_dev);
5212 #endif
5213         } else {
5214                 u32 addr, global_offsize, global_addr;
5215
5216                 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
5217                                             PUBLIC_GLOBAL);
5218                 global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
5219                 global_addr = SECTION_ADDR(global_offsize, 0);
5220                 addr = global_addr + OFFSETOF(struct public_global, max_ports);
5221                 p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
5222         }
5223 }
5224
5225 static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
5226                                    struct ecore_ptt *p_ptt)
5227 {
5228         struct ecore_mcp_link_capabilities *p_caps;
5229         u32 eee_status;
5230
5231         p_caps = &p_hwfn->mcp_info->link_capabilities;
5232         if (p_caps->default_eee == ECORE_MCP_EEE_UNSUPPORTED)
5233                 return;
5234
5235         p_caps->eee_speed_caps = 0;
5236         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
5237                               OFFSETOF(struct public_port, eee_status));
5238         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
5239                         EEE_SUPPORTED_SPEED_OFFSET;
5240         if (eee_status & EEE_1G_SUPPORTED)
5241                 p_caps->eee_speed_caps |= ECORE_EEE_1G_ADV;
5242         if (eee_status & EEE_10G_ADV)
5243                 p_caps->eee_speed_caps |= ECORE_EEE_10G_ADV;
5244 }
5245
5246 static enum _ecore_status_t
5247 ecore_get_hw_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
5248                   enum ecore_pci_personality personality,
5249                   struct ecore_hw_prepare_params *p_params)
5250 {
5251         bool drv_resc_alloc = p_params->drv_resc_alloc;
5252         enum _ecore_status_t rc;
5253
5254         if (IS_ECORE_PACING(p_hwfn)) {
5255                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_IOV,
5256                            "Skipping IOV as packet pacing is requested\n");
5257         }
5258
5259         /* Since all information is common, only first hwfns should do this */
5260         if (IS_LEAD_HWFN(p_hwfn) && !IS_ECORE_PACING(p_hwfn)) {
5261                 rc = ecore_iov_hw_info(p_hwfn);
5262                 if (rc != ECORE_SUCCESS) {
5263                         if (p_params->b_relaxed_probe)
5264                                 p_params->p_relaxed_res =
5265                                                 ECORE_HW_PREPARE_BAD_IOV;
5266                         else
5267                                 return rc;
5268                 }
5269         }
5270
5271         if (IS_LEAD_HWFN(p_hwfn))
5272                 ecore_hw_info_port_num(p_hwfn, p_ptt);
5273
5274         ecore_mcp_get_capabilities(p_hwfn, p_ptt);
5275
5276 #ifndef ASIC_ONLY
5277         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev)) {
5278 #endif
5279         rc = ecore_hw_get_nvm_info(p_hwfn, p_ptt, p_params);
5280         if (rc != ECORE_SUCCESS)
5281                 return rc;
5282 #ifndef ASIC_ONLY
5283         }
5284 #endif
5285
5286         rc = ecore_int_igu_read_cam(p_hwfn, p_ptt);
5287         if (rc != ECORE_SUCCESS) {
5288                 if (p_params->b_relaxed_probe)
5289                         p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_IGU;
5290                 else
5291                         return rc;
5292         }
5293
5294 #ifndef ASIC_ONLY
5295         if (CHIP_REV_IS_ASIC(p_hwfn->p_dev) && ecore_mcp_is_init(p_hwfn)) {
5296 #endif
5297                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr,
5298                             p_hwfn->mcp_info->func_info.mac, ETH_ALEN);
5299 #ifndef ASIC_ONLY
5300         } else {
5301                 static u8 mcp_hw_mac[6] = { 0, 2, 3, 4, 5, 6 };
5302
5303                 OSAL_MEMCPY(p_hwfn->hw_info.hw_mac_addr, mcp_hw_mac, ETH_ALEN);
5304                 p_hwfn->hw_info.hw_mac_addr[5] = p_hwfn->abs_pf_id;
5305         }
5306 #endif
5307
5308         if (ecore_mcp_is_init(p_hwfn)) {
5309                 if (p_hwfn->mcp_info->func_info.ovlan != ECORE_MCP_VLAN_UNSET)
5310                         p_hwfn->hw_info.ovlan =
5311                             p_hwfn->mcp_info->func_info.ovlan;
5312
5313                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
5314
5315                 ecore_mcp_get_eee_caps(p_hwfn, p_ptt);
5316
5317                 ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
5318         }
5319
5320         if (personality != ECORE_PCI_DEFAULT) {
5321                 p_hwfn->hw_info.personality = personality;
5322         } else if (ecore_mcp_is_init(p_hwfn)) {
5323                 enum ecore_pci_personality protocol;
5324
5325                 protocol = p_hwfn->mcp_info->func_info.protocol;
5326                 p_hwfn->hw_info.personality = protocol;
5327         }
5328
5329 #ifndef ASIC_ONLY
5330         /* To overcome ILT lack for emulation, until at least until we'll have
5331          * a definite answer from system about it, allow only PF0 to be RoCE.
5332          */
5333         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev)) {
5334                 if (!p_hwfn->rel_pf_id)
5335                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
5336                 else
5337                         p_hwfn->hw_info.personality = ECORE_PCI_ETH;
5338         }
5339 #endif
5340
5341         /* although in BB some constellations may support more than 4 tcs,
5342          * that can result in performance penalty in some cases. 4
5343          * represents a good tradeoff between performance and flexibility.
5344          */
5345         if (IS_ECORE_PACING(p_hwfn))
5346                 p_hwfn->hw_info.num_hw_tc = 1;
5347         else
5348                 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
5349
5350         /* start out with a single active tc. This can be increased either
5351          * by dcbx negotiation or by upper layer driver
5352          */
5353         p_hwfn->hw_info.num_active_tc = 1;
5354
5355         ecore_get_num_funcs(p_hwfn, p_ptt);
5356
5357         if (ecore_mcp_is_init(p_hwfn))
5358                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
5359
5360         /* In case of forcing the driver's default resource allocation, calling
5361          * ecore_hw_get_resc() should come after initializing the personality
5362          * and after getting the number of functions, since the calculation of
5363          * the resources/features depends on them.
5364          * This order is not harmful if not forcing.
5365          */
5366         rc = ecore_hw_get_resc(p_hwfn, p_ptt, drv_resc_alloc);
5367         if (rc != ECORE_SUCCESS && p_params->b_relaxed_probe) {
5368                 rc = ECORE_SUCCESS;
5369                 p_params->p_relaxed_res = ECORE_HW_PREPARE_BAD_MCP;
5370         }
5371
5372         return rc;
5373 }
5374
5375 static enum _ecore_status_t ecore_get_dev_info(struct ecore_hwfn *p_hwfn,
5376                                                struct ecore_ptt *p_ptt)
5377 {
5378         struct ecore_dev *p_dev = p_hwfn->p_dev;
5379         u16 device_id_mask;
5380         u32 tmp;
5381
5382         /* Read Vendor Id / Device Id */
5383         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
5384                                   &p_dev->vendor_id);
5385         OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
5386                                   &p_dev->device_id);
5387
5388         /* Determine type */
5389         device_id_mask = p_dev->device_id & ECORE_DEV_ID_MASK;
5390         switch (device_id_mask) {
5391         case ECORE_DEV_ID_MASK_BB:
5392                 p_dev->type = ECORE_DEV_TYPE_BB;
5393                 break;
5394         case ECORE_DEV_ID_MASK_AH:
5395                 p_dev->type = ECORE_DEV_TYPE_AH;
5396                 break;
5397         default:
5398                 DP_NOTICE(p_hwfn, true, "Unknown device id 0x%x\n",
5399                           p_dev->device_id);
5400                 return ECORE_ABORTED;
5401         }
5402
5403         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
5404         p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM);
5405         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
5406         p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV);
5407
5408         /* Learn number of HW-functions */
5409         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
5410
5411         if (tmp & (1 << p_hwfn->rel_pf_id)) {
5412                 DP_NOTICE(p_dev->hwfns, false, "device in CMT mode\n");
5413                 p_dev->num_hwfns = 2;
5414         } else {
5415                 p_dev->num_hwfns = 1;
5416         }
5417
5418 #ifndef ASIC_ONLY
5419         if (CHIP_REV_IS_EMUL(p_dev)) {
5420                 /* For some reason we have problems with this register
5421                  * in B0 emulation; Simply assume no CMT
5422                  */
5423                 DP_NOTICE(p_dev->hwfns, false,
5424                           "device on emul - assume no CMT\n");
5425                 p_dev->num_hwfns = 1;
5426         }
5427 #endif
5428
5429         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_TEST_REG);
5430         p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID);
5431         tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
5432         p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL);
5433
5434         DP_INFO(p_dev->hwfns,
5435                 "Chip details - %s %c%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n",
5436                 ECORE_IS_BB(p_dev) ? "BB" : "AH",
5437                 'A' + p_dev->chip_rev, (int)p_dev->chip_metal,
5438                 p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id,
5439                 p_dev->chip_metal);
5440
5441         if (ECORE_IS_BB_A0(p_dev)) {
5442                 DP_NOTICE(p_dev->hwfns, false,
5443                           "The chip type/rev (BB A0) is not supported!\n");
5444                 return ECORE_ABORTED;
5445         }
5446 #ifndef ASIC_ONLY
5447         if (CHIP_REV_IS_EMUL(p_dev) && ECORE_IS_AH(p_dev))
5448                 ecore_wr(p_hwfn, p_ptt, MISCS_REG_PLL_MAIN_CTRL_4, 0x1);
5449
5450         if (CHIP_REV_IS_EMUL(p_dev)) {
5451                 tmp = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
5452                 if (tmp & (1 << 29)) {
5453                         DP_NOTICE(p_hwfn, false,
5454                                   "Emulation: Running on a FULL build\n");
5455                         p_dev->b_is_emul_full = true;
5456                 } else {
5457                         DP_NOTICE(p_hwfn, false,
5458                                   "Emulation: Running on a REDUCED build\n");
5459                 }
5460         }
5461 #endif
5462
5463         return ECORE_SUCCESS;
5464 }
5465
5466 #ifndef LINUX_REMOVE
5467 void ecore_prepare_hibernate(struct ecore_dev *p_dev)
5468 {
5469         int j;
5470
5471         if (IS_VF(p_dev))
5472                 return;
5473
5474         for_each_hwfn(p_dev, j) {
5475                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[j];
5476
5477                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFDOWN,
5478                            "Mark hw/fw uninitialized\n");
5479
5480                 p_hwfn->hw_init_done = false;
5481
5482                 ecore_ptt_invalidate(p_hwfn);
5483         }
5484 }
5485 #endif
5486
5487 static enum _ecore_status_t
5488 ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
5489                         void OSAL_IOMEM *p_doorbells, u64 db_phys_addr,
5490                         struct ecore_hw_prepare_params *p_params)
5491 {
5492         struct ecore_mdump_retain_data mdump_retain;
5493         struct ecore_dev *p_dev = p_hwfn->p_dev;
5494         struct ecore_mdump_info mdump_info;
5495         enum _ecore_status_t rc = ECORE_SUCCESS;
5496
5497         /* Split PCI bars evenly between hwfns */
5498         p_hwfn->regview = p_regview;
5499         p_hwfn->doorbells = p_doorbells;
5500         p_hwfn->db_phys_addr = db_phys_addr;
5501
5502         if (IS_VF(p_dev))
5503                 return ecore_vf_hw_prepare(p_hwfn);
5504
5505         /* Validate that chip access is feasible */
5506         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
5507                 DP_ERR(p_hwfn,
5508                        "Reading the ME register returns all Fs; Preventing further chip access\n");
5509                 if (p_params->b_relaxed_probe)
5510                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_ME;
5511                 return ECORE_INVAL;
5512         }
5513
5514         get_function_id(p_hwfn);
5515
5516         /* Allocate PTT pool */
5517         rc = ecore_ptt_pool_alloc(p_hwfn);
5518         if (rc) {
5519                 DP_NOTICE(p_hwfn, false, "Failed to prepare hwfn's hw\n");
5520                 if (p_params->b_relaxed_probe)
5521                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5522                 goto err0;
5523         }
5524
5525         /* Allocate the main PTT */
5526         p_hwfn->p_main_ptt = ecore_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
5527
5528         /* First hwfn learns basic information, e.g., number of hwfns */
5529         if (!p_hwfn->my_id) {
5530                 rc = ecore_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
5531                 if (rc != ECORE_SUCCESS) {
5532                         if (p_params->b_relaxed_probe)
5533                                 p_params->p_relaxed_res =
5534                                         ECORE_HW_PREPARE_FAILED_DEV;
5535                         goto err1;
5536                 }
5537         }
5538
5539         ecore_hw_hwfn_prepare(p_hwfn);
5540
5541         /* Initialize MCP structure */
5542         rc = ecore_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
5543         if (rc) {
5544                 DP_NOTICE(p_hwfn, false, "Failed initializing mcp command\n");
5545                 if (p_params->b_relaxed_probe)
5546                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5547                 goto err1;
5548         }
5549
5550         /* Read the device configuration information from the HW and SHMEM */
5551         rc = ecore_get_hw_info(p_hwfn, p_hwfn->p_main_ptt,
5552                                p_params->personality, p_params);
5553         if (rc) {
5554                 DP_NOTICE(p_hwfn, false, "Failed to get HW information\n");
5555                 goto err2;
5556         }
5557
5558         /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
5559          * called, since among others it sets the ports number in an engine.
5560          */
5561         if (p_params->initiate_pf_flr && IS_LEAD_HWFN(p_hwfn) &&
5562             !p_dev->recov_in_prog) {
5563                 rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
5564                 if (rc != ECORE_SUCCESS)
5565                         DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
5566
5567                 /* Workaround for MFW issue where PF FLR does not cleanup
5568                  * IGU block
5569                  */
5570                 if (!(p_hwfn->mcp_info->capabilities &
5571                       FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
5572                         ecore_pf_flr_igu_cleanup(p_hwfn);
5573         }
5574
5575         /* Check if mdump logs/data are present and update the epoch value */
5576         if (IS_LEAD_HWFN(p_hwfn)) {
5577 #ifndef ASIC_ONLY
5578                 if (!CHIP_REV_IS_EMUL(p_dev)) {
5579 #endif
5580                 rc = ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt,
5581                                               &mdump_info);
5582                 if (rc == ECORE_SUCCESS && mdump_info.num_of_logs)
5583                         DP_NOTICE(p_hwfn, false,
5584                                   "* * * IMPORTANT - HW ERROR register dump captured by device * * *\n");
5585
5586                 rc = ecore_mcp_mdump_get_retain(p_hwfn, p_hwfn->p_main_ptt,
5587                                                 &mdump_retain);
5588                 if (rc == ECORE_SUCCESS && mdump_retain.valid)
5589                         DP_NOTICE(p_hwfn, false,
5590                                   "mdump retained data: epoch 0x%08x, pf 0x%x, status 0x%08x\n",
5591                                   mdump_retain.epoch, mdump_retain.pf,
5592                                   mdump_retain.status);
5593
5594                 ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
5595                                            p_params->epoch);
5596 #ifndef ASIC_ONLY
5597                 }
5598 #endif
5599         }
5600
5601         /* Allocate the init RT array and initialize the init-ops engine */
5602         rc = ecore_init_alloc(p_hwfn);
5603         if (rc) {
5604                 DP_NOTICE(p_hwfn, false, "Failed to allocate the init array\n");
5605                 if (p_params->b_relaxed_probe)
5606                         p_params->p_relaxed_res = ECORE_HW_PREPARE_FAILED_MEM;
5607                 goto err2;
5608         }
5609 #ifndef ASIC_ONLY
5610         if (CHIP_REV_IS_FPGA(p_dev)) {
5611                 DP_NOTICE(p_hwfn, false,
5612                           "FPGA: workaround; Prevent DMAE parities\n");
5613                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK_K2_E5,
5614                          7);
5615
5616                 DP_NOTICE(p_hwfn, false,
5617                           "FPGA: workaround: Set VF bar0 size\n");
5618                 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
5619                          PGLUE_B_REG_VF_BAR0_SIZE_K2_E5, 4);
5620         }
5621 #endif
5622
5623         return rc;
5624 err2:
5625         if (IS_LEAD_HWFN(p_hwfn))
5626                 ecore_iov_free_hw_info(p_dev);
5627         ecore_mcp_free(p_hwfn);
5628 err1:
5629         ecore_hw_hwfn_free(p_hwfn);
5630 err0:
5631         return rc;
5632 }
5633
5634 enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
5635                                       struct ecore_hw_prepare_params *p_params)
5636 {
5637         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5638         enum _ecore_status_t rc;
5639
5640         p_dev->chk_reg_fifo = p_params->chk_reg_fifo;
5641         p_dev->allow_mdump = p_params->allow_mdump;
5642         p_hwfn->b_en_pacing = p_params->b_en_pacing;
5643         p_dev->b_is_target = p_params->b_is_target;
5644
5645         if (p_params->b_relaxed_probe)
5646                 p_params->p_relaxed_res = ECORE_HW_PREPARE_SUCCESS;
5647
5648         /* Store the precompiled init data ptrs */
5649         if (IS_PF(p_dev))
5650                 ecore_init_iro_array(p_dev);
5651
5652         /* Initialize the first hwfn - will learn number of hwfns */
5653         rc = ecore_hw_prepare_single(p_hwfn, p_dev->regview,
5654                                      p_dev->doorbells, p_dev->db_phys_addr,
5655                                      p_params);
5656         if (rc != ECORE_SUCCESS)
5657                 return rc;
5658
5659         p_params->personality = p_hwfn->hw_info.personality;
5660
5661         /* initilalize 2nd hwfn if necessary */
5662         if (ECORE_IS_CMT(p_dev)) {
5663                 void OSAL_IOMEM *p_regview, *p_doorbell;
5664                 u8 OSAL_IOMEM *addr;
5665                 u64 db_phys_addr;
5666                 u32 offset;
5667
5668                 /* adjust bar offset for second engine */
5669                 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
5670                                            BAR_ID_0) / 2;
5671                 addr = (u8 OSAL_IOMEM *)p_dev->regview + offset;
5672                 p_regview = (void OSAL_IOMEM *)addr;
5673
5674                 offset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
5675                                            BAR_ID_1) / 2;
5676                 addr = (u8 OSAL_IOMEM *)p_dev->doorbells + offset;
5677                 p_doorbell = (void OSAL_IOMEM *)addr;
5678                 db_phys_addr = p_dev->db_phys_addr + offset;
5679
5680                 p_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;
5681                 /* prepare second hw function */
5682                 rc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,
5683                                              p_doorbell, db_phys_addr,
5684                                              p_params);
5685
5686                 /* in case of error, need to free the previously
5687                  * initiliazed hwfn 0.
5688                  */
5689                 if (rc != ECORE_SUCCESS) {
5690                         if (p_params->b_relaxed_probe)
5691                                 p_params->p_relaxed_res =
5692                                                 ECORE_HW_PREPARE_FAILED_ENG2;
5693
5694                         if (IS_PF(p_dev)) {
5695                                 ecore_init_free(p_hwfn);
5696                                 ecore_mcp_free(p_hwfn);
5697                                 ecore_hw_hwfn_free(p_hwfn);
5698                         } else {
5699                                 DP_NOTICE(p_dev, false, "What do we need to free when VF hwfn1 init fails\n");
5700                         }
5701                         return rc;
5702                 }
5703         }
5704
5705         return rc;
5706 }
5707
5708 void ecore_hw_remove(struct ecore_dev *p_dev)
5709 {
5710         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
5711         int i;
5712
5713         if (IS_PF(p_dev))
5714                 ecore_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
5715                                         ECORE_OV_DRIVER_STATE_NOT_LOADED);
5716
5717         for_each_hwfn(p_dev, i) {
5718                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
5719
5720                 if (IS_VF(p_dev)) {
5721                         ecore_vf_pf_release(p_hwfn);
5722                         continue;
5723                 }
5724
5725                 ecore_init_free(p_hwfn);
5726                 ecore_hw_hwfn_free(p_hwfn);
5727                 ecore_mcp_free(p_hwfn);
5728
5729 #ifdef CONFIG_ECORE_LOCK_ALLOC
5730                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->dmae_info.lock);
5731 #endif
5732         }
5733
5734         ecore_iov_free_hw_info(p_dev);
5735 }
5736
5737 static void ecore_chain_free_next_ptr(struct ecore_dev *p_dev,
5738                                       struct ecore_chain *p_chain)
5739 {
5740         void *p_virt = p_chain->p_virt_addr, *p_virt_next = OSAL_NULL;
5741         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
5742         struct ecore_chain_next *p_next;
5743         u32 size, i;
5744
5745         if (!p_virt)
5746                 return;
5747
5748         size = p_chain->elem_size * p_chain->usable_per_page;
5749
5750         for (i = 0; i < p_chain->page_cnt; i++) {
5751                 if (!p_virt)
5752                         break;
5753
5754                 p_next = (struct ecore_chain_next *)((u8 *)p_virt + size);
5755                 p_virt_next = p_next->next_virt;
5756                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
5757
5758                 OSAL_DMA_FREE_COHERENT(p_dev, p_virt, p_phys,
5759                                        ECORE_CHAIN_PAGE_SIZE);
5760
5761                 p_virt = p_virt_next;
5762                 p_phys = p_phys_next;
5763         }
5764 }
5765
5766 static void ecore_chain_free_single(struct ecore_dev *p_dev,
5767                                     struct ecore_chain *p_chain)
5768 {
5769         if (!p_chain->p_virt_addr)
5770                 return;
5771
5772         OSAL_DMA_FREE_COHERENT(p_dev, p_chain->p_virt_addr,
5773                                p_chain->p_phys_addr, ECORE_CHAIN_PAGE_SIZE);
5774 }
5775
5776 static void ecore_chain_free_pbl(struct ecore_dev *p_dev,
5777                                  struct ecore_chain *p_chain)
5778 {
5779         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
5780         u8 *p_pbl_virt = (u8 *)p_chain->pbl_sp.p_virt_table;
5781         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
5782
5783         if (!pp_virt_addr_tbl)
5784                 return;
5785
5786         if (!p_pbl_virt)
5787                 goto out;
5788
5789         for (i = 0; i < page_cnt; i++) {
5790                 if (!pp_virt_addr_tbl[i])
5791                         break;
5792
5793                 OSAL_DMA_FREE_COHERENT(p_dev, pp_virt_addr_tbl[i],
5794                                        *(dma_addr_t *)p_pbl_virt,
5795                                        ECORE_CHAIN_PAGE_SIZE);
5796
5797                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
5798         }
5799
5800         pbl_size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
5801
5802         if (!p_chain->b_external_pbl)
5803                 OSAL_DMA_FREE_COHERENT(p_dev, p_chain->pbl_sp.p_virt_table,
5804                                        p_chain->pbl_sp.p_phys_table, pbl_size);
5805 out:
5806         OSAL_VFREE(p_dev, p_chain->pbl.pp_virt_addr_tbl);
5807 }
5808
5809 void ecore_chain_free(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5810 {
5811         switch (p_chain->mode) {
5812         case ECORE_CHAIN_MODE_NEXT_PTR:
5813                 ecore_chain_free_next_ptr(p_dev, p_chain);
5814                 break;
5815         case ECORE_CHAIN_MODE_SINGLE:
5816                 ecore_chain_free_single(p_dev, p_chain);
5817                 break;
5818         case ECORE_CHAIN_MODE_PBL:
5819                 ecore_chain_free_pbl(p_dev, p_chain);
5820                 break;
5821         }
5822 }
5823
5824 static enum _ecore_status_t
5825 ecore_chain_alloc_sanity_check(struct ecore_dev *p_dev,
5826                                enum ecore_chain_cnt_type cnt_type,
5827                                osal_size_t elem_size, u32 page_cnt)
5828 {
5829         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
5830
5831         /* The actual chain size can be larger than the maximal possible value
5832          * after rounding up the requested elements number to pages, and after
5833          * taking into acount the unusuable elements (next-ptr elements).
5834          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
5835          * size/capacity fields are of a u32 type.
5836          */
5837         if ((cnt_type == ECORE_CHAIN_CNT_TYPE_U16 &&
5838              chain_size > ((u32)ECORE_U16_MAX + 1)) ||
5839             (cnt_type == ECORE_CHAIN_CNT_TYPE_U32 &&
5840              chain_size > ECORE_U32_MAX)) {
5841                 DP_NOTICE(p_dev, true,
5842                           "The actual chain size (0x%lx) is larger than the maximal possible value\n",
5843                           (unsigned long)chain_size);
5844                 return ECORE_INVAL;
5845         }
5846
5847         return ECORE_SUCCESS;
5848 }
5849
5850 static enum _ecore_status_t
5851 ecore_chain_alloc_next_ptr(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5852 {
5853         void *p_virt = OSAL_NULL, *p_virt_prev = OSAL_NULL;
5854         dma_addr_t p_phys = 0;
5855         u32 i;
5856
5857         for (i = 0; i < p_chain->page_cnt; i++) {
5858                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
5859                                                  ECORE_CHAIN_PAGE_SIZE);
5860                 if (!p_virt) {
5861                         DP_NOTICE(p_dev, false,
5862                                   "Failed to allocate chain memory\n");
5863                         return ECORE_NOMEM;
5864                 }
5865
5866                 if (i == 0) {
5867                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
5868                         ecore_chain_reset(p_chain);
5869                 } else {
5870                         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
5871                                                        p_virt, p_phys);
5872                 }
5873
5874                 p_virt_prev = p_virt;
5875         }
5876         /* Last page's next element should point to the beginning of the
5877          * chain.
5878          */
5879         ecore_chain_init_next_ptr_elem(p_chain, p_virt_prev,
5880                                        p_chain->p_virt_addr,
5881                                        p_chain->p_phys_addr);
5882
5883         return ECORE_SUCCESS;
5884 }
5885
5886 static enum _ecore_status_t
5887 ecore_chain_alloc_single(struct ecore_dev *p_dev, struct ecore_chain *p_chain)
5888 {
5889         dma_addr_t p_phys = 0;
5890         void *p_virt = OSAL_NULL;
5891
5892         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys, ECORE_CHAIN_PAGE_SIZE);
5893         if (!p_virt) {
5894                 DP_NOTICE(p_dev, false, "Failed to allocate chain memory\n");
5895                 return ECORE_NOMEM;
5896         }
5897
5898         ecore_chain_init_mem(p_chain, p_virt, p_phys);
5899         ecore_chain_reset(p_chain);
5900
5901         return ECORE_SUCCESS;
5902 }
5903
5904 static enum _ecore_status_t
5905 ecore_chain_alloc_pbl(struct ecore_dev *p_dev,
5906                       struct ecore_chain *p_chain,
5907                       struct ecore_chain_ext_pbl *ext_pbl)
5908 {
5909         u32 page_cnt = p_chain->page_cnt, size, i;
5910         dma_addr_t p_phys = 0, p_pbl_phys = 0;
5911         void **pp_virt_addr_tbl = OSAL_NULL;
5912         u8 *p_pbl_virt = OSAL_NULL;
5913         void *p_virt = OSAL_NULL;
5914
5915         size = page_cnt * sizeof(*pp_virt_addr_tbl);
5916         pp_virt_addr_tbl = (void **)OSAL_VZALLOC(p_dev, size);
5917         if (!pp_virt_addr_tbl) {
5918                 DP_NOTICE(p_dev, false,
5919                           "Failed to allocate memory for the chain virtual addresses table\n");
5920                 return ECORE_NOMEM;
5921         }
5922
5923         /* The allocation of the PBL table is done with its full size, since it
5924          * is expected to be successive.
5925          * ecore_chain_init_pbl_mem() is called even in a case of an allocation
5926          * failure, since pp_virt_addr_tbl was previously allocated, and it
5927          * should be saved to allow its freeing during the error flow.
5928          */
5929         size = page_cnt * ECORE_CHAIN_PBL_ENTRY_SIZE;
5930
5931         if (ext_pbl == OSAL_NULL) {
5932                 p_pbl_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_pbl_phys, size);
5933         } else {
5934                 p_pbl_virt = ext_pbl->p_pbl_virt;
5935                 p_pbl_phys = ext_pbl->p_pbl_phys;
5936                 p_chain->b_external_pbl = true;
5937         }
5938
5939         ecore_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
5940                                  pp_virt_addr_tbl);
5941         if (!p_pbl_virt) {
5942                 DP_NOTICE(p_dev, false, "Failed to allocate chain pbl memory\n");
5943                 return ECORE_NOMEM;
5944         }
5945
5946         for (i = 0; i < page_cnt; i++) {
5947                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
5948                                                  ECORE_CHAIN_PAGE_SIZE);
5949                 if (!p_virt) {
5950                         DP_NOTICE(p_dev, false,
5951                                   "Failed to allocate chain memory\n");
5952                         return ECORE_NOMEM;
5953                 }
5954
5955                 if (i == 0) {
5956                         ecore_chain_init_mem(p_chain, p_virt, p_phys);
5957                         ecore_chain_reset(p_chain);
5958                 }
5959
5960                 /* Fill the PBL table with the physical address of the page */
5961                 *(dma_addr_t *)p_pbl_virt = p_phys;
5962                 /* Keep the virtual address of the page */
5963                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
5964
5965                 p_pbl_virt += ECORE_CHAIN_PBL_ENTRY_SIZE;
5966         }
5967
5968         return ECORE_SUCCESS;
5969 }
5970
5971 enum _ecore_status_t ecore_chain_alloc(struct ecore_dev *p_dev,
5972                                        enum ecore_chain_use_mode intended_use,
5973                                        enum ecore_chain_mode mode,
5974                                        enum ecore_chain_cnt_type cnt_type,
5975                                        u32 num_elems, osal_size_t elem_size,
5976                                        struct ecore_chain *p_chain,
5977                                        struct ecore_chain_ext_pbl *ext_pbl)
5978 {
5979         u32 page_cnt;
5980         enum _ecore_status_t rc = ECORE_SUCCESS;
5981
5982         if (mode == ECORE_CHAIN_MODE_SINGLE)
5983                 page_cnt = 1;
5984         else
5985                 page_cnt = ECORE_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
5986
5987         rc = ecore_chain_alloc_sanity_check(p_dev, cnt_type, elem_size,
5988                                             page_cnt);
5989         if (rc) {
5990                 DP_NOTICE(p_dev, false,
5991                           "Cannot allocate a chain with the given arguments:\n"
5992                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
5993                           intended_use, mode, cnt_type, num_elems, elem_size);
5994                 return rc;
5995         }
5996
5997         ecore_chain_init_params(p_chain, page_cnt, (u8)elem_size, intended_use,
5998                                 mode, cnt_type, p_dev->dp_ctx);
5999
6000         switch (mode) {
6001         case ECORE_CHAIN_MODE_NEXT_PTR:
6002                 rc = ecore_chain_alloc_next_ptr(p_dev, p_chain);
6003                 break;
6004         case ECORE_CHAIN_MODE_SINGLE:
6005                 rc = ecore_chain_alloc_single(p_dev, p_chain);
6006                 break;
6007         case ECORE_CHAIN_MODE_PBL:
6008                 rc = ecore_chain_alloc_pbl(p_dev, p_chain, ext_pbl);
6009                 break;
6010         }
6011         if (rc)
6012                 goto nomem;
6013
6014         return ECORE_SUCCESS;
6015
6016 nomem:
6017         ecore_chain_free(p_dev, p_chain);
6018         return rc;
6019 }
6020
6021 enum _ecore_status_t ecore_fw_l2_queue(struct ecore_hwfn *p_hwfn,
6022                                        u16 src_id, u16 *dst_id)
6023 {
6024         if (src_id >= RESC_NUM(p_hwfn, ECORE_L2_QUEUE)) {
6025                 u16 min, max;
6026
6027                 min = (u16)RESC_START(p_hwfn, ECORE_L2_QUEUE);
6028                 max = min + RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
6029                 DP_NOTICE(p_hwfn, true,
6030                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
6031                           src_id, min, max);
6032
6033                 return ECORE_INVAL;
6034         }
6035
6036         *dst_id = RESC_START(p_hwfn, ECORE_L2_QUEUE) + src_id;
6037
6038         return ECORE_SUCCESS;
6039 }
6040
6041 enum _ecore_status_t ecore_fw_vport(struct ecore_hwfn *p_hwfn,
6042                                     u8 src_id, u8 *dst_id)
6043 {
6044         if (src_id >= RESC_NUM(p_hwfn, ECORE_VPORT)) {
6045                 u8 min, max;
6046
6047                 min = (u8)RESC_START(p_hwfn, ECORE_VPORT);
6048                 max = min + RESC_NUM(p_hwfn, ECORE_VPORT);
6049                 DP_NOTICE(p_hwfn, true,
6050                           "vport id [%d] is not valid, available indices [%d - %d]\n",
6051                           src_id, min, max);
6052
6053                 return ECORE_INVAL;
6054         }
6055
6056         *dst_id = RESC_START(p_hwfn, ECORE_VPORT) + src_id;
6057
6058         return ECORE_SUCCESS;
6059 }
6060
6061 enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
6062                                       u8 src_id, u8 *dst_id)
6063 {
6064         if (src_id >= RESC_NUM(p_hwfn, ECORE_RSS_ENG)) {
6065                 u8 min, max;
6066
6067                 min = (u8)RESC_START(p_hwfn, ECORE_RSS_ENG);
6068                 max = min + RESC_NUM(p_hwfn, ECORE_RSS_ENG);
6069                 DP_NOTICE(p_hwfn, true,
6070                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
6071                           src_id, min, max);
6072
6073                 return ECORE_INVAL;
6074         }
6075
6076         *dst_id = RESC_START(p_hwfn, ECORE_RSS_ENG) + src_id;
6077
6078         return ECORE_SUCCESS;
6079 }
6080
6081 enum _ecore_status_t
6082 ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
6083                                   struct ecore_ptt *p_ptt)
6084 {
6085         if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
6086                 ecore_wr(p_hwfn, p_ptt,
6087                          NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
6088                          1 << p_hwfn->abs_pf_id / 2);
6089                 ecore_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, 0);
6090                 return ECORE_SUCCESS;
6091         }
6092
6093         DP_NOTICE(p_hwfn, false,
6094                   "This function can't be set as default\n");
6095         return ECORE_INVAL;
6096 }
6097
6098 static enum _ecore_status_t ecore_set_coalesce(struct ecore_hwfn *p_hwfn,
6099                                                struct ecore_ptt *p_ptt,
6100                                                u32 hw_addr, void *p_eth_qzone,
6101                                                osal_size_t eth_qzone_size,
6102                                                u8 timeset)
6103 {
6104         struct coalescing_timeset *p_coal_timeset;
6105
6106         if (p_hwfn->p_dev->int_coalescing_mode != ECORE_COAL_MODE_ENABLE) {
6107                 DP_NOTICE(p_hwfn, true,
6108                           "Coalescing configuration not enabled\n");
6109                 return ECORE_INVAL;
6110         }
6111
6112         p_coal_timeset = p_eth_qzone;
6113         OSAL_MEMSET(p_eth_qzone, 0, eth_qzone_size);
6114         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
6115         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
6116         ecore_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
6117
6118         return ECORE_SUCCESS;
6119 }
6120
6121 enum _ecore_status_t ecore_set_queue_coalesce(struct ecore_hwfn *p_hwfn,
6122                                               u16 rx_coal, u16 tx_coal,
6123                                               void *p_handle)
6124 {
6125         struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle;
6126         enum _ecore_status_t rc = ECORE_SUCCESS;
6127         struct ecore_ptt *p_ptt;
6128
6129         /* TODO - Configuring a single queue's coalescing but
6130          * claiming all queues are abiding same configuration
6131          * for PF and VF both.
6132          */
6133
6134         if (IS_VF(p_hwfn->p_dev))
6135                 return ecore_vf_pf_set_coalesce(p_hwfn, rx_coal,
6136                                                 tx_coal, p_cid);
6137
6138         p_ptt = ecore_ptt_acquire(p_hwfn);
6139         if (!p_ptt)
6140                 return ECORE_AGAIN;
6141
6142         if (rx_coal) {
6143                 rc = ecore_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
6144                 if (rc)
6145                         goto out;
6146                 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
6147         }
6148
6149         if (tx_coal) {
6150                 rc = ecore_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
6151                 if (rc)
6152                         goto out;
6153                 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
6154         }
6155 out:
6156         ecore_ptt_release(p_hwfn, p_ptt);
6157
6158         return rc;
6159 }
6160
6161 enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
6162                                             struct ecore_ptt *p_ptt,
6163                                             u16 coalesce,
6164                                             struct ecore_queue_cid *p_cid)
6165 {
6166         struct ustorm_eth_queue_zone eth_qzone;
6167         u8 timeset, timer_res;
6168         u32 address;
6169         enum _ecore_status_t rc;
6170
6171         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6172         if (coalesce <= 0x7F) {
6173                 timer_res = 0;
6174         } else if (coalesce <= 0xFF) {
6175                 timer_res = 1;
6176         } else if (coalesce <= 0x1FF) {
6177                 timer_res = 2;
6178         } else {
6179                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6180                 return ECORE_INVAL;
6181         }
6182         timeset = (u8)(coalesce >> timer_res);
6183
6184         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6185                                      p_cid->sb_igu_id, false);
6186         if (rc != ECORE_SUCCESS)
6187                 goto out;
6188
6189         address = BAR0_MAP_REG_USDM_RAM +
6190                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6191
6192         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
6193                                 sizeof(struct ustorm_eth_queue_zone), timeset);
6194         if (rc != ECORE_SUCCESS)
6195                 goto out;
6196
6197 out:
6198         return rc;
6199 }
6200
6201 enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
6202                                             struct ecore_ptt *p_ptt,
6203                                             u16 coalesce,
6204                                             struct ecore_queue_cid *p_cid)
6205 {
6206         struct xstorm_eth_queue_zone eth_qzone;
6207         u8 timeset, timer_res;
6208         u32 address;
6209         enum _ecore_status_t rc;
6210
6211         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
6212         if (coalesce <= 0x7F) {
6213                 timer_res = 0;
6214         } else if (coalesce <= 0xFF) {
6215                 timer_res = 1;
6216         } else if (coalesce <= 0x1FF) {
6217                 timer_res = 2;
6218         } else {
6219                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
6220                 return ECORE_INVAL;
6221         }
6222
6223         timeset = (u8)(coalesce >> timer_res);
6224
6225         rc = ecore_int_set_timer_res(p_hwfn, p_ptt, timer_res,
6226                                      p_cid->sb_igu_id, true);
6227         if (rc != ECORE_SUCCESS)
6228                 goto out;
6229
6230         address = BAR0_MAP_REG_XSDM_RAM +
6231                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
6232
6233         rc = ecore_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
6234                                 sizeof(struct xstorm_eth_queue_zone), timeset);
6235 out:
6236         return rc;
6237 }
6238
6239 /* Calculate final WFQ values for all vports and configure it.
6240  * After this configuration each vport must have
6241  * approx min rate =  vport_wfq * min_pf_rate / ECORE_WFQ_UNIT
6242  */
6243 static void ecore_configure_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6244                                                struct ecore_ptt *p_ptt,
6245                                                u32 min_pf_rate)
6246 {
6247         struct init_qm_vport_params *vport_params;
6248         int i;
6249
6250         vport_params = p_hwfn->qm_info.qm_vport_params;
6251
6252         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6253                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6254
6255                 vport_params[i].vport_wfq = (wfq_speed * ECORE_WFQ_UNIT) /
6256                     min_pf_rate;
6257                 ecore_init_vport_wfq(p_hwfn, p_ptt,
6258                                      vport_params[i].first_tx_pq_id,
6259                                      vport_params[i].vport_wfq);
6260         }
6261 }
6262
6263 static void ecore_init_wfq_default_param(struct ecore_hwfn *p_hwfn)
6264 {
6265         int i;
6266
6267         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
6268                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
6269 }
6270
6271 static void ecore_disable_wfq_for_all_vports(struct ecore_hwfn *p_hwfn,
6272                                              struct ecore_ptt *p_ptt)
6273 {
6274         struct init_qm_vport_params *vport_params;
6275         int i;
6276
6277         vport_params = p_hwfn->qm_info.qm_vport_params;
6278
6279         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6280                 ecore_init_wfq_default_param(p_hwfn);
6281                 ecore_init_vport_wfq(p_hwfn, p_ptt,
6282                                      vport_params[i].first_tx_pq_id,
6283                                      vport_params[i].vport_wfq);
6284         }
6285 }
6286
6287 /* This function performs several validations for WFQ
6288  * configuration and required min rate for a given vport
6289  * 1. req_rate must be greater than one percent of min_pf_rate.
6290  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
6291  *    rates to get less than one percent of min_pf_rate.
6292  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
6293  */
6294 static enum _ecore_status_t ecore_init_wfq_param(struct ecore_hwfn *p_hwfn,
6295                                                  u16 vport_id, u32 req_rate,
6296                                                  u32 min_pf_rate)
6297 {
6298         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
6299         int non_requested_count = 0, req_count = 0, i, num_vports;
6300
6301         num_vports = p_hwfn->qm_info.num_vports;
6302
6303 /* Accounting for the vports which are configured for WFQ explicitly */
6304
6305         for (i = 0; i < num_vports; i++) {
6306                 u32 tmp_speed;
6307
6308                 if ((i != vport_id) && p_hwfn->qm_info.wfq_data[i].configured) {
6309                         req_count++;
6310                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
6311                         total_req_min_rate += tmp_speed;
6312                 }
6313         }
6314
6315         /* Include current vport data as well */
6316         req_count++;
6317         total_req_min_rate += req_rate;
6318         non_requested_count = num_vports - req_count;
6319
6320         /* validate possible error cases */
6321         if (req_rate < min_pf_rate / ECORE_WFQ_UNIT) {
6322                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6323                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6324                            vport_id, req_rate, min_pf_rate);
6325                 return ECORE_INVAL;
6326         }
6327
6328         /* TBD - for number of vports greater than 100 */
6329         if (num_vports > ECORE_WFQ_UNIT) {
6330                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6331                            "Number of vports is greater than %d\n",
6332                            ECORE_WFQ_UNIT);
6333                 return ECORE_INVAL;
6334         }
6335
6336         if (total_req_min_rate > min_pf_rate) {
6337                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6338                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
6339                            total_req_min_rate, min_pf_rate);
6340                 return ECORE_INVAL;
6341         }
6342
6343         /* Data left for non requested vports */
6344         total_left_rate = min_pf_rate - total_req_min_rate;
6345         left_rate_per_vp = total_left_rate / non_requested_count;
6346
6347         /* validate if non requested get < 1% of min bw */
6348         if (left_rate_per_vp < min_pf_rate / ECORE_WFQ_UNIT) {
6349                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6350                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
6351                            left_rate_per_vp, min_pf_rate);
6352                 return ECORE_INVAL;
6353         }
6354
6355         /* now req_rate for given vport passes all scenarios.
6356          * assign final wfq rates to all vports.
6357          */
6358         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
6359         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
6360
6361         for (i = 0; i < num_vports; i++) {
6362                 if (p_hwfn->qm_info.wfq_data[i].configured)
6363                         continue;
6364
6365                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
6366         }
6367
6368         return ECORE_SUCCESS;
6369 }
6370
6371 static int __ecore_configure_vport_wfq(struct ecore_hwfn *p_hwfn,
6372                                        struct ecore_ptt *p_ptt,
6373                                        u16 vp_id, u32 rate)
6374 {
6375         struct ecore_mcp_link_state *p_link;
6376         int rc = ECORE_SUCCESS;
6377
6378         p_link = &p_hwfn->p_dev->hwfns[0].mcp_info->link_output;
6379
6380         if (!p_link->min_pf_rate) {
6381                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
6382                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
6383                 return rc;
6384         }
6385
6386         rc = ecore_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
6387
6388         if (rc == ECORE_SUCCESS)
6389                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt,
6390                                                    p_link->min_pf_rate);
6391         else
6392                 DP_NOTICE(p_hwfn, false,
6393                           "Validation failed while configuring min rate\n");
6394
6395         return rc;
6396 }
6397
6398 static int __ecore_configure_vp_wfq_on_link_change(struct ecore_hwfn *p_hwfn,
6399                                                    struct ecore_ptt *p_ptt,
6400                                                    u32 min_pf_rate)
6401 {
6402         bool use_wfq = false;
6403         int rc = ECORE_SUCCESS;
6404         u16 i;
6405
6406         /* Validate all pre configured vports for wfq */
6407         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
6408                 u32 rate;
6409
6410                 if (!p_hwfn->qm_info.wfq_data[i].configured)
6411                         continue;
6412
6413                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
6414                 use_wfq = true;
6415
6416                 rc = ecore_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
6417                 if (rc != ECORE_SUCCESS) {
6418                         DP_NOTICE(p_hwfn, false,
6419                                   "WFQ validation failed while configuring min rate\n");
6420                         break;
6421                 }
6422         }
6423
6424         if (rc == ECORE_SUCCESS && use_wfq)
6425                 ecore_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
6426         else
6427                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6428
6429         return rc;
6430 }
6431
6432 /* Main API for ecore clients to configure vport min rate.
6433  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
6434  * rate - Speed in Mbps needs to be assigned to a given vport.
6435  */
6436 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate)
6437 {
6438         int i, rc = ECORE_INVAL;
6439
6440         /* TBD - for multiple hardware functions - that is 100 gig */
6441         if (ECORE_IS_CMT(p_dev)) {
6442                 DP_NOTICE(p_dev, false,
6443                           "WFQ configuration is not supported for this device\n");
6444                 return rc;
6445         }
6446
6447         for_each_hwfn(p_dev, i) {
6448                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6449                 struct ecore_ptt *p_ptt;
6450
6451                 p_ptt = ecore_ptt_acquire(p_hwfn);
6452                 if (!p_ptt)
6453                         return ECORE_TIMEOUT;
6454
6455                 rc = __ecore_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
6456
6457                 if (rc != ECORE_SUCCESS) {
6458                         ecore_ptt_release(p_hwfn, p_ptt);
6459                         return rc;
6460                 }
6461
6462                 ecore_ptt_release(p_hwfn, p_ptt);
6463         }
6464
6465         return rc;
6466 }
6467
6468 /* API to configure WFQ from mcp link change */
6469 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
6470                                            struct ecore_ptt *p_ptt,
6471                                            u32 min_pf_rate)
6472 {
6473         int i;
6474
6475         /* TBD - for multiple hardware functions - that is 100 gig */
6476         if (ECORE_IS_CMT(p_dev)) {
6477                 DP_VERBOSE(p_dev, ECORE_MSG_LINK,
6478                            "WFQ configuration is not supported for this device\n");
6479                 return;
6480         }
6481
6482         for_each_hwfn(p_dev, i) {
6483                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6484
6485                 __ecore_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
6486                                                         min_pf_rate);
6487         }
6488 }
6489
6490 int __ecore_configure_pf_max_bandwidth(struct ecore_hwfn *p_hwfn,
6491                                        struct ecore_ptt *p_ptt,
6492                                        struct ecore_mcp_link_state *p_link,
6493                                        u8 max_bw)
6494 {
6495         int rc = ECORE_SUCCESS;
6496
6497         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
6498
6499         if (!p_link->line_speed && (max_bw != 100))
6500                 return rc;
6501
6502         p_link->speed = (p_link->line_speed * max_bw) / 100;
6503         p_hwfn->qm_info.pf_rl = p_link->speed;
6504
6505         /* Since the limiter also affects Tx-switched traffic, we don't want it
6506          * to limit such traffic in case there's no actual limit.
6507          * In that case, set limit to imaginary high boundary.
6508          */
6509         if (max_bw == 100)
6510                 p_hwfn->qm_info.pf_rl = 100000;
6511
6512         rc = ecore_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
6513                               p_hwfn->qm_info.pf_rl);
6514
6515         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6516                    "Configured MAX bandwidth to be %08x Mb/sec\n",
6517                    p_link->speed);
6518
6519         return rc;
6520 }
6521
6522 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
6523 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw)
6524 {
6525         int i, rc = ECORE_INVAL;
6526
6527         if (max_bw < 1 || max_bw > 100) {
6528                 DP_NOTICE(p_dev, false, "PF max bw valid range is [1-100]\n");
6529                 return rc;
6530         }
6531
6532         for_each_hwfn(p_dev, i) {
6533                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6534                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6535                 struct ecore_mcp_link_state *p_link;
6536                 struct ecore_ptt *p_ptt;
6537
6538                 p_link = &p_lead->mcp_info->link_output;
6539
6540                 p_ptt = ecore_ptt_acquire(p_hwfn);
6541                 if (!p_ptt)
6542                         return ECORE_TIMEOUT;
6543
6544                 rc = __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
6545                                                         p_link, max_bw);
6546
6547                 ecore_ptt_release(p_hwfn, p_ptt);
6548
6549                 if (rc != ECORE_SUCCESS)
6550                         break;
6551         }
6552
6553         return rc;
6554 }
6555
6556 int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
6557                                        struct ecore_ptt *p_ptt,
6558                                        struct ecore_mcp_link_state *p_link,
6559                                        u8 min_bw)
6560 {
6561         int rc = ECORE_SUCCESS;
6562
6563         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
6564         p_hwfn->qm_info.pf_wfq = min_bw;
6565
6566         if (!p_link->line_speed)
6567                 return rc;
6568
6569         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
6570
6571         rc = ecore_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
6572
6573         DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
6574                    "Configured MIN bandwidth to be %d Mb/sec\n",
6575                    p_link->min_pf_rate);
6576
6577         return rc;
6578 }
6579
6580 /* Main API to configure PF min bandwidth where bw range is [1-100] */
6581 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw)
6582 {
6583         int i, rc = ECORE_INVAL;
6584
6585         if (min_bw < 1 || min_bw > 100) {
6586                 DP_NOTICE(p_dev, false, "PF min bw valid range is [1-100]\n");
6587                 return rc;
6588         }
6589
6590         for_each_hwfn(p_dev, i) {
6591                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
6592                 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_dev);
6593                 struct ecore_mcp_link_state *p_link;
6594                 struct ecore_ptt *p_ptt;
6595
6596                 p_link = &p_lead->mcp_info->link_output;
6597
6598                 p_ptt = ecore_ptt_acquire(p_hwfn);
6599                 if (!p_ptt)
6600                         return ECORE_TIMEOUT;
6601
6602                 rc = __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
6603                                                         p_link, min_bw);
6604                 if (rc != ECORE_SUCCESS) {
6605                         ecore_ptt_release(p_hwfn, p_ptt);
6606                         return rc;
6607                 }
6608
6609                 if (p_link->min_pf_rate) {
6610                         u32 min_rate = p_link->min_pf_rate;
6611
6612                         rc = __ecore_configure_vp_wfq_on_link_change(p_hwfn,
6613                                                                      p_ptt,
6614                                                                      min_rate);
6615                 }
6616
6617                 ecore_ptt_release(p_hwfn, p_ptt);
6618         }
6619
6620         return rc;
6621 }
6622
6623 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
6624 {
6625         struct ecore_mcp_link_state *p_link;
6626
6627         p_link = &p_hwfn->mcp_info->link_output;
6628
6629         if (p_link->min_pf_rate)
6630                 ecore_disable_wfq_for_all_vports(p_hwfn, p_ptt);
6631
6632         OSAL_MEMSET(p_hwfn->qm_info.wfq_data, 0,
6633                     sizeof(*p_hwfn->qm_info.wfq_data) *
6634                     p_hwfn->qm_info.num_vports);
6635 }
6636
6637 int ecore_device_num_engines(struct ecore_dev *p_dev)
6638 {
6639         return ECORE_IS_BB(p_dev) ? 2 : 1;
6640 }
6641
6642 int ecore_device_num_ports(struct ecore_dev *p_dev)
6643 {
6644         return p_dev->num_ports;
6645 }
6646
6647 void ecore_set_fw_mac_addr(__le16 *fw_msb,
6648                           __le16 *fw_mid,
6649                           __le16 *fw_lsb,
6650                           u8 *mac)
6651 {
6652         ((u8 *)fw_msb)[0] = mac[1];
6653         ((u8 *)fw_msb)[1] = mac[0];
6654         ((u8 *)fw_mid)[0] = mac[3];
6655         ((u8 *)fw_mid)[1] = mac[2];
6656         ((u8 *)fw_lsb)[0] = mac[5];
6657         ((u8 *)fw_lsb)[1] = mac[4];
6658 }
6659
6660 bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
6661 {
6662         return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);
6663 }