drivers/net/qede/base/ecore_hw.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "bcm_osal.h"
   8 #include "ecore_hsi_common.h"
   9 #include "ecore_status.h"
  10 #include "ecore.h"
  11 #include "ecore_hw.h"
  12 #include "reg_addr.h"
  13 #include "ecore_utils.h"
  14 #include "ecore_iov_api.h"
  15
  16 #ifndef ASIC_ONLY
  17 #define ECORE_EMUL_FACTOR 2000
  18 #define ECORE_FPGA_FACTOR 200
  19 #endif
  20
  21 #define ECORE_BAR_ACQUIRE_TIMEOUT 1000
  22
  23 /* Invalid values */
  24 #define ECORE_BAR_INVALID_OFFSET        (OSAL_CPU_TO_LE32(-1))
  25
  26 struct ecore_ptt {
  27         osal_list_entry_t list_entry;
  28         unsigned int idx;
  29         struct pxp_ptt_entry pxp;
  30         u8 hwfn_id;
  31 };
  32
  33 struct ecore_ptt_pool {
  34         osal_list_t free_list;
  35         osal_spinlock_t lock; /* ptt synchronized access */
  36         struct ecore_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM];
  37 };
  38
  39 void __ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn)
  40 {
  41         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_ptt_pool);
  42         p_hwfn->p_ptt_pool = OSAL_NULL;
  43 }
  44
  45 enum _ecore_status_t ecore_ptt_pool_alloc(struct ecore_hwfn *p_hwfn)
  46 {
  47         struct ecore_ptt_pool *p_pool = OSAL_ALLOC(p_hwfn->p_dev,
  48                                                    GFP_KERNEL,
  49                                                    sizeof(*p_pool));
  50         int i;
  51
  52         if (!p_pool)
  53                 return ECORE_NOMEM;
  54
  55         OSAL_LIST_INIT(&p_pool->free_list);
  56         for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
  57                 p_pool->ptts[i].idx = i;
  58                 p_pool->ptts[i].pxp.offset = ECORE_BAR_INVALID_OFFSET;
  59                 p_pool->ptts[i].pxp.pretend.control = 0;
  60                 p_pool->ptts[i].hwfn_id = p_hwfn->my_id;
  61
  62                 /* There are special PTT entries that are taken only by design.
  63                  * The rest are added ot the list for general usage.
  64                  */
  65                 if (i >= RESERVED_PTT_MAX)
  66                         OSAL_LIST_PUSH_HEAD(&p_pool->ptts[i].list_entry,
  67                                             &p_pool->free_list);
  68         }
  69
  70         p_hwfn->p_ptt_pool = p_pool;
  71 #ifdef CONFIG_ECORE_LOCK_ALLOC
  72         if (OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_pool->lock)) {
  73                 __ecore_ptt_pool_free(p_hwfn);
  74                 return ECORE_NOMEM;
  75         }
  76 #endif
  77         OSAL_SPIN_LOCK_INIT(&p_pool->lock);
  78         return ECORE_SUCCESS;
  79 }
  80
  81 void ecore_ptt_invalidate(struct ecore_hwfn *p_hwfn)
  82 {
  83         struct ecore_ptt *p_ptt;
  84         int i;
  85
  86         for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
  87                 p_ptt = &p_hwfn->p_ptt_pool->ptts[i];
  88                 p_ptt->pxp.offset = ECORE_BAR_INVALID_OFFSET;
  89         }
  90 }
  91
  92 void ecore_ptt_pool_free(struct ecore_hwfn *p_hwfn)
  93 {
  94 #ifdef CONFIG_ECORE_LOCK_ALLOC
  95         if (p_hwfn->p_ptt_pool)
  96                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->p_ptt_pool->lock);
  97 #endif
  98         __ecore_ptt_pool_free(p_hwfn);
  99 }
 100
 101 struct ecore_ptt *ecore_ptt_acquire(struct ecore_hwfn *p_hwfn)
 102 {
 103         struct ecore_ptt *p_ptt;
 104         unsigned int i;
 105
 106         /* Take the free PTT from the list */
 107         for (i = 0; i < ECORE_BAR_ACQUIRE_TIMEOUT; i++) {
 108                 OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
 109                 if (!OSAL_LIST_IS_EMPTY(&p_hwfn->p_ptt_pool->free_list)) {
 110                         p_ptt = OSAL_LIST_FIRST_ENTRY(
 111                                                 &p_hwfn->p_ptt_pool->free_list,
 112                                                 struct ecore_ptt, list_entry);
 113                         OSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry,
 114                                                &p_hwfn->p_ptt_pool->free_list);
 115
 116                         OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
 117
 118                         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 119                                    "allocated ptt %d\n", p_ptt->idx);
 120
 121                         return p_ptt;
 122                 }
 123
 124                 OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
 125                 OSAL_MSLEEP(1);
 126         }
 127
 128         DP_NOTICE(p_hwfn, true,
 129                   "PTT acquire timeout - failed to allocate PTT\n");
 130         return OSAL_NULL;
 131 }
 132
 133 void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 134 {
 135         /* This PTT should not be set to pretend if it is being released */
 136         /* TODO - add some pretend sanity checks, to make sure pretend
 137          * isn't set on this ptt
 138          */
 139
 140         OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
 141         OSAL_LIST_PUSH_HEAD(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list);
 142         OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
 143 }
 144
 145 static u32 ecore_ptt_get_hw_addr(struct ecore_ptt *p_ptt)
 146 {
 147         /* The HW is using DWORDS and we need to translate it to Bytes */
 148         return OSAL_LE32_TO_CPU(p_ptt->pxp.offset) << 2;
 149 }
 150
 151 static u32 ecore_ptt_config_addr(struct ecore_ptt *p_ptt)
 152 {
 153         return PXP_PF_WINDOW_ADMIN_PER_PF_START +
 154             p_ptt->idx * sizeof(struct pxp_ptt_entry);
 155 }
 156
 157 u32 ecore_ptt_get_bar_addr(struct ecore_ptt *p_ptt)
 158 {
 159         return PXP_EXTERNAL_BAR_PF_WINDOW_START +
 160             p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE;
 161 }
 162
 163 void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn,
 164                        struct ecore_ptt *p_ptt, u32 new_hw_addr)
 165 {
 166         u32 prev_hw_addr;
 167
 168         prev_hw_addr = ecore_ptt_get_hw_addr(p_ptt);
 169
 170         if (new_hw_addr == prev_hw_addr)
 171                 return;
 172
 173         /* Update PTT entery in admin window */
 174         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 175                    "Updating PTT entry %d to offset 0x%x\n",
 176                    p_ptt->idx, new_hw_addr);
 177
 178         /* The HW is using DWORDS and the address is in Bytes */
 179         p_ptt->pxp.offset = OSAL_CPU_TO_LE32(new_hw_addr >> 2);
 180
 181         REG_WR(p_hwfn,
 182                ecore_ptt_config_addr(p_ptt) +
 183                OFFSETOF(struct pxp_ptt_entry, offset),
 184                OSAL_LE32_TO_CPU(p_ptt->pxp.offset));
 185 }
 186
 187 static u32 ecore_set_ptt(struct ecore_hwfn *p_hwfn,
 188                          struct ecore_ptt *p_ptt, u32 hw_addr)
 189 {
 190         u32 win_hw_addr = ecore_ptt_get_hw_addr(p_ptt);
 191         u32 offset;
 192
 193         offset = hw_addr - win_hw_addr;
 194
 195         if (p_ptt->hwfn_id != p_hwfn->my_id)
 196                 DP_NOTICE(p_hwfn, true,
 197                           "ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n",
 198                           p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id);
 199
 200         /* Verify the address is within the window */
 201         if (hw_addr < win_hw_addr ||
 202             offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) {
 203                 ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr);
 204                 offset = 0;
 205         }
 206
 207         return ecore_ptt_get_bar_addr(p_ptt) + offset;
 208 }
 209
 210 struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,
 211                                          enum reserved_ptts ptt_idx)
 212 {
 213         if (ptt_idx >= RESERVED_PTT_MAX) {
 214                 DP_NOTICE(p_hwfn, true,
 215                           "Requested PTT %d is out of range\n", ptt_idx);
 216                 return OSAL_NULL;
 217         }
 218
 219         return &p_hwfn->p_ptt_pool->ptts[ptt_idx];
 220 }
 221
 222 static bool ecore_is_reg_fifo_empty(struct ecore_hwfn *p_hwfn,
 223                                     struct ecore_ptt *p_ptt)
 224 {
 225         bool is_empty = true;
 226         u32 bar_addr;
 227
 228         if (!p_hwfn->p_dev->chk_reg_fifo)
 229                 goto out;
 230
 231         /* ecore_rd() cannot be used here since it calls this function */
 232         bar_addr = ecore_set_ptt(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA);
 233         is_empty = REG_RD(p_hwfn, bar_addr) == 0;
 234
 235 #ifndef ASIC_ONLY
 236         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
 237                 OSAL_UDELAY(100);
 238 #endif
 239
 240 out:
 241         return is_empty;
 242 }
 243
 244 void ecore_wr(struct ecore_hwfn *p_hwfn,
 245               struct ecore_ptt *p_ptt, u32 hw_addr, u32 val)
 246 {
 247         bool prev_fifo_err;
 248         u32 bar_addr;
 249
 250         prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
 251
 252         bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
 253         REG_WR(p_hwfn, bar_addr, val);
 254         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 255                    "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
 256                    bar_addr, hw_addr, val);
 257
 258 #ifndef ASIC_ONLY
 259         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
 260                 OSAL_UDELAY(100);
 261 #endif
 262
 263         OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
 264                   "reg_fifo err was caused by a call to ecore_wr(0x%x, 0x%x)\n",
 265                   hw_addr, val);
 266 }
 267
 268 u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr)
 269 {
 270         bool prev_fifo_err;
 271         u32 bar_addr, val;
 272
 273         prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
 274
 275         bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
 276         val = REG_RD(p_hwfn, bar_addr);
 277
 278         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 279                    "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
 280                    bar_addr, hw_addr, val);
 281
 282 #ifndef ASIC_ONLY
 283         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
 284                 OSAL_UDELAY(100);
 285 #endif
 286
 287         OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
 288                   "reg_fifo error was caused by a call to ecore_rd(0x%x)\n",
 289                   hw_addr);
 290
 291         return val;
 292 }
 293
 294 static void ecore_memcpy_hw(struct ecore_hwfn *p_hwfn,
 295                             struct ecore_ptt *p_ptt,
 296                             void *addr,
 297                             u32 hw_addr, osal_size_t n, bool to_device)
 298 {
 299         u32 dw_count, *host_addr, hw_offset;
 300         osal_size_t quota, done = 0;
 301         u32 OSAL_IOMEM *reg_addr;
 302
 303         while (done < n) {
 304                 quota = OSAL_MIN_T(osal_size_t, n - done,
 305                                    PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE);
 306
 307                 if (IS_PF(p_hwfn->p_dev)) {
 308                         ecore_ptt_set_win(p_hwfn, p_ptt, hw_addr + done);
 309                         hw_offset = ecore_ptt_get_bar_addr(p_ptt);
 310                 } else {
 311                         hw_offset = hw_addr + done;
 312                 }
 313
 314                 dw_count = quota / 4;
 315                 host_addr = (u32 *)((u8 *)addr + done);
 316                 reg_addr = (u32 OSAL_IOMEM *)OSAL_REG_ADDR(p_hwfn, hw_offset);
 317
 318                 if (to_device)
 319                         while (dw_count--)
 320                                 DIRECT_REG_WR(p_hwfn, reg_addr++, *host_addr++);
 321                 else
 322                         while (dw_count--)
 323                                 *host_addr++ = DIRECT_REG_RD(p_hwfn,
 324                                                              reg_addr++);
 325
 326                 done += quota;
 327         }
 328 }
 329
 330 void ecore_memcpy_from(struct ecore_hwfn *p_hwfn,
 331                        struct ecore_ptt *p_ptt,
 332                        void *dest, u32 hw_addr, osal_size_t n)
 333 {
 334         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 335                    "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n",
 336                    hw_addr, dest, hw_addr, (unsigned long)n);
 337
 338         ecore_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false);
 339 }
 340
 341 void ecore_memcpy_to(struct ecore_hwfn *p_hwfn,
 342                      struct ecore_ptt *p_ptt,
 343                      u32 hw_addr, void *src, osal_size_t n)
 344 {
 345         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 346                    "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n",
 347                    hw_addr, hw_addr, src, (unsigned long)n);
 348
 349         ecore_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true);
 350 }
 351
 352 void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,
 353                        struct ecore_ptt *p_ptt, u16 fid)
 354 {
 355         u16 control = 0;
 356
 357         SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
 358         SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
 359
 360 /* Every pretend undos prev pretends, including previous port pretend */
 361
 362         SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
 363         SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
 364         SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
 365
 366         if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
 367                 fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
 368
 369         p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
 370         p_ptt->pxp.pretend.fid.concrete_fid.fid = OSAL_CPU_TO_LE16(fid);
 371
 372         REG_WR(p_hwfn,
 373                ecore_ptt_config_addr(p_ptt) +
 374                OFFSETOF(struct pxp_ptt_entry, pretend),
 375                         *(u32 *)&p_ptt->pxp.pretend);
 376 }
 377
 378 void ecore_port_pretend(struct ecore_hwfn *p_hwfn,
 379                         struct ecore_ptt *p_ptt, u8 port_id)
 380 {
 381         u16 control = 0;
 382
 383         SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
 384         SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
 385         SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
 386         p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
 387
 388         REG_WR(p_hwfn,
 389                ecore_ptt_config_addr(p_ptt) +
 390                OFFSETOF(struct pxp_ptt_entry, pretend),
 391                         *(u32 *)&p_ptt->pxp.pretend);
 392 }
 393
 394 void ecore_port_unpretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 395 {
 396         u16 control = 0;
 397
 398         SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
 399         SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
 400         SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
 401
 402         p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
 403
 404         REG_WR(p_hwfn,
 405                ecore_ptt_config_addr(p_ptt) +
 406                OFFSETOF(struct pxp_ptt_entry, pretend),
 407                         *(u32 *)&p_ptt->pxp.pretend);
 408 }
 409
 410 void ecore_port_fid_pretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 411                             u8 port_id, u16 fid)
 412 {
 413         u16 control = 0;
 414
 415         SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
 416         SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
 417         SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
 418
 419         SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
 420         SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
 421
 422         if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
 423                 fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
 424
 425         p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
 426         p_ptt->pxp.pretend.fid.concrete_fid.fid = OSAL_CPU_TO_LE16(fid);
 427
 428         REG_WR(p_hwfn,
 429                ecore_ptt_config_addr(p_ptt) +
 430                OFFSETOF(struct pxp_ptt_entry, pretend),
 431                *(u32 *)&p_ptt->pxp.pretend);
 432 }
 433
 434 u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid)
 435 {
 436         u32 concrete_fid = 0;
 437
 438         SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id);
 439         SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid);
 440         SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1);
 441
 442         return concrete_fid;
 443 }
 444
 445 /* Not in use @DPDK
 446  * Ecore HW lock
 447  * =============
 448  * Although the implementation is ready, today we don't have any flow that
 449  * utliizes said locks - and we want to keep it this way.
 450  * If this changes, this needs to be revisted.
 451  */
 452
 453 /* DMAE */
 454
 455 #define ECORE_DMAE_FLAGS_IS_SET(params, flag)   \
 456         ((params) != OSAL_NULL && ((params)->flags & ECORE_DMAE_FLAG_##flag))
 457
 458 static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
 459                               const u8 is_src_type_grc,
 460                               const u8 is_dst_type_grc,
 461                               struct ecore_dmae_params *p_params)
 462 {
 463         u8 src_pfid, dst_pfid, port_id;
 464         u16 opcode_b = 0;
 465         u32 opcode = 0;
 466
 467         /* Whether the source is the PCIe or the GRC.
 468          * 0- The source is the PCIe
 469          * 1- The source is the GRC.
 470          */
 471         opcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC
 472                    : DMAE_CMD_SRC_MASK_PCIE) << DMAE_CMD_SRC_SHIFT;
 473         src_pfid = ECORE_DMAE_FLAGS_IS_SET(p_params, PF_SRC) ?
 474                    p_params->src_pfid : p_hwfn->rel_pf_id;
 475         opcode |= (src_pfid & DMAE_CMD_SRC_PF_ID_MASK) <<
 476                   DMAE_CMD_SRC_PF_ID_SHIFT;
 477
 478         /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
 479         opcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC
 480                    : DMAE_CMD_DST_MASK_PCIE) << DMAE_CMD_DST_SHIFT;
 481         dst_pfid = ECORE_DMAE_FLAGS_IS_SET(p_params, PF_DST) ?
 482                    p_params->dst_pfid : p_hwfn->rel_pf_id;
 483         opcode |= (dst_pfid & DMAE_CMD_DST_PF_ID_MASK) <<
 484                   DMAE_CMD_DST_PF_ID_SHIFT;
 485
 486         /* DMAE_E4_TODO need to check which value to specify here. */
 487         /* opcode |= (!b_complete_to_host)<< DMAE_CMD_C_DST_SHIFT; */
 488
 489         /* Whether to write a completion word to the completion destination:
 490          * 0-Do not write a completion word
 491          * 1-Write the completion word
 492          */
 493         opcode |= DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT;
 494         opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
 495
 496         if (ECORE_DMAE_FLAGS_IS_SET(p_params, COMPLETION_DST))
 497                 opcode |= 1 << DMAE_CMD_COMP_FUNC_SHIFT;
 498
 499         /* swapping mode 3 - big endian there should be a define ifdefed in
 500          * the HSI somewhere. Since it is currently
 501          */
 502         opcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT;
 503
 504         port_id = (ECORE_DMAE_FLAGS_IS_SET(p_params, PORT)) ?
 505                   p_params->port_id : p_hwfn->port_id;
 506         opcode |= port_id << DMAE_CMD_PORT_ID_SHIFT;
 507
 508         /* reset source address in next go */
 509         opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
 510
 511         /* reset dest address in next go */
 512         opcode |= DMAE_CMD_DST_ADDR_RESET_MASK << DMAE_CMD_DST_ADDR_RESET_SHIFT;
 513
 514         /* SRC/DST VFID: all 1's - pf, otherwise VF id */
 515         if (ECORE_DMAE_FLAGS_IS_SET(p_params, VF_SRC)) {
 516                 opcode |= (1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT);
 517                 opcode_b |= (p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT);
 518         } else {
 519                 opcode_b |= (DMAE_CMD_SRC_VF_ID_MASK <<
 520                              DMAE_CMD_SRC_VF_ID_SHIFT);
 521         }
 522         if (ECORE_DMAE_FLAGS_IS_SET(p_params, VF_DST)) {
 523                 opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT;
 524                 opcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT;
 525         } else {
 526                 opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT;
 527         }
 528
 529         p_hwfn->dmae_info.p_dmae_cmd->opcode = OSAL_CPU_TO_LE32(opcode);
 530         p_hwfn->dmae_info.p_dmae_cmd->opcode_b = OSAL_CPU_TO_LE16(opcode_b);
 531 }
 532
 533 static u32 ecore_dmae_idx_to_go_cmd(u8 idx)
 534 {
 535         OSAL_BUILD_BUG_ON((DMAE_REG_GO_C31 - DMAE_REG_GO_C0) != 31 * 4);
 536
 537         /* All the DMAE 'go' registers form an array in internal memory */
 538         return DMAE_REG_GO_C0 + (idx << 2);
 539 }
 540
 541 static enum _ecore_status_t ecore_dmae_post_command(struct ecore_hwfn *p_hwfn,
 542                                                     struct ecore_ptt *p_ptt)
 543 {
 544         struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd;
 545         u8 idx_cmd = p_hwfn->dmae_info.channel, i;
 546         enum _ecore_status_t ecore_status = ECORE_SUCCESS;
 547
 548         /* verify address is not OSAL_NULL */
 549         if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) ||
 550              ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) {
 551                 DP_NOTICE(p_hwfn, true,
 552                           "source or destination address 0 idx_cmd=%d\n"
 553                           "opcode = [0x%08x,0x%04x] len=0x%x"
 554                           " src=0x%x:%x dst=0x%x:%x\n",
 555                           idx_cmd,
 556                           OSAL_LE32_TO_CPU(p_command->opcode),
 557                           OSAL_LE16_TO_CPU(p_command->opcode_b),
 558                           OSAL_LE16_TO_CPU(p_command->length_dw),
 559                           OSAL_LE32_TO_CPU(p_command->src_addr_hi),
 560                           OSAL_LE32_TO_CPU(p_command->src_addr_lo),
 561                           OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
 562                           OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
 563
 564                 return ECORE_INVAL;
 565         }
 566
 567         DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 568                    "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x]"
 569                    "len=0x%x src=0x%x:%x dst=0x%x:%x\n",
 570                    idx_cmd,
 571                    OSAL_LE32_TO_CPU(p_command->opcode),
 572                    OSAL_LE16_TO_CPU(p_command->opcode_b),
 573                    OSAL_LE16_TO_CPU(p_command->length_dw),
 574                    OSAL_LE32_TO_CPU(p_command->src_addr_hi),
 575                    OSAL_LE32_TO_CPU(p_command->src_addr_lo),
 576                    OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
 577                    OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
 578
 579         /* Copy the command to DMAE - need to do it before every call
 580          * for source/dest address no reset.
 581          * The number of commands have been increased to 16 (previous was 14)
 582          * The first 9 DWs are the command registers, the 10 DW is the
 583          * GO register, and
 584          * the rest are result registers (which are read only by the client).
 585          */
 586         for (i = 0; i < DMAE_CMD_SIZE; i++) {
 587                 u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ?
 588                     *(((u32 *)p_command) + i) : 0;
 589
 590                 ecore_wr(p_hwfn, p_ptt,
 591                          DMAE_REG_CMD_MEM +
 592                          (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) +
 593                          (i * sizeof(u32)), data);
 594         }
 595
 596         ecore_wr(p_hwfn, p_ptt,
 597                  ecore_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE);
 598
 599         return ecore_status;
 600 }
 601
 602 enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn)
 603 {
 604         dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr;
 605         struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd;
 606         u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer;
 607         u32 **p_comp = &p_hwfn->dmae_info.p_completion_word;
 608
 609         *p_comp = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr, sizeof(u32));
 610         if (*p_comp == OSAL_NULL) {
 611                 DP_NOTICE(p_hwfn, false,
 612                           "Failed to allocate `p_completion_word'\n");
 613                 goto err;
 614         }
 615
 616         p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr;
 617         *p_cmd = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
 618                                          sizeof(struct dmae_cmd));
 619         if (*p_cmd == OSAL_NULL) {
 620                 DP_NOTICE(p_hwfn, false,
 621                           "Failed to allocate `struct dmae_cmd'\n");
 622                 goto err;
 623         }
 624
 625         p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr;
 626         *p_buff = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, p_addr,
 627                                           sizeof(u32) * DMAE_MAX_RW_SIZE);
 628         if (*p_buff == OSAL_NULL) {
 629                 DP_NOTICE(p_hwfn, false,
 630                           "Failed to allocate `intermediate_buffer'\n");
 631                 goto err;
 632         }
 633
 634                 p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id;
 635                 p_hwfn->dmae_info.b_mem_ready = true;
 636
 637         return ECORE_SUCCESS;
 638 err:
 639         ecore_dmae_info_free(p_hwfn);
 640         return ECORE_NOMEM;
 641 }
 642
 643 void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn)
 644 {
 645         dma_addr_t p_phys;
 646
 647         OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
 648         p_hwfn->dmae_info.b_mem_ready = false;
 649         OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
 650
 651         if (p_hwfn->dmae_info.p_completion_word != OSAL_NULL) {
 652                 p_phys = p_hwfn->dmae_info.completion_word_phys_addr;
 653                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 654                                        p_hwfn->dmae_info.p_completion_word,
 655                                        p_phys, sizeof(u32));
 656                 p_hwfn->dmae_info.p_completion_word = OSAL_NULL;
 657         }
 658
 659         if (p_hwfn->dmae_info.p_dmae_cmd != OSAL_NULL) {
 660                 p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr;
 661                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 662                                        p_hwfn->dmae_info.p_dmae_cmd,
 663                                        p_phys, sizeof(struct dmae_cmd));
 664                 p_hwfn->dmae_info.p_dmae_cmd = OSAL_NULL;
 665         }
 666
 667         if (p_hwfn->dmae_info.p_intermediate_buffer != OSAL_NULL) {
 668                 p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
 669                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 670                                        p_hwfn->dmae_info.p_intermediate_buffer,
 671                                        p_phys, sizeof(u32) * DMAE_MAX_RW_SIZE);
 672                 p_hwfn->dmae_info.p_intermediate_buffer = OSAL_NULL;
 673         }
 674 }
 675
 676 static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn)
 677 {
 678         u32 wait_cnt_limit = 10000, wait_cnt = 0;
 679         enum _ecore_status_t ecore_status = ECORE_SUCCESS;
 680
 681 #ifndef ASIC_ONLY
 682         u32 factor = (CHIP_REV_IS_EMUL(p_hwfn->p_dev) ?
 683                       ECORE_EMUL_FACTOR :
 684                       (CHIP_REV_IS_FPGA(p_hwfn->p_dev) ?
 685                        ECORE_FPGA_FACTOR : 1));
 686
 687         wait_cnt_limit *= factor;
 688 #endif
 689
 690         /* DMAE_E4_TODO : TODO check if we have to call any other function
 691          * other than BARRIER to sync the completion_word since we are not
 692          * using the volatile keyword for this
 693          */
 694         OSAL_BARRIER(p_hwfn->p_dev);
 695         while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) {
 696                 OSAL_UDELAY(DMAE_MIN_WAIT_TIME);
 697                 if (++wait_cnt > wait_cnt_limit) {
 698                         DP_NOTICE(p_hwfn->p_dev, ECORE_MSG_HW,
 699                                   "Timed-out waiting for operation to"
 700                                   " complete. Completion word is 0x%08x"
 701                                   " expected 0x%08x.\n",
 702                                   *p_hwfn->dmae_info.p_completion_word,
 703                                   DMAE_COMPLETION_VAL);
 704                         ecore_status = ECORE_TIMEOUT;
 705                         break;
 706                 }
 707                 /* to sync the completion_word since we are not
 708                  * using the volatile keyword for p_completion_word
 709                  */
 710                 OSAL_BARRIER(p_hwfn->p_dev);
 711         }
 712
 713         if (ecore_status == ECORE_SUCCESS)
 714                 *p_hwfn->dmae_info.p_completion_word = 0;
 715
 716         return ecore_status;
 717 }
 718
 719 static enum _ecore_status_t
 720 ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
 721                                  struct ecore_ptt *p_ptt,
 722                                  u64 src_addr,
 723                                  u64 dst_addr,
 724                                  u8 src_type, u8 dst_type, u32 length_dw)
 725 {
 726         dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
 727         struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
 728         enum _ecore_status_t ecore_status = ECORE_SUCCESS;
 729
 730         switch (src_type) {
 731         case ECORE_DMAE_ADDRESS_GRC:
 732         case ECORE_DMAE_ADDRESS_HOST_PHYS:
 733                 cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(src_addr));
 734                 cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(src_addr));
 735                 break;
 736                 /* for virt source addresses we use the intermediate buffer. */
 737         case ECORE_DMAE_ADDRESS_HOST_VIRT:
 738                 cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
 739                 cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
 740                 OSAL_MEMCPY(&p_hwfn->dmae_info.p_intermediate_buffer[0],
 741                             (void *)(osal_uintptr_t)src_addr,
 742                             length_dw * sizeof(u32));
 743                 break;
 744         default:
 745                 return ECORE_INVAL;
 746         }
 747
 748         switch (dst_type) {
 749         case ECORE_DMAE_ADDRESS_GRC:
 750         case ECORE_DMAE_ADDRESS_HOST_PHYS:
 751                 cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(dst_addr));
 752                 cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(dst_addr));
 753                 break;
 754                 /* for virt destination address we use the intermediate buff. */
 755         case ECORE_DMAE_ADDRESS_HOST_VIRT:
 756                 cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
 757                 cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
 758                 break;
 759         default:
 760                 return ECORE_INVAL;
 761         }
 762
 763         cmd->length_dw = OSAL_CPU_TO_LE16((u16)length_dw);
 764
 765         if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
 766             src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
 767                 OSAL_DMA_SYNC(p_hwfn->p_dev,
 768                               (void *)HILO_U64(cmd->src_addr_hi,
 769                                                cmd->src_addr_lo),
 770                               length_dw * sizeof(u32), false);
 771
 772         ecore_dmae_post_command(p_hwfn, p_ptt);
 773
 774         ecore_status = ecore_dmae_operation_wait(p_hwfn);
 775
 776         /* TODO - is it true ? */
 777         if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
 778             src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
 779                 OSAL_DMA_SYNC(p_hwfn->p_dev,
 780                               (void *)HILO_U64(cmd->src_addr_hi,
 781                                                cmd->src_addr_lo),
 782                               length_dw * sizeof(u32), true);
 783
 784         if (ecore_status != ECORE_SUCCESS) {
 785                 DP_NOTICE(p_hwfn, ECORE_MSG_HW,
 786                           "Wait Failed. source_addr 0x%lx, grc_addr 0x%lx, size_in_dwords 0x%x, intermediate buffer 0x%lx.\n",
 787                           (unsigned long)src_addr, (unsigned long)dst_addr,
 788                           length_dw,
 789                           (unsigned long)p_hwfn->dmae_info.intermediate_buffer_phys_addr);
 790                 return ecore_status;
 791         }
 792
 793         if (dst_type == ECORE_DMAE_ADDRESS_HOST_VIRT)
 794                 OSAL_MEMCPY((void *)(osal_uintptr_t)(dst_addr),
 795                             &p_hwfn->dmae_info.p_intermediate_buffer[0],
 796                             length_dw * sizeof(u32));
 797
 798         return ECORE_SUCCESS;
 799 }
 800
 801 static enum _ecore_status_t
 802 ecore_dmae_execute_command(struct ecore_hwfn *p_hwfn,
 803                            struct ecore_ptt *p_ptt,
 804                            u64 src_addr,
 805                            u64 dst_addr,
 806                            u8 src_type,
 807                            u8 dst_type,
 808                            u32 size_in_dwords,
 809                            struct ecore_dmae_params *p_params)
 810 {
 811         dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr;
 812         u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0;
 813         struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
 814         u64 src_addr_split = 0, dst_addr_split = 0;
 815         u16 length_limit = DMAE_MAX_RW_SIZE;
 816         enum _ecore_status_t ecore_status = ECORE_SUCCESS;
 817         u32 offset = 0;
 818
 819         if (!p_hwfn->dmae_info.b_mem_ready) {
 820                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 821                            "No buffers allocated. Avoid DMAE transaction [{src: addr 0x%lx, type %d}, {dst: addr 0x%lx, type %d}, size %d].\n",
 822                            (unsigned long)src_addr, src_type,
 823                            (unsigned long)dst_addr, dst_type,
 824                            size_in_dwords);
 825                 return ECORE_NOMEM;
 826         }
 827
 828         if (p_hwfn->p_dev->recov_in_prog) {
 829                 DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
 830                            "Recovery is in progress. Avoid DMAE transaction [{src: addr 0x%lx, type %d}, {dst: addr 0x%lx, type %d}, size %d].\n",
 831                            (unsigned long)src_addr, src_type,
 832                            (unsigned long)dst_addr, dst_type,
 833                            size_in_dwords);
 834                 /* Return success to let the flow to be completed successfully
 835                  * w/o any error handling.
 836                  */
 837                 return ECORE_SUCCESS;
 838         }
 839
 840         if (!cmd) {
 841                 DP_NOTICE(p_hwfn, true,
 842                           "ecore_dmae_execute_sub_operation failed. Invalid state. source_addr 0x%lx, destination addr 0x%lx, size_in_dwords 0x%x\n",
 843                           (unsigned long)src_addr,
 844                           (unsigned long)dst_addr,
 845                           length_cur);
 846                 return ECORE_INVAL;
 847         }
 848
 849         ecore_dmae_opcode(p_hwfn,
 850                           (src_type == ECORE_DMAE_ADDRESS_GRC),
 851                           (dst_type == ECORE_DMAE_ADDRESS_GRC), p_params);
 852
 853         cmd->comp_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
 854         cmd->comp_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
 855         cmd->comp_val = OSAL_CPU_TO_LE32(DMAE_COMPLETION_VAL);
 856
 857         /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */
 858         cnt_split = size_in_dwords / length_limit;
 859         length_mod = size_in_dwords % length_limit;
 860
 861         src_addr_split = src_addr;
 862         dst_addr_split = dst_addr;
 863
 864         for (i = 0; i <= cnt_split; i++) {
 865                 offset = length_limit * i;
 866
 867                 if (!ECORE_DMAE_FLAGS_IS_SET(p_params, RW_REPL_SRC)) {
 868                         if (src_type == ECORE_DMAE_ADDRESS_GRC)
 869                                 src_addr_split = src_addr + offset;
 870                         else
 871                                 src_addr_split = src_addr + (offset * 4);
 872                 }
 873
 874                 if (dst_type == ECORE_DMAE_ADDRESS_GRC)
 875                         dst_addr_split = dst_addr + offset;
 876                 else
 877                         dst_addr_split = dst_addr + (offset * 4);
 878
 879                 length_cur = (cnt_split == i) ? length_mod : length_limit;
 880
 881                 /* might be zero on last iteration */
 882                 if (!length_cur)
 883                         continue;
 884
 885                 ecore_status = ecore_dmae_execute_sub_operation(p_hwfn,
 886                                                                 p_ptt,
 887                                                                 src_addr_split,
 888                                                                 dst_addr_split,
 889                                                                 src_type,
 890                                                                 dst_type,
 891                                                                 length_cur);
 892                 if (ecore_status != ECORE_SUCCESS) {
 893                         DP_NOTICE(p_hwfn, false,
 894                                   "ecore_dmae_execute_sub_operation Failed"
 895                                   " with error 0x%x. source_addr 0x%lx,"
 896                                   " dest addr 0x%lx, size_in_dwords 0x%x\n",
 897                                   ecore_status, (unsigned long)src_addr,
 898                                   (unsigned long)dst_addr, length_cur);
 899
 900                         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_DMAE_FAIL);
 901                         break;
 902                 }
 903         }
 904
 905         return ecore_status;
 906 }
 907
 908 enum _ecore_status_t ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
 909                                          struct ecore_ptt *p_ptt,
 910                                          u64 source_addr,
 911                                          u32 grc_addr,
 912                                          u32 size_in_dwords,
 913                                          struct ecore_dmae_params *p_params)
 914 {
 915         u32 grc_addr_in_dw = grc_addr / sizeof(u32);
 916         enum _ecore_status_t rc;
 917
 918         OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
 919
 920         rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
 921                                         grc_addr_in_dw,
 922                                         ECORE_DMAE_ADDRESS_HOST_VIRT,
 923                                         ECORE_DMAE_ADDRESS_GRC,
 924                                         size_in_dwords, p_params);
 925
 926         OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
 927
 928         return rc;
 929 }
 930
 931 enum _ecore_status_t ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
 932                                          struct ecore_ptt *p_ptt,
 933                                          u32 grc_addr,
 934                                          dma_addr_t dest_addr,
 935                                          u32 size_in_dwords,
 936                                          struct ecore_dmae_params *p_params)
 937 {
 938         u32 grc_addr_in_dw = grc_addr / sizeof(u32);
 939         enum _ecore_status_t rc;
 940
 941         OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
 942
 943         rc = ecore_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,
 944                                         dest_addr, ECORE_DMAE_ADDRESS_GRC,
 945                                         ECORE_DMAE_ADDRESS_HOST_VIRT,
 946                                         size_in_dwords, p_params);
 947
 948         OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
 949
 950         return rc;
 951 }
 952
 953 enum _ecore_status_t
 954 ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,
 955                      struct ecore_ptt *p_ptt,
 956                      dma_addr_t source_addr,
 957                      dma_addr_t dest_addr,
 958                      u32 size_in_dwords, struct ecore_dmae_params *p_params)
 959 {
 960         enum _ecore_status_t rc;
 961
 962         OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
 963
 964         rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
 965                                         dest_addr,
 966                                         ECORE_DMAE_ADDRESS_HOST_PHYS,
 967                                         ECORE_DMAE_ADDRESS_HOST_PHYS,
 968                                         size_in_dwords, p_params);
 969
 970         OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
 971
 972         return rc;
 973 }
 974
 975 void ecore_hw_err_notify(struct ecore_hwfn *p_hwfn,
 976                          enum ecore_hw_err_type err_type)
 977 {
 978         /* Fan failure cannot be masked by handling of another HW error */
 979         if (p_hwfn->p_dev->recov_in_prog && err_type != ECORE_HW_ERR_FAN_FAIL) {
 980                 DP_VERBOSE(p_hwfn, ECORE_MSG_DRV,
 981                            "Recovery is in progress."
 982                            "Avoid notifying about HW error %d.\n",
 983                            err_type);
 984                 return;
 985         }
 986
 987         OSAL_HW_ERROR_OCCURRED(p_hwfn, err_type);
 988 }
 989
 990 enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,
 991                                        struct ecore_ptt *p_ptt,
 992                                        const char *phase)
 993 {
 994         u32 size = OSAL_PAGE_SIZE / 2, val;
 995         enum _ecore_status_t rc = ECORE_SUCCESS;
 996         dma_addr_t p_phys;
 997         void *p_virt;
 998         u32 *p_tmp;
 999
1000         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, &p_phys, 2 * size);
1001         if (!p_virt) {
1002                 DP_NOTICE(p_hwfn, false,
1003                           "DMAE sanity [%s]: failed to allocate memory\n",
1004                           phase);
1005                 return ECORE_NOMEM;
1006         }
1007
1008         /* Fill the bottom half of the allocated memory with a known pattern */
1009         for (p_tmp = (u32 *)p_virt;
1010              p_tmp < (u32 *)((u8 *)p_virt + size);
1011              p_tmp++) {
1012                 /* Save the address itself as the value */
1013                 val = (u32)(osal_uintptr_t)p_tmp;
1014                 *p_tmp = val;
1015         }
1016
1017         /* Zero the top half of the allocated memory */
1018         OSAL_MEM_ZERO((u8 *)p_virt + size, size);
1019
1020         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1021                    "DMAE sanity [%s]: src_addr={phys 0x%lx, virt %p}, dst_addr={phys 0x%lx, virt %p}, size 0x%x\n",
1022                    phase, (unsigned long)p_phys, p_virt,
1023                    (unsigned long)(p_phys + size),
1024                    (u8 *)p_virt + size, size);
1025
1026         rc = ecore_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size,
1027                                   size / 4 /* size_in_dwords */,
1028                                   OSAL_NULL /* default parameters */);
1029         if (rc != ECORE_SUCCESS) {
1030                 DP_NOTICE(p_hwfn, false,
1031                           "DMAE sanity [%s]: ecore_dmae_host2host() failed. rc = %d.\n",
1032                           phase, rc);
1033                 goto out;
1034         }
1035
1036         /* Verify that the top half of the allocated memory has the pattern */
1037         for (p_tmp = (u32 *)((u8 *)p_virt + size);
1038              p_tmp < (u32 *)((u8 *)p_virt + (2 * size));
1039              p_tmp++) {
1040                 /* The corresponding address in the bottom half */
1041                 val = (u32)(osal_uintptr_t)p_tmp - size;
1042
1043                 if (*p_tmp != val) {
1044                         DP_NOTICE(p_hwfn, false,
1045                                   "DMAE sanity [%s]: addr={phys 0x%lx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n",
1046                                   phase,
1047                                   (unsigned long)p_phys +
1048                                    ((u8 *)p_tmp - (u8 *)p_virt),
1049                                   p_tmp, *p_tmp, val);
1050                         rc = ECORE_UNKNOWN_ERROR;
1051                         goto out;
1052                 }
1053         }
1054
1055 out:
1056         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_virt, p_phys, 2 * size);
1057         return rc;
1058 }
1059
1060 void ecore_ppfid_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1061                     u8 abs_ppfid, u32 hw_addr, u32 val)
1062 {
1063         u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
1064
1065         ecore_fid_pretend(p_hwfn, p_ptt,
1066                           pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
1067         ecore_wr(p_hwfn, p_ptt, hw_addr, val);
1068         ecore_fid_pretend(p_hwfn, p_ptt,
1069                           p_hwfn->rel_pf_id <<
1070                           PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
1071 }
1072
1073 u32 ecore_ppfid_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1074                    u8 abs_ppfid, u32 hw_addr)
1075 {
1076         u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
1077         u32 val;
1078
1079         ecore_fid_pretend(p_hwfn, p_ptt,
1080                           pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
1081         val = ecore_rd(p_hwfn, p_ptt, hw_addr);
1082         ecore_fid_pretend(p_hwfn, p_ptt,
1083                           p_hwfn->rel_pf_id <<
1084                           PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
1085
1086         return val;
1087 }