2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 /* include the precompiled configuration values - only once */
11 #include "ecore_hsi_common.h"
14 #include "ecore_status.h"
15 #include "ecore_rt_defs.h"
16 #include "ecore_init_fw_funcs.h"
18 #include "ecore_iro_values.h"
19 #include "ecore_sriov.h"
20 #include "ecore_gtt_values.h"
22 #include "ecore_init_ops.h"
24 #define ECORE_INIT_MAX_POLL_COUNT 100
25 #define ECORE_INIT_POLL_PERIOD_US 500
27 void ecore_init_iro_array(struct ecore_dev *p_dev)
29 p_dev->iro_arr = iro_arr;
32 /* Runtime configuration helpers */
33 void ecore_init_clear_rt_data(struct ecore_hwfn *p_hwfn)
37 for (i = 0; i < RUNTIME_ARRAY_SIZE; i++)
38 p_hwfn->rt_data.b_valid[i] = false;
41 void ecore_init_store_rt_reg(struct ecore_hwfn *p_hwfn, u32 rt_offset, u32 val)
43 p_hwfn->rt_data.init_val[rt_offset] = val;
44 p_hwfn->rt_data.b_valid[rt_offset] = true;
47 void ecore_init_store_rt_agg(struct ecore_hwfn *p_hwfn,
48 u32 rt_offset, u32 *p_val, osal_size_t size)
52 for (i = 0; i < size / sizeof(u32); i++) {
53 p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i];
54 p_hwfn->rt_data.b_valid[rt_offset + i] = true;
58 static enum _ecore_status_t ecore_init_rt(struct ecore_hwfn *p_hwfn,
59 struct ecore_ptt *p_ptt,
62 u16 size, bool b_must_dmae)
64 u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset];
65 bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset];
67 enum _ecore_status_t rc = ECORE_SUCCESS;
69 /* Since not all RT entries are initialized, go over the RT and
70 * for each segment of initialized values use DMA.
72 for (i = 0; i < size; i++) {
76 /* In case there isn't any wide-bus configuration here,
77 * simply write the data instead of using dmae.
80 ecore_wr(p_hwfn, p_ptt, addr + (i << 2), p_init_val[i]);
84 /* Start of a new segment */
85 for (segment = 1; i + segment < size; segment++)
86 if (!p_valid[i + segment])
89 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
90 (osal_uintptr_t)(p_init_val + i),
91 addr + (i << 2), segment, 0);
92 if (rc != ECORE_SUCCESS)
95 /* Jump over the entire segment, including invalid entry */
102 enum _ecore_status_t ecore_init_alloc(struct ecore_hwfn *p_hwfn)
104 struct ecore_rt_data *rt_data = &p_hwfn->rt_data;
106 if (IS_VF(p_hwfn->p_dev))
107 return ECORE_SUCCESS;
109 rt_data->b_valid = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
110 sizeof(bool) * RUNTIME_ARRAY_SIZE);
111 if (!rt_data->b_valid)
114 rt_data->init_val = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
115 sizeof(u32) * RUNTIME_ARRAY_SIZE);
116 if (!rt_data->init_val) {
117 OSAL_FREE(p_hwfn->p_dev, rt_data->b_valid);
121 return ECORE_SUCCESS;
124 void ecore_init_free(struct ecore_hwfn *p_hwfn)
126 OSAL_FREE(p_hwfn->p_dev, p_hwfn->rt_data.init_val);
127 OSAL_FREE(p_hwfn->p_dev, p_hwfn->rt_data.b_valid);
130 static enum _ecore_status_t ecore_init_array_dmae(struct ecore_hwfn *p_hwfn,
131 struct ecore_ptt *p_ptt,
133 u32 dmae_data_offset,
134 u32 size, const u32 *p_buf,
138 enum _ecore_status_t rc = ECORE_SUCCESS;
140 /* Perform DMAE only for lengthy enough sections or for wide-bus */
142 if ((CHIP_REV_IS_SLOW(p_hwfn->p_dev) && (size < 16)) ||
143 !b_can_dmae || (!b_must_dmae && (size < 16))) {
145 if (!b_can_dmae || (!b_must_dmae && (size < 16))) {
147 const u32 *data = p_buf + dmae_data_offset;
150 for (i = 0; i < size; i++)
151 ecore_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]);
153 rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
154 (osal_uintptr_t)(p_buf +
162 static enum _ecore_status_t ecore_init_fill_dmae(struct ecore_hwfn *p_hwfn,
163 struct ecore_ptt *p_ptt,
167 static u32 zero_buffer[DMAE_MAX_RW_SIZE];
169 OSAL_MEMSET(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
171 return ecore_dmae_host2grc(p_hwfn, p_ptt,
172 (osal_uintptr_t)&zero_buffer[0],
174 ECORE_DMAE_FLAG_RW_REPL_SRC);
177 static void ecore_init_fill(struct ecore_hwfn *p_hwfn,
178 struct ecore_ptt *p_ptt,
179 u32 addr, u32 fill, u32 fill_count)
183 for (i = 0; i < fill_count; i++, addr += sizeof(u32))
184 ecore_wr(p_hwfn, p_ptt, addr, fill);
187 static enum _ecore_status_t ecore_init_cmd_array(struct ecore_hwfn *p_hwfn,
188 struct ecore_ptt *p_ptt,
189 struct init_write_op *cmd,
193 u32 dmae_array_offset = OSAL_LE32_TO_CPU(cmd->args.array_offset);
194 u32 data = OSAL_LE32_TO_CPU(cmd->data);
195 u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
196 #ifdef CONFIG_ECORE_ZIPPED_FW
197 u32 offset, output_len, input_len, max_size;
199 struct ecore_dev *p_dev = p_hwfn->p_dev;
200 union init_array_hdr *hdr;
201 const u32 *array_data;
202 enum _ecore_status_t rc = ECORE_SUCCESS;
205 array_data = p_dev->fw_data->arr_data;
207 hdr = (union init_array_hdr *)
208 (uintptr_t)(array_data + dmae_array_offset);
209 data = OSAL_LE32_TO_CPU(hdr->raw.data);
210 switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) {
211 case INIT_ARR_ZIPPED:
212 #ifdef CONFIG_ECORE_ZIPPED_FW
213 offset = dmae_array_offset + 1;
214 input_len = GET_FIELD(data, INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE);
215 max_size = MAX_ZIPPED_SIZE * 4;
216 OSAL_MEMSET(p_hwfn->unzip_buf, 0, max_size);
218 output_len = OSAL_UNZIP_DATA(p_hwfn, input_len,
219 (u8 *)(uintptr_t)&array_data[offset],
221 (u8 *)p_hwfn->unzip_buf);
223 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr, 0,
226 b_must_dmae, b_can_dmae);
228 DP_NOTICE(p_hwfn, true, "Failed to unzip dmae data\n");
232 DP_NOTICE(p_hwfn, true,
233 "Using zipped firmware without config enabled\n");
237 case INIT_ARR_PATTERN:
239 u32 repeats = GET_FIELD(data,
240 INIT_ARRAY_PATTERN_HDR_REPETITIONS);
243 size = GET_FIELD(data,
244 INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE);
246 for (i = 0; i < repeats; i++, addr += size << 2) {
247 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr,
257 case INIT_ARR_STANDARD:
258 size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE);
259 rc = ecore_init_array_dmae(p_hwfn, p_ptt, addr,
260 dmae_array_offset + 1,
262 b_must_dmae, b_can_dmae);
269 /* init_ops write command */
270 static enum _ecore_status_t ecore_init_cmd_wr(struct ecore_hwfn *p_hwfn,
271 struct ecore_ptt *p_ptt,
272 struct init_write_op *p_cmd,
275 u32 data = OSAL_LE32_TO_CPU(p_cmd->data);
276 bool b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
277 u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
278 enum _ecore_status_t rc = ECORE_SUCCESS;
281 if (b_must_dmae && !b_can_dmae) {
282 DP_NOTICE(p_hwfn, true,
283 "Need to write to %08x for Wide-bus but DMAE isn't"
289 switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) {
290 case INIT_SRC_INLINE:
291 data = OSAL_LE32_TO_CPU(p_cmd->args.inline_val);
292 ecore_wr(p_hwfn, p_ptt, addr, data);
295 data = OSAL_LE32_TO_CPU(p_cmd->args.zeros_count);
296 if (b_must_dmae || (b_can_dmae && (data >= 64)))
297 rc = ecore_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data);
299 ecore_init_fill(p_hwfn, p_ptt, addr, 0, data);
302 rc = ecore_init_cmd_array(p_hwfn, p_ptt, p_cmd,
303 b_must_dmae, b_can_dmae);
305 case INIT_SRC_RUNTIME:
306 ecore_init_rt(p_hwfn, p_ptt, addr,
307 OSAL_LE16_TO_CPU(p_cmd->args.runtime.offset),
308 OSAL_LE16_TO_CPU(p_cmd->args.runtime.size),
316 static OSAL_INLINE bool comp_eq(u32 val, u32 expected_val)
318 return (val == expected_val);
321 static OSAL_INLINE bool comp_and(u32 val, u32 expected_val)
323 return (val & expected_val) == expected_val;
326 static OSAL_INLINE bool comp_or(u32 val, u32 expected_val)
328 return (val | expected_val) > 0;
331 /* init_ops read/poll commands */
332 static void ecore_init_cmd_rd(struct ecore_hwfn *p_hwfn,
333 struct ecore_ptt *p_ptt, struct init_read_op *cmd)
335 bool (*comp_check)(u32 val, u32 expected_val);
336 u32 delay = ECORE_INIT_POLL_PERIOD_US, val;
337 u32 data, addr, poll;
340 data = OSAL_LE32_TO_CPU(cmd->op_data);
341 addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2;
342 poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE);
345 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
349 val = ecore_rd(p_hwfn, p_ptt, addr);
351 if (poll == INIT_POLL_NONE)
356 comp_check = comp_eq;
359 comp_check = comp_or;
362 comp_check = comp_and;
365 DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n",
370 data = OSAL_LE32_TO_CPU(cmd->expected_val);
372 i < ECORE_INIT_MAX_POLL_COUNT && !comp_check(val, data); i++) {
374 val = ecore_rd(p_hwfn, p_ptt, addr);
377 if (i == ECORE_INIT_MAX_POLL_COUNT)
379 "Timeout when polling reg: 0x%08x [ Waiting-for: %08x"
380 " Got: %08x (comparsion %08x)]\n",
381 addr, OSAL_LE32_TO_CPU(cmd->expected_val), val,
382 OSAL_LE32_TO_CPU(cmd->op_data));
385 /* init_ops callbacks entry point */
386 static void ecore_init_cmd_cb(struct ecore_hwfn *p_hwfn,
387 struct ecore_ptt *p_ptt,
388 struct init_callback_op *p_cmd)
390 DP_NOTICE(p_hwfn, true,
391 "Currently init values have no need of callbacks\n");
394 static u8 ecore_init_cmd_mode_match(struct ecore_hwfn *p_hwfn,
395 u16 *p_offset, int modes)
397 struct ecore_dev *p_dev = p_hwfn->p_dev;
398 const u8 *modes_tree_buf;
399 u8 arg1, arg2, tree_val;
401 modes_tree_buf = p_dev->fw_data->modes_tree_buf;
402 tree_val = modes_tree_buf[(*p_offset)++];
404 case INIT_MODE_OP_NOT:
405 return ecore_init_cmd_mode_match(p_hwfn, p_offset, modes) ^ 1;
406 case INIT_MODE_OP_OR:
407 arg1 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
408 arg2 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
410 case INIT_MODE_OP_AND:
411 arg1 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
412 arg2 = ecore_init_cmd_mode_match(p_hwfn, p_offset, modes);
415 tree_val -= MAX_INIT_MODE_OPS;
416 return (modes & (1 << tree_val)) ? 1 : 0;
420 static u32 ecore_init_cmd_mode(struct ecore_hwfn *p_hwfn,
421 struct init_if_mode_op *p_cmd, int modes)
423 u16 offset = OSAL_LE16_TO_CPU(p_cmd->modes_buf_offset);
425 if (ecore_init_cmd_mode_match(p_hwfn, &offset, modes))
428 return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data),
429 INIT_IF_MODE_OP_CMD_OFFSET);
432 static u32 ecore_init_cmd_phase(struct ecore_hwfn *p_hwfn,
433 struct init_if_phase_op *p_cmd,
434 u32 phase, u32 phase_id)
436 u32 data = OSAL_LE32_TO_CPU(p_cmd->phase_data);
438 if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase &&
439 (GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID ||
440 GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id)))
441 return GET_FIELD(OSAL_LE32_TO_CPU(p_cmd->op_data),
442 INIT_IF_PHASE_OP_CMD_OFFSET);
447 enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
448 struct ecore_ptt *p_ptt,
449 int phase, int phase_id, int modes)
451 struct ecore_dev *p_dev = p_hwfn->p_dev;
452 u32 cmd_num, num_init_ops;
453 union init_op *init_ops;
455 enum _ecore_status_t rc = ECORE_SUCCESS;
457 num_init_ops = p_dev->fw_data->init_ops_size;
458 init_ops = p_dev->fw_data->init_ops;
460 #ifdef CONFIG_ECORE_ZIPPED_FW
461 p_hwfn->unzip_buf = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
462 MAX_ZIPPED_SIZE * 4);
463 if (!p_hwfn->unzip_buf) {
464 DP_NOTICE(p_hwfn, true, "Failed to allocate unzip buffer\n");
469 for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) {
470 union init_op *cmd = &init_ops[cmd_num];
471 u32 data = OSAL_LE32_TO_CPU(cmd->raw.op_data);
473 switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) {
475 rc = ecore_init_cmd_wr(p_hwfn, p_ptt, &cmd->write,
480 ecore_init_cmd_rd(p_hwfn, p_ptt, &cmd->read);
483 case INIT_OP_IF_MODE:
484 cmd_num += ecore_init_cmd_mode(p_hwfn, &cmd->if_mode,
487 case INIT_OP_IF_PHASE:
488 cmd_num += ecore_init_cmd_phase(p_hwfn, &cmd->if_phase,
490 b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE);
493 /* ecore_init_run is always invoked from
496 OSAL_UDELAY(cmd->delay.delay);
499 case INIT_OP_CALLBACK:
500 ecore_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
507 #ifdef CONFIG_ECORE_ZIPPED_FW
508 OSAL_FREE(p_hwfn->p_dev, p_hwfn->unzip_buf);
513 void ecore_gtt_init(struct ecore_hwfn *p_hwfn)
519 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
520 /* This is done by MFW on ASIC; regardless, this should only
521 * be done once per chip [i.e., common]. Implementation is
522 * not too bright, but it should work on the simple FPGA/EMUL
525 static bool initialized;
529 /* initialize PTT/GTT (poll for completion) */
531 ecore_wr(p_hwfn, p_hwfn->p_main_ptt,
532 PGLUE_B_REG_START_INIT_PTT_GTT, 1);
537 /* ptt might be overrided by HW until this is done */
539 ecore_ptt_invalidate(p_hwfn);
540 val = ecore_rd(p_hwfn, p_hwfn->p_main_ptt,
541 PGLUE_B_REG_INIT_DONE_PTT_GTT);
542 } while ((val != 1) && --poll_cnt);
546 "PGLUE_B_REG_INIT_DONE didn't complete\n");
550 /* Set the global windows */
551 gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;
553 for (i = 0; i < OSAL_ARRAY_SIZE(pxp_global_win); i++)
554 if (pxp_global_win[i])
555 REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
559 enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
562 struct ecore_fw_data *fw = p_dev->fw_data;
564 #ifdef CONFIG_ECORE_BINARY_FW
565 struct bin_buffer_hdr *buf_hdr;
569 DP_NOTICE(p_dev, true, "Invalid fw data\n");
573 buf_hdr = (struct bin_buffer_hdr *)(uintptr_t)data;
575 offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
576 fw->fw_ver_info = (struct fw_ver_info *)((uintptr_t)(data + offset));
578 offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
579 fw->init_ops = (union init_op *)((uintptr_t)(data + offset));
581 offset = buf_hdr[BIN_BUF_INIT_VAL].offset;
582 fw->arr_data = (u32 *)((uintptr_t)(data + offset));
584 offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset;
585 fw->modes_tree_buf = (u8 *)((uintptr_t)(data + offset));
586 len = buf_hdr[BIN_BUF_INIT_CMD].length;
587 fw->init_ops_size = len / sizeof(struct init_raw_op);
589 fw->init_ops = (union init_op *)init_ops;
590 fw->arr_data = (u32 *)init_val;
591 fw->modes_tree_buf = (u8 *)modes_tree_buf;
592 fw->init_ops_size = init_ops_size;
595 return ECORE_SUCCESS;