drivers/net/qede/base/ecore_int.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include <rte_string_fns.h>
  10
  11 #include "bcm_osal.h"
  12 #include "ecore.h"
  13 #include "ecore_spq.h"
  14 #include "reg_addr.h"
  15 #include "ecore_gtt_reg_addr.h"
  16 #include "ecore_init_ops.h"
  17 #include "ecore_rt_defs.h"
  18 #include "ecore_int.h"
  19 #include "reg_addr.h"
  20 #include "ecore_hw.h"
  21 #include "ecore_sriov.h"
  22 #include "ecore_vf.h"
  23 #include "ecore_hw_defs.h"
  24 #include "ecore_hsi_common.h"
  25 #include "ecore_mcp.h"
  26
  27 struct ecore_pi_info {
  28         ecore_int_comp_cb_t comp_cb;
  29         void *cookie;           /* Will be sent to the compl cb function */
  30 };
  31
  32 struct ecore_sb_sp_info {
  33         struct ecore_sb_info sb_info;
  34         /* per protocol index data */
  35         struct ecore_pi_info pi_info_arr[PIS_PER_SB];
  36 };
  37
  38 enum ecore_attention_type {
  39         ECORE_ATTN_TYPE_ATTN,
  40         ECORE_ATTN_TYPE_PARITY,
  41 };
  42
  43 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  44         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  45
  46 struct aeu_invert_reg_bit {
  47         char bit_name[30];
  48
  49 #define ATTENTION_PARITY                (1 << 0)
  50
  51 #define ATTENTION_LENGTH_MASK           (0x00000ff0)
  52 #define ATTENTION_LENGTH_SHIFT          (4)
  53 #define ATTENTION_LENGTH(flags)         (((flags) & ATTENTION_LENGTH_MASK) >> \
  54                                          ATTENTION_LENGTH_SHIFT)
  55 #define ATTENTION_SINGLE                (1 << ATTENTION_LENGTH_SHIFT)
  56 #define ATTENTION_PAR                   (ATTENTION_SINGLE | ATTENTION_PARITY)
  57 #define ATTENTION_PAR_INT               ((2 << ATTENTION_LENGTH_SHIFT) | \
  58                                          ATTENTION_PARITY)
  59
  60 /* Multiple bits start with this offset */
  61 #define ATTENTION_OFFSET_MASK           (0x000ff000)
  62 #define ATTENTION_OFFSET_SHIFT          (12)
  63
  64 #define ATTENTION_CLEAR_ENABLE          (1 << 28)
  65         unsigned int flags;
  66
  67         /* Callback to call if attention will be triggered */
  68         enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
  69
  70         enum block_id block_index;
  71 };
  72
  73 struct aeu_invert_reg {
  74         struct aeu_invert_reg_bit bits[32];
  75 };
  76
  77 #define MAX_ATTN_GRPS           (8)
  78 #define NUM_ATTN_REGS           (9)
  79
  80 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
  81 {
  82         u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
  83
  84         DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", tmp);
  85         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 0xffffffff);
  86
  87         return ECORE_SUCCESS;
  88 }
  89
  90 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK         (0x3c000)
  91 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT        (14)
  92 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK         (0x03fc0)
  93 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT        (6)
  94 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK      (0x00020)
  95 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT     (5)
  96 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK     (0x0001e)
  97 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT    (1)
  98 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK      (0x1)
  99 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT     (0)
 100 #define ECORE_PSWHST_ATTENTION_VF_DISABLED              (0x1)
 101 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS         (0x1)
 102 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK         (0x1)
 103 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT        (0)
 104 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK     (0x1e)
 105 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT    (1)
 106 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK   (0x20)
 107 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT  (5)
 108 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK      (0x3fc0)
 109 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT     (6)
 110 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK      (0x3c000)
 111 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT     (14)
 112 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK    (0x3fc0000)
 113 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT   (18)
 114 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
 115 {
 116         u32 tmp =
 117             ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 118                      PSWHST_REG_VF_DISABLED_ERROR_VALID);
 119
 120         /* Disabled VF access */
 121         if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
 122                 u32 addr, data;
 123
 124                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 125                                 PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
 126                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 127                                 PSWHST_REG_VF_DISABLED_ERROR_DATA);
 128                 DP_INFO(p_hwfn->p_dev,
 129                         "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x]"
 130                         " Write [0x%02x] Addr [0x%08x]\n",
 131                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK)
 132                              >> ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
 133                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK)
 134                              >> ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
 135                         (u8)((data &
 136                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
 137                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
 138                         (u8)((data &
 139                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
 140                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
 141                         (u8)((data &
 142                               ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
 143                               ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
 144                         addr);
 145         }
 146
 147         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 148                        PSWHST_REG_INCORRECT_ACCESS_VALID);
 149         if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
 150                 u32 addr, data, length;
 151
 152                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 153                                 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
 154                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 155                                 PSWHST_REG_INCORRECT_ACCESS_DATA);
 156                 length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 157                                   PSWHST_REG_INCORRECT_ACCESS_LENGTH);
 158
 159                 DP_INFO(p_hwfn->p_dev,
 160                         "Incorrect access to %08x of length %08x - PF [%02x]"
 161                         " VF [%04x] [valid %02x] client [%02x] write [%02x]"
 162                         " Byte-Enable [%04x] [%08x]\n",
 163                         addr, length,
 164                         (u8)((data &
 165                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
 166                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
 167                         (u8)((data &
 168                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
 169                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
 170                         (u8)((data &
 171                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
 172                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
 173                         (u8)((data &
 174                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
 175                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
 176                         (u8)((data &
 177                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
 178                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
 179                         (u8)((data &
 180                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
 181                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
 182                         data);
 183         }
 184
 185         /* TODO - We know 'some' of these are legal due to virtualization,
 186          * but is it true for all of them?
 187          */
 188         return ECORE_SUCCESS;
 189 }
 190
 191 #define ECORE_GRC_ATTENTION_VALID_BIT           (1 << 0)
 192 #define ECORE_GRC_ATTENTION_ADDRESS_MASK        (0x7fffff << 0)
 193 #define ECORE_GRC_ATTENTION_RDWR_BIT            (1 << 23)
 194 #define ECORE_GRC_ATTENTION_MASTER_MASK         (0xf << 24)
 195 #define ECORE_GRC_ATTENTION_MASTER_SHIFT        (24)
 196 #define ECORE_GRC_ATTENTION_PF_MASK             (0xf)
 197 #define ECORE_GRC_ATTENTION_VF_MASK             (0xff << 4)
 198 #define ECORE_GRC_ATTENTION_VF_SHIFT            (4)
 199 #define ECORE_GRC_ATTENTION_PRIV_MASK           (0x3 << 14)
 200 #define ECORE_GRC_ATTENTION_PRIV_SHIFT          (14)
 201 #define ECORE_GRC_ATTENTION_PRIV_VF             (0)
 202 static const char *grc_timeout_attn_master_to_str(u8 master)
 203 {
 204         switch (master) {
 205         case 1:
 206                 return "PXP";
 207         case 2:
 208                 return "MCP";
 209         case 3:
 210                 return "MSDM";
 211         case 4:
 212                 return "PSDM";
 213         case 5:
 214                 return "YSDM";
 215         case 6:
 216                 return "USDM";
 217         case 7:
 218                 return "TSDM";
 219         case 8:
 220                 return "XSDM";
 221         case 9:
 222                 return "DBU";
 223         case 10:
 224                 return "DMAE";
 225         default:
 226                 return "Unknown";
 227         }
 228 }
 229
 230 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
 231 {
 232         u32 tmp, tmp2;
 233
 234         /* We've already cleared the timeout interrupt register, so we learn
 235          * of interrupts via the validity register
 236          */
 237         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 238                        GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
 239         if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT))
 240                 goto out;
 241
 242         /* Read the GRC timeout information */
 243         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 244                        GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
 245         tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 246                         GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
 247
 248         DP_INFO(p_hwfn->p_dev,
 249                 "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s]"
 250                 " [PF: %02x %s %02x]\n",
 251                 tmp2, tmp,
 252                 (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
 253                 (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
 254                 grc_timeout_attn_master_to_str((tmp &
 255                                         ECORE_GRC_ATTENTION_MASTER_MASK) >>
 256                                        ECORE_GRC_ATTENTION_MASTER_SHIFT),
 257                 (tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
 258                 (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
 259                   ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
 260                  ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
 261                 (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
 262                 ECORE_GRC_ATTENTION_VF_SHIFT);
 263
 264 out:
 265         /* Regardles of anything else, clean the validity bit */
 266         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 267                  GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
 268         return ECORE_SUCCESS;
 269 }
 270
 271 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
 272 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
 273 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
 274 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
 275 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
 276 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
 277 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
 278 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
 279 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME      (1 << 22)
 280 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
 281 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
 282 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
 283 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
 284 static enum _ecore_status_t ecore_pglub_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
 285 {
 286         u32 tmp;
 287
 288         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 289                        PGLUE_B_REG_TX_ERR_WR_DETAILS2);
 290         if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
 291                 u32 addr_lo, addr_hi, details;
 292
 293                 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 294                                    PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
 295                 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 296                                    PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
 297                 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 298                                    PGLUE_B_REG_TX_ERR_WR_DETAILS);
 299
 300                 DP_INFO(p_hwfn,
 301                         "Illegal write by chip to [%08x:%08x] blocked."
 302                         "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]"
 303                         " Details2 %08x [Was_error %02x BME deassert %02x"
 304                         " FID_enable deassert %02x]\n",
 305                         addr_hi, addr_lo, details,
 306                         (u8)((details &
 307                               ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 308                              ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 309                         (u8)((details &
 310                               ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 311                              ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 312                         (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID)
 313                              ? 1 : 0), tmp,
 314                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1
 315                              : 0),
 316                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 :
 317                              0),
 318                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1
 319                              : 0));
 320         }
 321
 322         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 323                        PGLUE_B_REG_TX_ERR_RD_DETAILS2);
 324         if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
 325                 u32 addr_lo, addr_hi, details;
 326
 327                 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 328                                    PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
 329                 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 330                                    PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
 331                 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 332                                    PGLUE_B_REG_TX_ERR_RD_DETAILS);
 333
 334                 DP_INFO(p_hwfn,
 335                         "Illegal read by chip from [%08x:%08x] blocked."
 336                         " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]"
 337                         " Details2 %08x [Was_error %02x BME deassert %02x"
 338                         " FID_enable deassert %02x]\n",
 339                         addr_hi, addr_lo, details,
 340                         (u8)((details &
 341                               ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 342                              ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 343                         (u8)((details &
 344                               ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 345                              ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 346                         (u8)((details & ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID)
 347                              ? 1 : 0), tmp,
 348                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1
 349                              : 0),
 350                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ? 1 :
 351                              0),
 352                         (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1
 353                              : 0));
 354         }
 355
 356         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 357                        PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
 358         if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
 359                 DP_INFO(p_hwfn, "ICPL error - %08x\n", tmp);
 360
 361         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 362                        PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
 363         if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
 364                 u32 addr_hi, addr_lo;
 365
 366                 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 367                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
 368                 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 369                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
 370
 371                 DP_INFO(p_hwfn, "ICPL error - %08x [Address %08x:%08x]\n",
 372                         tmp, addr_hi, addr_lo);
 373         }
 374
 375         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 376                        PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
 377         if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
 378                 u32 addr_hi, addr_lo, details;
 379
 380                 addr_lo = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 381                                    PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
 382                 addr_hi = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 383                                    PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
 384                 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 385                                    PGLUE_B_REG_VF_ILT_ERR_DETAILS);
 386
 387                 DP_INFO(p_hwfn,
 388                         "ILT error - Details %08x Details2 %08x"
 389                         " [Address %08x:%08x]\n",
 390                         details, tmp, addr_hi, addr_lo);
 391         }
 392
 393         /* Clear the indications */
 394         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 395                  PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
 396
 397         return ECORE_SUCCESS;
 398 }
 399
 400 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
 401 {
 402         DP_NOTICE(p_hwfn, false, "FW assertion!\n");
 403
 404         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
 405
 406         return ECORE_INVAL;
 407 }
 408
 409 static enum _ecore_status_t
 410 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
 411 {
 412         DP_INFO(p_hwfn, "General attention 35!\n");
 413
 414         return ECORE_SUCCESS;
 415 }
 416
 417 #define ECORE_DORQ_ATTENTION_REASON_MASK (0xfffff)
 418 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
 419 #define ECORE_DORQ_ATTENTION_SIZE_MASK   (0x7f)
 420 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT  (16)
 421
 422 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
 423 {
 424         u32 reason;
 425
 426         reason = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) &
 427             ECORE_DORQ_ATTENTION_REASON_MASK;
 428         if (reason) {
 429                 u32 details = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 430                                        DORQ_REG_DB_DROP_DETAILS);
 431
 432                 DP_INFO(p_hwfn->p_dev,
 433                         "DORQ db_drop: address 0x%08x Opaque FID 0x%04x"
 434                         " Size [bytes] 0x%08x Reason: 0x%08x\n",
 435                         ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 436                                  DORQ_REG_DB_DROP_DETAILS_ADDRESS),
 437                         (u16)(details & ECORE_DORQ_ATTENTION_OPAQUE_MASK),
 438                         ((details & ECORE_DORQ_ATTENTION_SIZE_MASK) >>
 439                          ECORE_DORQ_ATTENTION_SIZE_SHIFT) * 4, reason);
 440         }
 441
 442         return ECORE_INVAL;
 443 }
 444
 445 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
 446 {
 447 #ifndef ASIC_ONLY
 448         if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
 449                 u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 450                                    TM_REG_INT_STS_1);
 451
 452                 if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
 453                             TM_REG_INT_STS_1_PEND_CONN_SCAN))
 454                         return ECORE_INVAL;
 455
 456                 if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
 457                            TM_REG_INT_STS_1_PEND_CONN_SCAN))
 458                         DP_INFO(p_hwfn,
 459                                 "TM attention on emulation - most likely"
 460                                 " results of clock-ratios\n");
 461                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
 462                 val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
 463                     TM_REG_INT_MASK_1_PEND_TASK_SCAN;
 464                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
 465
 466                 return ECORE_SUCCESS;
 467         }
 468 #endif
 469
 470         return ECORE_INVAL;
 471 }
 472
 473 /* Notice aeu_invert_reg must be defined in the same order of bits as HW;  */
 474 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
 475         {
 476          {                      /* After Invert 1 */
 477           {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 478            MAX_BLOCK_ID},
 479           }
 480          },
 481
 482         {
 483          {                      /* After Invert 2 */
 484           {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 485           {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 486           {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglub_rbc_attn_cb,
 487            BLOCK_PGLUE_B},
 488           {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 489           {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 490           {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 491           {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 492           {"SW timers #%d",
 493            (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT),
 494            OSAL_NULL, MAX_BLOCK_ID},
 495           {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 496            BLOCK_PGLCS},
 497           }
 498          },
 499
 500         {
 501          {                      /* After Invert 3 */
 502           {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 503            MAX_BLOCK_ID},
 504           }
 505          },
 506
 507         {
 508          {                      /* After Invert 4 */
 509           {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 510            ecore_fw_assertion, MAX_BLOCK_ID},
 511           {"General Attention %d",
 512            (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT),
 513            OSAL_NULL, MAX_BLOCK_ID},
 514           {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 515            ecore_general_attention_35, MAX_BLOCK_ID},
 516           {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 517            BLOCK_CNIG},
 518           {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
 519           {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 520           {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 521           {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 522           {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 523           {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 524           {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 525            MAX_BLOCK_ID},
 526           {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
 527           {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
 528           {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
 529           {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
 530           {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
 531           }
 532          },
 533
 534         {
 535          {                      /* After Invert 5 */
 536           {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
 537           {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
 538           {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
 539           {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
 540           {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
 541           {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
 542           {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
 543           {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
 544           {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
 545           {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
 546           {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
 547           {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
 548           {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
 549           {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
 550           {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
 551           {"TSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSEM},
 552           }
 553          },
 554
 555         {
 556          {                      /* After Invert 6 */
 557           {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
 558           {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
 559           {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
 560           {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
 561           {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
 562           {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
 563           {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
 564           {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
 565           {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
 566           {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
 567           {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
 568           {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
 569           {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
 570           {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
 571           {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
 572           {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
 573           }
 574          },
 575
 576         {
 577          {                      /* After Invert 7 */
 578           {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
 579           {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
 580           {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
 581           {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
 582           {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 583           {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
 584           {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
 585           {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
 586           {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
 587           {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
 588           {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
 589           {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
 590           {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
 591           {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
 592           {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
 593           {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 594           {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
 595           }
 596          },
 597
 598         {
 599          {                      /* After Invert 8 */
 600           {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
 601           {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
 602           {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
 603           {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
 604           {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
 605           {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
 606           {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
 607           {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
 608           {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
 609           {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
 610           {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 611           {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 612           {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 613           {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 614           {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 615           {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 616           {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
 617           {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 618           {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 619           {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 620           {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 621            MAX_BLOCK_ID},
 622           }
 623          },
 624
 625         {
 626          {                      /* After Invert 9 */
 627           {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 628           {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL,
 629            MAX_BLOCK_ID},
 630           {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 631           {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 632           {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 633            MAX_BLOCK_ID},
 634           }
 635          },
 636
 637 };
 638
 639 #define ATTN_STATE_BITS         (0xfff)
 640 #define ATTN_BITS_MASKABLE      (0x3ff)
 641 struct ecore_sb_attn_info {
 642         /* Virtual & Physical address of the SB */
 643         struct atten_status_block *sb_attn;
 644         dma_addr_t sb_phys;
 645
 646         /* Last seen running index */
 647         u16 index;
 648
 649         /* A mask of the AEU bits resulting in a parity error */
 650         u32 parity_mask[NUM_ATTN_REGS];
 651
 652         /* A pointer to the attention description structure */
 653         struct aeu_invert_reg *p_aeu_desc;
 654
 655         /* Previously asserted attentions, which are still unasserted */
 656         u16 known_attn;
 657
 658         /* Cleanup address for the link's general hw attention */
 659         u32 mfw_attn_addr;
 660 };
 661
 662 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
 663                                  struct ecore_sb_attn_info *p_sb_desc)
 664 {
 665         u16 rc = 0, index;
 666
 667         OSAL_MMIOWB(p_hwfn->p_dev);
 668
 669         index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
 670         if (p_sb_desc->index != index) {
 671                 p_sb_desc->index = index;
 672                 rc = ECORE_SB_ATT_IDX;
 673         }
 674
 675         OSAL_MMIOWB(p_hwfn->p_dev);
 676
 677         return rc;
 678 }
 679
 680 /**
 681  * @brief ecore_int_assertion - handles asserted attention bits
 682  *
 683  * @param p_hwfn
 684  * @param asserted_bits newly asserted bits
 685  * @return enum _ecore_status_t
 686  */
 687 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
 688                                                 u16 asserted_bits)
 689 {
 690         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 691         u32 igu_mask;
 692
 693         /* Mask the source of the attention in the IGU */
 694         igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 695                             IGU_REG_ATTENTION_ENABLE);
 696         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 697                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 698         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 699         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 700
 701         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 702                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 703                    sb_attn_sw->known_attn,
 704                    sb_attn_sw->known_attn | asserted_bits);
 705         sb_attn_sw->known_attn |= asserted_bits;
 706
 707         /* Handle MCP events */
 708         if (asserted_bits & 0x100) {
 709                 ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 710                 /* Clean the MCP attention */
 711                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 712                          sb_attn_sw->mfw_attn_addr, 0);
 713         }
 714
 715         /* FIXME - this will change once we'll have GOOD gtt definitions */
 716         DIRECT_REG_WR(p_hwfn,
 717                       (u8 OSAL_IOMEM *) p_hwfn->regview +
 718                       GTT_BAR0_MAP_REG_IGU_CMD +
 719                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 720                         IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
 721
 722         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
 723                    asserted_bits);
 724
 725         return ECORE_SUCCESS;
 726 }
 727
 728 static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
 729                                  enum block_id id, enum dbg_attn_type type,
 730                                  bool b_clear)
 731 {
 732         /* @DPDK */
 733         DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n", id, type);
 734 }
 735
 736 /**
 737  * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
 738  * cause of the attention
 739  *
 740  * @param p_hwfn
 741  * @param p_aeu - descriptor of an AEU bit which caused the attention
 742  * @param aeu_en_reg - register offset of the AEU enable reg. which configured
 743  *  this bit to this group.
 744  * @param bit_index - index of this bit in the aeu_en_reg
 745  *
 746  * @return enum _ecore_status_t
 747  */
 748 static enum _ecore_status_t
 749 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
 750                               struct aeu_invert_reg_bit *p_aeu,
 751                               u32 aeu_en_reg,
 752                               const char *p_bit_name,
 753                               u32 bitmask)
 754 {
 755         enum _ecore_status_t rc = ECORE_INVAL;
 756         bool b_fatal = false;
 757
 758         DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
 759                 p_bit_name, bitmask);
 760
 761         /* Call callback before clearing the interrupt status */
 762         if (p_aeu->cb) {
 763                 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
 764                         p_bit_name);
 765                 rc = p_aeu->cb(p_hwfn);
 766         }
 767
 768         if (rc != ECORE_SUCCESS)
 769                 b_fatal = true;
 770
 771         /* Print HW block interrupt registers */
 772         if (p_aeu->block_index != MAX_BLOCK_ID) {
 773                 ecore_int_attn_print(p_hwfn, p_aeu->block_index,
 774                                      ATTN_TYPE_INTERRUPT, !b_fatal);
 775 }
 776
 777         /* Reach assertion if attention is fatal */
 778         if (b_fatal) {
 779                 DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
 780                           p_bit_name);
 781
 782                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
 783         }
 784
 785         /* Prevent this Attention from being asserted in the future */
 786         if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
 787             p_hwfn->p_dev->attn_clr_en) {
 788                 u32 val;
 789                 u32 mask = ~bitmask;
 790                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 791                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
 792                 DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
 793                         p_bit_name);
 794         }
 795
 796         return rc;
 797 }
 798
 799 /**
 800  * @brief ecore_int_deassertion_parity - handle a single parity AEU source
 801  *
 802  * @param p_hwfn
 803  * @param p_aeu - descriptor of an AEU bit which caused the
 804  *              parity
 805  * @param bit_index
 806  */
 807 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
 808                                          struct aeu_invert_reg_bit *p_aeu,
 809                                          u8 bit_index)
 810 {
 811         u32 block_id = p_aeu->block_index;
 812
 813         DP_INFO(p_hwfn->p_dev, "%s[%d] parity attention is set\n",
 814                 p_aeu->bit_name, bit_index);
 815
 816         if (block_id == MAX_BLOCK_ID)
 817                 return;
 818
 819         ecore_int_attn_print(p_hwfn, block_id,
 820                              ATTN_TYPE_PARITY, false);
 821
 822         /* In A0, there's a single parity bit for several blocks */
 823         if (block_id == BLOCK_BTB) {
 824                 ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
 825                                      ATTN_TYPE_PARITY, false);
 826                 ecore_int_attn_print(p_hwfn, BLOCK_MCP,
 827                                      ATTN_TYPE_PARITY, false);
 828         }
 829 }
 830
 831 /**
 832  * @brief - handles deassertion of previously asserted attentions.
 833  *
 834  * @param p_hwfn
 835  * @param deasserted_bits - newly deasserted bits
 836  * @return enum _ecore_status_t
 837  *
 838  */
 839 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
 840                                                   u16 deasserted_bits)
 841 {
 842         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 843         u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask;
 844         bool b_parity = false;
 845         u8 i, j, k, bit_idx;
 846         enum _ecore_status_t rc = ECORE_SUCCESS;
 847
 848         /* Read the attention registers in the AEU */
 849         for (i = 0; i < NUM_ATTN_REGS; i++) {
 850                 aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 851                                           MISC_REG_AEU_AFTER_INVERT_1_IGU +
 852                                           i * 0x4);
 853                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 854                            "Deasserted bits [%d]: %08x\n", i, aeu_inv_arr[i]);
 855         }
 856
 857         /* Handle parity attentions first */
 858         for (i = 0; i < NUM_ATTN_REGS; i++) {
 859                 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
 860                 u32 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 861                                   MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
 862                                   i * sizeof(u32));
 863
 864                 u32 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
 865
 866                 /* Skip register in which no parity bit is currently set */
 867                 if (!parities)
 868                         continue;
 869
 870                 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
 871                         struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
 872
 873                         if ((p_bit->flags & ATTENTION_PARITY) &&
 874                             !!(parities & (1 << bit_idx))) {
 875                                 ecore_int_deassertion_parity(p_hwfn, p_bit,
 876                                                              bit_idx);
 877                                 b_parity = true;
 878                         }
 879
 880                         bit_idx += ATTENTION_LENGTH(p_bit->flags);
 881                 }
 882         }
 883
 884         /* Find non-parity cause for attention and act */
 885         for (k = 0; k < MAX_ATTN_GRPS; k++) {
 886                 struct aeu_invert_reg_bit *p_aeu;
 887
 888                 /* Handle only groups whose attention is currently deasserted */
 889                 if (!(deasserted_bits & (1 << k)))
 890                         continue;
 891
 892                 for (i = 0; i < NUM_ATTN_REGS; i++) {
 893                         u32 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
 894                             i * sizeof(u32) + k * sizeof(u32) * NUM_ATTN_REGS;
 895                         u32 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
 896                         u32 bits = aeu_inv_arr[i] & en;
 897
 898                         /* Skip if no bit from this group is currently set */
 899                         if (!bits)
 900                                 continue;
 901
 902                         /* Find all set bits from current register which belong
 903                          * to current group, making them responsible for the
 904                          * previous assertion.
 905                          */
 906                         for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
 907                                 unsigned long int bitmask;
 908                                 u8 bit, bit_len;
 909
 910                                 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
 911
 912                                 /* No need to handle attention-only bits */
 913                                 if (p_aeu->flags == ATTENTION_PAR)
 914                                         continue;
 915
 916                                 bit = bit_idx;
 917                                 bit_len = ATTENTION_LENGTH(p_aeu->flags);
 918                                 if (p_aeu->flags & ATTENTION_PAR_INT) {
 919                                         /* Skip Parity */
 920                                         bit++;
 921                                         bit_len--;
 922                                 }
 923
 924                                 bitmask = bits & (((1 << bit_len) - 1) << bit);
 925                                 if (bitmask) {
 926                                         u32 flags = p_aeu->flags;
 927                                         char bit_name[30];
 928
 929                                         bit = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
 930                                                                 bit_len);
 931
 932                                         /* Some bits represent more than a
 933                                          * a single interrupt. Correctly print
 934                                          * their name.
 935                                          */
 936                                         if (ATTENTION_LENGTH(flags) > 2 ||
 937                                             ((flags & ATTENTION_PAR_INT) &&
 938                                             ATTENTION_LENGTH(flags) > 1))
 939                                                 OSAL_SNPRINTF(bit_name, 30,
 940                                                               p_aeu->bit_name,
 941                                                               bit);
 942                                         else
 943                                                 strlcpy(bit_name,
 944                                                         p_aeu->bit_name,
 945                                                         sizeof(bit_name));
 946
 947                                         /* Handle source of the attention */
 948                                         ecore_int_deassertion_aeu_bit(p_hwfn,
 949                                                                       p_aeu,
 950                                                                       aeu_en,
 951                                                                       bit_name,
 952                                                                       bitmask);
 953                                 }
 954
 955                                 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
 956                         }
 957                 }
 958         }
 959
 960         /* Clear IGU indication for the deasserted bits */
 961         /* FIXME - this will change once we'll have GOOD gtt definitions */
 962         DIRECT_REG_WR(p_hwfn,
 963                       (u8 OSAL_IOMEM *) p_hwfn->regview +
 964                       GTT_BAR0_MAP_REG_IGU_CMD +
 965                       ((IGU_CMD_ATTN_BIT_CLR_UPPER -
 966                         IGU_CMD_INT_ACK_BASE) << 3), ~((u32)deasserted_bits));
 967
 968         /* Unmask deasserted attentions in IGU */
 969         aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 970                             IGU_REG_ATTENTION_ENABLE);
 971         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
 972         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
 973
 974         /* Clear deassertion from inner state */
 975         sb_attn_sw->known_attn &= ~deasserted_bits;
 976
 977         return rc;
 978 }
 979
 980 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
 981 {
 982         struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
 983         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
 984         u16 index = 0, asserted_bits, deasserted_bits;
 985         u32 attn_bits = 0, attn_acks = 0;
 986         enum _ecore_status_t rc = ECORE_SUCCESS;
 987
 988         /* Read current attention bits/acks - safeguard against attentions
 989          * by guaranting work on a synchronized timeframe
 990          */
 991         do {
 992                 index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
 993                 attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
 994                 attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
 995         } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
 996         p_sb_attn->sb_index = index;
 997
 998         /* Attention / Deassertion are meaningful (and in correct state)
 999          * only when they differ and consistent with known state - deassertion
1000          * when previous attention & current ack, and assertion when current
1001          * attention with no previous attention
1002          */
1003         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1004             ~p_sb_attn_sw->known_attn;
1005         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1006             p_sb_attn_sw->known_attn;
1007
1008         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1009                 DP_INFO(p_hwfn,
1010                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1011                         index, attn_bits, attn_acks, asserted_bits,
1012                         deasserted_bits, p_sb_attn_sw->known_attn);
1013         else if (asserted_bits == 0x100)
1014                 DP_INFO(p_hwfn, "MFW indication via attention\n");
1015         else
1016                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1017                            "MFW indication [deassertion]\n");
1018
1019         if (asserted_bits) {
1020                 rc = ecore_int_assertion(p_hwfn, asserted_bits);
1021                 if (rc)
1022                         return rc;
1023         }
1024
1025         if (deasserted_bits)
1026                 rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1027
1028         return rc;
1029 }
1030
1031 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1032                               void OSAL_IOMEM *igu_addr, u32 ack_cons)
1033 {
1034         struct igu_prod_cons_update igu_ack = { 0 };
1035
1036         igu_ack.sb_id_and_flags =
1037             ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1038              (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1039              (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1040              (IGU_SEG_ACCESS_ATTN <<
1041               IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1042
1043         DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1044
1045         /* Both segments (interrupts & acks) are written to same place address;
1046          * Need to guarantee all commands will be received (in-order) by HW.
1047          */
1048         OSAL_MMIOWB(p_hwfn->p_dev);
1049         OSAL_BARRIER(p_hwfn->p_dev);
1050 }
1051
1052 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1053 {
1054         struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1055         struct ecore_pi_info *pi_info = OSAL_NULL;
1056         struct ecore_sb_attn_info *sb_attn;
1057         struct ecore_sb_info *sb_info;
1058         int arr_size;
1059         u16 rc = 0;
1060
1061         if (!p_hwfn)
1062                 return;
1063
1064         if (!p_hwfn->p_sp_sb) {
1065                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1066                 return;
1067         }
1068
1069         sb_info = &p_hwfn->p_sp_sb->sb_info;
1070         arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1071         if (!sb_info) {
1072                 DP_ERR(p_hwfn->p_dev,
1073                        "Status block is NULL - cannot ack interrupts\n");
1074                 return;
1075         }
1076
1077         if (!p_hwfn->p_sb_attn) {
1078                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1079                 return;
1080         }
1081         sb_attn = p_hwfn->p_sb_attn;
1082
1083         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1084                    p_hwfn, p_hwfn->my_id);
1085
1086         /* Disable ack for def status block. Required both for msix +
1087          * inta in non-mask mode, in inta does no harm.
1088          */
1089         ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1090
1091         /* Gather Interrupts/Attentions information */
1092         if (!sb_info->sb_virt) {
1093                 DP_ERR(p_hwfn->p_dev,
1094                        "Interrupt Status block is NULL -"
1095                        " cannot check for new interrupts!\n");
1096         } else {
1097                 u32 tmp_index = sb_info->sb_ack;
1098                 rc = ecore_sb_update_sb_idx(sb_info);
1099                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1100                            "Interrupt indices: 0x%08x --> 0x%08x\n",
1101                            tmp_index, sb_info->sb_ack);
1102         }
1103
1104         if (!sb_attn || !sb_attn->sb_attn) {
1105                 DP_ERR(p_hwfn->p_dev,
1106                        "Attentions Status block is NULL -"
1107                        " cannot check for new attentions!\n");
1108         } else {
1109                 u16 tmp_index = sb_attn->index;
1110
1111                 rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1112                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1113                            "Attention indices: 0x%08x --> 0x%08x\n",
1114                            tmp_index, sb_attn->index);
1115         }
1116
1117         /* Check if we expect interrupts at this time. if not just ack them */
1118         if (!(rc & ECORE_SB_EVENT_MASK)) {
1119                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1120                 return;
1121         }
1122
1123 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1124
1125         if (!p_hwfn->p_dpc_ptt) {
1126                 DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1127                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1128                 return;
1129         }
1130
1131         if (rc & ECORE_SB_ATT_IDX)
1132                 ecore_int_attentions(p_hwfn);
1133
1134         if (rc & ECORE_SB_IDX) {
1135                 int pi;
1136
1137                 /* Since we only looked at the SB index, it's possible more
1138                  * than a single protocol-index on the SB incremented.
1139                  * Iterate over all configured protocol indices and check
1140                  * whether something happened for each.
1141                  */
1142                 for (pi = 0; pi < arr_size; pi++) {
1143                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1144                         if (pi_info->comp_cb != OSAL_NULL)
1145                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1146                 }
1147         }
1148
1149         if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1150                 /* This should be done before the interrupts are enabled,
1151                  * since otherwise a new attention will be generated.
1152                  */
1153                 ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1154         }
1155
1156         ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1157 }
1158
1159 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1160 {
1161         struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1162
1163         if (!p_sb)
1164                 return;
1165
1166         if (p_sb->sb_attn) {
1167                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1168                                        p_sb->sb_phys,
1169                                        SB_ATTN_ALIGNED_SIZE(p_hwfn));
1170         }
1171         OSAL_FREE(p_hwfn->p_dev, p_sb);
1172 }
1173
1174 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1175                                     struct ecore_ptt *p_ptt)
1176 {
1177         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1178
1179         OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1180
1181         sb_info->index = 0;
1182         sb_info->known_attn = 0;
1183
1184         /* Configure Attention Status Block in IGU */
1185         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1186                  DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1187         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1188                  DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1189 }
1190
1191 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1192                                    struct ecore_ptt *p_ptt,
1193                                    void *sb_virt_addr, dma_addr_t sb_phy_addr)
1194 {
1195         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1196         int i, j, k;
1197
1198         sb_info->sb_attn = sb_virt_addr;
1199         sb_info->sb_phys = sb_phy_addr;
1200
1201         /* Set the pointer to the AEU descriptors */
1202         sb_info->p_aeu_desc = aeu_descs;
1203
1204         /* Calculate Parity Masks */
1205         OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1206         for (i = 0; i < NUM_ATTN_REGS; i++) {
1207                 /* j is array index, k is bit index */
1208                 for (j = 0, k = 0; k < 32; j++) {
1209                         unsigned int flags = aeu_descs[i].bits[j].flags;
1210
1211                         if (flags & ATTENTION_PARITY)
1212                                 sb_info->parity_mask[i] |= 1 << k;
1213
1214                         k += ATTENTION_LENGTH(flags);
1215                 }
1216                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1217                            "Attn Mask [Reg %d]: 0x%08x\n",
1218                            i, sb_info->parity_mask[i]);
1219         }
1220
1221         /* Set the address of cleanup for the mcp attention */
1222         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1223             MISC_REG_AEU_GENERAL_ATTN_0;
1224
1225         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1226 }
1227
1228 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1229                                                     struct ecore_ptt *p_ptt)
1230 {
1231         struct ecore_dev *p_dev = p_hwfn->p_dev;
1232         struct ecore_sb_attn_info *p_sb;
1233         dma_addr_t p_phys = 0;
1234         void *p_virt;
1235
1236         /* SB struct */
1237         p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
1238         if (!p_sb) {
1239                 DP_NOTICE(p_dev, true,
1240                           "Failed to allocate `struct ecore_sb_attn_info'");
1241                 return ECORE_NOMEM;
1242         }
1243
1244         /* SB ring  */
1245         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1246                                          SB_ATTN_ALIGNED_SIZE(p_hwfn));
1247         if (!p_virt) {
1248                 DP_NOTICE(p_dev, true,
1249                           "Failed to allocate status block (attentions)");
1250                 OSAL_FREE(p_dev, p_sb);
1251                 return ECORE_NOMEM;
1252         }
1253
1254         /* Attention setup */
1255         p_hwfn->p_sb_attn = p_sb;
1256         ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1257
1258         return ECORE_SUCCESS;
1259 }
1260
1261 /* coalescing timeout = timeset << (timer_res + 1) */
1262 #define ECORE_CAU_DEF_RX_USECS 24
1263 #define ECORE_CAU_DEF_TX_USECS 48
1264
1265 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1266                              struct cau_sb_entry *p_sb_entry,
1267                              u8 pf_id, u16 vf_number, u8 vf_valid)
1268 {
1269         struct ecore_dev *p_dev = p_hwfn->p_dev;
1270         u32 cau_state;
1271         u8 timer_res;
1272
1273         OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1274
1275         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1276         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1277         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1278         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1279         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1280
1281         cau_state = CAU_HC_DISABLE_STATE;
1282
1283         if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1284                 cau_state = CAU_HC_ENABLE_STATE;
1285                 if (!p_dev->rx_coalesce_usecs)
1286                         p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1287                 if (!p_dev->tx_coalesce_usecs)
1288                         p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1289         }
1290
1291         /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1292         if (p_dev->rx_coalesce_usecs <= 0x7F)
1293                 timer_res = 0;
1294         else if (p_dev->rx_coalesce_usecs <= 0xFF)
1295                 timer_res = 1;
1296         else
1297                 timer_res = 2;
1298         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1299
1300         if (p_dev->tx_coalesce_usecs <= 0x7F)
1301                 timer_res = 0;
1302         else if (p_dev->tx_coalesce_usecs <= 0xFF)
1303                 timer_res = 1;
1304         else
1305                 timer_res = 2;
1306         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1307
1308         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1309         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1310 }
1311
1312 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1313                            struct ecore_ptt *p_ptt,
1314                            dma_addr_t sb_phys, u16 igu_sb_id,
1315                            u16 vf_number, u8 vf_valid)
1316 {
1317         struct cau_sb_entry sb_entry;
1318
1319         ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1320                                 vf_number, vf_valid);
1321
1322         if (p_hwfn->hw_init_done) {
1323                 /* Wide-bus, initialize via DMAE */
1324                 u64 phys_addr = (u64)sb_phys;
1325
1326                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1327                                     (u64)(osal_uintptr_t)&phys_addr,
1328                                     CAU_REG_SB_ADDR_MEMORY +
1329                                     igu_sb_id * sizeof(u64), 2, 0);
1330                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1331                                     (u64)(osal_uintptr_t)&sb_entry,
1332                                     CAU_REG_SB_VAR_MEMORY +
1333                                     igu_sb_id * sizeof(u64), 2, 0);
1334         } else {
1335                 /* Initialize Status Block Address */
1336                 STORE_RT_REG_AGG(p_hwfn,
1337                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1338                                  igu_sb_id * 2, sb_phys);
1339
1340                 STORE_RT_REG_AGG(p_hwfn,
1341                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1342                                  igu_sb_id * 2, sb_entry);
1343         }
1344
1345         /* Configure pi coalescing if set */
1346         if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1347                 /* eth will open queues for all tcs, so configure all of them
1348                  * properly, rather than just the active ones
1349                  */
1350                 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1351
1352                 u8 timeset, timer_res;
1353                 u8 i;
1354
1355                 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1356                 if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
1357                         timer_res = 0;
1358                 else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
1359                         timer_res = 1;
1360                 else
1361                         timer_res = 2;
1362                 timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
1363                 ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1364                                       ECORE_COAL_RX_STATE_MACHINE, timeset);
1365
1366                 if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
1367                         timer_res = 0;
1368                 else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
1369                         timer_res = 1;
1370                 else
1371                         timer_res = 2;
1372                 timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
1373                 for (i = 0; i < num_tc; i++) {
1374                         ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1375                                               igu_sb_id, TX_PI(i),
1376                                               ECORE_COAL_TX_STATE_MACHINE,
1377                                               timeset);
1378                 }
1379         }
1380 }
1381
1382 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1383                            struct ecore_ptt *p_ptt,
1384                            u16 igu_sb_id, u32 pi_index,
1385                            enum ecore_coalescing_fsm coalescing_fsm, u8 timeset)
1386 {
1387         struct cau_pi_entry pi_entry;
1388         u32 sb_offset, pi_offset;
1389
1390         if (IS_VF(p_hwfn->p_dev))
1391                 return;         /* @@@TBD MichalK- VF CAU... */
1392
1393         sb_offset = igu_sb_id * PIS_PER_SB;
1394         OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1395
1396         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1397         if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1398                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1399         else
1400                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1401
1402         pi_offset = sb_offset + pi_index;
1403         if (p_hwfn->hw_init_done) {
1404                 ecore_wr(p_hwfn, p_ptt,
1405                          CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1406                          *((u32 *)&(pi_entry)));
1407         } else {
1408                 STORE_RT_REG(p_hwfn,
1409                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1410                              *((u32 *)&(pi_entry)));
1411         }
1412 }
1413
1414 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1415                         struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info)
1416 {
1417         /* zero status block and ack counter */
1418         sb_info->sb_ack = 0;
1419         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1420
1421         if (IS_PF(p_hwfn->p_dev))
1422                 ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1423                                       sb_info->igu_sb_id, 0, 0);
1424 }
1425
1426 /**
1427  * @brief ecore_get_igu_sb_id - given a sw sb_id return the
1428  *        igu_sb_id
1429  *
1430  * @param p_hwfn
1431  * @param sb_id
1432  *
1433  * @return u16
1434  */
1435 static u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1436 {
1437         u16 igu_sb_id;
1438
1439         /* Assuming continuous set of IGU SBs dedicated for given PF */
1440         if (sb_id == ECORE_SP_SB_ID)
1441                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1442         else if (IS_PF(p_hwfn->p_dev))
1443                 igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb;
1444         else
1445                 igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1446
1447         if (sb_id == ECORE_SP_SB_ID)
1448                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1449                            "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1450         else
1451                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1452                            "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1453
1454         return igu_sb_id;
1455 }
1456
1457 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1458                                        struct ecore_ptt *p_ptt,
1459                                        struct ecore_sb_info *sb_info,
1460                                        void *sb_virt_addr,
1461                                        dma_addr_t sb_phy_addr, u16 sb_id)
1462 {
1463         sb_info->sb_virt = sb_virt_addr;
1464         sb_info->sb_phys = sb_phy_addr;
1465
1466         sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1467
1468         if (sb_id != ECORE_SP_SB_ID) {
1469                 p_hwfn->sbs_info[sb_id] = sb_info;
1470                 p_hwfn->num_sbs++;
1471         }
1472 #ifdef ECORE_CONFIG_DIRECT_HWFN
1473         sb_info->p_hwfn = p_hwfn;
1474 #endif
1475         sb_info->p_dev = p_hwfn->p_dev;
1476
1477         /* The igu address will hold the absolute address that needs to be
1478          * written to for a specific status block
1479          */
1480         if (IS_PF(p_hwfn->p_dev)) {
1481                 sb_info->igu_addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
1482                     GTT_BAR0_MAP_REG_IGU_CMD + (sb_info->igu_sb_id << 3);
1483
1484         } else {
1485                 sb_info->igu_addr =
1486                     (u8 OSAL_IOMEM *)p_hwfn->regview +
1487                     PXP_VF_BAR0_START_IGU +
1488                     ((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
1489         }
1490
1491         sb_info->flags |= ECORE_SB_INFO_INIT;
1492
1493         ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1494
1495         return ECORE_SUCCESS;
1496 }
1497
1498 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1499                                           struct ecore_sb_info *sb_info,
1500                                           u16 sb_id)
1501 {
1502         if (sb_id == ECORE_SP_SB_ID) {
1503                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1504                 return ECORE_INVAL;
1505         }
1506
1507         /* zero status block and ack counter */
1508         sb_info->sb_ack = 0;
1509         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1510
1511         if (p_hwfn->sbs_info[sb_id] != OSAL_NULL) {
1512                 p_hwfn->sbs_info[sb_id] = OSAL_NULL;
1513                 p_hwfn->num_sbs--;
1514         }
1515
1516         return ECORE_SUCCESS;
1517 }
1518
1519 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1520 {
1521         struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1522
1523         if (!p_sb)
1524                 return;
1525
1526         if (p_sb->sb_info.sb_virt) {
1527                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1528                                        p_sb->sb_info.sb_virt,
1529                                        p_sb->sb_info.sb_phys,
1530                                        SB_ALIGNED_SIZE(p_hwfn));
1531         }
1532
1533         OSAL_FREE(p_hwfn->p_dev, p_sb);
1534 }
1535
1536 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1537                                                   struct ecore_ptt *p_ptt)
1538 {
1539         struct ecore_sb_sp_info *p_sb;
1540         dma_addr_t p_phys = 0;
1541         void *p_virt;
1542
1543         /* SB struct */
1544         p_sb =
1545             OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
1546                        sizeof(*p_sb));
1547         if (!p_sb) {
1548                 DP_NOTICE(p_hwfn, true,
1549                           "Failed to allocate `struct ecore_sb_info'\n");
1550                 return ECORE_NOMEM;
1551         }
1552
1553         /* SB ring  */
1554         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1555                                          &p_phys, SB_ALIGNED_SIZE(p_hwfn));
1556         if (!p_virt) {
1557                 DP_NOTICE(p_hwfn, true, "Failed to allocate status block\n");
1558                 OSAL_FREE(p_hwfn->p_dev, p_sb);
1559                 return ECORE_NOMEM;
1560         }
1561
1562         /* Status Block setup */
1563         p_hwfn->p_sp_sb = p_sb;
1564         ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1565                           p_virt, p_phys, ECORE_SP_SB_ID);
1566
1567         OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1568
1569         return ECORE_SUCCESS;
1570 }
1571
1572 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1573                                            ecore_int_comp_cb_t comp_cb,
1574                                            void *cookie,
1575                                            u8 *sb_idx, __le16 **p_fw_cons)
1576 {
1577         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1578         enum _ecore_status_t rc = ECORE_NOMEM;
1579         u8 pi;
1580
1581         /* Look for a free index */
1582         for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1583                 if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1584                         continue;
1585
1586                 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1587                 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1588                 *sb_idx = pi;
1589                 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1590                 rc = ECORE_SUCCESS;
1591                 break;
1592         }
1593
1594         return rc;
1595 }
1596
1597 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi)
1598 {
1599         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1600
1601         if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1602                 return ECORE_NOMEM;
1603
1604         p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1605         p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1606         return ECORE_SUCCESS;
1607 }
1608
1609 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1610 {
1611         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1612 }
1613
1614 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1615                               struct ecore_ptt *p_ptt,
1616                               enum ecore_int_mode int_mode)
1617 {
1618         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1619
1620 #ifndef ASIC_ONLY
1621         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1622                 DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1623                 igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
1624         }
1625 #endif
1626
1627         p_hwfn->p_dev->int_mode = int_mode;
1628         switch (p_hwfn->p_dev->int_mode) {
1629         case ECORE_INT_MODE_INTA:
1630                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1631                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1632                 break;
1633
1634         case ECORE_INT_MODE_MSI:
1635                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1636                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1637                 break;
1638
1639         case ECORE_INT_MODE_MSIX:
1640                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1641                 break;
1642         case ECORE_INT_MODE_POLL:
1643                 break;
1644         }
1645
1646         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1647 }
1648
1649 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1650                                       struct ecore_ptt *p_ptt)
1651 {
1652 #ifndef ASIC_ONLY
1653         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1654                 DP_INFO(p_hwfn,
1655                         "FPGA - Don't enable Attentions in IGU and MISC\n");
1656                 return;
1657         }
1658 #endif
1659
1660         /* Configure AEU signal change to produce attentions */
1661         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1662         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1663         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1664         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1665
1666         /* Flush the writes to IGU */
1667         OSAL_MMIOWB(p_hwfn->p_dev);
1668
1669         /* Unmask AEU signals toward IGU */
1670         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1671 }
1672
1673 enum _ecore_status_t
1674 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1675                           enum ecore_int_mode int_mode)
1676 {
1677         enum _ecore_status_t rc = ECORE_SUCCESS;
1678         u32 tmp;
1679
1680         /* @@@tmp - Starting with MFW 8.2.1.0 we've started hitting AVS stop
1681          * attentions. Since we're waiting for BRCM answer regarding this
1682          * attention, in the meanwhile we simply mask it.
1683          */
1684         tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
1685         tmp &= ~0x800;
1686         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);
1687
1688         ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1689
1690         if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1691                 rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1692                 if (rc != ECORE_SUCCESS) {
1693                         DP_NOTICE(p_hwfn, true,
1694                                   "Slowpath IRQ request failed\n");
1695                         return ECORE_NORESOURCES;
1696                 }
1697                 p_hwfn->b_int_requested = true;
1698         }
1699
1700         /* Enable interrupt Generation */
1701         ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1702
1703         p_hwfn->b_int_enabled = 1;
1704
1705         return rc;
1706 }
1707
1708 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
1709                                struct ecore_ptt *p_ptt)
1710 {
1711         p_hwfn->b_int_enabled = 0;
1712
1713         if (IS_VF(p_hwfn->p_dev))
1714                 return;
1715
1716         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1717 }
1718
1719 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
1720 static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
1721                               struct ecore_ptt *p_ptt,
1722                               u32 sb_id, bool cleanup_set, u16 opaque_fid)
1723 {
1724         u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1725         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id;
1726         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1727         u8 type = 0;            /* FIXME MichalS type??? */
1728
1729         OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
1730                            IGU_REG_CLEANUP_STATUS_0) != 0x200);
1731
1732         /* USE Control Command Register to perform cleanup. There is an
1733          * option to do this using IGU bar, but then it can't be used for VFs.
1734          */
1735
1736         /* Set the data field */
1737         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1738         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
1739         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1740
1741         /* Set the control register */
1742         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1743         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1744         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1745
1746         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1747
1748         OSAL_BARRIER(p_hwfn->p_dev);
1749
1750         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1751
1752         /* Flush the write to IGU */
1753         OSAL_MMIOWB(p_hwfn->p_dev);
1754
1755         /* calculate where to read the status bit from */
1756         sb_bit = 1 << (sb_id % 32);
1757         sb_bit_addr = sb_id / 32 * sizeof(u32);
1758
1759         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
1760
1761         /* Now wait for the command to complete */
1762         while (--sleep_cnt) {
1763                 val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
1764                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
1765                         break;
1766                 OSAL_MSLEEP(5);
1767         }
1768
1769         if (!sleep_cnt)
1770                 DP_NOTICE(p_hwfn, true,
1771                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
1772                           val, sb_id);
1773 }
1774
1775 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
1776                                        struct ecore_ptt *p_ptt,
1777                                        u32 sb_id, u16 opaque, bool b_set)
1778 {
1779         int pi, i;
1780
1781         /* Set */
1782         if (b_set)
1783                 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque);
1784
1785         /* Clear */
1786         ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
1787
1788         /* Wait for the IGU SB to cleanup */
1789         for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
1790                 u32 val;
1791
1792                 val = ecore_rd(p_hwfn, p_ptt,
1793                                IGU_REG_WRITE_DONE_PENDING +
1794                                ((sb_id / 32) * 4));
1795                 if (val & (1 << (sb_id % 32)))
1796                         OSAL_UDELAY(10);
1797                 else
1798                         break;
1799         }
1800         if (i == IGU_CLEANUP_SLEEP_LENGTH)
1801                 DP_NOTICE(p_hwfn, true,
1802                           "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
1803                           sb_id);
1804
1805         /* Clear the CAU for the SB */
1806         for (pi = 0; pi < 12; pi++)
1807                 ecore_wr(p_hwfn, p_ptt,
1808                          CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0);
1809 }
1810
1811 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
1812                                 struct ecore_ptt *p_ptt,
1813                                 bool b_set, bool b_slowpath)
1814 {
1815         u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb;
1816         u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt;
1817         u32 sb_id = 0, val = 0;
1818
1819         /* @@@TBD MichalK temporary... should be moved to init-tool... */
1820         val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
1821         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
1822         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
1823         ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
1824         /* end temporary */
1825
1826         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1827                    "IGU cleaning SBs [%d,...,%d]\n",
1828                    igu_base_sb, igu_base_sb + igu_sb_cnt - 1);
1829
1830         for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++)
1831                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
1832                                                   p_hwfn->hw_info.opaque_fid,
1833                                                   b_set);
1834
1835         if (!b_slowpath)
1836                 return;
1837
1838         sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1839         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1840                    "IGU cleaning slowpath SB [%d]\n", sb_id);
1841         ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id,
1842                                           p_hwfn->hw_info.opaque_fid, b_set);
1843 }
1844
1845 static u32 ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
1846                                         struct ecore_ptt *p_ptt, u16 sb_id)
1847 {
1848         u32 val = ecore_rd(p_hwfn, p_ptt,
1849                            IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id);
1850         struct ecore_igu_block *p_block;
1851
1852         p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id];
1853
1854         /* stop scanning when hit first invalid PF entry */
1855         if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
1856             GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
1857                 goto out;
1858
1859         /* Fill the block information */
1860         p_block->status = ECORE_IGU_STATUS_VALID;
1861         p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
1862         p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
1863         p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
1864
1865         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1866                    "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d"
1867                    " is_pf = %d vector_num = 0x%x\n",
1868                    sb_id, val, p_block->function_id, p_block->is_pf,
1869                    p_block->vector_number);
1870
1871 out:
1872         return val;
1873 }
1874
1875 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
1876                                             struct ecore_ptt *p_ptt)
1877 {
1878         struct ecore_igu_info *p_igu_info;
1879         struct ecore_igu_block *p_block;
1880         u32 min_vf = 0, max_vf = 0, val;
1881         u16 sb_id, last_iov_sb_id = 0;
1882         u16 prev_sb_id = 0xFF;
1883
1884         p_hwfn->hw_info.p_igu_info = OSAL_ALLOC(p_hwfn->p_dev,
1885                                                 GFP_KERNEL,
1886                                                 sizeof(*p_igu_info));
1887         if (!p_hwfn->hw_info.p_igu_info)
1888                 return ECORE_NOMEM;
1889
1890         OSAL_MEMSET(p_hwfn->hw_info.p_igu_info, 0, sizeof(*p_igu_info));
1891
1892         p_igu_info = p_hwfn->hw_info.p_igu_info;
1893
1894         /* Initialize base sb / sb cnt for PFs and VFs */
1895         p_igu_info->igu_base_sb = 0xffff;
1896         p_igu_info->igu_sb_cnt = 0;
1897         p_igu_info->igu_dsb_id = 0xffff;
1898         p_igu_info->igu_base_sb_iov = 0xffff;
1899
1900         if (p_hwfn->p_dev->p_iov_info) {
1901                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1902
1903                 min_vf = p_iov->first_vf_in_pf;
1904                 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
1905         }
1906         for (sb_id = 0;
1907              sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1908              sb_id++) {
1909                 p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
1910                 val = ecore_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id);
1911                 if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) &&
1912                     GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID))
1913                         break;
1914
1915                 if (p_block->is_pf) {
1916                         if (p_block->function_id == p_hwfn->rel_pf_id) {
1917                                 p_block->status |= ECORE_IGU_STATUS_PF;
1918
1919                                 if (p_block->vector_number == 0) {
1920                                         if (p_igu_info->igu_dsb_id == 0xffff)
1921                                                 p_igu_info->igu_dsb_id = sb_id;
1922                                 } else {
1923                                         if (p_igu_info->igu_base_sb == 0xffff) {
1924                                                 p_igu_info->igu_base_sb = sb_id;
1925                                         } else if (prev_sb_id != sb_id - 1) {
1926                                                 DP_NOTICE(p_hwfn->p_dev, false,
1927                                                           "consecutive igu"
1928                                                           " vectors for HWFN"
1929                                                           " %x broken",
1930                                                           p_hwfn->rel_pf_id);
1931                                                 break;
1932                                         }
1933                                         prev_sb_id = sb_id;
1934                                         /* we don't count the default */
1935                                         (p_igu_info->igu_sb_cnt)++;
1936                                 }
1937                         }
1938                 } else {
1939                         if ((p_block->function_id >= min_vf) &&
1940                             (p_block->function_id < max_vf)) {
1941                                 /* Available for VFs of this PF */
1942                                 if (p_igu_info->igu_base_sb_iov == 0xffff) {
1943                                         p_igu_info->igu_base_sb_iov = sb_id;
1944                                 } else if (last_iov_sb_id != sb_id - 1) {
1945                                         if (!val)
1946                                                 DP_VERBOSE(p_hwfn->p_dev,
1947                                                            ECORE_MSG_INTR,
1948                                                            "First uninited IGU"
1949                                                            " CAM entry at"
1950                                                            " index 0x%04x\n",
1951                                                            sb_id);
1952                                         else
1953                                                 DP_NOTICE(p_hwfn->p_dev, false,
1954                                                           "Consecutive igu"
1955                                                           " vectors for HWFN"
1956                                                           " %x vfs is broken"
1957                                                           " [jumps from %04x"
1958                                                           " to %04x]\n",
1959                                                           p_hwfn->rel_pf_id,
1960                                                           last_iov_sb_id,
1961                                                           sb_id);
1962                                         break;
1963                                 }
1964                                 p_block->status |= ECORE_IGU_STATUS_FREE;
1965                                 p_hwfn->hw_info.p_igu_info->free_blks++;
1966                                 last_iov_sb_id = sb_id;
1967                         }
1968                 }
1969         }
1970         p_igu_info->igu_sb_cnt_iov = p_igu_info->free_blks;
1971
1972         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1973                    "IGU igu_base_sb=0x%x [IOV 0x%x] igu_sb_cnt=%d [IOV 0x%x] "
1974                    "igu_dsb_id=0x%x\n",
1975                    p_igu_info->igu_base_sb, p_igu_info->igu_base_sb_iov,
1976                    p_igu_info->igu_sb_cnt, p_igu_info->igu_sb_cnt_iov,
1977                    p_igu_info->igu_dsb_id);
1978
1979         if (p_igu_info->igu_base_sb == 0xffff ||
1980             p_igu_info->igu_dsb_id == 0xffff || p_igu_info->igu_sb_cnt == 0) {
1981                 DP_NOTICE(p_hwfn, true,
1982                           "IGU CAM returned invalid values igu_base_sb=0x%x "
1983                           "igu_sb_cnt=%d igu_dsb_id=0x%x\n",
1984                           p_igu_info->igu_base_sb, p_igu_info->igu_sb_cnt,
1985                           p_igu_info->igu_dsb_id);
1986                 return ECORE_INVAL;
1987         }
1988
1989         return ECORE_SUCCESS;
1990 }
1991
1992 /**
1993  * @brief Initialize igu runtime registers
1994  *
1995  * @param p_hwfn
1996  */
1997 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
1998 {
1999         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2000
2001         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2002 }
2003
2004 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2005                           IGU_CMD_INT_ACK_BASE)
2006 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2007                           IGU_CMD_INT_ACK_BASE)
2008 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2009 {
2010         u32 intr_status_hi = 0, intr_status_lo = 0;
2011         u64 intr_status = 0;
2012
2013         intr_status_lo = REG_RD(p_hwfn,
2014                                 GTT_BAR0_MAP_REG_IGU_CMD +
2015                                 LSB_IGU_CMD_ADDR * 8);
2016         intr_status_hi = REG_RD(p_hwfn,
2017                                 GTT_BAR0_MAP_REG_IGU_CMD +
2018                                 MSB_IGU_CMD_ADDR * 8);
2019         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2020
2021         return intr_status;
2022 }
2023
2024 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2025 {
2026         OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2027         p_hwfn->b_sp_dpc_enabled = true;
2028 }
2029
2030 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2031 {
2032         p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2033         if (!p_hwfn->sp_dpc)
2034                 return ECORE_NOMEM;
2035
2036         return ECORE_SUCCESS;
2037 }
2038
2039 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2040 {
2041         OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2042 }
2043
2044 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2045                                      struct ecore_ptt *p_ptt)
2046 {
2047         enum _ecore_status_t rc = ECORE_SUCCESS;
2048
2049         rc = ecore_int_sp_dpc_alloc(p_hwfn);
2050         if (rc != ECORE_SUCCESS) {
2051                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2052                 return rc;
2053         }
2054
2055         rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2056         if (rc != ECORE_SUCCESS) {
2057                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2058                 return rc;
2059         }
2060
2061         rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2062         if (rc != ECORE_SUCCESS)
2063                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2064
2065         return rc;
2066 }
2067
2068 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2069 {
2070         ecore_int_sp_sb_free(p_hwfn);
2071         ecore_int_sb_attn_free(p_hwfn);
2072         ecore_int_sp_dpc_free(p_hwfn);
2073 }
2074
2075 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2076 {
2077         if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2078                 return;
2079
2080         ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2081         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2082         ecore_int_sp_dpc_setup(p_hwfn);
2083 }
2084
2085 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2086                            struct ecore_sb_cnt_info *p_sb_cnt_info)
2087 {
2088         struct ecore_igu_info *info = p_hwfn->hw_info.p_igu_info;
2089
2090         if (!info || !p_sb_cnt_info)
2091                 return;
2092
2093         p_sb_cnt_info->sb_cnt = info->igu_sb_cnt;
2094         p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov;
2095         p_sb_cnt_info->sb_free_blk = info->free_blks;
2096 }
2097
2098 u16 ecore_int_queue_id_from_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
2099 {
2100         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2101
2102         /* Determine origin of SB id */
2103         if ((sb_id >= p_info->igu_base_sb) &&
2104             (sb_id < p_info->igu_base_sb + p_info->igu_sb_cnt)) {
2105                 return sb_id - p_info->igu_base_sb;
2106         } else if ((sb_id >= p_info->igu_base_sb_iov) &&
2107                    (sb_id < p_info->igu_base_sb_iov + p_info->igu_sb_cnt_iov)) {
2108                 return sb_id - p_info->igu_base_sb_iov + p_info->igu_sb_cnt;
2109         } else {
2110                 DP_NOTICE(p_hwfn, true, "SB %d not in range for function\n",
2111                           sb_id);
2112                 return 0;
2113         }
2114 }
2115
2116 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2117 {
2118         int i;
2119
2120         for_each_hwfn(p_dev, i)
2121                 p_dev->hwfns[i].b_int_requested = false;
2122 }
2123
2124 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
2125 {
2126         p_dev->attn_clr_en = clr_enable;
2127 }
2128
2129 enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
2130                                              struct ecore_ptt *p_ptt,
2131                                              u8 timer_res, u16 sb_id, bool tx)
2132 {
2133         enum _ecore_status_t rc;
2134         struct cau_sb_entry sb_entry;
2135
2136         if (!p_hwfn->hw_init_done) {
2137                 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2138                 return ECORE_INVAL;
2139         }
2140
2141         rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2142                                  sb_id * sizeof(u64),
2143                                  (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2144         if (rc != ECORE_SUCCESS) {
2145                 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2146                 return rc;
2147         }
2148
2149         if (tx)
2150                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2151         else
2152                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2153
2154         rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
2155                                  (u64)(osal_uintptr_t)&sb_entry,
2156                                  CAU_REG_SB_VAR_MEMORY +
2157                                  sb_id * sizeof(u64), 2, 0);
2158         if (rc != ECORE_SUCCESS) {
2159                 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2160                 return rc;
2161         }
2162
2163         return rc;
2164 }