drivers/net/qede/base/ecore_int.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include <rte_string_fns.h>
  10
  11 #include "bcm_osal.h"
  12 #include "ecore.h"
  13 #include "ecore_spq.h"
  14 #include "ecore_gtt_reg_addr.h"
  15 #include "ecore_init_ops.h"
  16 #include "ecore_rt_defs.h"
  17 #include "ecore_int.h"
  18 #include "reg_addr.h"
  19 #include "ecore_hw.h"
  20 #include "ecore_sriov.h"
  21 #include "ecore_vf.h"
  22 #include "ecore_hw_defs.h"
  23 #include "ecore_hsi_common.h"
  24 #include "ecore_mcp.h"
  25
  26 struct ecore_pi_info {
  27         ecore_int_comp_cb_t comp_cb;
  28         void *cookie;           /* Will be sent to the compl cb function */
  29 };
  30
  31 struct ecore_sb_sp_info {
  32         struct ecore_sb_info sb_info;
  33         /* per protocol index data */
  34         struct ecore_pi_info pi_info_arr[PIS_PER_SB_E4];
  35 };
  36
  37 enum ecore_attention_type {
  38         ECORE_ATTN_TYPE_ATTN,
  39         ECORE_ATTN_TYPE_PARITY,
  40 };
  41
  42 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  43         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  44
  45 struct aeu_invert_reg_bit {
  46         char bit_name[30];
  47
  48 #define ATTENTION_PARITY                (1 << 0)
  49
  50 #define ATTENTION_LENGTH_MASK           (0x00000ff0)
  51 #define ATTENTION_LENGTH_SHIFT          (4)
  52 #define ATTENTION_LENGTH(flags)         (((flags) & ATTENTION_LENGTH_MASK) >> \
  53                                          ATTENTION_LENGTH_SHIFT)
  54 #define ATTENTION_SINGLE                (1 << ATTENTION_LENGTH_SHIFT)
  55 #define ATTENTION_PAR                   (ATTENTION_SINGLE | ATTENTION_PARITY)
  56 #define ATTENTION_PAR_INT               ((2 << ATTENTION_LENGTH_SHIFT) | \
  57                                          ATTENTION_PARITY)
  58
  59 /* Multiple bits start with this offset */
  60 #define ATTENTION_OFFSET_MASK           (0x000ff000)
  61 #define ATTENTION_OFFSET_SHIFT          (12)
  62
  63 #define ATTENTION_BB_MASK               (0x00700000)
  64 #define ATTENTION_BB_SHIFT              (20)
  65 #define ATTENTION_BB(value)             ((value) << ATTENTION_BB_SHIFT)
  66 #define ATTENTION_BB_DIFFERENT          (1 << 23)
  67
  68 #define ATTENTION_CLEAR_ENABLE          (1 << 28)
  69         unsigned int flags;
  70
  71         /* Callback to call if attention will be triggered */
  72         enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
  73
  74         enum block_id block_index;
  75 };
  76
  77 struct aeu_invert_reg {
  78         struct aeu_invert_reg_bit bits[32];
  79 };
  80
  81 #define MAX_ATTN_GRPS           (8)
  82 #define NUM_ATTN_REGS           (9)
  83
  84 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
  85 {
  86         u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
  87
  88         DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", tmp);
  89         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 0xffffffff);
  90
  91         return ECORE_SUCCESS;
  92 }
  93
  94 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK         (0x3c000)
  95 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT        (14)
  96 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK         (0x03fc0)
  97 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT        (6)
  98 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK      (0x00020)
  99 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT     (5)
 100 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK     (0x0001e)
 101 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT    (1)
 102 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK      (0x1)
 103 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT     (0)
 104 #define ECORE_PSWHST_ATTENTION_VF_DISABLED              (0x1)
 105 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS         (0x1)
 106 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK         (0x1)
 107 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT        (0)
 108 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK     (0x1e)
 109 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT    (1)
 110 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK   (0x20)
 111 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT  (5)
 112 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK      (0x3fc0)
 113 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT     (6)
 114 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK      (0x3c000)
 115 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT     (14)
 116 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK    (0x3fc0000)
 117 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT   (18)
 118 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
 119 {
 120         u32 tmp =
 121             ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 122                      PSWHST_REG_VF_DISABLED_ERROR_VALID);
 123
 124         /* Disabled VF access */
 125         if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
 126                 u32 addr, data;
 127
 128                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 129                                 PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
 130                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 131                                 PSWHST_REG_VF_DISABLED_ERROR_DATA);
 132                 DP_INFO(p_hwfn->p_dev,
 133                         "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x]"
 134                         " Write [0x%02x] Addr [0x%08x]\n",
 135                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK)
 136                              >> ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
 137                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK)
 138                              >> ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
 139                         (u8)((data &
 140                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
 141                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
 142                         (u8)((data &
 143                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
 144                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
 145                         (u8)((data &
 146                               ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
 147                               ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
 148                         addr);
 149         }
 150
 151         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 152                        PSWHST_REG_INCORRECT_ACCESS_VALID);
 153         if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
 154                 u32 addr, data, length;
 155
 156                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 157                                 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
 158                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 159                                 PSWHST_REG_INCORRECT_ACCESS_DATA);
 160                 length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 161                                   PSWHST_REG_INCORRECT_ACCESS_LENGTH);
 162
 163                 DP_INFO(p_hwfn->p_dev,
 164                         "Incorrect access to %08x of length %08x - PF [%02x]"
 165                         " VF [%04x] [valid %02x] client [%02x] write [%02x]"
 166                         " Byte-Enable [%04x] [%08x]\n",
 167                         addr, length,
 168                         (u8)((data &
 169                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
 170                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
 171                         (u8)((data &
 172                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
 173                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
 174                         (u8)((data &
 175                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
 176                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
 177                         (u8)((data &
 178                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
 179                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
 180                         (u8)((data &
 181                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
 182                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
 183                         (u8)((data &
 184                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
 185                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
 186                         data);
 187         }
 188
 189         /* TODO - We know 'some' of these are legal due to virtualization,
 190          * but is it true for all of them?
 191          */
 192         return ECORE_SUCCESS;
 193 }
 194
 195 #define ECORE_GRC_ATTENTION_VALID_BIT           (1 << 0)
 196 #define ECORE_GRC_ATTENTION_ADDRESS_MASK        (0x7fffff << 0)
 197 #define ECORE_GRC_ATTENTION_RDWR_BIT            (1 << 23)
 198 #define ECORE_GRC_ATTENTION_MASTER_MASK         (0xf << 24)
 199 #define ECORE_GRC_ATTENTION_MASTER_SHIFT        (24)
 200 #define ECORE_GRC_ATTENTION_PF_MASK             (0xf)
 201 #define ECORE_GRC_ATTENTION_VF_MASK             (0xff << 4)
 202 #define ECORE_GRC_ATTENTION_VF_SHIFT            (4)
 203 #define ECORE_GRC_ATTENTION_PRIV_MASK           (0x3 << 14)
 204 #define ECORE_GRC_ATTENTION_PRIV_SHIFT          (14)
 205 #define ECORE_GRC_ATTENTION_PRIV_VF             (0)
 206 static const char *grc_timeout_attn_master_to_str(u8 master)
 207 {
 208         switch (master) {
 209         case 1:
 210                 return "PXP";
 211         case 2:
 212                 return "MCP";
 213         case 3:
 214                 return "MSDM";
 215         case 4:
 216                 return "PSDM";
 217         case 5:
 218                 return "YSDM";
 219         case 6:
 220                 return "USDM";
 221         case 7:
 222                 return "TSDM";
 223         case 8:
 224                 return "XSDM";
 225         case 9:
 226                 return "DBU";
 227         case 10:
 228                 return "DMAE";
 229         default:
 230                 return "Unknown";
 231         }
 232 }
 233
 234 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
 235 {
 236         enum _ecore_status_t rc = ECORE_SUCCESS;
 237         u32 tmp, tmp2;
 238
 239         /* We've already cleared the timeout interrupt register, so we learn
 240          * of interrupts via the validity register.
 241          * Any attention which is not for a timeout event is treated as fatal.
 242          */
 243         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 244                        GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
 245         if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT)) {
 246                 rc = ECORE_INVAL;
 247                 goto out;
 248         }
 249
 250         /* Read the GRC timeout information */
 251         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 252                        GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
 253         tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 254                         GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
 255
 256         DP_NOTICE(p_hwfn->p_dev, false,
 257                   "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
 258                   tmp2, tmp,
 259                   (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to"
 260                                                        : "Read from",
 261                   (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
 262                   grc_timeout_attn_master_to_str(
 263                         (tmp & ECORE_GRC_ATTENTION_MASTER_MASK) >>
 264                          ECORE_GRC_ATTENTION_MASTER_SHIFT),
 265                   (tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
 266                   (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
 267                   ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
 268                   ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
 269                   (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
 270                   ECORE_GRC_ATTENTION_VF_SHIFT);
 271
 272         /* Clean the validity bit */
 273         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 274                  GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
 275 out:
 276         return rc;
 277 }
 278
 279 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
 280 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
 281 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
 282 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
 283 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
 284 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
 285 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
 286 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
 287 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME      (1 << 22)
 288 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
 289 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
 290 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
 291 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
 292
 293 enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
 294                                                    struct ecore_ptt *p_ptt)
 295 {
 296         u32 tmp;
 297
 298         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
 299         if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
 300                 u32 addr_lo, addr_hi, details;
 301
 302                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 303                                    PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
 304                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 305                                    PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
 306                 details = ecore_rd(p_hwfn, p_ptt,
 307                                    PGLUE_B_REG_TX_ERR_WR_DETAILS);
 308
 309                 DP_NOTICE(p_hwfn, false,
 310                           "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 311                           addr_hi, addr_lo, details,
 312                           (u8)((details &
 313                                 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 314                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 315                           (u8)((details &
 316                                 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 317                                ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 318                           (u8)((details &
 319                                ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 320                           tmp,
 321                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
 322                                 1 : 0),
 323                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
 324                                 1 : 0),
 325                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
 326                                 1 : 0));
 327         }
 328
 329         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
 330         if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
 331                 u32 addr_lo, addr_hi, details;
 332
 333                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 334                                    PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
 335                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 336                                    PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
 337                 details = ecore_rd(p_hwfn, p_ptt,
 338                                    PGLUE_B_REG_TX_ERR_RD_DETAILS);
 339
 340                 DP_NOTICE(p_hwfn, false,
 341                           "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 342                           addr_hi, addr_lo, details,
 343                           (u8)((details &
 344                                 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 345                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 346                           (u8)((details &
 347                                 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 348                                ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 349                           (u8)((details &
 350                                ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 351                           tmp,
 352                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
 353                                 1 : 0),
 354                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
 355                                 1 : 0),
 356                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
 357                                 1 : 0));
 358         }
 359
 360         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
 361         if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
 362                 DP_NOTICE(p_hwfn, false, "ICPL erorr - %08x\n", tmp);
 363
 364         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
 365         if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
 366                 u32 addr_hi, addr_lo;
 367
 368                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 369                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
 370                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 371                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
 372
 373                 DP_NOTICE(p_hwfn, false,
 374                           "ICPL erorr - %08x [Address %08x:%08x]\n",
 375                           tmp, addr_hi, addr_lo);
 376         }
 377
 378         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
 379         if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
 380                 u32 addr_hi, addr_lo, details;
 381
 382                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 383                                    PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
 384                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 385                                    PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
 386                 details = ecore_rd(p_hwfn, p_ptt,
 387                                    PGLUE_B_REG_VF_ILT_ERR_DETAILS);
 388
 389                 DP_NOTICE(p_hwfn, false,
 390                           "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
 391                           details, tmp, addr_hi, addr_lo);
 392         }
 393
 394         /* Clear the indications */
 395         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
 396
 397         return ECORE_SUCCESS;
 398 }
 399
 400 static enum _ecore_status_t ecore_pglueb_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
 401 {
 402         return ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt);
 403 }
 404
 405 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
 406 {
 407         DP_NOTICE(p_hwfn, false, "FW assertion!\n");
 408
 409         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
 410
 411         return ECORE_INVAL;
 412 }
 413
 414 static enum _ecore_status_t
 415 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
 416 {
 417         DP_INFO(p_hwfn, "General attention 35!\n");
 418
 419         return ECORE_SUCCESS;
 420 }
 421
 422 #define ECORE_DORQ_ATTENTION_REASON_MASK        (0xfffff)
 423 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK        (0xffff)
 424 #define ECORE_DORQ_ATTENTION_OPAQUE_SHIFT       (0x0)
 425 #define ECORE_DORQ_ATTENTION_SIZE_MASK          (0x7f)
 426 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT         (16)
 427
 428 #define ECORE_DB_REC_COUNT                      10
 429 #define ECORE_DB_REC_INTERVAL                   100
 430
 431 /* assumes sticky overflow indication was set for this PF */
 432 static enum _ecore_status_t ecore_db_rec_attn(struct ecore_hwfn *p_hwfn,
 433                                               struct ecore_ptt *p_ptt)
 434 {
 435         u8 count = ECORE_DB_REC_COUNT;
 436         u32 usage = 1;
 437
 438         /* wait for usage to zero or count to run out. This is necessary since
 439          * EDPM doorbell transactions can take multiple 64b cycles, and as such
 440          * can "split" over the pci. Possibly, the doorbell drop can happen with
 441          * half an EDPM in the queue and other half dropped. Another EDPM
 442          * doorbell to the same address (from doorbell recovery mechanism or
 443          * from the doorbelling entity) could have first half dropped and second
 444          * half interperted as continuation of the first. To prevent such
 445          * malformed doorbells from reaching the device, flush the queue before
 446          * releaseing the overflow sticky indication.
 447          */
 448         while (count-- && usage) {
 449                 usage = ecore_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT);
 450                 OSAL_UDELAY(ECORE_DB_REC_INTERVAL);
 451         }
 452
 453         /* should have been depleted by now */
 454         if (usage) {
 455                 DP_NOTICE(p_hwfn->p_dev, false,
 456                           "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n",
 457                           ECORE_DB_REC_INTERVAL * ECORE_DB_REC_COUNT, usage);
 458                 return ECORE_TIMEOUT;
 459         }
 460
 461         /* flush any pedning (e)dpm as they may never arrive */
 462         ecore_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1);
 463
 464         /* release overflow sticky indication (stop silently dropping
 465          * everything)
 466          */
 467         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
 468
 469         /* repeat all last doorbells (doorbell drop recovery) */
 470         ecore_db_recovery_execute(p_hwfn, DB_REC_REAL_DEAL);
 471
 472         return ECORE_SUCCESS;
 473 }
 474
 475 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
 476 {
 477         u32 int_sts, first_drop_reason, details, address, overflow,
 478                 all_drops_reason;
 479         struct ecore_ptt *p_ptt = p_hwfn->p_dpc_ptt;
 480         enum _ecore_status_t rc;
 481
 482         int_sts = ecore_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS);
 483         DP_NOTICE(p_hwfn->p_dev, false, "DORQ attention. int_sts was %x\n",
 484                   int_sts);
 485
 486         /* int_sts may be zero since all PFs were interrupted for doorbell
 487          * overflow but another one already handled it. Can abort here. If
 488          * This PF also requires overflow recovery we will be interrupted again
 489          */
 490         if (!int_sts)
 491                 return ECORE_SUCCESS;
 492
 493         /* check if db_drop or overflow happened */
 494         if (int_sts & (DORQ_REG_INT_STS_DB_DROP |
 495                        DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) {
 496                 /* obtain data about db drop/overflow */
 497                 first_drop_reason = ecore_rd(p_hwfn, p_ptt,
 498                                   DORQ_REG_DB_DROP_REASON) &
 499                                   ECORE_DORQ_ATTENTION_REASON_MASK;
 500                 details = ecore_rd(p_hwfn, p_ptt,
 501                                    DORQ_REG_DB_DROP_DETAILS);
 502                 address = ecore_rd(p_hwfn, p_ptt,
 503                                    DORQ_REG_DB_DROP_DETAILS_ADDRESS);
 504                 overflow = ecore_rd(p_hwfn, p_ptt,
 505                                     DORQ_REG_PF_OVFL_STICKY);
 506                 all_drops_reason = ecore_rd(p_hwfn, p_ptt,
 507                                             DORQ_REG_DB_DROP_DETAILS_REASON);
 508
 509                 /* log info */
 510                 DP_NOTICE(p_hwfn->p_dev, false,
 511                           "Doorbell drop occurred\n"
 512                           "Address\t\t0x%08x\t(second BAR address)\n"
 513                           "FID\t\t0x%04x\t\t(Opaque FID)\n"
 514                           "Size\t\t0x%04x\t\t(in bytes)\n"
 515                           "1st drop reason\t0x%08x\t(details on first drop since last handling)\n"
 516                           "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n"
 517                           "Overflow\t0x%x\t\t(a per PF indication)\n",
 518                           address,
 519                           GET_FIELD(details, ECORE_DORQ_ATTENTION_OPAQUE),
 520                           GET_FIELD(details, ECORE_DORQ_ATTENTION_SIZE) * 4,
 521                           first_drop_reason, all_drops_reason, overflow);
 522
 523                 /* if this PF caused overflow, initiate recovery */
 524                 if (overflow) {
 525                         rc = ecore_db_rec_attn(p_hwfn, p_ptt);
 526                         if (rc != ECORE_SUCCESS)
 527                                 return rc;
 528                 }
 529
 530                 /* clear the doorbell drop details and prepare for next drop */
 531                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0);
 532
 533                 /* mark interrupt as handeld (note: even if drop was due to a
 534                  * different reason than overflow we mark as handled)
 535                  */
 536                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_INT_STS_WR,
 537                          DORQ_REG_INT_STS_DB_DROP |
 538                          DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR);
 539
 540                 /* if there are no indications otherthan drop indications,
 541                  * success
 542                  */
 543                 if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP |
 544                                  DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR |
 545                                  DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0)
 546                         return ECORE_SUCCESS;
 547         }
 548
 549         /* some other indication was present - non recoverable */
 550         DP_INFO(p_hwfn, "DORQ fatal attention\n");
 551
 552         return ECORE_INVAL;
 553 }
 554
 555 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
 556 {
 557 #ifndef ASIC_ONLY
 558         if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
 559                 u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 560                                    TM_REG_INT_STS_1);
 561
 562                 if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
 563                             TM_REG_INT_STS_1_PEND_CONN_SCAN))
 564                         return ECORE_INVAL;
 565
 566                 if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
 567                            TM_REG_INT_STS_1_PEND_CONN_SCAN))
 568                         DP_INFO(p_hwfn,
 569                                 "TM attention on emulation - most likely"
 570                                 " results of clock-ratios\n");
 571                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
 572                 val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
 573                     TM_REG_INT_MASK_1_PEND_TASK_SCAN;
 574                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
 575
 576                 return ECORE_SUCCESS;
 577         }
 578 #endif
 579
 580         return ECORE_INVAL;
 581 }
 582
 583 /* Instead of major changes to the data-structure, we have a some 'special'
 584  * identifiers for sources that changed meaning between adapters.
 585  */
 586 enum aeu_invert_reg_special_type {
 587         AEU_INVERT_REG_SPECIAL_CNIG_0,
 588         AEU_INVERT_REG_SPECIAL_CNIG_1,
 589         AEU_INVERT_REG_SPECIAL_CNIG_2,
 590         AEU_INVERT_REG_SPECIAL_CNIG_3,
 591         AEU_INVERT_REG_SPECIAL_MAX,
 592 };
 593
 594 static struct aeu_invert_reg_bit
 595 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
 596         {"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 597         {"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 598         {"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 599         {"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 600 };
 601
 602 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
 603 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
 604         {
 605          {                      /* After Invert 1 */
 606           {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 607            MAX_BLOCK_ID},
 608           }
 609          },
 610
 611         {
 612          {                      /* After Invert 2 */
 613           {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 614           {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 615           {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglueb_rbc_attn_cb,
 616            BLOCK_PGLUE_B},
 617           {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 618           {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 619           {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 620           {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 621           {"SW timers #%d",
 622            (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT),
 623            OSAL_NULL, MAX_BLOCK_ID},
 624           {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 625            BLOCK_PGLCS},
 626           }
 627          },
 628
 629         {
 630          {                      /* After Invert 3 */
 631           {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 632            MAX_BLOCK_ID},
 633           }
 634          },
 635
 636         {
 637          {                      /* After Invert 4 */
 638           {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 639            ecore_fw_assertion, MAX_BLOCK_ID},
 640           {"General Attention %d",
 641            (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT),
 642            OSAL_NULL, MAX_BLOCK_ID},
 643           {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 644            ecore_general_attention_35, MAX_BLOCK_ID},
 645           {"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 646                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
 647                          OSAL_NULL, BLOCK_NWS},
 648           {"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 649                             ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
 650                             OSAL_NULL, BLOCK_NWS},
 651           {"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 652                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
 653                          OSAL_NULL, BLOCK_NWM},
 654           {"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 655                             ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
 656                             OSAL_NULL, BLOCK_NWM},
 657           {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
 658           {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 659           {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 660           {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 661           {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 662           {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 663           {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 664            MAX_BLOCK_ID},
 665           {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
 666           {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
 667           {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
 668           {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
 669           {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
 670           }
 671          },
 672
 673         {
 674          {                      /* After Invert 5 */
 675           {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
 676           {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
 677           {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
 678           {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
 679           {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
 680           {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
 681           {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
 682           {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
 683           {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
 684           {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
 685           {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
 686           {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
 687           {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
 688           {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
 689           {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
 690           {"TSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSEM},
 691           }
 692          },
 693
 694         {
 695          {                      /* After Invert 6 */
 696           {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
 697           {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
 698           {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
 699           {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
 700           {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
 701           {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
 702           {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
 703           {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
 704           {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
 705           {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
 706           {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
 707           {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
 708           {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
 709           {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
 710           {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
 711           {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
 712           }
 713          },
 714
 715         {
 716          {                      /* After Invert 7 */
 717           {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
 718           {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
 719           {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
 720           {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
 721           {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 722           {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
 723           {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
 724           {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
 725           {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
 726           {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
 727           {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
 728           {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
 729           {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
 730           {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
 731           {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
 732           {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 733           {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
 734           }
 735          },
 736
 737         {
 738          {                      /* After Invert 8 */
 739           {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
 740           {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
 741           {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
 742           {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
 743           {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
 744           {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
 745           {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
 746           {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
 747           {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
 748           {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
 749           {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 750           {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 751           {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 752           {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 753           {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 754           {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 755           {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
 756           {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 757           {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 758           {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 759           {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 760            MAX_BLOCK_ID},
 761           }
 762          },
 763
 764         {
 765          {                      /* After Invert 9 */
 766           {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 767           {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL,
 768            MAX_BLOCK_ID},
 769           {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 770           {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 771           {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 772            MAX_BLOCK_ID},
 773           }
 774          },
 775
 776 };
 777
 778 static struct aeu_invert_reg_bit *
 779 ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn,
 780                         struct aeu_invert_reg_bit *p_bit)
 781 {
 782         if (!ECORE_IS_BB(p_hwfn->p_dev))
 783                 return p_bit;
 784
 785         if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
 786                 return p_bit;
 787
 788         return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
 789                                   ATTENTION_BB_SHIFT];
 790 }
 791
 792 static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn,
 793                                      struct aeu_invert_reg_bit *p_bit)
 794 {
 795         return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags &
 796                   ATTENTION_PARITY);
 797 }
 798
 799 #define ATTN_STATE_BITS         (0xfff)
 800 #define ATTN_BITS_MASKABLE      (0x3ff)
 801 struct ecore_sb_attn_info {
 802         /* Virtual & Physical address of the SB */
 803         struct atten_status_block *sb_attn;
 804         dma_addr_t sb_phys;
 805
 806         /* Last seen running index */
 807         u16 index;
 808
 809         /* A mask of the AEU bits resulting in a parity error */
 810         u32 parity_mask[NUM_ATTN_REGS];
 811
 812         /* A pointer to the attention description structure */
 813         struct aeu_invert_reg *p_aeu_desc;
 814
 815         /* Previously asserted attentions, which are still unasserted */
 816         u16 known_attn;
 817
 818         /* Cleanup address for the link's general hw attention */
 819         u32 mfw_attn_addr;
 820 };
 821
 822 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
 823                                  struct ecore_sb_attn_info *p_sb_desc)
 824 {
 825         u16 rc = 0, index;
 826
 827         OSAL_MMIOWB(p_hwfn->p_dev);
 828
 829         index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
 830         if (p_sb_desc->index != index) {
 831                 p_sb_desc->index = index;
 832                 rc = ECORE_SB_ATT_IDX;
 833         }
 834
 835         OSAL_MMIOWB(p_hwfn->p_dev);
 836
 837         return rc;
 838 }
 839
 840 /**
 841  * @brief ecore_int_assertion - handles asserted attention bits
 842  *
 843  * @param p_hwfn
 844  * @param asserted_bits newly asserted bits
 845  * @return enum _ecore_status_t
 846  */
 847 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
 848                                                 u16 asserted_bits)
 849 {
 850         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 851         u32 igu_mask;
 852
 853         /* Mask the source of the attention in the IGU */
 854         igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 855                             IGU_REG_ATTENTION_ENABLE);
 856         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 857                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 858         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 859         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 860
 861         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 862                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 863                    sb_attn_sw->known_attn,
 864                    sb_attn_sw->known_attn | asserted_bits);
 865         sb_attn_sw->known_attn |= asserted_bits;
 866
 867         /* Handle MCP events */
 868         if (asserted_bits & 0x100) {
 869                 ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 870                 /* Clean the MCP attention */
 871                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 872                          sb_attn_sw->mfw_attn_addr, 0);
 873         }
 874
 875         /* FIXME - this will change once we'll have GOOD gtt definitions */
 876         DIRECT_REG_WR(p_hwfn,
 877                       (u8 OSAL_IOMEM *) p_hwfn->regview +
 878                       GTT_BAR0_MAP_REG_IGU_CMD +
 879                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 880                         IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
 881
 882         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
 883                    asserted_bits);
 884
 885         return ECORE_SUCCESS;
 886 }
 887
 888 static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
 889                                  enum block_id id, enum dbg_attn_type type,
 890                                  bool b_clear)
 891 {
 892         /* @DPDK */
 893         DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n", id, type);
 894 }
 895
 896 /**
 897  * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
 898  * cause of the attention
 899  *
 900  * @param p_hwfn
 901  * @param p_aeu - descriptor of an AEU bit which caused the attention
 902  * @param aeu_en_reg - register offset of the AEU enable reg. which configured
 903  *  this bit to this group.
 904  * @param bit_index - index of this bit in the aeu_en_reg
 905  *
 906  * @return enum _ecore_status_t
 907  */
 908 static enum _ecore_status_t
 909 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
 910                               struct aeu_invert_reg_bit *p_aeu,
 911                               u32 aeu_en_reg,
 912                               const char *p_bit_name,
 913                               u32 bitmask)
 914 {
 915         enum _ecore_status_t rc = ECORE_INVAL;
 916         bool b_fatal = false;
 917
 918         DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
 919                 p_bit_name, bitmask);
 920
 921         /* Call callback before clearing the interrupt status */
 922         if (p_aeu->cb) {
 923                 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
 924                         p_bit_name);
 925                 rc = p_aeu->cb(p_hwfn);
 926         }
 927
 928         if (rc != ECORE_SUCCESS)
 929                 b_fatal = true;
 930
 931         /* Print HW block interrupt registers */
 932         if (p_aeu->block_index != MAX_BLOCK_ID) {
 933                 ecore_int_attn_print(p_hwfn, p_aeu->block_index,
 934                                      ATTN_TYPE_INTERRUPT, !b_fatal);
 935 }
 936
 937         /* @DPDK */
 938         /* Reach assertion if attention is fatal */
 939         if (b_fatal || (strcmp(p_bit_name, "PGLUE B RBC") == 0)) {
 940                 DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
 941                           p_bit_name);
 942
 943                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
 944         }
 945
 946         /* Prevent this Attention from being asserted in the future */
 947         if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
 948             p_hwfn->p_dev->attn_clr_en) {
 949                 u32 val;
 950                 u32 mask = ~bitmask;
 951                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 952                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
 953                 DP_ERR(p_hwfn, "`%s' - Disabled future attentions\n",
 954                         p_bit_name);
 955         }
 956
 957         return rc;
 958 }
 959
 960 /**
 961  * @brief ecore_int_deassertion_parity - handle a single parity AEU source
 962  *
 963  * @param p_hwfn
 964  * @param p_aeu - descriptor of an AEU bit which caused the parity
 965  * @param aeu_en_reg - address of the AEU enable register
 966  * @param bit_index
 967  */
 968 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
 969                                          struct aeu_invert_reg_bit *p_aeu,
 970                                          u32 aeu_en_reg, u8 bit_index)
 971 {
 972         u32 block_id = p_aeu->block_index, mask, val;
 973
 974         DP_NOTICE(p_hwfn->p_dev, false,
 975                   "%s parity attention is set [address 0x%08x, bit %d]\n",
 976                   p_aeu->bit_name, aeu_en_reg, bit_index);
 977
 978         if (block_id != MAX_BLOCK_ID) {
 979                 ecore_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
 980
 981                 /* In A0, there's a single parity bit for several blocks */
 982                 if (block_id == BLOCK_BTB) {
 983                         ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
 984                                              ATTN_TYPE_PARITY, false);
 985                         ecore_int_attn_print(p_hwfn, BLOCK_MCP,
 986                                              ATTN_TYPE_PARITY, false);
 987                 }
 988         }
 989
 990         /* Prevent this parity error from being re-asserted */
 991         mask = ~(0x1 << bit_index);
 992         val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 993         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
 994         DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
 995                 p_aeu->bit_name);
 996 }
 997
 998 /**
 999  * @brief - handles deassertion of previously asserted attentions.
1000  *
1001  * @param p_hwfn
1002  * @param deasserted_bits - newly deasserted bits
1003  * @return enum _ecore_status_t
1004  *
1005  */
1006 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
1007                                                   u16 deasserted_bits)
1008 {
1009         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
1010         u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
1011         u8 i, j, k, bit_idx;
1012         enum _ecore_status_t rc = ECORE_SUCCESS;
1013
1014         /* Read the attention registers in the AEU */
1015         for (i = 0; i < NUM_ATTN_REGS; i++) {
1016                 aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1017                                           MISC_REG_AEU_AFTER_INVERT_1_IGU +
1018                                           i * 0x4);
1019                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1020                            "Deasserted bits [%d]: %08x\n", i, aeu_inv_arr[i]);
1021         }
1022
1023         /* Handle parity attentions first */
1024         for (i = 0; i < NUM_ATTN_REGS; i++) {
1025                 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
1026                 u32 parities;
1027
1028                 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
1029                 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1030                 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
1031
1032                 /* Skip register in which no parity bit is currently set */
1033                 if (!parities)
1034                         continue;
1035
1036                 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1037                         struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
1038
1039                         if (ecore_int_is_parity_flag(p_hwfn, p_bit) &&
1040                             !!(parities & (1 << bit_idx)))
1041                                 ecore_int_deassertion_parity(p_hwfn, p_bit,
1042                                                              aeu_en, bit_idx);
1043
1044                         bit_idx += ATTENTION_LENGTH(p_bit->flags);
1045                 }
1046         }
1047
1048         /* Find non-parity cause for attention and act */
1049         for (k = 0; k < MAX_ATTN_GRPS; k++) {
1050                 struct aeu_invert_reg_bit *p_aeu;
1051
1052                 /* Handle only groups whose attention is currently deasserted */
1053                 if (!(deasserted_bits & (1 << k)))
1054                         continue;
1055
1056                 for (i = 0; i < NUM_ATTN_REGS; i++) {
1057                         u32 bits;
1058
1059                         aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
1060                                  i * sizeof(u32) +
1061                                  k * sizeof(u32) * NUM_ATTN_REGS;
1062                         en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1063                         bits = aeu_inv_arr[i] & en;
1064
1065                         /* Skip if no bit from this group is currently set */
1066                         if (!bits)
1067                                 continue;
1068
1069                         /* Find all set bits from current register which belong
1070                          * to current group, making them responsible for the
1071                          * previous assertion.
1072                          */
1073                         for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1074                                 unsigned long int bitmask;
1075                                 u8 bit, bit_len;
1076
1077                                 /* Need to account bits with changed meaning */
1078                                 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
1079
1080                                 bit = bit_idx;
1081                                 bit_len = ATTENTION_LENGTH(p_aeu->flags);
1082                                 if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) {
1083                                         /* Skip Parity */
1084                                         bit++;
1085                                         bit_len--;
1086                                 }
1087
1088                                 /* Find the bits relating to HW-block, then
1089                                  * shift so they'll become LSB.
1090                                  */
1091                                 bitmask = bits & (((1 << bit_len) - 1) << bit);
1092                                 bitmask >>= bit;
1093
1094                                 if (bitmask) {
1095                                         u32 flags = p_aeu->flags;
1096                                         char bit_name[30];
1097                                         u8 num;
1098
1099                                         num = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
1100                                                                 bit_len);
1101
1102                                         /* Some bits represent more than a
1103                                          * a single interrupt. Correctly print
1104                                          * their name.
1105                                          */
1106                                         if (ATTENTION_LENGTH(flags) > 2 ||
1107                                             ((flags & ATTENTION_PAR_INT) &&
1108                                             ATTENTION_LENGTH(flags) > 1))
1109                                                 OSAL_SNPRINTF(bit_name, 30,
1110                                                               p_aeu->bit_name,
1111                                                               num);
1112                                         else
1113                                                 strlcpy(bit_name,
1114                                                         p_aeu->bit_name,
1115                                                         sizeof(bit_name));
1116
1117                                         /* We now need to pass bitmask in its
1118                                          * correct position.
1119                                          */
1120                                         bitmask <<= bit;
1121
1122                                         /* Handle source of the attention */
1123                                         ecore_int_deassertion_aeu_bit(p_hwfn,
1124                                                                       p_aeu,
1125                                                                       aeu_en,
1126                                                                       bit_name,
1127                                                                       bitmask);
1128                                 }
1129
1130                                 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1131                         }
1132                 }
1133         }
1134
1135         /* Clear IGU indication for the deasserted bits */
1136         /* FIXME - this will change once we'll have GOOD gtt definitions */
1137         DIRECT_REG_WR(p_hwfn,
1138                       (u8 OSAL_IOMEM *) p_hwfn->regview +
1139                       GTT_BAR0_MAP_REG_IGU_CMD +
1140                       ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1141                         IGU_CMD_INT_ACK_BASE) << 3), ~((u32)deasserted_bits));
1142
1143         /* Unmask deasserted attentions in IGU */
1144         aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1145                             IGU_REG_ATTENTION_ENABLE);
1146         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1147         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1148
1149         /* Clear deassertion from inner state */
1150         sb_attn_sw->known_attn &= ~deasserted_bits;
1151
1152         return rc;
1153 }
1154
1155 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
1156 {
1157         struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1158         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1159         u16 index = 0, asserted_bits, deasserted_bits;
1160         u32 attn_bits = 0, attn_acks = 0;
1161         enum _ecore_status_t rc = ECORE_SUCCESS;
1162
1163         /* Read current attention bits/acks - safeguard against attentions
1164          * by guaranting work on a synchronized timeframe
1165          */
1166         do {
1167                 index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
1168                 attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
1169                 attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
1170         } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
1171         p_sb_attn->sb_index = index;
1172
1173         /* Attention / Deassertion are meaningful (and in correct state)
1174          * only when they differ and consistent with known state - deassertion
1175          * when previous attention & current ack, and assertion when current
1176          * attention with no previous attention
1177          */
1178         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1179             ~p_sb_attn_sw->known_attn;
1180         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1181             p_sb_attn_sw->known_attn;
1182
1183         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1184                 DP_INFO(p_hwfn,
1185                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1186                         index, attn_bits, attn_acks, asserted_bits,
1187                         deasserted_bits, p_sb_attn_sw->known_attn);
1188         else if (asserted_bits == 0x100)
1189                 DP_INFO(p_hwfn, "MFW indication via attention\n");
1190         else
1191                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1192                            "MFW indication [deassertion]\n");
1193
1194         if (asserted_bits) {
1195                 rc = ecore_int_assertion(p_hwfn, asserted_bits);
1196                 if (rc)
1197                         return rc;
1198         }
1199
1200         if (deasserted_bits)
1201                 rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1202
1203         return rc;
1204 }
1205
1206 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1207                               void OSAL_IOMEM *igu_addr, u32 ack_cons)
1208 {
1209         struct igu_prod_cons_update igu_ack = { 0 };
1210
1211         igu_ack.sb_id_and_flags =
1212             ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1213              (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1214              (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1215              (IGU_SEG_ACCESS_ATTN <<
1216               IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1217
1218         DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1219
1220         /* Both segments (interrupts & acks) are written to same place address;
1221          * Need to guarantee all commands will be received (in-order) by HW.
1222          */
1223         OSAL_MMIOWB(p_hwfn->p_dev);
1224         OSAL_BARRIER(p_hwfn->p_dev);
1225 }
1226
1227 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1228 {
1229         struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1230         struct ecore_pi_info *pi_info = OSAL_NULL;
1231         struct ecore_sb_attn_info *sb_attn;
1232         struct ecore_sb_info *sb_info;
1233         int arr_size;
1234         u16 rc = 0;
1235
1236         if (!p_hwfn)
1237                 return;
1238
1239         if (!p_hwfn->p_sp_sb) {
1240                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1241                 return;
1242         }
1243
1244         sb_info = &p_hwfn->p_sp_sb->sb_info;
1245         arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1246         if (!sb_info) {
1247                 DP_ERR(p_hwfn->p_dev,
1248                        "Status block is NULL - cannot ack interrupts\n");
1249                 return;
1250         }
1251
1252         if (!p_hwfn->p_sb_attn) {
1253                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1254                 return;
1255         }
1256         sb_attn = p_hwfn->p_sb_attn;
1257
1258         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1259                    p_hwfn, p_hwfn->my_id);
1260
1261         /* Disable ack for def status block. Required both for msix +
1262          * inta in non-mask mode, in inta does no harm.
1263          */
1264         ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1265
1266         /* Gather Interrupts/Attentions information */
1267         if (!sb_info->sb_virt) {
1268                 DP_ERR(p_hwfn->p_dev,
1269                        "Interrupt Status block is NULL -"
1270                        " cannot check for new interrupts!\n");
1271         } else {
1272                 u32 tmp_index = sb_info->sb_ack;
1273                 rc = ecore_sb_update_sb_idx(sb_info);
1274                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1275                            "Interrupt indices: 0x%08x --> 0x%08x\n",
1276                            tmp_index, sb_info->sb_ack);
1277         }
1278
1279         if (!sb_attn || !sb_attn->sb_attn) {
1280                 DP_ERR(p_hwfn->p_dev,
1281                        "Attentions Status block is NULL -"
1282                        " cannot check for new attentions!\n");
1283         } else {
1284                 u16 tmp_index = sb_attn->index;
1285
1286                 rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1287                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1288                            "Attention indices: 0x%08x --> 0x%08x\n",
1289                            tmp_index, sb_attn->index);
1290         }
1291
1292         /* Check if we expect interrupts at this time. if not just ack them */
1293         if (!(rc & ECORE_SB_EVENT_MASK)) {
1294                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1295                 return;
1296         }
1297
1298 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1299
1300         if (!p_hwfn->p_dpc_ptt) {
1301                 DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1302                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1303                 return;
1304         }
1305
1306         if (rc & ECORE_SB_ATT_IDX)
1307                 ecore_int_attentions(p_hwfn);
1308
1309         if (rc & ECORE_SB_IDX) {
1310                 int pi;
1311
1312                 /* Since we only looked at the SB index, it's possible more
1313                  * than a single protocol-index on the SB incremented.
1314                  * Iterate over all configured protocol indices and check
1315                  * whether something happened for each.
1316                  */
1317                 for (pi = 0; pi < arr_size; pi++) {
1318                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1319                         if (pi_info->comp_cb != OSAL_NULL)
1320                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1321                 }
1322         }
1323
1324         if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1325                 /* This should be done before the interrupts are enabled,
1326                  * since otherwise a new attention will be generated.
1327                  */
1328                 ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1329         }
1330
1331         ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1332 }
1333
1334 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1335 {
1336         struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1337
1338         if (!p_sb)
1339                 return;
1340
1341         if (p_sb->sb_attn) {
1342                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1343                                        p_sb->sb_phys,
1344                                        SB_ATTN_ALIGNED_SIZE(p_hwfn));
1345         }
1346         OSAL_FREE(p_hwfn->p_dev, p_sb);
1347 }
1348
1349 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1350                                     struct ecore_ptt *p_ptt)
1351 {
1352         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1353
1354         OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1355
1356         sb_info->index = 0;
1357         sb_info->known_attn = 0;
1358
1359         /* Configure Attention Status Block in IGU */
1360         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1361                  DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1362         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1363                  DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1364 }
1365
1366 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1367                                    struct ecore_ptt *p_ptt,
1368                                    void *sb_virt_addr, dma_addr_t sb_phy_addr)
1369 {
1370         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1371         int i, j, k;
1372
1373         sb_info->sb_attn = sb_virt_addr;
1374         sb_info->sb_phys = sb_phy_addr;
1375
1376         /* Set the pointer to the AEU descriptors */
1377         sb_info->p_aeu_desc = aeu_descs;
1378
1379         /* Calculate Parity Masks */
1380         OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1381         for (i = 0; i < NUM_ATTN_REGS; i++) {
1382                 /* j is array index, k is bit index */
1383                 for (j = 0, k = 0; k < 32; j++) {
1384                         struct aeu_invert_reg_bit *p_aeu;
1385
1386                         p_aeu = &aeu_descs[i].bits[j];
1387                         if (ecore_int_is_parity_flag(p_hwfn, p_aeu))
1388                                 sb_info->parity_mask[i] |= 1 << k;
1389
1390                         k += ATTENTION_LENGTH(p_aeu->flags);
1391                 }
1392                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1393                            "Attn Mask [Reg %d]: 0x%08x\n",
1394                            i, sb_info->parity_mask[i]);
1395         }
1396
1397         /* Set the address of cleanup for the mcp attention */
1398         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1399             MISC_REG_AEU_GENERAL_ATTN_0;
1400
1401         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1402 }
1403
1404 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1405                                                     struct ecore_ptt *p_ptt)
1406 {
1407         struct ecore_dev *p_dev = p_hwfn->p_dev;
1408         struct ecore_sb_attn_info *p_sb;
1409         dma_addr_t p_phys = 0;
1410         void *p_virt;
1411
1412         /* SB struct */
1413         p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
1414         if (!p_sb) {
1415                 DP_NOTICE(p_dev, true,
1416                           "Failed to allocate `struct ecore_sb_attn_info'\n");
1417                 return ECORE_NOMEM;
1418         }
1419
1420         /* SB ring  */
1421         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1422                                          SB_ATTN_ALIGNED_SIZE(p_hwfn));
1423         if (!p_virt) {
1424                 DP_NOTICE(p_dev, true,
1425                           "Failed to allocate status block (attentions)\n");
1426                 OSAL_FREE(p_dev, p_sb);
1427                 return ECORE_NOMEM;
1428         }
1429
1430         /* Attention setup */
1431         p_hwfn->p_sb_attn = p_sb;
1432         ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1433
1434         return ECORE_SUCCESS;
1435 }
1436
1437 /* coalescing timeout = timeset << (timer_res + 1) */
1438 #define ECORE_CAU_DEF_RX_USECS 24
1439 #define ECORE_CAU_DEF_TX_USECS 48
1440
1441 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1442                              struct cau_sb_entry *p_sb_entry,
1443                              u8 pf_id, u16 vf_number, u8 vf_valid)
1444 {
1445         struct ecore_dev *p_dev = p_hwfn->p_dev;
1446         u32 cau_state;
1447         u8 timer_res;
1448
1449         OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1450
1451         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1452         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1453         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1454         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1455         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1456
1457         cau_state = CAU_HC_DISABLE_STATE;
1458
1459         if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1460                 cau_state = CAU_HC_ENABLE_STATE;
1461                 if (!p_dev->rx_coalesce_usecs)
1462                         p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1463                 if (!p_dev->tx_coalesce_usecs)
1464                         p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1465         }
1466
1467         /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1468         if (p_dev->rx_coalesce_usecs <= 0x7F)
1469                 timer_res = 0;
1470         else if (p_dev->rx_coalesce_usecs <= 0xFF)
1471                 timer_res = 1;
1472         else
1473                 timer_res = 2;
1474         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1475
1476         if (p_dev->tx_coalesce_usecs <= 0x7F)
1477                 timer_res = 0;
1478         else if (p_dev->tx_coalesce_usecs <= 0xFF)
1479                 timer_res = 1;
1480         else
1481                 timer_res = 2;
1482         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1483
1484         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1485         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1486 }
1487
1488 static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1489                                    struct ecore_ptt *p_ptt,
1490                                    u16 igu_sb_id, u32 pi_index,
1491                                    enum ecore_coalescing_fsm coalescing_fsm,
1492                                    u8 timeset)
1493 {
1494         struct cau_pi_entry pi_entry;
1495         u32 sb_offset, pi_offset;
1496
1497         if (IS_VF(p_hwfn->p_dev))
1498                 return;/* @@@TBD MichalK- VF CAU... */
1499
1500         sb_offset = igu_sb_id * PIS_PER_SB_E4;
1501         OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1502
1503         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1504         if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1505                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1506         else
1507                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1508
1509         pi_offset = sb_offset + pi_index;
1510         if (p_hwfn->hw_init_done) {
1511                 ecore_wr(p_hwfn, p_ptt,
1512                          CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1513                          *((u32 *)&(pi_entry)));
1514         } else {
1515                 STORE_RT_REG(p_hwfn,
1516                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1517                              *((u32 *)&(pi_entry)));
1518         }
1519 }
1520
1521 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1522                            struct ecore_ptt *p_ptt,
1523                            struct ecore_sb_info *p_sb, u32 pi_index,
1524                            enum ecore_coalescing_fsm coalescing_fsm,
1525                            u8 timeset)
1526 {
1527         _ecore_int_cau_conf_pi(p_hwfn, p_ptt, p_sb->igu_sb_id,
1528                                pi_index, coalescing_fsm, timeset);
1529 }
1530
1531 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1532                            struct ecore_ptt *p_ptt,
1533                            dma_addr_t sb_phys, u16 igu_sb_id,
1534                            u16 vf_number, u8 vf_valid)
1535 {
1536         struct cau_sb_entry sb_entry;
1537
1538         ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1539                                 vf_number, vf_valid);
1540
1541         if (p_hwfn->hw_init_done) {
1542                 /* Wide-bus, initialize via DMAE */
1543                 u64 phys_addr = (u64)sb_phys;
1544
1545                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1546                                     (u64)(osal_uintptr_t)&phys_addr,
1547                                     CAU_REG_SB_ADDR_MEMORY +
1548                                     igu_sb_id * sizeof(u64), 2, 0);
1549                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1550                                     (u64)(osal_uintptr_t)&sb_entry,
1551                                     CAU_REG_SB_VAR_MEMORY +
1552                                     igu_sb_id * sizeof(u64), 2, 0);
1553         } else {
1554                 /* Initialize Status Block Address */
1555                 STORE_RT_REG_AGG(p_hwfn,
1556                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1557                                  igu_sb_id * 2, sb_phys);
1558
1559                 STORE_RT_REG_AGG(p_hwfn,
1560                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1561                                  igu_sb_id * 2, sb_entry);
1562         }
1563
1564         /* Configure pi coalescing if set */
1565         if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1566                 /* eth will open queues for all tcs, so configure all of them
1567                  * properly, rather than just the active ones
1568                  */
1569                 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1570
1571                 u8 timeset, timer_res;
1572                 u8 i;
1573
1574                 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1575                 if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
1576                         timer_res = 0;
1577                 else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
1578                         timer_res = 1;
1579                 else
1580                         timer_res = 2;
1581                 timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
1582                 _ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1583                                        ECORE_COAL_RX_STATE_MACHINE,
1584                                        timeset);
1585
1586                 if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
1587                         timer_res = 0;
1588                 else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
1589                         timer_res = 1;
1590                 else
1591                         timer_res = 2;
1592                 timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
1593                 for (i = 0; i < num_tc; i++) {
1594                         _ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1595                                                igu_sb_id, TX_PI(i),
1596                                                ECORE_COAL_TX_STATE_MACHINE,
1597                                                timeset);
1598                 }
1599         }
1600 }
1601
1602 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1603                         struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info)
1604 {
1605         /* zero status block and ack counter */
1606         sb_info->sb_ack = 0;
1607         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1608
1609         if (IS_PF(p_hwfn->p_dev))
1610                 ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1611                                       sb_info->igu_sb_id, 0, 0);
1612 }
1613
1614 struct ecore_igu_block *
1615 ecore_get_igu_free_sb(struct ecore_hwfn *p_hwfn, bool b_is_pf)
1616 {
1617         struct ecore_igu_block *p_block;
1618         u16 igu_id;
1619
1620         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1621              igu_id++) {
1622                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1623
1624                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1625                     !(p_block->status & ECORE_IGU_STATUS_FREE))
1626                         continue;
1627
1628                 if (!!(p_block->status & ECORE_IGU_STATUS_PF) ==
1629                     b_is_pf)
1630                         return p_block;
1631         }
1632
1633         return OSAL_NULL;
1634 }
1635
1636 static u16 ecore_get_pf_igu_sb_id(struct ecore_hwfn *p_hwfn,
1637                                   u16 vector_id)
1638 {
1639         struct ecore_igu_block *p_block;
1640         u16 igu_id;
1641
1642         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1643              igu_id++) {
1644                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1645
1646                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1647                     !p_block->is_pf ||
1648                     p_block->vector_number != vector_id)
1649                         continue;
1650
1651                 return igu_id;
1652         }
1653
1654         return ECORE_SB_INVALID_IDX;
1655 }
1656
1657 u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1658 {
1659         u16 igu_sb_id;
1660
1661         /* Assuming continuous set of IGU SBs dedicated for given PF */
1662         if (sb_id == ECORE_SP_SB_ID)
1663                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1664         else if (IS_PF(p_hwfn->p_dev))
1665                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1666         else
1667                 igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1668
1669         if (igu_sb_id == ECORE_SB_INVALID_IDX)
1670                 DP_NOTICE(p_hwfn, true,
1671                           "Slowpath SB vector %04x doesn't exist\n",
1672                           sb_id);
1673         else if (sb_id == ECORE_SP_SB_ID)
1674                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1675                            "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1676         else
1677                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1678                            "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1679
1680         return igu_sb_id;
1681 }
1682
1683 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1684                                        struct ecore_ptt *p_ptt,
1685                                        struct ecore_sb_info *sb_info,
1686                                        void *sb_virt_addr,
1687                                        dma_addr_t sb_phy_addr, u16 sb_id)
1688 {
1689         sb_info->sb_virt = sb_virt_addr;
1690         sb_info->sb_phys = sb_phy_addr;
1691
1692         sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1693
1694         if (sb_info->igu_sb_id == ECORE_SB_INVALID_IDX)
1695                 return ECORE_INVAL;
1696
1697         /* Let the igu info reference the client's SB info */
1698         if (sb_id != ECORE_SP_SB_ID) {
1699                 if (IS_PF(p_hwfn->p_dev)) {
1700                         struct ecore_igu_info *p_info;
1701                         struct ecore_igu_block *p_block;
1702
1703                         p_info = p_hwfn->hw_info.p_igu_info;
1704                         p_block = &p_info->entry[sb_info->igu_sb_id];
1705
1706                         p_block->sb_info = sb_info;
1707                         p_block->status &= ~ECORE_IGU_STATUS_FREE;
1708                         p_info->usage.free_cnt--;
1709                 } else {
1710                         ecore_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1711                 }
1712         }
1713 #ifdef ECORE_CONFIG_DIRECT_HWFN
1714         sb_info->p_hwfn = p_hwfn;
1715 #endif
1716         sb_info->p_dev = p_hwfn->p_dev;
1717
1718         /* The igu address will hold the absolute address that needs to be
1719          * written to for a specific status block
1720          */
1721         if (IS_PF(p_hwfn->p_dev)) {
1722                 sb_info->igu_addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
1723                     GTT_BAR0_MAP_REG_IGU_CMD + (sb_info->igu_sb_id << 3);
1724
1725         } else {
1726                 sb_info->igu_addr =
1727                     (u8 OSAL_IOMEM *)p_hwfn->regview +
1728                     PXP_VF_BAR0_START_IGU +
1729                     ((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
1730         }
1731
1732         sb_info->flags |= ECORE_SB_INFO_INIT;
1733
1734         ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1735
1736         return ECORE_SUCCESS;
1737 }
1738
1739 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1740                                           struct ecore_sb_info *sb_info,
1741                                           u16 sb_id)
1742 {
1743         struct ecore_igu_info *p_info;
1744         struct ecore_igu_block *p_block;
1745
1746         if (sb_info == OSAL_NULL)
1747                 return ECORE_SUCCESS;
1748
1749         /* zero status block and ack counter */
1750         sb_info->sb_ack = 0;
1751         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1752
1753         if (IS_VF(p_hwfn->p_dev)) {
1754                 ecore_vf_set_sb_info(p_hwfn, sb_id, OSAL_NULL);
1755                 return ECORE_SUCCESS;
1756         }
1757
1758         p_info = p_hwfn->hw_info.p_igu_info;
1759         p_block = &p_info->entry[sb_info->igu_sb_id];
1760
1761         /* Vector 0 is reserved to Default SB */
1762         if (p_block->vector_number == 0) {
1763                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1764                 return ECORE_INVAL;
1765         }
1766
1767         /* Lose reference to client's SB info, and fix counters */
1768         p_block->sb_info = OSAL_NULL;
1769         p_block->status |= ECORE_IGU_STATUS_FREE;
1770         p_info->usage.free_cnt++;
1771
1772         return ECORE_SUCCESS;
1773 }
1774
1775 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1776 {
1777         struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1778
1779         if (!p_sb)
1780                 return;
1781
1782         if (p_sb->sb_info.sb_virt) {
1783                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1784                                        p_sb->sb_info.sb_virt,
1785                                        p_sb->sb_info.sb_phys,
1786                                        SB_ALIGNED_SIZE(p_hwfn));
1787         }
1788
1789         OSAL_FREE(p_hwfn->p_dev, p_sb);
1790 }
1791
1792 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1793                                                   struct ecore_ptt *p_ptt)
1794 {
1795         struct ecore_sb_sp_info *p_sb;
1796         dma_addr_t p_phys = 0;
1797         void *p_virt;
1798
1799         /* SB struct */
1800         p_sb =
1801             OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
1802                        sizeof(*p_sb));
1803         if (!p_sb) {
1804                 DP_NOTICE(p_hwfn, true,
1805                           "Failed to allocate `struct ecore_sb_info'\n");
1806                 return ECORE_NOMEM;
1807         }
1808
1809         /* SB ring  */
1810         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1811                                          &p_phys, SB_ALIGNED_SIZE(p_hwfn));
1812         if (!p_virt) {
1813                 DP_NOTICE(p_hwfn, true, "Failed to allocate status block\n");
1814                 OSAL_FREE(p_hwfn->p_dev, p_sb);
1815                 return ECORE_NOMEM;
1816         }
1817
1818         /* Status Block setup */
1819         p_hwfn->p_sp_sb = p_sb;
1820         ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1821                           p_virt, p_phys, ECORE_SP_SB_ID);
1822
1823         OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1824
1825         return ECORE_SUCCESS;
1826 }
1827
1828 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1829                                            ecore_int_comp_cb_t comp_cb,
1830                                            void *cookie,
1831                                            u8 *sb_idx, __le16 **p_fw_cons)
1832 {
1833         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1834         enum _ecore_status_t rc = ECORE_NOMEM;
1835         u8 pi;
1836
1837         /* Look for a free index */
1838         for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1839                 if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1840                         continue;
1841
1842                 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1843                 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1844                 *sb_idx = pi;
1845                 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1846                 rc = ECORE_SUCCESS;
1847                 break;
1848         }
1849
1850         return rc;
1851 }
1852
1853 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi)
1854 {
1855         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1856
1857         if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1858                 return ECORE_NOMEM;
1859
1860         p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1861         p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1862         return ECORE_SUCCESS;
1863 }
1864
1865 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1866 {
1867         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1868 }
1869
1870 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1871                               struct ecore_ptt *p_ptt,
1872                               enum ecore_int_mode int_mode)
1873 {
1874         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1875
1876 #ifndef ASIC_ONLY
1877         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1878                 DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1879                 igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
1880         }
1881 #endif
1882
1883         p_hwfn->p_dev->int_mode = int_mode;
1884         switch (p_hwfn->p_dev->int_mode) {
1885         case ECORE_INT_MODE_INTA:
1886                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1887                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1888                 break;
1889
1890         case ECORE_INT_MODE_MSI:
1891                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1892                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1893                 break;
1894
1895         case ECORE_INT_MODE_MSIX:
1896                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1897                 break;
1898         case ECORE_INT_MODE_POLL:
1899                 break;
1900         }
1901
1902         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1903 }
1904
1905 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1906                                       struct ecore_ptt *p_ptt)
1907 {
1908 #ifndef ASIC_ONLY
1909         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1910                 DP_INFO(p_hwfn,
1911                         "FPGA - Don't enable Attentions in IGU and MISC\n");
1912                 return;
1913         }
1914 #endif
1915
1916         /* Configure AEU signal change to produce attentions */
1917         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1918         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1919         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1920         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1921
1922         /* Flush the writes to IGU */
1923         OSAL_MMIOWB(p_hwfn->p_dev);
1924
1925         /* Unmask AEU signals toward IGU */
1926         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1927 }
1928
1929 enum _ecore_status_t
1930 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1931                           enum ecore_int_mode int_mode)
1932 {
1933         enum _ecore_status_t rc = ECORE_SUCCESS;
1934
1935         ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1936
1937         if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1938                 rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1939                 if (rc != ECORE_SUCCESS) {
1940                         DP_NOTICE(p_hwfn, true,
1941                                   "Slowpath IRQ request failed\n");
1942                         return ECORE_NORESOURCES;
1943                 }
1944                 p_hwfn->b_int_requested = true;
1945         }
1946
1947         /* Enable interrupt Generation */
1948         ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1949
1950         p_hwfn->b_int_enabled = 1;
1951
1952         return rc;
1953 }
1954
1955 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
1956                                struct ecore_ptt *p_ptt)
1957 {
1958         p_hwfn->b_int_enabled = 0;
1959
1960         if (IS_VF(p_hwfn->p_dev))
1961                 return;
1962
1963         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1964 }
1965
1966 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
1967 static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
1968                                      struct ecore_ptt *p_ptt,
1969                                      u32 igu_sb_id,
1970                                      bool cleanup_set,
1971                                      u16 opaque_fid)
1972 {
1973         u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1974         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1975         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1976         u8 type = 0;            /* FIXME MichalS type??? */
1977
1978         OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
1979                            IGU_REG_CLEANUP_STATUS_0) != 0x200);
1980
1981         /* USE Control Command Register to perform cleanup. There is an
1982          * option to do this using IGU bar, but then it can't be used for VFs.
1983          */
1984
1985         /* Set the data field */
1986         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1987         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
1988         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1989
1990         /* Set the control register */
1991         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1992         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1993         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1994
1995         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1996
1997         OSAL_BARRIER(p_hwfn->p_dev);
1998
1999         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
2000
2001         /* Flush the write to IGU */
2002         OSAL_MMIOWB(p_hwfn->p_dev);
2003
2004         /* calculate where to read the status bit from */
2005         sb_bit = 1 << (igu_sb_id % 32);
2006         sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
2007
2008         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
2009
2010         /* Now wait for the command to complete */
2011         while (--sleep_cnt) {
2012                 val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
2013                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
2014                         break;
2015                 OSAL_MSLEEP(5);
2016         }
2017
2018         if (!sleep_cnt)
2019                 DP_NOTICE(p_hwfn, true,
2020                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
2021                           val, igu_sb_id);
2022 }
2023
2024 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
2025                                        struct ecore_ptt *p_ptt,
2026                                        u16 igu_sb_id, u16 opaque, bool b_set)
2027 {
2028         struct ecore_igu_block *p_block;
2029         int pi, i;
2030
2031         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2032         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2033                    "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
2034                    igu_sb_id, p_block->function_id, p_block->is_pf,
2035                    p_block->vector_number);
2036
2037         /* Set */
2038         if (b_set)
2039                 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
2040
2041         /* Clear */
2042         ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
2043
2044         /* Wait for the IGU SB to cleanup */
2045         for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
2046                 u32 val;
2047
2048                 val = ecore_rd(p_hwfn, p_ptt,
2049                                IGU_REG_WRITE_DONE_PENDING +
2050                                ((igu_sb_id / 32) * 4));
2051                 if (val & (1 << (igu_sb_id % 32)))
2052                         OSAL_UDELAY(10);
2053                 else
2054                         break;
2055         }
2056         if (i == IGU_CLEANUP_SLEEP_LENGTH)
2057                 DP_NOTICE(p_hwfn, true,
2058                           "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
2059                           igu_sb_id);
2060
2061         /* Clear the CAU for the SB */
2062         for (pi = 0; pi < 12; pi++)
2063                 ecore_wr(p_hwfn, p_ptt,
2064                          CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
2065 }
2066
2067 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
2068                                 struct ecore_ptt *p_ptt,
2069                                 bool b_set, bool b_slowpath)
2070 {
2071         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2072         struct ecore_igu_block *p_block;
2073         u16 igu_sb_id = 0;
2074         u32 val = 0;
2075
2076         /* @@@TBD MichalK temporary... should be moved to init-tool... */
2077         val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
2078         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
2079         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
2080         ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2081         /* end temporary */
2082
2083         for (igu_sb_id = 0;
2084              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2085              igu_sb_id++) {
2086                 p_block = &p_info->entry[igu_sb_id];
2087
2088                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2089                     !p_block->is_pf ||
2090                     (p_block->status & ECORE_IGU_STATUS_DSB))
2091                         continue;
2092
2093                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
2094                                                   p_hwfn->hw_info.opaque_fid,
2095                                                   b_set);
2096         }
2097
2098         if (b_slowpath)
2099                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2100                                                   p_info->igu_dsb_id,
2101                                                   p_hwfn->hw_info.opaque_fid,
2102                                                   b_set);
2103 }
2104
2105 int ecore_int_igu_reset_cam(struct ecore_hwfn *p_hwfn,
2106                             struct ecore_ptt *p_ptt)
2107 {
2108         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2109         struct ecore_igu_block *p_block;
2110         int pf_sbs, vf_sbs;
2111         u16 igu_sb_id;
2112         u32 val, rval;
2113
2114         if (!RESC_NUM(p_hwfn, ECORE_SB)) {
2115                 /* We're using an old MFW - have to prevent any switching
2116                  * of SBs between PF and VFs as later driver wouldn't be
2117                  * able to tell which belongs to which.
2118                  */
2119                 p_info->b_allow_pf_vf_change = false;
2120         } else {
2121                 /* Use the numbers the MFW have provided -
2122                  * don't forget MFW accounts for the default SB as well.
2123                  */
2124                 p_info->b_allow_pf_vf_change = true;
2125
2126                 if (p_info->usage.cnt != RESC_NUM(p_hwfn, ECORE_SB) - 1) {
2127                         DP_INFO(p_hwfn,
2128                                 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2129                                 RESC_NUM(p_hwfn, ECORE_SB) - 1,
2130                                 p_info->usage.cnt);
2131                         p_info->usage.cnt = RESC_NUM(p_hwfn, ECORE_SB) - 1;
2132                 }
2133
2134                 /* TODO - how do we learn about VF SBs from MFW? */
2135                 if (IS_PF_SRIOV(p_hwfn)) {
2136                         u16 vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
2137
2138                         if (vfs != p_info->usage.iov_cnt)
2139                                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2140                                            "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2141                                            p_info->usage.iov_cnt, vfs);
2142
2143                         /* At this point we know how many SBs we have totally
2144                          * in IGU + number of PF SBs. So we can validate that
2145                          * we'd have sufficient for VF.
2146                          */
2147                         if (vfs > p_info->usage.free_cnt +
2148                                   p_info->usage.free_cnt_iov -
2149                                   p_info->usage.cnt) {
2150                                 DP_NOTICE(p_hwfn, true,
2151                                           "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2152                                           p_info->usage.free_cnt +
2153                                           p_info->usage.free_cnt_iov,
2154                                           p_info->usage.cnt, vfs);
2155                                 return ECORE_INVAL;
2156                         }
2157                 }
2158         }
2159
2160         /* Cap the number of VFs SBs by the number of VFs */
2161         if (IS_PF_SRIOV(p_hwfn))
2162                 p_info->usage.iov_cnt = p_hwfn->p_dev->p_iov_info->total_vfs;
2163
2164         /* Mark all SBs as free, now in the right PF/VFs division */
2165         p_info->usage.free_cnt = p_info->usage.cnt;
2166         p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2167         p_info->usage.orig = p_info->usage.cnt;
2168         p_info->usage.iov_orig = p_info->usage.iov_cnt;
2169
2170         /* We now proceed to re-configure the IGU cam to reflect the initial
2171          * configuration. We can start with the Default SB.
2172          */
2173         pf_sbs = p_info->usage.cnt;
2174         vf_sbs = p_info->usage.iov_cnt;
2175
2176         for (igu_sb_id = p_info->igu_dsb_id;
2177              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2178              igu_sb_id++) {
2179                 p_block = &p_info->entry[igu_sb_id];
2180                 val = 0;
2181
2182                 if (!(p_block->status & ECORE_IGU_STATUS_VALID))
2183                         continue;
2184
2185                 if (p_block->status & ECORE_IGU_STATUS_DSB) {
2186                         p_block->function_id = p_hwfn->rel_pf_id;
2187                         p_block->is_pf = 1;
2188                         p_block->vector_number = 0;
2189                         p_block->status = ECORE_IGU_STATUS_VALID |
2190                                           ECORE_IGU_STATUS_PF |
2191                                           ECORE_IGU_STATUS_DSB;
2192                 } else if (pf_sbs) {
2193                         pf_sbs--;
2194                         p_block->function_id = p_hwfn->rel_pf_id;
2195                         p_block->is_pf = 1;
2196                         p_block->vector_number = p_info->usage.cnt - pf_sbs;
2197                         p_block->status = ECORE_IGU_STATUS_VALID |
2198                                           ECORE_IGU_STATUS_PF |
2199                                           ECORE_IGU_STATUS_FREE;
2200                 } else if (vf_sbs) {
2201                         p_block->function_id =
2202                                 p_hwfn->p_dev->p_iov_info->first_vf_in_pf +
2203                                 p_info->usage.iov_cnt - vf_sbs;
2204                         p_block->is_pf = 0;
2205                         p_block->vector_number = 0;
2206                         p_block->status = ECORE_IGU_STATUS_VALID |
2207                                           ECORE_IGU_STATUS_FREE;
2208                         vf_sbs--;
2209                 } else {
2210                         p_block->function_id = 0;
2211                         p_block->is_pf = 0;
2212                         p_block->vector_number = 0;
2213                 }
2214
2215                 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2216                           p_block->function_id);
2217                 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2218                 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2219                           p_block->vector_number);
2220
2221                 /* VF entries would be enabled when VF is initializaed */
2222                 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2223
2224                 rval = ecore_rd(p_hwfn, p_ptt,
2225                                 IGU_REG_MAPPING_MEMORY +
2226                                 sizeof(u32) * igu_sb_id);
2227
2228                 if (rval != val) {
2229                         ecore_wr(p_hwfn, p_ptt,
2230                                  IGU_REG_MAPPING_MEMORY +
2231                                  sizeof(u32) * igu_sb_id,
2232                                  val);
2233
2234                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2235                                    "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2236                                    igu_sb_id, p_block->function_id,
2237                                    p_block->is_pf, p_block->vector_number,
2238                                    rval, val);
2239                 }
2240         }
2241
2242         return 0;
2243 }
2244
2245 int ecore_int_igu_reset_cam_default(struct ecore_hwfn *p_hwfn,
2246                                     struct ecore_ptt *p_ptt)
2247 {
2248         struct ecore_sb_cnt_info *p_cnt = &p_hwfn->hw_info.p_igu_info->usage;
2249
2250         /* Return all the usage indications to default prior to the reset;
2251          * The reset expects the !orig to reflect the initial status of the
2252          * SBs, and would re-calculate the originals based on those.
2253          */
2254         p_cnt->cnt = p_cnt->orig;
2255         p_cnt->free_cnt = p_cnt->orig;
2256         p_cnt->iov_cnt = p_cnt->iov_orig;
2257         p_cnt->free_cnt_iov = p_cnt->iov_orig;
2258         p_cnt->orig = 0;
2259         p_cnt->iov_orig = 0;
2260
2261         /* TODO - we probably need to re-configure the CAU as well... */
2262         return ecore_int_igu_reset_cam(p_hwfn, p_ptt);
2263 }
2264
2265 static void ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
2266                                          struct ecore_ptt *p_ptt,
2267                                          u16 igu_sb_id)
2268 {
2269         u32 val = ecore_rd(p_hwfn, p_ptt,
2270                            IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2271         struct ecore_igu_block *p_block;
2272
2273         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2274
2275         /* Fill the block information */
2276         p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
2277         p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2278         p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
2279
2280         p_block->igu_sb_id = igu_sb_id;
2281 }
2282
2283 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
2284                                             struct ecore_ptt *p_ptt)
2285 {
2286         struct ecore_igu_info *p_igu_info;
2287         struct ecore_igu_block *p_block;
2288         u32 min_vf = 0, max_vf = 0;
2289         u16 igu_sb_id;
2290
2291         p_hwfn->hw_info.p_igu_info = OSAL_ZALLOC(p_hwfn->p_dev,
2292                                                  GFP_KERNEL,
2293                                                  sizeof(*p_igu_info));
2294         if (!p_hwfn->hw_info.p_igu_info)
2295                 return ECORE_NOMEM;
2296         p_igu_info = p_hwfn->hw_info.p_igu_info;
2297
2298         /* Distinguish between existent and onn-existent default SB */
2299         p_igu_info->igu_dsb_id = ECORE_SB_INVALID_IDX;
2300
2301         /* Find the range of VF ids whose SB belong to this PF */
2302         if (p_hwfn->p_dev->p_iov_info) {
2303                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
2304
2305                 min_vf = p_iov->first_vf_in_pf;
2306                 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2307         }
2308
2309         for (igu_sb_id = 0;
2310              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2311              igu_sb_id++) {
2312                 /* Read current entry; Notice it might not belong to this PF */
2313                 ecore_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2314                 p_block = &p_igu_info->entry[igu_sb_id];
2315
2316                 if ((p_block->is_pf) &&
2317                     (p_block->function_id == p_hwfn->rel_pf_id)) {
2318                         p_block->status = ECORE_IGU_STATUS_PF |
2319                                           ECORE_IGU_STATUS_VALID |
2320                                           ECORE_IGU_STATUS_FREE;
2321
2322                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2323                                 p_igu_info->usage.cnt++;
2324                 } else if (!(p_block->is_pf) &&
2325                            (p_block->function_id >= min_vf) &&
2326                            (p_block->function_id < max_vf)) {
2327                         /* Available for VFs of this PF */
2328                         p_block->status = ECORE_IGU_STATUS_VALID |
2329                                           ECORE_IGU_STATUS_FREE;
2330
2331                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2332                                 p_igu_info->usage.iov_cnt++;
2333                 }
2334
2335                 /* Mark the First entry belonging to the PF or its VFs
2336                  * as the default SB [we'll reset IGU prior to first usage].
2337                  */
2338                 if ((p_block->status & ECORE_IGU_STATUS_VALID) &&
2339                     (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX)) {
2340                         p_igu_info->igu_dsb_id = igu_sb_id;
2341                         p_block->status |= ECORE_IGU_STATUS_DSB;
2342                 }
2343
2344                 /* While this isn't suitable for all clients, limit number
2345                  * of prints by having each PF print only its entries with the
2346                  * exception of PF0 which would print everything.
2347                  */
2348                 if ((p_block->status & ECORE_IGU_STATUS_VALID) ||
2349                     (p_hwfn->abs_pf_id == 0))
2350                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2351                                    "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2352                                    igu_sb_id, p_block->function_id,
2353                                    p_block->is_pf, p_block->vector_number);
2354         }
2355
2356         if (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX) {
2357                 DP_NOTICE(p_hwfn, true,
2358                           "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2359                           p_igu_info->igu_dsb_id);
2360                 return ECORE_INVAL;
2361         }
2362
2363         /* All non default SB are considered free at this point */
2364         p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2365         p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2366
2367         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2368                    "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2369                    p_igu_info->igu_dsb_id, p_igu_info->usage.cnt,
2370                    p_igu_info->usage.iov_cnt);
2371
2372         return ECORE_SUCCESS;
2373 }
2374
2375 enum _ecore_status_t
2376 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2377                           u16 sb_id, bool b_to_vf)
2378 {
2379         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2380         struct ecore_igu_block *p_block = OSAL_NULL;
2381         u16 igu_sb_id = 0, vf_num = 0;
2382         u32 val = 0;
2383
2384         if (IS_VF(p_hwfn->p_dev) || !IS_PF_SRIOV(p_hwfn))
2385                 return ECORE_INVAL;
2386
2387         if (sb_id == ECORE_SP_SB_ID)
2388                 return ECORE_INVAL;
2389
2390         if (!p_info->b_allow_pf_vf_change) {
2391                 DP_INFO(p_hwfn, "Can't relocate SBs as MFW is too old.\n");
2392                 return ECORE_INVAL;
2393         }
2394
2395         /* If we're moving a SB from PF to VF, the client had to specify
2396          * which vector it wants to move.
2397          */
2398         if (b_to_vf) {
2399                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
2400                 if (igu_sb_id == ECORE_SB_INVALID_IDX)
2401                         return ECORE_INVAL;
2402         }
2403
2404         /* If we're moving a SB from VF to PF, need to validate there isn't
2405          * already a line configured for that vector.
2406          */
2407         if (!b_to_vf) {
2408                 if (ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1) !=
2409                     ECORE_SB_INVALID_IDX)
2410                         return ECORE_INVAL;
2411         }
2412
2413         /* We need to validate that the SB can actually be relocated.
2414          * This would also handle the previous case where we've explicitly
2415          * stated which IGU SB needs to move.
2416          */
2417         for (; igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2418              igu_sb_id++) {
2419                 p_block = &p_info->entry[igu_sb_id];
2420
2421                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2422                     !(p_block->status & ECORE_IGU_STATUS_FREE) ||
2423                     (!!(p_block->status & ECORE_IGU_STATUS_PF) != b_to_vf)) {
2424                         if (b_to_vf)
2425                                 return ECORE_INVAL;
2426                         else
2427                                 continue;
2428                 }
2429
2430                 break;
2431         }
2432
2433         if (igu_sb_id == ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev)) {
2434                 DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV),
2435                            "Failed to find a free SB to move\n");
2436                 return ECORE_INVAL;
2437         }
2438
2439         /* At this point, p_block points to the SB we want to relocate */
2440         if (b_to_vf) {
2441                 p_block->status &= ~ECORE_IGU_STATUS_PF;
2442
2443                 /* It doesn't matter which VF number we choose, since we're
2444                  * going to disable the line; But let's keep it in range.
2445                  */
2446                 vf_num = (u16)p_hwfn->p_dev->p_iov_info->first_vf_in_pf;
2447
2448                 p_block->function_id = (u8)vf_num;
2449                 p_block->is_pf = 0;
2450                 p_block->vector_number = 0;
2451
2452                 p_info->usage.cnt--;
2453                 p_info->usage.free_cnt--;
2454                 p_info->usage.iov_cnt++;
2455                 p_info->usage.free_cnt_iov++;
2456
2457                 /* TODO - if SBs aren't really the limiting factor,
2458                  * then it might not be accurate [in the since that
2459                  * we might not need decrement the feature].
2460                  */
2461                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]--;
2462                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]++;
2463         } else {
2464                 p_block->status |= ECORE_IGU_STATUS_PF;
2465                 p_block->function_id = p_hwfn->rel_pf_id;
2466                 p_block->is_pf = 1;
2467                 p_block->vector_number = sb_id + 1;
2468
2469                 p_info->usage.cnt++;
2470                 p_info->usage.free_cnt++;
2471                 p_info->usage.iov_cnt--;
2472                 p_info->usage.free_cnt_iov--;
2473
2474                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]++;
2475                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]--;
2476         }
2477
2478         /* Update the IGU and CAU with the new configuration */
2479         SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2480                   p_block->function_id);
2481         SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2482         SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2483         SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2484                   p_block->vector_number);
2485
2486         ecore_wr(p_hwfn, p_ptt,
2487                  IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id,
2488                  val);
2489
2490         ecore_int_cau_conf_sb(p_hwfn, p_ptt, 0,
2491                               igu_sb_id, vf_num,
2492                               p_block->is_pf ? 0 : 1);
2493
2494         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2495                    "Relocation: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2496                    igu_sb_id, p_block->function_id,
2497                    p_block->is_pf, p_block->vector_number);
2498
2499         return ECORE_SUCCESS;
2500 }
2501
2502 /**
2503  * @brief Initialize igu runtime registers
2504  *
2505  * @param p_hwfn
2506  */
2507 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
2508 {
2509         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2510
2511         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2512 }
2513
2514 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2515                           IGU_CMD_INT_ACK_BASE)
2516 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2517                           IGU_CMD_INT_ACK_BASE)
2518 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2519 {
2520         u32 intr_status_hi = 0, intr_status_lo = 0;
2521         u64 intr_status = 0;
2522
2523         intr_status_lo = REG_RD(p_hwfn,
2524                                 GTT_BAR0_MAP_REG_IGU_CMD +
2525                                 LSB_IGU_CMD_ADDR * 8);
2526         intr_status_hi = REG_RD(p_hwfn,
2527                                 GTT_BAR0_MAP_REG_IGU_CMD +
2528                                 MSB_IGU_CMD_ADDR * 8);
2529         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2530
2531         return intr_status;
2532 }
2533
2534 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2535 {
2536         OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2537         p_hwfn->b_sp_dpc_enabled = true;
2538 }
2539
2540 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2541 {
2542         p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2543         if (!p_hwfn->sp_dpc)
2544                 return ECORE_NOMEM;
2545
2546         return ECORE_SUCCESS;
2547 }
2548
2549 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2550 {
2551         OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2552 }
2553
2554 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2555                                      struct ecore_ptt *p_ptt)
2556 {
2557         enum _ecore_status_t rc = ECORE_SUCCESS;
2558
2559         rc = ecore_int_sp_dpc_alloc(p_hwfn);
2560         if (rc != ECORE_SUCCESS) {
2561                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2562                 return rc;
2563         }
2564
2565         rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2566         if (rc != ECORE_SUCCESS) {
2567                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2568                 return rc;
2569         }
2570
2571         rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2572         if (rc != ECORE_SUCCESS)
2573                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2574
2575         return rc;
2576 }
2577
2578 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2579 {
2580         ecore_int_sp_sb_free(p_hwfn);
2581         ecore_int_sb_attn_free(p_hwfn);
2582         ecore_int_sp_dpc_free(p_hwfn);
2583 }
2584
2585 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2586 {
2587         if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2588                 return;
2589
2590         ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2591         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2592         ecore_int_sp_dpc_setup(p_hwfn);
2593 }
2594
2595 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2596                            struct ecore_sb_cnt_info *p_sb_cnt_info)
2597 {
2598         struct ecore_igu_info *p_igu_info = p_hwfn->hw_info.p_igu_info;
2599
2600         if (!p_igu_info || !p_sb_cnt_info)
2601                 return;
2602
2603         OSAL_MEMCPY(p_sb_cnt_info, &p_igu_info->usage,
2604                     sizeof(*p_sb_cnt_info));
2605 }
2606
2607 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2608 {
2609         int i;
2610
2611         for_each_hwfn(p_dev, i)
2612                 p_dev->hwfns[i].b_int_requested = false;
2613 }
2614
2615 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
2616 {
2617         p_dev->attn_clr_en = clr_enable;
2618 }
2619
2620 enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
2621                                              struct ecore_ptt *p_ptt,
2622                                              u8 timer_res, u16 sb_id, bool tx)
2623 {
2624         struct cau_sb_entry sb_entry;
2625         enum _ecore_status_t rc;
2626
2627         if (!p_hwfn->hw_init_done) {
2628                 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2629                 return ECORE_INVAL;
2630         }
2631
2632         rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2633                                  sb_id * sizeof(u64),
2634                                  (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2635         if (rc != ECORE_SUCCESS) {
2636                 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2637                 return rc;
2638         }
2639
2640         if (tx)
2641                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2642         else
2643                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2644
2645         rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
2646                                  (u64)(osal_uintptr_t)&sb_entry,
2647                                  CAU_REG_SB_VAR_MEMORY +
2648                                  sb_id * sizeof(u64), 2, 0);
2649         if (rc != ECORE_SUCCESS) {
2650                 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2651                 return rc;
2652         }
2653
2654         return rc;
2655 }
2656
2657 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
2658                                           struct ecore_ptt *p_ptt,
2659                                           struct ecore_sb_info *p_sb,
2660                                           struct ecore_sb_info_dbg *p_info)
2661 {
2662         u16 sbid = p_sb->igu_sb_id;
2663         int i;
2664
2665         if (IS_VF(p_hwfn->p_dev))
2666                 return ECORE_INVAL;
2667
2668         if (sbid > NUM_OF_SBS(p_hwfn->p_dev))
2669                 return ECORE_INVAL;
2670
2671         p_info->igu_prod = ecore_rd(p_hwfn, p_ptt,
2672                                     IGU_REG_PRODUCER_MEMORY + sbid * 4);
2673         p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
2674                                     IGU_REG_CONSUMER_MEM + sbid * 4);
2675
2676         for (i = 0; i < PIS_PER_SB_E4; i++)
2677                 p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
2678                                               CAU_REG_PI_MEMORY +
2679                                               sbid * 4 * PIS_PER_SB_E4 +
2680                                               i * 4);
2681
2682         return ECORE_SUCCESS;
2683 }
2684
2685 void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn)
2686 {
2687         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2688         struct ecore_ptt *p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
2689                                                              RESERVED_PTT_DPC);
2690         int i;
2691
2692         /* Do not reorder the following cleanup sequence */
2693         /* Ack all attentions */
2694         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ACK_BITS, 0xfff);
2695
2696         /* Clear driver attention */
2697         ecore_wr(p_hwfn,  p_dpc_ptt,
2698                 ((p_hwfn->rel_pf_id << 3) + MISC_REG_AEU_GENERAL_ATTN_0), 0);
2699
2700         /* Clear per-PF IGU registers to restore them as if the IGU
2701          * was reset for this PF
2702          */
2703         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2704         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2705         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
2706
2707         /* Execute IGU clean up*/
2708         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_FUNCTIONAL_CLEANUP, 1);
2709
2710         /* Clear Stats */
2711         ecore_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED, 0);
2712
2713         for (i = 0; i < IGU_REG_PBA_STS_PF_SIZE; i++)
2714                 ecore_wr(p_hwfn, p_ptt, IGU_REG_PBA_STS_PF + i * 4, 0);
2715 }