drivers/net/qede/base/ecore_int.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include <rte_string_fns.h>
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_spq.h"
  12 #include "ecore_gtt_reg_addr.h"
  13 #include "ecore_init_ops.h"
  14 #include "ecore_rt_defs.h"
  15 #include "ecore_int.h"
  16 #include "reg_addr.h"
  17 #include "ecore_hw.h"
  18 #include "ecore_sriov.h"
  19 #include "ecore_vf.h"
  20 #include "ecore_hw_defs.h"
  21 #include "ecore_hsi_common.h"
  22 #include "ecore_mcp.h"
  23
  24 struct ecore_pi_info {
  25         ecore_int_comp_cb_t comp_cb;
  26         void *cookie;           /* Will be sent to the compl cb function */
  27 };
  28
  29 struct ecore_sb_sp_info {
  30         struct ecore_sb_info sb_info;
  31         /* per protocol index data */
  32         struct ecore_pi_info pi_info_arr[PIS_PER_SB_E4];
  33 };
  34
  35 enum ecore_attention_type {
  36         ECORE_ATTN_TYPE_ATTN,
  37         ECORE_ATTN_TYPE_PARITY,
  38 };
  39
  40 #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
  41         ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
  42
  43 struct aeu_invert_reg_bit {
  44         char bit_name[30];
  45
  46 #define ATTENTION_PARITY                (1 << 0)
  47
  48 #define ATTENTION_LENGTH_MASK           (0x00000ff0)
  49 #define ATTENTION_LENGTH_SHIFT          (4)
  50 #define ATTENTION_LENGTH(flags)         (((flags) & ATTENTION_LENGTH_MASK) >> \
  51                                          ATTENTION_LENGTH_SHIFT)
  52 #define ATTENTION_SINGLE                (1 << ATTENTION_LENGTH_SHIFT)
  53 #define ATTENTION_PAR                   (ATTENTION_SINGLE | ATTENTION_PARITY)
  54 #define ATTENTION_PAR_INT               ((2 << ATTENTION_LENGTH_SHIFT) | \
  55                                          ATTENTION_PARITY)
  56
  57 /* Multiple bits start with this offset */
  58 #define ATTENTION_OFFSET_MASK           (0x000ff000)
  59 #define ATTENTION_OFFSET_SHIFT          (12)
  60
  61 #define ATTENTION_BB_MASK               (0x00700000)
  62 #define ATTENTION_BB_SHIFT              (20)
  63 #define ATTENTION_BB(value)             ((value) << ATTENTION_BB_SHIFT)
  64 #define ATTENTION_BB_DIFFERENT          (1 << 23)
  65
  66 #define ATTENTION_CLEAR_ENABLE          (1 << 28)
  67         unsigned int flags;
  68
  69         /* Callback to call if attention will be triggered */
  70         enum _ecore_status_t (*cb)(struct ecore_hwfn *p_hwfn);
  71
  72         enum block_id block_index;
  73 };
  74
  75 struct aeu_invert_reg {
  76         struct aeu_invert_reg_bit bits[32];
  77 };
  78
  79 #define MAX_ATTN_GRPS           (8)
  80 #define NUM_ATTN_REGS           (9)
  81
  82 static enum _ecore_status_t ecore_mcp_attn_cb(struct ecore_hwfn *p_hwfn)
  83 {
  84         u32 tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
  85
  86         DP_INFO(p_hwfn->p_dev, "MCP_REG_CPU_STATE: %08x - Masking...\n", tmp);
  87         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 0xffffffff);
  88
  89         return ECORE_SUCCESS;
  90 }
  91
  92 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK         (0x3c000)
  93 #define ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT        (14)
  94 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK         (0x03fc0)
  95 #define ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT        (6)
  96 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK      (0x00020)
  97 #define ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT     (5)
  98 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK     (0x0001e)
  99 #define ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT    (1)
 100 #define ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK      (0x1)
 101 #define ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT     (0)
 102 #define ECORE_PSWHST_ATTENTION_VF_DISABLED              (0x1)
 103 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS         (0x1)
 104 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK         (0x1)
 105 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT        (0)
 106 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK     (0x1e)
 107 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT    (1)
 108 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK   (0x20)
 109 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT  (5)
 110 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK      (0x3fc0)
 111 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT     (6)
 112 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK      (0x3c000)
 113 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT     (14)
 114 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK    (0x3fc0000)
 115 #define ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT   (18)
 116 static enum _ecore_status_t ecore_pswhst_attn_cb(struct ecore_hwfn *p_hwfn)
 117 {
 118         u32 tmp =
 119             ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 120                      PSWHST_REG_VF_DISABLED_ERROR_VALID);
 121
 122         /* Disabled VF access */
 123         if (tmp & ECORE_PSWHST_ATTENTION_VF_DISABLED) {
 124                 u32 addr, data;
 125
 126                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 127                                 PSWHST_REG_VF_DISABLED_ERROR_ADDRESS);
 128                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 129                                 PSWHST_REG_VF_DISABLED_ERROR_DATA);
 130                 DP_INFO(p_hwfn->p_dev,
 131                         "PF[0x%02x] VF [0x%02x] [Valid 0x%02x] Client [0x%02x]"
 132                         " Write [0x%02x] Addr [0x%08x]\n",
 133                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_PF_MASK)
 134                              >> ECORE_PSWHST_ATTENTION_DISABLED_PF_SHIFT),
 135                         (u8)((data & ECORE_PSWHST_ATTENTION_DISABLED_VF_MASK)
 136                              >> ECORE_PSWHST_ATTENTION_DISABLED_VF_SHIFT),
 137                         (u8)((data &
 138                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_MASK) >>
 139                               ECORE_PSWHST_ATTENTION_DISABLED_VALID_SHIFT),
 140                         (u8)((data &
 141                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_MASK) >>
 142                               ECORE_PSWHST_ATTENTION_DISABLED_CLIENT_SHIFT),
 143                         (u8)((data &
 144                               ECORE_PSWHST_ATTENTION_DISABLED_WRITE_MASK) >>
 145                               ECORE_PSWHST_ATTNETION_DISABLED_WRITE_SHIFT),
 146                         addr);
 147         }
 148
 149         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 150                        PSWHST_REG_INCORRECT_ACCESS_VALID);
 151         if (tmp & ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS) {
 152                 u32 addr, data, length;
 153
 154                 addr = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 155                                 PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
 156                 data = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 157                                 PSWHST_REG_INCORRECT_ACCESS_DATA);
 158                 length = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 159                                   PSWHST_REG_INCORRECT_ACCESS_LENGTH);
 160
 161                 DP_INFO(p_hwfn->p_dev,
 162                         "Incorrect access to %08x of length %08x - PF [%02x]"
 163                         " VF [%04x] [valid %02x] client [%02x] write [%02x]"
 164                         " Byte-Enable [%04x] [%08x]\n",
 165                         addr, length,
 166                         (u8)((data &
 167                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_MASK) >>
 168                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT),
 169                         (u8)((data &
 170                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_MASK) >>
 171                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT),
 172                         (u8)((data &
 173                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK) >>
 174                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT),
 175                         (u8)((data &
 176                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_MASK) >>
 177                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT),
 178                         (u8)((data &
 179                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_MASK) >>
 180                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_WR_SHIFT),
 181                         (u8)((data &
 182                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK) >>
 183                       ECORE_PSWHST_ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT),
 184                         data);
 185         }
 186
 187         /* TODO - We know 'some' of these are legal due to virtualization,
 188          * but is it true for all of them?
 189          */
 190         return ECORE_SUCCESS;
 191 }
 192
 193 #define ECORE_GRC_ATTENTION_VALID_BIT           (1 << 0)
 194 #define ECORE_GRC_ATTENTION_ADDRESS_MASK        (0x7fffff << 0)
 195 #define ECORE_GRC_ATTENTION_RDWR_BIT            (1 << 23)
 196 #define ECORE_GRC_ATTENTION_MASTER_MASK         (0xf << 24)
 197 #define ECORE_GRC_ATTENTION_MASTER_SHIFT        (24)
 198 #define ECORE_GRC_ATTENTION_PF_MASK             (0xf)
 199 #define ECORE_GRC_ATTENTION_VF_MASK             (0xff << 4)
 200 #define ECORE_GRC_ATTENTION_VF_SHIFT            (4)
 201 #define ECORE_GRC_ATTENTION_PRIV_MASK           (0x3 << 14)
 202 #define ECORE_GRC_ATTENTION_PRIV_SHIFT          (14)
 203 #define ECORE_GRC_ATTENTION_PRIV_VF             (0)
 204 static const char *grc_timeout_attn_master_to_str(u8 master)
 205 {
 206         switch (master) {
 207         case 1:
 208                 return "PXP";
 209         case 2:
 210                 return "MCP";
 211         case 3:
 212                 return "MSDM";
 213         case 4:
 214                 return "PSDM";
 215         case 5:
 216                 return "YSDM";
 217         case 6:
 218                 return "USDM";
 219         case 7:
 220                 return "TSDM";
 221         case 8:
 222                 return "XSDM";
 223         case 9:
 224                 return "DBU";
 225         case 10:
 226                 return "DMAE";
 227         default:
 228                 return "Unknown";
 229         }
 230 }
 231
 232 static enum _ecore_status_t ecore_grc_attn_cb(struct ecore_hwfn *p_hwfn)
 233 {
 234         enum _ecore_status_t rc = ECORE_SUCCESS;
 235         u32 tmp, tmp2;
 236
 237         /* We've already cleared the timeout interrupt register, so we learn
 238          * of interrupts via the validity register.
 239          * Any attention which is not for a timeout event is treated as fatal.
 240          */
 241         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 242                        GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
 243         if (!(tmp & ECORE_GRC_ATTENTION_VALID_BIT)) {
 244                 rc = ECORE_INVAL;
 245                 goto out;
 246         }
 247
 248         /* Read the GRC timeout information */
 249         tmp = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 250                        GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
 251         tmp2 = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 252                         GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
 253
 254         DP_NOTICE(p_hwfn->p_dev, false,
 255                   "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
 256                   tmp2, tmp,
 257                   (tmp & ECORE_GRC_ATTENTION_RDWR_BIT) ? "Write to"
 258                                                        : "Read from",
 259                   (tmp & ECORE_GRC_ATTENTION_ADDRESS_MASK) << 2,
 260                   grc_timeout_attn_master_to_str(
 261                         (tmp & ECORE_GRC_ATTENTION_MASTER_MASK) >>
 262                          ECORE_GRC_ATTENTION_MASTER_SHIFT),
 263                   (tmp2 & ECORE_GRC_ATTENTION_PF_MASK),
 264                   (((tmp2 & ECORE_GRC_ATTENTION_PRIV_MASK) >>
 265                   ECORE_GRC_ATTENTION_PRIV_SHIFT) ==
 266                   ECORE_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant:)",
 267                   (tmp2 & ECORE_GRC_ATTENTION_VF_MASK) >>
 268                   ECORE_GRC_ATTENTION_VF_SHIFT);
 269
 270         /* Clean the validity bit */
 271         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 272                  GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
 273 out:
 274         return rc;
 275 }
 276
 277 #define ECORE_PGLUE_ATTENTION_VALID (1 << 29)
 278 #define ECORE_PGLUE_ATTENTION_RD_VALID (1 << 26)
 279 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf << 20)
 280 #define ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
 281 #define ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID (1 << 19)
 282 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff << 24)
 283 #define ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
 284 #define ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR (1 << 21)
 285 #define ECORE_PGLUE_ATTENTION_DETAILS2_BME      (1 << 22)
 286 #define ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN (1 << 23)
 287 #define ECORE_PGLUE_ATTENTION_ICPL_VALID (1 << 23)
 288 #define ECORE_PGLUE_ATTENTION_ZLR_VALID (1 << 25)
 289 #define ECORE_PGLUE_ATTENTION_ILT_VALID (1 << 23)
 290
 291 enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
 292                                                    struct ecore_ptt *p_ptt,
 293                                                    bool is_hw_init)
 294 {
 295         u32 tmp;
 296         char str[512] = {0};
 297
 298         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
 299         if (tmp & ECORE_PGLUE_ATTENTION_VALID) {
 300                 u32 addr_lo, addr_hi, details;
 301
 302                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 303                                    PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
 304                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 305                                    PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
 306                 details = ecore_rd(p_hwfn, p_ptt,
 307                                    PGLUE_B_REG_TX_ERR_WR_DETAILS);
 308                 OSAL_SNPRINTF(str, 512,
 309                          "Illegal write by chip to [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 310                           addr_hi, addr_lo, details,
 311                           (u8)((details &
 312                                 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 313                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 314                           (u8)((details &
 315                                 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 316                                ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 317                           (u8)((details &
 318                                ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 319                           tmp,
 320                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
 321                                 1 : 0),
 322                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
 323                                 1 : 0),
 324                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
 325                                 1 : 0));
 326                 if (is_hw_init)
 327                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "%s", str);
 328                 else
 329                         DP_NOTICE(p_hwfn, false, "%s", str);
 330         }
 331
 332         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
 333         if (tmp & ECORE_PGLUE_ATTENTION_RD_VALID) {
 334                 u32 addr_lo, addr_hi, details;
 335
 336                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 337                                    PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
 338                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 339                                    PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
 340                 details = ecore_rd(p_hwfn, p_ptt,
 341                                    PGLUE_B_REG_TX_ERR_RD_DETAILS);
 342
 343                 DP_NOTICE(p_hwfn, false,
 344                           "Illegal read by chip from [%08x:%08x] blocked. Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x] Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
 345                           addr_hi, addr_lo, details,
 346                           (u8)((details &
 347                                 ECORE_PGLUE_ATTENTION_DETAILS_PFID_MASK) >>
 348                                ECORE_PGLUE_ATTENTION_DETAILS_PFID_SHIFT),
 349                           (u8)((details &
 350                                 ECORE_PGLUE_ATTENTION_DETAILS_VFID_MASK) >>
 351                                ECORE_PGLUE_ATTENTION_DETAILS_VFID_SHIFT),
 352                           (u8)((details &
 353                                ECORE_PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0),
 354                           tmp,
 355                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_WAS_ERR) ?
 356                                 1 : 0),
 357                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_BME) ?
 358                                 1 : 0),
 359                           (u8)((tmp & ECORE_PGLUE_ATTENTION_DETAILS2_FID_EN) ?
 360                                 1 : 0));
 361         }
 362
 363         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
 364         if (tmp & ECORE_PGLUE_ATTENTION_ICPL_VALID)
 365                 DP_NOTICE(p_hwfn, false, "ICPL erorr - %08x\n", tmp);
 366
 367         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
 368         if (tmp & ECORE_PGLUE_ATTENTION_ZLR_VALID) {
 369                 u32 addr_hi, addr_lo;
 370
 371                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 372                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
 373                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 374                                    PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
 375
 376                 DP_NOTICE(p_hwfn, false,
 377                           "ICPL erorr - %08x [Address %08x:%08x]\n",
 378                           tmp, addr_hi, addr_lo);
 379         }
 380
 381         tmp = ecore_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
 382         if (tmp & ECORE_PGLUE_ATTENTION_ILT_VALID) {
 383                 u32 addr_hi, addr_lo, details;
 384
 385                 addr_lo = ecore_rd(p_hwfn, p_ptt,
 386                                    PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
 387                 addr_hi = ecore_rd(p_hwfn, p_ptt,
 388                                    PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
 389                 details = ecore_rd(p_hwfn, p_ptt,
 390                                    PGLUE_B_REG_VF_ILT_ERR_DETAILS);
 391
 392                 DP_NOTICE(p_hwfn, false,
 393                           "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
 394                           details, tmp, addr_hi, addr_lo);
 395         }
 396
 397         /* Clear the indications */
 398         ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2));
 399
 400         return ECORE_SUCCESS;
 401 }
 402
 403 static enum _ecore_status_t ecore_pglueb_rbc_attn_cb(struct ecore_hwfn *p_hwfn)
 404 {
 405         return ecore_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt, false);
 406 }
 407
 408 static enum _ecore_status_t ecore_fw_assertion(struct ecore_hwfn *p_hwfn)
 409 {
 410         DP_NOTICE(p_hwfn, false, "FW assertion!\n");
 411
 412         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FW_ASSERT);
 413
 414         return ECORE_INVAL;
 415 }
 416
 417 static enum _ecore_status_t
 418 ecore_general_attention_35(struct ecore_hwfn *p_hwfn)
 419 {
 420         DP_INFO(p_hwfn, "General attention 35!\n");
 421
 422         return ECORE_SUCCESS;
 423 }
 424
 425 #define ECORE_DORQ_ATTENTION_REASON_MASK        (0xfffff)
 426 #define ECORE_DORQ_ATTENTION_OPAQUE_MASK        (0xffff)
 427 #define ECORE_DORQ_ATTENTION_OPAQUE_SHIFT       (0x0)
 428 #define ECORE_DORQ_ATTENTION_SIZE_MASK          (0x7f)
 429 #define ECORE_DORQ_ATTENTION_SIZE_SHIFT         (16)
 430
 431 #define ECORE_DB_REC_COUNT                      10
 432 #define ECORE_DB_REC_INTERVAL                   100
 433
 434 /* assumes sticky overflow indication was set for this PF */
 435 static enum _ecore_status_t ecore_db_rec_attn(struct ecore_hwfn *p_hwfn,
 436                                               struct ecore_ptt *p_ptt)
 437 {
 438         u8 count = ECORE_DB_REC_COUNT;
 439         u32 usage = 1;
 440
 441         /* wait for usage to zero or count to run out. This is necessary since
 442          * EDPM doorbell transactions can take multiple 64b cycles, and as such
 443          * can "split" over the pci. Possibly, the doorbell drop can happen with
 444          * half an EDPM in the queue and other half dropped. Another EDPM
 445          * doorbell to the same address (from doorbell recovery mechanism or
 446          * from the doorbelling entity) could have first half dropped and second
 447          * half interperted as continuation of the first. To prevent such
 448          * malformed doorbells from reaching the device, flush the queue before
 449          * releaseing the overflow sticky indication.
 450          */
 451         while (count-- && usage) {
 452                 usage = ecore_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT);
 453                 OSAL_UDELAY(ECORE_DB_REC_INTERVAL);
 454         }
 455
 456         /* should have been depleted by now */
 457         if (usage) {
 458                 DP_NOTICE(p_hwfn->p_dev, false,
 459                           "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n",
 460                           ECORE_DB_REC_INTERVAL * ECORE_DB_REC_COUNT, usage);
 461                 return ECORE_TIMEOUT;
 462         }
 463
 464         /* flush any pedning (e)dpm as they may never arrive */
 465         ecore_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1);
 466
 467         /* release overflow sticky indication (stop silently dropping
 468          * everything)
 469          */
 470         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
 471
 472         /* repeat all last doorbells (doorbell drop recovery) */
 473         ecore_db_recovery_execute(p_hwfn, DB_REC_REAL_DEAL);
 474
 475         return ECORE_SUCCESS;
 476 }
 477
 478 static enum _ecore_status_t ecore_dorq_attn_cb(struct ecore_hwfn *p_hwfn)
 479 {
 480         u32 int_sts, first_drop_reason, details, address, overflow,
 481                 all_drops_reason;
 482         struct ecore_ptt *p_ptt = p_hwfn->p_dpc_ptt;
 483         enum _ecore_status_t rc;
 484
 485         int_sts = ecore_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS);
 486         DP_NOTICE(p_hwfn->p_dev, false, "DORQ attention. int_sts was %x\n",
 487                   int_sts);
 488
 489         /* int_sts may be zero since all PFs were interrupted for doorbell
 490          * overflow but another one already handled it. Can abort here. If
 491          * This PF also requires overflow recovery we will be interrupted again
 492          */
 493         if (!int_sts)
 494                 return ECORE_SUCCESS;
 495
 496         /* check if db_drop or overflow happened */
 497         if (int_sts & (DORQ_REG_INT_STS_DB_DROP |
 498                        DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) {
 499                 /* obtain data about db drop/overflow */
 500                 first_drop_reason = ecore_rd(p_hwfn, p_ptt,
 501                                   DORQ_REG_DB_DROP_REASON) &
 502                                   ECORE_DORQ_ATTENTION_REASON_MASK;
 503                 details = ecore_rd(p_hwfn, p_ptt,
 504                                    DORQ_REG_DB_DROP_DETAILS);
 505                 address = ecore_rd(p_hwfn, p_ptt,
 506                                    DORQ_REG_DB_DROP_DETAILS_ADDRESS);
 507                 overflow = ecore_rd(p_hwfn, p_ptt,
 508                                     DORQ_REG_PF_OVFL_STICKY);
 509                 all_drops_reason = ecore_rd(p_hwfn, p_ptt,
 510                                             DORQ_REG_DB_DROP_DETAILS_REASON);
 511
 512                 /* log info */
 513                 DP_NOTICE(p_hwfn->p_dev, false,
 514                           "Doorbell drop occurred\n"
 515                           "Address\t\t0x%08x\t(second BAR address)\n"
 516                           "FID\t\t0x%04x\t\t(Opaque FID)\n"
 517                           "Size\t\t0x%04x\t\t(in bytes)\n"
 518                           "1st drop reason\t0x%08x\t(details on first drop since last handling)\n"
 519                           "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n"
 520                           "Overflow\t0x%x\t\t(a per PF indication)\n",
 521                           address,
 522                           GET_FIELD(details, ECORE_DORQ_ATTENTION_OPAQUE),
 523                           GET_FIELD(details, ECORE_DORQ_ATTENTION_SIZE) * 4,
 524                           first_drop_reason, all_drops_reason, overflow);
 525
 526                 /* if this PF caused overflow, initiate recovery */
 527                 if (overflow) {
 528                         rc = ecore_db_rec_attn(p_hwfn, p_ptt);
 529                         if (rc != ECORE_SUCCESS)
 530                                 return rc;
 531                 }
 532
 533                 /* clear the doorbell drop details and prepare for next drop */
 534                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0);
 535
 536                 /* mark interrupt as handeld (note: even if drop was due to a
 537                  * different reason than overflow we mark as handled)
 538                  */
 539                 ecore_wr(p_hwfn, p_ptt, DORQ_REG_INT_STS_WR,
 540                          DORQ_REG_INT_STS_DB_DROP |
 541                          DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR);
 542
 543                 /* if there are no indications otherthan drop indications,
 544                  * success
 545                  */
 546                 if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP |
 547                                  DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR |
 548                                  DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0)
 549                         return ECORE_SUCCESS;
 550         }
 551
 552         /* some other indication was present - non recoverable */
 553         DP_INFO(p_hwfn, "DORQ fatal attention\n");
 554
 555         return ECORE_INVAL;
 556 }
 557
 558 static enum _ecore_status_t ecore_tm_attn_cb(struct ecore_hwfn *p_hwfn)
 559 {
 560 #ifndef ASIC_ONLY
 561         if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev)) {
 562                 u32 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 563                                    TM_REG_INT_STS_1);
 564
 565                 if (val & ~(TM_REG_INT_STS_1_PEND_TASK_SCAN |
 566                             TM_REG_INT_STS_1_PEND_CONN_SCAN))
 567                         return ECORE_INVAL;
 568
 569                 if (val & (TM_REG_INT_STS_1_PEND_TASK_SCAN |
 570                            TM_REG_INT_STS_1_PEND_CONN_SCAN))
 571                         DP_INFO(p_hwfn,
 572                                 "TM attention on emulation - most likely"
 573                                 " results of clock-ratios\n");
 574                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1);
 575                 val |= TM_REG_INT_MASK_1_PEND_CONN_SCAN |
 576                     TM_REG_INT_MASK_1_PEND_TASK_SCAN;
 577                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, TM_REG_INT_MASK_1, val);
 578
 579                 return ECORE_SUCCESS;
 580         }
 581 #endif
 582
 583         return ECORE_INVAL;
 584 }
 585
 586 /* Instead of major changes to the data-structure, we have a some 'special'
 587  * identifiers for sources that changed meaning between adapters.
 588  */
 589 enum aeu_invert_reg_special_type {
 590         AEU_INVERT_REG_SPECIAL_CNIG_0,
 591         AEU_INVERT_REG_SPECIAL_CNIG_1,
 592         AEU_INVERT_REG_SPECIAL_CNIG_2,
 593         AEU_INVERT_REG_SPECIAL_CNIG_3,
 594         AEU_INVERT_REG_SPECIAL_MAX,
 595 };
 596
 597 static struct aeu_invert_reg_bit
 598 aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
 599         {"CNIG port 0", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 600         {"CNIG port 1", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 601         {"CNIG port 2", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 602         {"CNIG port 3", ATTENTION_SINGLE, OSAL_NULL, BLOCK_CNIG},
 603 };
 604
 605 /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
 606 static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
 607         {
 608          {                      /* After Invert 1 */
 609           {"GPIO0 function%d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 610            MAX_BLOCK_ID},
 611           }
 612          },
 613
 614         {
 615          {                      /* After Invert 2 */
 616           {"PGLUE config_space", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 617           {"PGLUE misc_flr", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 618           {"PGLUE B RBC", ATTENTION_PAR_INT, ecore_pglueb_rbc_attn_cb,
 619            BLOCK_PGLUE_B},
 620           {"PGLUE misc_mctp", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 621           {"Flash event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 622           {"SMB event", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 623           {"Main Power", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 624           {"SW timers #%d",
 625            (8 << ATTENTION_LENGTH_SHIFT) | (1 << ATTENTION_OFFSET_SHIFT),
 626            OSAL_NULL, MAX_BLOCK_ID},
 627           {"PCIE glue/PXP VPD %d", (16 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 628            BLOCK_PGLCS},
 629           }
 630          },
 631
 632         {
 633          {                      /* After Invert 3 */
 634           {"General Attention %d", (32 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 635            MAX_BLOCK_ID},
 636           }
 637          },
 638
 639         {
 640          {                      /* After Invert 4 */
 641           {"General Attention 32", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 642            ecore_fw_assertion, MAX_BLOCK_ID},
 643           {"General Attention %d",
 644            (2 << ATTENTION_LENGTH_SHIFT) | (33 << ATTENTION_OFFSET_SHIFT),
 645            OSAL_NULL, MAX_BLOCK_ID},
 646           {"General Attention 35", ATTENTION_SINGLE | ATTENTION_CLEAR_ENABLE,
 647            ecore_general_attention_35, MAX_BLOCK_ID},
 648           {"NWS Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 649                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
 650                          OSAL_NULL, BLOCK_NWS},
 651           {"NWS Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 652                             ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
 653                             OSAL_NULL, BLOCK_NWS},
 654           {"NWM Parity", ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
 655                          ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
 656                          OSAL_NULL, BLOCK_NWM},
 657           {"NWM Interrupt", ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
 658                             ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
 659                             OSAL_NULL, BLOCK_NWM},
 660           {"MCP CPU", ATTENTION_SINGLE, ecore_mcp_attn_cb, MAX_BLOCK_ID},
 661           {"MCP Watchdog timer", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 662           {"MCP M2P", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 663           {"AVS stop status ready", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 664           {"MSTAT", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 665           {"MSTAT per-path", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 666           {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 667            MAX_BLOCK_ID},
 668           {"NIG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NIG},
 669           {"BMB/OPTE/MCP", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BMB},
 670           {"BTB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BTB},
 671           {"BRB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_BRB},
 672           {"PRS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRS},
 673           }
 674          },
 675
 676         {
 677          {                      /* After Invert 5 */
 678           {"SRC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_SRC},
 679           {"PB Client1", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB1},
 680           {"PB Client2", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF_PB2},
 681           {"RPB", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RPB},
 682           {"PBF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PBF},
 683           {"QM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_QM},
 684           {"TM", ATTENTION_PAR_INT, ecore_tm_attn_cb, BLOCK_TM},
 685           {"MCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MCM},
 686           {"MSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSDM},
 687           {"MSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MSEM},
 688           {"PCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PCM},
 689           {"PSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSDM},
 690           {"PSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSEM},
 691           {"TCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCM},
 692           {"TSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSDM},
 693           {"TSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TSEM},
 694           }
 695          },
 696
 697         {
 698          {                      /* After Invert 6 */
 699           {"UCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_UCM},
 700           {"USDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USDM},
 701           {"USEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_USEM},
 702           {"XCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XCM},
 703           {"XSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSDM},
 704           {"XSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XSEM},
 705           {"YCM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YCM},
 706           {"YSDM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSDM},
 707           {"YSEM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YSEM},
 708           {"XYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_XYLD},
 709           {"TMLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TMLD},
 710           {"MYLD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MULD},
 711           {"YULD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_YULD},
 712           {"DORQ", ATTENTION_PAR_INT, ecore_dorq_attn_cb, BLOCK_DORQ},
 713           {"DBG", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DBG},
 714           {"IPC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IPC},
 715           }
 716          },
 717
 718         {
 719          {                      /* After Invert 7 */
 720           {"CCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CCFC},
 721           {"CDU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CDU},
 722           {"DMAE", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_DMAE},
 723           {"IGU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_IGU},
 724           {"ATC", ATTENTION_PAR_INT, OSAL_NULL, MAX_BLOCK_ID},
 725           {"CAU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CAU},
 726           {"PTU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PTU},
 727           {"PRM", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PRM},
 728           {"TCFC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TCFC},
 729           {"RDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RDIF},
 730           {"TDIF", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_TDIF},
 731           {"RSS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_RSS},
 732           {"MISC", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISC},
 733           {"MISCS", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_MISCS},
 734           {"PCIE", ATTENTION_PAR, OSAL_NULL, BLOCK_PCIE},
 735           {"Vaux PCI core", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 736           {"PSWRQ", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ},
 737           }
 738          },
 739
 740         {
 741          {                      /* After Invert 8 */
 742           {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRQ2},
 743           {"PSWWR", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR},
 744           {"PSWWR (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWWR2},
 745           {"PSWRD", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD},
 746           {"PSWRD (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWRD2},
 747           {"PSWHST", ATTENTION_PAR_INT, ecore_pswhst_attn_cb, BLOCK_PSWHST},
 748           {"PSWHST (pci_clk)", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_PSWHST2},
 749           {"GRC", ATTENTION_PAR_INT, ecore_grc_attn_cb, BLOCK_GRC},
 750           {"CPMU", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_CPMU},
 751           {"NCSI", ATTENTION_PAR_INT, OSAL_NULL, BLOCK_NCSI},
 752           {"MSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 753           {"PSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 754           {"TSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 755           {"USEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 756           {"XSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 757           {"YSEM PRAM", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 758           {"pxp_misc_mps", ATTENTION_PAR, OSAL_NULL, BLOCK_PGLCS},
 759           {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, OSAL_NULL, BLOCK_PGLCS},
 760           {"PERST_B assertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 761           {"PERST_B deassertion", ATTENTION_SINGLE, OSAL_NULL, MAX_BLOCK_ID},
 762           {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 763            MAX_BLOCK_ID},
 764           }
 765          },
 766
 767         {
 768          {                      /* After Invert 9 */
 769           {"MCP Latched memory", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 770           {"MCP Latched scratchpad cache", ATTENTION_SINGLE, OSAL_NULL,
 771            MAX_BLOCK_ID},
 772           {"MCP Latched ump_tx", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 773           {"MCP Latched scratchpad", ATTENTION_PAR, OSAL_NULL, MAX_BLOCK_ID},
 774           {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), OSAL_NULL,
 775            MAX_BLOCK_ID},
 776           }
 777          },
 778
 779 };
 780
 781 static struct aeu_invert_reg_bit *
 782 ecore_int_aeu_translate(struct ecore_hwfn *p_hwfn,
 783                         struct aeu_invert_reg_bit *p_bit)
 784 {
 785         if (!ECORE_IS_BB(p_hwfn->p_dev))
 786                 return p_bit;
 787
 788         if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
 789                 return p_bit;
 790
 791         return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
 792                                   ATTENTION_BB_SHIFT];
 793 }
 794
 795 static bool ecore_int_is_parity_flag(struct ecore_hwfn *p_hwfn,
 796                                      struct aeu_invert_reg_bit *p_bit)
 797 {
 798         return !!(ecore_int_aeu_translate(p_hwfn, p_bit)->flags &
 799                   ATTENTION_PARITY);
 800 }
 801
 802 #define ATTN_STATE_BITS         (0xfff)
 803 #define ATTN_BITS_MASKABLE      (0x3ff)
 804 struct ecore_sb_attn_info {
 805         /* Virtual & Physical address of the SB */
 806         struct atten_status_block *sb_attn;
 807         dma_addr_t sb_phys;
 808
 809         /* Last seen running index */
 810         u16 index;
 811
 812         /* A mask of the AEU bits resulting in a parity error */
 813         u32 parity_mask[NUM_ATTN_REGS];
 814
 815         /* A pointer to the attention description structure */
 816         struct aeu_invert_reg *p_aeu_desc;
 817
 818         /* Previously asserted attentions, which are still unasserted */
 819         u16 known_attn;
 820
 821         /* Cleanup address for the link's general hw attention */
 822         u32 mfw_attn_addr;
 823 };
 824
 825 static u16 ecore_attn_update_idx(struct ecore_hwfn *p_hwfn,
 826                                  struct ecore_sb_attn_info *p_sb_desc)
 827 {
 828         u16 rc = 0, index;
 829
 830         OSAL_MMIOWB(p_hwfn->p_dev);
 831
 832         index = OSAL_LE16_TO_CPU(p_sb_desc->sb_attn->sb_index);
 833         if (p_sb_desc->index != index) {
 834                 p_sb_desc->index = index;
 835                 rc = ECORE_SB_ATT_IDX;
 836         }
 837
 838         OSAL_MMIOWB(p_hwfn->p_dev);
 839
 840         return rc;
 841 }
 842
 843 /**
 844  * @brief ecore_int_assertion - handles asserted attention bits
 845  *
 846  * @param p_hwfn
 847  * @param asserted_bits newly asserted bits
 848  * @return enum _ecore_status_t
 849  */
 850 static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
 851                                                 u16 asserted_bits)
 852 {
 853         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
 854         u32 igu_mask;
 855
 856         /* Mask the source of the attention in the IGU */
 857         igu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
 858                             IGU_REG_ATTENTION_ENABLE);
 859         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
 860                    igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
 861         igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
 862         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
 863
 864         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
 865                    "inner known ATTN state: 0x%04x --> 0x%04x\n",
 866                    sb_attn_sw->known_attn,
 867                    sb_attn_sw->known_attn | asserted_bits);
 868         sb_attn_sw->known_attn |= asserted_bits;
 869
 870         /* Handle MCP events */
 871         if (asserted_bits & 0x100) {
 872                 ecore_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
 873                 /* Clean the MCP attention */
 874                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt,
 875                          sb_attn_sw->mfw_attn_addr, 0);
 876         }
 877
 878         /* FIXME - this will change once we'll have GOOD gtt definitions */
 879         DIRECT_REG_WR(p_hwfn,
 880                       (u8 OSAL_IOMEM *) p_hwfn->regview +
 881                       GTT_BAR0_MAP_REG_IGU_CMD +
 882                       ((IGU_CMD_ATTN_BIT_SET_UPPER -
 883                         IGU_CMD_INT_ACK_BASE) << 3), (u32)asserted_bits);
 884
 885         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "set cmd IGU: 0x%04x\n",
 886                    asserted_bits);
 887
 888         return ECORE_SUCCESS;
 889 }
 890
 891 static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
 892                                  enum block_id id, enum dbg_attn_type type,
 893                                  bool b_clear)
 894 {
 895         /* @DPDK */
 896         DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n", id, type);
 897 }
 898
 899 /**
 900  * @brief ecore_int_deassertion_aeu_bit - handles the effects of a single
 901  * cause of the attention
 902  *
 903  * @param p_hwfn
 904  * @param p_aeu - descriptor of an AEU bit which caused the attention
 905  * @param aeu_en_reg - register offset of the AEU enable reg. which configured
 906  *  this bit to this group.
 907  * @param bit_index - index of this bit in the aeu_en_reg
 908  *
 909  * @return enum _ecore_status_t
 910  */
 911 static enum _ecore_status_t
 912 ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
 913                               struct aeu_invert_reg_bit *p_aeu,
 914                               u32 aeu_en_reg,
 915                               const char *p_bit_name,
 916                               u32 bitmask)
 917 {
 918         enum _ecore_status_t rc = ECORE_INVAL;
 919         bool b_fatal = false;
 920
 921         DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
 922                 p_bit_name, bitmask);
 923
 924         /* Call callback before clearing the interrupt status */
 925         if (p_aeu->cb) {
 926                 DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
 927                         p_bit_name);
 928                 rc = p_aeu->cb(p_hwfn);
 929         }
 930
 931         if (rc != ECORE_SUCCESS)
 932                 b_fatal = true;
 933
 934         /* Print HW block interrupt registers */
 935         if (p_aeu->block_index != MAX_BLOCK_ID) {
 936                 ecore_int_attn_print(p_hwfn, p_aeu->block_index,
 937                                      ATTN_TYPE_INTERRUPT, !b_fatal);
 938 }
 939
 940         /* @DPDK */
 941         /* Reach assertion if attention is fatal */
 942         if (b_fatal || (strcmp(p_bit_name, "PGLUE B RBC") == 0)) {
 943                 DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
 944                           p_bit_name);
 945
 946                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
 947         }
 948
 949         /* Prevent this Attention from being asserted in the future */
 950         if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
 951             p_hwfn->p_dev->attn_clr_en) {
 952                 u32 val;
 953                 u32 mask = ~bitmask;
 954                 val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 955                 ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
 956                 DP_ERR(p_hwfn, "`%s' - Disabled future attentions\n",
 957                         p_bit_name);
 958         }
 959
 960         return rc;
 961 }
 962
 963 /**
 964  * @brief ecore_int_deassertion_parity - handle a single parity AEU source
 965  *
 966  * @param p_hwfn
 967  * @param p_aeu - descriptor of an AEU bit which caused the parity
 968  * @param aeu_en_reg - address of the AEU enable register
 969  * @param bit_index
 970  */
 971 static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
 972                                          struct aeu_invert_reg_bit *p_aeu,
 973                                          u32 aeu_en_reg, u8 bit_index)
 974 {
 975         u32 block_id = p_aeu->block_index, mask, val;
 976
 977         DP_NOTICE(p_hwfn->p_dev, false,
 978                   "%s parity attention is set [address 0x%08x, bit %d]\n",
 979                   p_aeu->bit_name, aeu_en_reg, bit_index);
 980
 981         if (block_id != MAX_BLOCK_ID) {
 982                 ecore_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
 983
 984                 /* In A0, there's a single parity bit for several blocks */
 985                 if (block_id == BLOCK_BTB) {
 986                         ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
 987                                              ATTN_TYPE_PARITY, false);
 988                         ecore_int_attn_print(p_hwfn, BLOCK_MCP,
 989                                              ATTN_TYPE_PARITY, false);
 990                 }
 991         }
 992
 993         /* Prevent this parity error from being re-asserted */
 994         mask = ~(0x1 << bit_index);
 995         val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
 996         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
 997         DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
 998                 p_aeu->bit_name);
 999 }
1000
1001 /**
1002  * @brief - handles deassertion of previously asserted attentions.
1003  *
1004  * @param p_hwfn
1005  * @param deasserted_bits - newly deasserted bits
1006  * @return enum _ecore_status_t
1007  *
1008  */
1009 static enum _ecore_status_t ecore_int_deassertion(struct ecore_hwfn *p_hwfn,
1010                                                   u16 deasserted_bits)
1011 {
1012         struct ecore_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
1013         u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
1014         u8 i, j, k, bit_idx;
1015         enum _ecore_status_t rc = ECORE_SUCCESS;
1016
1017         /* Read the attention registers in the AEU */
1018         for (i = 0; i < NUM_ATTN_REGS; i++) {
1019                 aeu_inv_arr[i] = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1020                                           MISC_REG_AEU_AFTER_INVERT_1_IGU +
1021                                           i * 0x4);
1022                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1023                            "Deasserted bits [%d]: %08x\n", i, aeu_inv_arr[i]);
1024         }
1025
1026         /* Handle parity attentions first */
1027         for (i = 0; i < NUM_ATTN_REGS; i++) {
1028                 struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
1029                 u32 parities;
1030
1031                 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
1032                 en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1033                 parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
1034
1035                 /* Skip register in which no parity bit is currently set */
1036                 if (!parities)
1037                         continue;
1038
1039                 for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1040                         struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
1041
1042                         if (ecore_int_is_parity_flag(p_hwfn, p_bit) &&
1043                             !!(parities & (1 << bit_idx)))
1044                                 ecore_int_deassertion_parity(p_hwfn, p_bit,
1045                                                              aeu_en, bit_idx);
1046
1047                         bit_idx += ATTENTION_LENGTH(p_bit->flags);
1048                 }
1049         }
1050
1051         /* Find non-parity cause for attention and act */
1052         for (k = 0; k < MAX_ATTN_GRPS; k++) {
1053                 struct aeu_invert_reg_bit *p_aeu;
1054
1055                 /* Handle only groups whose attention is currently deasserted */
1056                 if (!(deasserted_bits & (1 << k)))
1057                         continue;
1058
1059                 for (i = 0; i < NUM_ATTN_REGS; i++) {
1060                         u32 bits;
1061
1062                         aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
1063                                  i * sizeof(u32) +
1064                                  k * sizeof(u32) * NUM_ATTN_REGS;
1065                         en = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
1066                         bits = aeu_inv_arr[i] & en;
1067
1068                         /* Skip if no bit from this group is currently set */
1069                         if (!bits)
1070                                 continue;
1071
1072                         /* Find all set bits from current register which belong
1073                          * to current group, making them responsible for the
1074                          * previous assertion.
1075                          */
1076                         for (j = 0, bit_idx = 0; bit_idx < 32; j++) {
1077                                 unsigned long int bitmask;
1078                                 u8 bit, bit_len;
1079
1080                                 /* Need to account bits with changed meaning */
1081                                 p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
1082
1083                                 bit = bit_idx;
1084                                 bit_len = ATTENTION_LENGTH(p_aeu->flags);
1085                                 if (ecore_int_is_parity_flag(p_hwfn, p_aeu)) {
1086                                         /* Skip Parity */
1087                                         bit++;
1088                                         bit_len--;
1089                                 }
1090
1091                                 /* Find the bits relating to HW-block, then
1092                                  * shift so they'll become LSB.
1093                                  */
1094                                 bitmask = bits & (((1 << bit_len) - 1) << bit);
1095                                 bitmask >>= bit;
1096
1097                                 if (bitmask) {
1098                                         u32 flags = p_aeu->flags;
1099                                         char bit_name[30];
1100                                         u8 num;
1101
1102                                         num = (u8)OSAL_FIND_FIRST_BIT(&bitmask,
1103                                                                 bit_len);
1104
1105                                         /* Some bits represent more than a
1106                                          * a single interrupt. Correctly print
1107                                          * their name.
1108                                          */
1109                                         if (ATTENTION_LENGTH(flags) > 2 ||
1110                                             ((flags & ATTENTION_PAR_INT) &&
1111                                             ATTENTION_LENGTH(flags) > 1))
1112                                                 OSAL_SNPRINTF(bit_name, 30,
1113                                                               p_aeu->bit_name,
1114                                                               num);
1115                                         else
1116                                                 strlcpy(bit_name,
1117                                                         p_aeu->bit_name,
1118                                                         sizeof(bit_name));
1119
1120                                         /* We now need to pass bitmask in its
1121                                          * correct position.
1122                                          */
1123                                         bitmask <<= bit;
1124
1125                                         /* Handle source of the attention */
1126                                         ecore_int_deassertion_aeu_bit(p_hwfn,
1127                                                                       p_aeu,
1128                                                                       aeu_en,
1129                                                                       bit_name,
1130                                                                       bitmask);
1131                                 }
1132
1133                                 bit_idx += ATTENTION_LENGTH(p_aeu->flags);
1134                         }
1135                 }
1136         }
1137
1138         /* Clear IGU indication for the deasserted bits */
1139         /* FIXME - this will change once we'll have GOOD gtt definitions */
1140         DIRECT_REG_WR(p_hwfn,
1141                       (u8 OSAL_IOMEM *) p_hwfn->regview +
1142                       GTT_BAR0_MAP_REG_IGU_CMD +
1143                       ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1144                         IGU_CMD_INT_ACK_BASE) << 3), ~((u32)deasserted_bits));
1145
1146         /* Unmask deasserted attentions in IGU */
1147         aeu_mask = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt,
1148                             IGU_REG_ATTENTION_ENABLE);
1149         aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1150         ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1151
1152         /* Clear deassertion from inner state */
1153         sb_attn_sw->known_attn &= ~deasserted_bits;
1154
1155         return rc;
1156 }
1157
1158 static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
1159 {
1160         struct ecore_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1161         struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1162         u16 index = 0, asserted_bits, deasserted_bits;
1163         u32 attn_bits = 0, attn_acks = 0;
1164         enum _ecore_status_t rc = ECORE_SUCCESS;
1165
1166         /* Read current attention bits/acks - safeguard against attentions
1167          * by guaranting work on a synchronized timeframe
1168          */
1169         do {
1170                 index = OSAL_LE16_TO_CPU(p_sb_attn->sb_index);
1171                 attn_bits = OSAL_LE32_TO_CPU(p_sb_attn->atten_bits);
1172                 attn_acks = OSAL_LE32_TO_CPU(p_sb_attn->atten_ack);
1173         } while (index != OSAL_LE16_TO_CPU(p_sb_attn->sb_index));
1174         p_sb_attn->sb_index = index;
1175
1176         /* Attention / Deassertion are meaningful (and in correct state)
1177          * only when they differ and consistent with known state - deassertion
1178          * when previous attention & current ack, and assertion when current
1179          * attention with no previous attention
1180          */
1181         asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1182             ~p_sb_attn_sw->known_attn;
1183         deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1184             p_sb_attn_sw->known_attn;
1185
1186         if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100))
1187                 DP_INFO(p_hwfn,
1188                         "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1189                         index, attn_bits, attn_acks, asserted_bits,
1190                         deasserted_bits, p_sb_attn_sw->known_attn);
1191         else if (asserted_bits == 0x100)
1192                 DP_INFO(p_hwfn, "MFW indication via attention\n");
1193         else
1194                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1195                            "MFW indication [deassertion]\n");
1196
1197         if (asserted_bits) {
1198                 rc = ecore_int_assertion(p_hwfn, asserted_bits);
1199                 if (rc)
1200                         return rc;
1201         }
1202
1203         if (deasserted_bits)
1204                 rc = ecore_int_deassertion(p_hwfn, deasserted_bits);
1205
1206         return rc;
1207 }
1208
1209 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
1210                               void OSAL_IOMEM *igu_addr, u32 ack_cons)
1211 {
1212         struct igu_prod_cons_update igu_ack = { 0 };
1213
1214         igu_ack.sb_id_and_flags =
1215             ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1216              (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1217              (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1218              (IGU_SEG_ACCESS_ATTN <<
1219               IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1220
1221         DIRECT_REG_WR(p_hwfn, igu_addr, igu_ack.sb_id_and_flags);
1222
1223         /* Both segments (interrupts & acks) are written to same place address;
1224          * Need to guarantee all commands will be received (in-order) by HW.
1225          */
1226         OSAL_MMIOWB(p_hwfn->p_dev);
1227         OSAL_BARRIER(p_hwfn->p_dev);
1228 }
1229
1230 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
1231 {
1232         struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
1233         struct ecore_pi_info *pi_info = OSAL_NULL;
1234         struct ecore_sb_attn_info *sb_attn;
1235         struct ecore_sb_info *sb_info;
1236         int arr_size;
1237         u16 rc = 0;
1238
1239         if (!p_hwfn)
1240                 return;
1241
1242         if (!p_hwfn->p_sp_sb) {
1243                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
1244                 return;
1245         }
1246
1247         sb_info = &p_hwfn->p_sp_sb->sb_info;
1248         arr_size = OSAL_ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1249         if (!sb_info) {
1250                 DP_ERR(p_hwfn->p_dev,
1251                        "Status block is NULL - cannot ack interrupts\n");
1252                 return;
1253         }
1254
1255         if (!p_hwfn->p_sb_attn) {
1256                 DP_ERR(p_hwfn->p_dev, "DPC called - no p_sb_attn");
1257                 return;
1258         }
1259         sb_attn = p_hwfn->p_sb_attn;
1260
1261         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1262                    p_hwfn, p_hwfn->my_id);
1263
1264         /* Disable ack for def status block. Required both for msix +
1265          * inta in non-mask mode, in inta does no harm.
1266          */
1267         ecore_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1268
1269         /* Gather Interrupts/Attentions information */
1270         if (!sb_info->sb_virt) {
1271                 DP_ERR(p_hwfn->p_dev,
1272                        "Interrupt Status block is NULL -"
1273                        " cannot check for new interrupts!\n");
1274         } else {
1275                 u32 tmp_index = sb_info->sb_ack;
1276                 rc = ecore_sb_update_sb_idx(sb_info);
1277                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1278                            "Interrupt indices: 0x%08x --> 0x%08x\n",
1279                            tmp_index, sb_info->sb_ack);
1280         }
1281
1282         if (!sb_attn || !sb_attn->sb_attn) {
1283                 DP_ERR(p_hwfn->p_dev,
1284                        "Attentions Status block is NULL -"
1285                        " cannot check for new attentions!\n");
1286         } else {
1287                 u16 tmp_index = sb_attn->index;
1288
1289                 rc |= ecore_attn_update_idx(p_hwfn, sb_attn);
1290                 DP_VERBOSE(p_hwfn->p_dev, ECORE_MSG_INTR,
1291                            "Attention indices: 0x%08x --> 0x%08x\n",
1292                            tmp_index, sb_attn->index);
1293         }
1294
1295         /* Check if we expect interrupts at this time. if not just ack them */
1296         if (!(rc & ECORE_SB_EVENT_MASK)) {
1297                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1298                 return;
1299         }
1300
1301 /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1302
1303         if (!p_hwfn->p_dpc_ptt) {
1304                 DP_NOTICE(p_hwfn->p_dev, true, "Failed to allocate PTT\n");
1305                 ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1306                 return;
1307         }
1308
1309         if (rc & ECORE_SB_ATT_IDX)
1310                 ecore_int_attentions(p_hwfn);
1311
1312         if (rc & ECORE_SB_IDX) {
1313                 int pi;
1314
1315                 /* Since we only looked at the SB index, it's possible more
1316                  * than a single protocol-index on the SB incremented.
1317                  * Iterate over all configured protocol indices and check
1318                  * whether something happened for each.
1319                  */
1320                 for (pi = 0; pi < arr_size; pi++) {
1321                         pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1322                         if (pi_info->comp_cb != OSAL_NULL)
1323                                 pi_info->comp_cb(p_hwfn, pi_info->cookie);
1324                 }
1325         }
1326
1327         if (sb_attn && (rc & ECORE_SB_ATT_IDX)) {
1328                 /* This should be done before the interrupts are enabled,
1329                  * since otherwise a new attention will be generated.
1330                  */
1331                 ecore_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1332         }
1333
1334         ecore_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1335 }
1336
1337 static void ecore_int_sb_attn_free(struct ecore_hwfn *p_hwfn)
1338 {
1339         struct ecore_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1340
1341         if (!p_sb)
1342                 return;
1343
1344         if (p_sb->sb_attn) {
1345                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_sb->sb_attn,
1346                                        p_sb->sb_phys,
1347                                        SB_ATTN_ALIGNED_SIZE(p_hwfn));
1348         }
1349         OSAL_FREE(p_hwfn->p_dev, p_sb);
1350 }
1351
1352 static void ecore_int_sb_attn_setup(struct ecore_hwfn *p_hwfn,
1353                                     struct ecore_ptt *p_ptt)
1354 {
1355         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1356
1357         OSAL_MEMSET(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1358
1359         sb_info->index = 0;
1360         sb_info->known_attn = 0;
1361
1362         /* Configure Attention Status Block in IGU */
1363         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1364                  DMA_LO(p_hwfn->p_sb_attn->sb_phys));
1365         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1366                  DMA_HI(p_hwfn->p_sb_attn->sb_phys));
1367 }
1368
1369 static void ecore_int_sb_attn_init(struct ecore_hwfn *p_hwfn,
1370                                    struct ecore_ptt *p_ptt,
1371                                    void *sb_virt_addr, dma_addr_t sb_phy_addr)
1372 {
1373         struct ecore_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1374         int i, j, k;
1375
1376         sb_info->sb_attn = sb_virt_addr;
1377         sb_info->sb_phys = sb_phy_addr;
1378
1379         /* Set the pointer to the AEU descriptors */
1380         sb_info->p_aeu_desc = aeu_descs;
1381
1382         /* Calculate Parity Masks */
1383         OSAL_MEMSET(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
1384         for (i = 0; i < NUM_ATTN_REGS; i++) {
1385                 /* j is array index, k is bit index */
1386                 for (j = 0, k = 0; k < 32; j++) {
1387                         struct aeu_invert_reg_bit *p_aeu;
1388
1389                         p_aeu = &aeu_descs[i].bits[j];
1390                         if (ecore_int_is_parity_flag(p_hwfn, p_aeu))
1391                                 sb_info->parity_mask[i] |= 1 << k;
1392
1393                         k += ATTENTION_LENGTH(p_aeu->flags);
1394                 }
1395                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1396                            "Attn Mask [Reg %d]: 0x%08x\n",
1397                            i, sb_info->parity_mask[i]);
1398         }
1399
1400         /* Set the address of cleanup for the mcp attention */
1401         sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1402             MISC_REG_AEU_GENERAL_ATTN_0;
1403
1404         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
1405 }
1406
1407 static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
1408                                                     struct ecore_ptt *p_ptt)
1409 {
1410         struct ecore_dev *p_dev = p_hwfn->p_dev;
1411         struct ecore_sb_attn_info *p_sb;
1412         dma_addr_t p_phys = 0;
1413         void *p_virt;
1414
1415         /* SB struct */
1416         p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
1417         if (!p_sb) {
1418                 DP_NOTICE(p_dev, false, "Failed to allocate `struct ecore_sb_attn_info'\n");
1419                 return ECORE_NOMEM;
1420         }
1421
1422         /* SB ring  */
1423         p_virt = OSAL_DMA_ALLOC_COHERENT(p_dev, &p_phys,
1424                                          SB_ATTN_ALIGNED_SIZE(p_hwfn));
1425         if (!p_virt) {
1426                 DP_NOTICE(p_dev, false, "Failed to allocate status block (attentions)\n");
1427                 OSAL_FREE(p_dev, p_sb);
1428                 return ECORE_NOMEM;
1429         }
1430
1431         /* Attention setup */
1432         p_hwfn->p_sb_attn = p_sb;
1433         ecore_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1434
1435         return ECORE_SUCCESS;
1436 }
1437
1438 /* coalescing timeout = timeset << (timer_res + 1) */
1439 #define ECORE_CAU_DEF_RX_USECS 24
1440 #define ECORE_CAU_DEF_TX_USECS 48
1441
1442 void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
1443                              struct cau_sb_entry *p_sb_entry,
1444                              u8 pf_id, u16 vf_number, u8 vf_valid)
1445 {
1446         struct ecore_dev *p_dev = p_hwfn->p_dev;
1447         u32 cau_state;
1448         u8 timer_res;
1449
1450         OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
1451
1452         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
1453         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
1454         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid);
1455         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
1456         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1457
1458         cau_state = CAU_HC_DISABLE_STATE;
1459
1460         if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1461                 cau_state = CAU_HC_ENABLE_STATE;
1462                 if (!p_dev->rx_coalesce_usecs)
1463                         p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
1464                 if (!p_dev->tx_coalesce_usecs)
1465                         p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
1466         }
1467
1468         /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1469         if (p_dev->rx_coalesce_usecs <= 0x7F)
1470                 timer_res = 0;
1471         else if (p_dev->rx_coalesce_usecs <= 0xFF)
1472                 timer_res = 1;
1473         else
1474                 timer_res = 2;
1475         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1476
1477         if (p_dev->tx_coalesce_usecs <= 0x7F)
1478                 timer_res = 0;
1479         else if (p_dev->tx_coalesce_usecs <= 0xFF)
1480                 timer_res = 1;
1481         else
1482                 timer_res = 2;
1483         SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
1484
1485         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
1486         SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
1487 }
1488
1489 static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1490                                    struct ecore_ptt *p_ptt,
1491                                    u16 igu_sb_id, u32 pi_index,
1492                                    enum ecore_coalescing_fsm coalescing_fsm,
1493                                    u8 timeset)
1494 {
1495         struct cau_pi_entry pi_entry;
1496         u32 sb_offset, pi_offset;
1497
1498         if (IS_VF(p_hwfn->p_dev))
1499                 return;/* @@@TBD MichalK- VF CAU... */
1500
1501         sb_offset = igu_sb_id * PIS_PER_SB_E4;
1502         OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
1503
1504         SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
1505         if (coalescing_fsm == ECORE_COAL_RX_STATE_MACHINE)
1506                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
1507         else
1508                 SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
1509
1510         pi_offset = sb_offset + pi_index;
1511         if (p_hwfn->hw_init_done) {
1512                 ecore_wr(p_hwfn, p_ptt,
1513                          CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
1514                          *((u32 *)&(pi_entry)));
1515         } else {
1516                 STORE_RT_REG(p_hwfn,
1517                              CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
1518                              *((u32 *)&(pi_entry)));
1519         }
1520 }
1521
1522 void ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
1523                            struct ecore_ptt *p_ptt,
1524                            struct ecore_sb_info *p_sb, u32 pi_index,
1525                            enum ecore_coalescing_fsm coalescing_fsm,
1526                            u8 timeset)
1527 {
1528         _ecore_int_cau_conf_pi(p_hwfn, p_ptt, p_sb->igu_sb_id,
1529                                pi_index, coalescing_fsm, timeset);
1530 }
1531
1532 void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
1533                            struct ecore_ptt *p_ptt,
1534                            dma_addr_t sb_phys, u16 igu_sb_id,
1535                            u16 vf_number, u8 vf_valid)
1536 {
1537         struct cau_sb_entry sb_entry;
1538
1539         ecore_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1540                                 vf_number, vf_valid);
1541
1542         if (p_hwfn->hw_init_done) {
1543                 /* Wide-bus, initialize via DMAE */
1544                 u64 phys_addr = (u64)sb_phys;
1545
1546                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1547                                     (u64)(osal_uintptr_t)&phys_addr,
1548                                     CAU_REG_SB_ADDR_MEMORY +
1549                                     igu_sb_id * sizeof(u64), 2, 0);
1550                 ecore_dmae_host2grc(p_hwfn, p_ptt,
1551                                     (u64)(osal_uintptr_t)&sb_entry,
1552                                     CAU_REG_SB_VAR_MEMORY +
1553                                     igu_sb_id * sizeof(u64), 2, 0);
1554         } else {
1555                 /* Initialize Status Block Address */
1556                 STORE_RT_REG_AGG(p_hwfn,
1557                                  CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1558                                  igu_sb_id * 2, sb_phys);
1559
1560                 STORE_RT_REG_AGG(p_hwfn,
1561                                  CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1562                                  igu_sb_id * 2, sb_entry);
1563         }
1564
1565         /* Configure pi coalescing if set */
1566         if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
1567                 /* eth will open queues for all tcs, so configure all of them
1568                  * properly, rather than just the active ones
1569                  */
1570                 u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1571
1572                 u8 timeset, timer_res;
1573                 u8 i;
1574
1575                 /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1576                 if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
1577                         timer_res = 0;
1578                 else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
1579                         timer_res = 1;
1580                 else
1581                         timer_res = 2;
1582                 timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
1583                 _ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
1584                                        ECORE_COAL_RX_STATE_MACHINE,
1585                                        timeset);
1586
1587                 if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
1588                         timer_res = 0;
1589                 else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
1590                         timer_res = 1;
1591                 else
1592                         timer_res = 2;
1593                 timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
1594                 for (i = 0; i < num_tc; i++) {
1595                         _ecore_int_cau_conf_pi(p_hwfn, p_ptt,
1596                                                igu_sb_id, TX_PI(i),
1597                                                ECORE_COAL_TX_STATE_MACHINE,
1598                                                timeset);
1599                 }
1600         }
1601 }
1602
1603 void ecore_int_sb_setup(struct ecore_hwfn *p_hwfn,
1604                         struct ecore_ptt *p_ptt, struct ecore_sb_info *sb_info)
1605 {
1606         /* zero status block and ack counter */
1607         sb_info->sb_ack = 0;
1608         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1609
1610         if (IS_PF(p_hwfn->p_dev))
1611                 ecore_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1612                                       sb_info->igu_sb_id, 0, 0);
1613 }
1614
1615 struct ecore_igu_block *
1616 ecore_get_igu_free_sb(struct ecore_hwfn *p_hwfn, bool b_is_pf)
1617 {
1618         struct ecore_igu_block *p_block;
1619         u16 igu_id;
1620
1621         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1622              igu_id++) {
1623                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1624
1625                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1626                     !(p_block->status & ECORE_IGU_STATUS_FREE))
1627                         continue;
1628
1629                 if (!!(p_block->status & ECORE_IGU_STATUS_PF) ==
1630                     b_is_pf)
1631                         return p_block;
1632         }
1633
1634         return OSAL_NULL;
1635 }
1636
1637 static u16 ecore_get_pf_igu_sb_id(struct ecore_hwfn *p_hwfn,
1638                                   u16 vector_id)
1639 {
1640         struct ecore_igu_block *p_block;
1641         u16 igu_id;
1642
1643         for (igu_id = 0; igu_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
1644              igu_id++) {
1645                 p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1646
1647                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
1648                     !p_block->is_pf ||
1649                     p_block->vector_number != vector_id)
1650                         continue;
1651
1652                 return igu_id;
1653         }
1654
1655         return ECORE_SB_INVALID_IDX;
1656 }
1657
1658 u16 ecore_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
1659 {
1660         u16 igu_sb_id;
1661
1662         /* Assuming continuous set of IGU SBs dedicated for given PF */
1663         if (sb_id == ECORE_SP_SB_ID)
1664                 igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
1665         else if (IS_PF(p_hwfn->p_dev))
1666                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
1667         else
1668                 igu_sb_id = ecore_vf_get_igu_sb_id(p_hwfn, sb_id);
1669
1670         if (igu_sb_id == ECORE_SB_INVALID_IDX)
1671                 DP_NOTICE(p_hwfn, true,
1672                           "Slowpath SB vector %04x doesn't exist\n",
1673                           sb_id);
1674         else if (sb_id == ECORE_SP_SB_ID)
1675                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1676                            "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1677         else
1678                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
1679                            "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1680
1681         return igu_sb_id;
1682 }
1683
1684 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn *p_hwfn,
1685                                        struct ecore_ptt *p_ptt,
1686                                        struct ecore_sb_info *sb_info,
1687                                        void *sb_virt_addr,
1688                                        dma_addr_t sb_phy_addr, u16 sb_id)
1689 {
1690         sb_info->sb_virt = sb_virt_addr;
1691         sb_info->sb_phys = sb_phy_addr;
1692
1693         sb_info->igu_sb_id = ecore_get_igu_sb_id(p_hwfn, sb_id);
1694
1695         if (sb_info->igu_sb_id == ECORE_SB_INVALID_IDX)
1696                 return ECORE_INVAL;
1697
1698         /* Let the igu info reference the client's SB info */
1699         if (sb_id != ECORE_SP_SB_ID) {
1700                 if (IS_PF(p_hwfn->p_dev)) {
1701                         struct ecore_igu_info *p_info;
1702                         struct ecore_igu_block *p_block;
1703
1704                         p_info = p_hwfn->hw_info.p_igu_info;
1705                         p_block = &p_info->entry[sb_info->igu_sb_id];
1706
1707                         p_block->sb_info = sb_info;
1708                         p_block->status &= ~ECORE_IGU_STATUS_FREE;
1709                         p_info->usage.free_cnt--;
1710                 } else {
1711                         ecore_vf_set_sb_info(p_hwfn, sb_id, sb_info);
1712                 }
1713         }
1714 #ifdef ECORE_CONFIG_DIRECT_HWFN
1715         sb_info->p_hwfn = p_hwfn;
1716 #endif
1717         sb_info->p_dev = p_hwfn->p_dev;
1718
1719         /* The igu address will hold the absolute address that needs to be
1720          * written to for a specific status block
1721          */
1722         if (IS_PF(p_hwfn->p_dev)) {
1723                 sb_info->igu_addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
1724                     GTT_BAR0_MAP_REG_IGU_CMD + (sb_info->igu_sb_id << 3);
1725
1726         } else {
1727                 sb_info->igu_addr =
1728                     (u8 OSAL_IOMEM *)p_hwfn->regview +
1729                     PXP_VF_BAR0_START_IGU +
1730                     ((IGU_CMD_INT_ACK_BASE + sb_info->igu_sb_id) << 3);
1731         }
1732
1733         sb_info->flags |= ECORE_SB_INFO_INIT;
1734
1735         ecore_int_sb_setup(p_hwfn, p_ptt, sb_info);
1736
1737         return ECORE_SUCCESS;
1738 }
1739
1740 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn *p_hwfn,
1741                                           struct ecore_sb_info *sb_info,
1742                                           u16 sb_id)
1743 {
1744         struct ecore_igu_info *p_info;
1745         struct ecore_igu_block *p_block;
1746
1747         if (sb_info == OSAL_NULL)
1748                 return ECORE_SUCCESS;
1749
1750         /* zero status block and ack counter */
1751         sb_info->sb_ack = 0;
1752         OSAL_MEMSET(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1753
1754         if (IS_VF(p_hwfn->p_dev)) {
1755                 ecore_vf_set_sb_info(p_hwfn, sb_id, OSAL_NULL);
1756                 return ECORE_SUCCESS;
1757         }
1758
1759         p_info = p_hwfn->hw_info.p_igu_info;
1760         p_block = &p_info->entry[sb_info->igu_sb_id];
1761
1762         /* Vector 0 is reserved to Default SB */
1763         if (p_block->vector_number == 0) {
1764                 DP_ERR(p_hwfn, "Do Not free sp sb using this function");
1765                 return ECORE_INVAL;
1766         }
1767
1768         /* Lose reference to client's SB info, and fix counters */
1769         p_block->sb_info = OSAL_NULL;
1770         p_block->status |= ECORE_IGU_STATUS_FREE;
1771         p_info->usage.free_cnt++;
1772
1773         return ECORE_SUCCESS;
1774 }
1775
1776 static void ecore_int_sp_sb_free(struct ecore_hwfn *p_hwfn)
1777 {
1778         struct ecore_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1779
1780         if (!p_sb)
1781                 return;
1782
1783         if (p_sb->sb_info.sb_virt) {
1784                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1785                                        p_sb->sb_info.sb_virt,
1786                                        p_sb->sb_info.sb_phys,
1787                                        SB_ALIGNED_SIZE(p_hwfn));
1788         }
1789
1790         OSAL_FREE(p_hwfn->p_dev, p_sb);
1791 }
1792
1793 static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
1794                                                   struct ecore_ptt *p_ptt)
1795 {
1796         struct ecore_sb_sp_info *p_sb;
1797         dma_addr_t p_phys = 0;
1798         void *p_virt;
1799
1800         /* SB struct */
1801         p_sb =
1802             OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
1803                        sizeof(*p_sb));
1804         if (!p_sb) {
1805                 DP_NOTICE(p_hwfn, false, "Failed to allocate `struct ecore_sb_info'\n");
1806                 return ECORE_NOMEM;
1807         }
1808
1809         /* SB ring  */
1810         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1811                                          &p_phys, SB_ALIGNED_SIZE(p_hwfn));
1812         if (!p_virt) {
1813                 DP_NOTICE(p_hwfn, false, "Failed to allocate status block\n");
1814                 OSAL_FREE(p_hwfn->p_dev, p_sb);
1815                 return ECORE_NOMEM;
1816         }
1817
1818         /* Status Block setup */
1819         p_hwfn->p_sp_sb = p_sb;
1820         ecore_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info,
1821                           p_virt, p_phys, ECORE_SP_SB_ID);
1822
1823         OSAL_MEMSET(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1824
1825         return ECORE_SUCCESS;
1826 }
1827
1828 enum _ecore_status_t ecore_int_register_cb(struct ecore_hwfn *p_hwfn,
1829                                            ecore_int_comp_cb_t comp_cb,
1830                                            void *cookie,
1831                                            u8 *sb_idx, __le16 **p_fw_cons)
1832 {
1833         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1834         enum _ecore_status_t rc = ECORE_NOMEM;
1835         u8 pi;
1836
1837         /* Look for a free index */
1838         for (pi = 0; pi < OSAL_ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
1839                 if (p_sp_sb->pi_info_arr[pi].comp_cb != OSAL_NULL)
1840                         continue;
1841
1842                 p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1843                 p_sp_sb->pi_info_arr[pi].cookie = cookie;
1844                 *sb_idx = pi;
1845                 *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
1846                 rc = ECORE_SUCCESS;
1847                 break;
1848         }
1849
1850         return rc;
1851 }
1852
1853 enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi)
1854 {
1855         struct ecore_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1856
1857         if (p_sp_sb->pi_info_arr[pi].comp_cb == OSAL_NULL)
1858                 return ECORE_NOMEM;
1859
1860         p_sp_sb->pi_info_arr[pi].comp_cb = OSAL_NULL;
1861         p_sp_sb->pi_info_arr[pi].cookie = OSAL_NULL;
1862         return ECORE_SUCCESS;
1863 }
1864
1865 u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn)
1866 {
1867         return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1868 }
1869
1870 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
1871                               struct ecore_ptt *p_ptt,
1872                               enum ecore_int_mode int_mode)
1873 {
1874         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1875
1876 #ifndef ASIC_ONLY
1877         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1878                 DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
1879                 igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
1880         }
1881 #endif
1882
1883         p_hwfn->p_dev->int_mode = int_mode;
1884         switch (p_hwfn->p_dev->int_mode) {
1885         case ECORE_INT_MODE_INTA:
1886                 igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1887                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1888                 break;
1889
1890         case ECORE_INT_MODE_MSI:
1891                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1892                 igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1893                 break;
1894
1895         case ECORE_INT_MODE_MSIX:
1896                 igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1897                 break;
1898         case ECORE_INT_MODE_POLL:
1899                 break;
1900         }
1901
1902         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1903 }
1904
1905 static void ecore_int_igu_enable_attn(struct ecore_hwfn *p_hwfn,
1906                                       struct ecore_ptt *p_ptt)
1907 {
1908 #ifndef ASIC_ONLY
1909         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
1910                 DP_INFO(p_hwfn,
1911                         "FPGA - Don't enable Attentions in IGU and MISC\n");
1912                 return;
1913         }
1914 #endif
1915
1916         /* Configure AEU signal change to produce attentions */
1917         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1918         ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1919         ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
1920         ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1921
1922         /* Flush the writes to IGU */
1923         OSAL_MMIOWB(p_hwfn->p_dev);
1924
1925         /* Unmask AEU signals toward IGU */
1926         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1927 }
1928
1929 enum _ecore_status_t
1930 ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1931                           enum ecore_int_mode int_mode)
1932 {
1933         enum _ecore_status_t rc = ECORE_SUCCESS;
1934
1935         ecore_int_igu_enable_attn(p_hwfn, p_ptt);
1936
1937         if ((int_mode != ECORE_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
1938                 rc = OSAL_SLOWPATH_IRQ_REQ(p_hwfn);
1939                 if (rc != ECORE_SUCCESS) {
1940                         DP_NOTICE(p_hwfn, true,
1941                                   "Slowpath IRQ request failed\n");
1942                         return ECORE_NORESOURCES;
1943                 }
1944                 p_hwfn->b_int_requested = true;
1945         }
1946
1947         /* Enable interrupt Generation */
1948         ecore_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
1949
1950         p_hwfn->b_int_enabled = 1;
1951
1952         return rc;
1953 }
1954
1955 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
1956                                struct ecore_ptt *p_ptt)
1957 {
1958         p_hwfn->b_int_enabled = 0;
1959
1960         if (IS_VF(p_hwfn->p_dev))
1961                 return;
1962
1963         ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1964 }
1965
1966 #define IGU_CLEANUP_SLEEP_LENGTH                (1000)
1967 static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
1968                                      struct ecore_ptt *p_ptt,
1969                                      u32 igu_sb_id,
1970                                      bool cleanup_set,
1971                                      u16 opaque_fid)
1972 {
1973         u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1974         u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1975         u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1976         u8 type = 0;            /* FIXME MichalS type??? */
1977
1978         OSAL_BUILD_BUG_ON((IGU_REG_CLEANUP_STATUS_4 -
1979                            IGU_REG_CLEANUP_STATUS_0) != 0x200);
1980
1981         /* USE Control Command Register to perform cleanup. There is an
1982          * option to do this using IGU bar, but then it can't be used for VFs.
1983          */
1984
1985         /* Set the data field */
1986         SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1987         SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, type);
1988         SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1989
1990         /* Set the control register */
1991         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1992         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1993         SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1994
1995         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1996
1997         OSAL_BARRIER(p_hwfn->p_dev);
1998
1999         ecore_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
2000
2001         /* Flush the write to IGU */
2002         OSAL_MMIOWB(p_hwfn->p_dev);
2003
2004         /* calculate where to read the status bit from */
2005         sb_bit = 1 << (igu_sb_id % 32);
2006         sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
2007
2008         sb_bit_addr += IGU_REG_CLEANUP_STATUS_0 + (0x80 * type);
2009
2010         /* Now wait for the command to complete */
2011         while (--sleep_cnt) {
2012                 val = ecore_rd(p_hwfn, p_ptt, sb_bit_addr);
2013                 if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
2014                         break;
2015                 OSAL_MSLEEP(5);
2016         }
2017
2018         if (!sleep_cnt)
2019                 DP_NOTICE(p_hwfn, true,
2020                           "Timeout waiting for clear status 0x%08x [for sb %d]\n",
2021                           val, igu_sb_id);
2022 }
2023
2024 void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
2025                                        struct ecore_ptt *p_ptt,
2026                                        u16 igu_sb_id, u16 opaque, bool b_set)
2027 {
2028         struct ecore_igu_block *p_block;
2029         int pi, i;
2030
2031         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2032         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2033                    "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
2034                    igu_sb_id, p_block->function_id, p_block->is_pf,
2035                    p_block->vector_number);
2036
2037         /* Set */
2038         if (b_set)
2039                 ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
2040
2041         /* Clear */
2042         ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
2043
2044         /* Wait for the IGU SB to cleanup */
2045         for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
2046                 u32 val;
2047
2048                 val = ecore_rd(p_hwfn, p_ptt,
2049                                IGU_REG_WRITE_DONE_PENDING +
2050                                ((igu_sb_id / 32) * 4));
2051                 if (val & (1 << (igu_sb_id % 32)))
2052                         OSAL_UDELAY(10);
2053                 else
2054                         break;
2055         }
2056         if (i == IGU_CLEANUP_SLEEP_LENGTH)
2057                 DP_NOTICE(p_hwfn, true,
2058                           "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
2059                           igu_sb_id);
2060
2061         /* Clear the CAU for the SB */
2062         for (pi = 0; pi < 12; pi++)
2063                 ecore_wr(p_hwfn, p_ptt,
2064                          CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
2065 }
2066
2067 void ecore_int_igu_init_pure_rt(struct ecore_hwfn *p_hwfn,
2068                                 struct ecore_ptt *p_ptt,
2069                                 bool b_set, bool b_slowpath)
2070 {
2071         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2072         struct ecore_igu_block *p_block;
2073         u16 igu_sb_id = 0;
2074         u32 val = 0;
2075
2076         /* @@@TBD MichalK temporary... should be moved to init-tool... */
2077         val = ecore_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
2078         val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
2079         val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
2080         ecore_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2081         /* end temporary */
2082
2083         for (igu_sb_id = 0;
2084              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2085              igu_sb_id++) {
2086                 p_block = &p_info->entry[igu_sb_id];
2087
2088                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2089                     !p_block->is_pf ||
2090                     (p_block->status & ECORE_IGU_STATUS_DSB))
2091                         continue;
2092
2093                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
2094                                                   p_hwfn->hw_info.opaque_fid,
2095                                                   b_set);
2096         }
2097
2098         if (b_slowpath)
2099                 ecore_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
2100                                                   p_info->igu_dsb_id,
2101                                                   p_hwfn->hw_info.opaque_fid,
2102                                                   b_set);
2103 }
2104
2105 int ecore_int_igu_reset_cam(struct ecore_hwfn *p_hwfn,
2106                             struct ecore_ptt *p_ptt)
2107 {
2108         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2109         struct ecore_igu_block *p_block;
2110         int pf_sbs, vf_sbs;
2111         u16 igu_sb_id;
2112         u32 val, rval;
2113
2114         if (!RESC_NUM(p_hwfn, ECORE_SB)) {
2115                 /* We're using an old MFW - have to prevent any switching
2116                  * of SBs between PF and VFs as later driver wouldn't be
2117                  * able to tell which belongs to which.
2118                  */
2119                 p_info->b_allow_pf_vf_change = false;
2120         } else {
2121                 /* Use the numbers the MFW have provided -
2122                  * don't forget MFW accounts for the default SB as well.
2123                  */
2124                 p_info->b_allow_pf_vf_change = true;
2125
2126                 if (p_info->usage.cnt != RESC_NUM(p_hwfn, ECORE_SB) - 1) {
2127                         DP_INFO(p_hwfn,
2128                                 "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2129                                 RESC_NUM(p_hwfn, ECORE_SB) - 1,
2130                                 p_info->usage.cnt);
2131                         p_info->usage.cnt = RESC_NUM(p_hwfn, ECORE_SB) - 1;
2132                 }
2133
2134                 /* TODO - how do we learn about VF SBs from MFW? */
2135                 if (IS_PF_SRIOV(p_hwfn)) {
2136                         u16 vfs = p_hwfn->p_dev->p_iov_info->total_vfs;
2137
2138                         if (vfs != p_info->usage.iov_cnt)
2139                                 DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2140                                            "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2141                                            p_info->usage.iov_cnt, vfs);
2142
2143                         /* At this point we know how many SBs we have totally
2144                          * in IGU + number of PF SBs. So we can validate that
2145                          * we'd have sufficient for VF.
2146                          */
2147                         if (vfs > p_info->usage.free_cnt +
2148                                   p_info->usage.free_cnt_iov -
2149                                   p_info->usage.cnt) {
2150                                 DP_NOTICE(p_hwfn, true,
2151                                           "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2152                                           p_info->usage.free_cnt +
2153                                           p_info->usage.free_cnt_iov,
2154                                           p_info->usage.cnt, vfs);
2155                                 return ECORE_INVAL;
2156                         }
2157                 }
2158         }
2159
2160         /* Cap the number of VFs SBs by the number of VFs */
2161         if (IS_PF_SRIOV(p_hwfn))
2162                 p_info->usage.iov_cnt = p_hwfn->p_dev->p_iov_info->total_vfs;
2163
2164         /* Mark all SBs as free, now in the right PF/VFs division */
2165         p_info->usage.free_cnt = p_info->usage.cnt;
2166         p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2167         p_info->usage.orig = p_info->usage.cnt;
2168         p_info->usage.iov_orig = p_info->usage.iov_cnt;
2169
2170         /* We now proceed to re-configure the IGU cam to reflect the initial
2171          * configuration. We can start with the Default SB.
2172          */
2173         pf_sbs = p_info->usage.cnt;
2174         vf_sbs = p_info->usage.iov_cnt;
2175
2176         for (igu_sb_id = p_info->igu_dsb_id;
2177              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2178              igu_sb_id++) {
2179                 p_block = &p_info->entry[igu_sb_id];
2180                 val = 0;
2181
2182                 if (!(p_block->status & ECORE_IGU_STATUS_VALID))
2183                         continue;
2184
2185                 if (p_block->status & ECORE_IGU_STATUS_DSB) {
2186                         p_block->function_id = p_hwfn->rel_pf_id;
2187                         p_block->is_pf = 1;
2188                         p_block->vector_number = 0;
2189                         p_block->status = ECORE_IGU_STATUS_VALID |
2190                                           ECORE_IGU_STATUS_PF |
2191                                           ECORE_IGU_STATUS_DSB;
2192                 } else if (pf_sbs) {
2193                         pf_sbs--;
2194                         p_block->function_id = p_hwfn->rel_pf_id;
2195                         p_block->is_pf = 1;
2196                         p_block->vector_number = p_info->usage.cnt - pf_sbs;
2197                         p_block->status = ECORE_IGU_STATUS_VALID |
2198                                           ECORE_IGU_STATUS_PF |
2199                                           ECORE_IGU_STATUS_FREE;
2200                 } else if (vf_sbs) {
2201                         p_block->function_id =
2202                                 p_hwfn->p_dev->p_iov_info->first_vf_in_pf +
2203                                 p_info->usage.iov_cnt - vf_sbs;
2204                         p_block->is_pf = 0;
2205                         p_block->vector_number = 0;
2206                         p_block->status = ECORE_IGU_STATUS_VALID |
2207                                           ECORE_IGU_STATUS_FREE;
2208                         vf_sbs--;
2209                 } else {
2210                         p_block->function_id = 0;
2211                         p_block->is_pf = 0;
2212                         p_block->vector_number = 0;
2213                 }
2214
2215                 SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2216                           p_block->function_id);
2217                 SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2218                 SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2219                           p_block->vector_number);
2220
2221                 /* VF entries would be enabled when VF is initializaed */
2222                 SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2223
2224                 rval = ecore_rd(p_hwfn, p_ptt,
2225                                 IGU_REG_MAPPING_MEMORY +
2226                                 sizeof(u32) * igu_sb_id);
2227
2228                 if (rval != val) {
2229                         ecore_wr(p_hwfn, p_ptt,
2230                                  IGU_REG_MAPPING_MEMORY +
2231                                  sizeof(u32) * igu_sb_id,
2232                                  val);
2233
2234                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2235                                    "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2236                                    igu_sb_id, p_block->function_id,
2237                                    p_block->is_pf, p_block->vector_number,
2238                                    rval, val);
2239                 }
2240         }
2241
2242         return 0;
2243 }
2244
2245 int ecore_int_igu_reset_cam_default(struct ecore_hwfn *p_hwfn,
2246                                     struct ecore_ptt *p_ptt)
2247 {
2248         struct ecore_sb_cnt_info *p_cnt = &p_hwfn->hw_info.p_igu_info->usage;
2249
2250         /* Return all the usage indications to default prior to the reset;
2251          * The reset expects the !orig to reflect the initial status of the
2252          * SBs, and would re-calculate the originals based on those.
2253          */
2254         p_cnt->cnt = p_cnt->orig;
2255         p_cnt->free_cnt = p_cnt->orig;
2256         p_cnt->iov_cnt = p_cnt->iov_orig;
2257         p_cnt->free_cnt_iov = p_cnt->iov_orig;
2258         p_cnt->orig = 0;
2259         p_cnt->iov_orig = 0;
2260
2261         /* TODO - we probably need to re-configure the CAU as well... */
2262         return ecore_int_igu_reset_cam(p_hwfn, p_ptt);
2263 }
2264
2265 static void ecore_int_igu_read_cam_block(struct ecore_hwfn *p_hwfn,
2266                                          struct ecore_ptt *p_ptt,
2267                                          u16 igu_sb_id)
2268 {
2269         u32 val = ecore_rd(p_hwfn, p_ptt,
2270                            IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2271         struct ecore_igu_block *p_block;
2272
2273         p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
2274
2275         /* Fill the block information */
2276         p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
2277         p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2278         p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
2279
2280         p_block->igu_sb_id = igu_sb_id;
2281 }
2282
2283 enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
2284                                             struct ecore_ptt *p_ptt)
2285 {
2286         struct ecore_igu_info *p_igu_info;
2287         struct ecore_igu_block *p_block;
2288         u32 min_vf = 0, max_vf = 0;
2289         u16 igu_sb_id;
2290
2291         p_hwfn->hw_info.p_igu_info = OSAL_ZALLOC(p_hwfn->p_dev,
2292                                                  GFP_KERNEL,
2293                                                  sizeof(*p_igu_info));
2294         if (!p_hwfn->hw_info.p_igu_info)
2295                 return ECORE_NOMEM;
2296         p_igu_info = p_hwfn->hw_info.p_igu_info;
2297
2298         /* Distinguish between existent and onn-existent default SB */
2299         p_igu_info->igu_dsb_id = ECORE_SB_INVALID_IDX;
2300
2301         /* Find the range of VF ids whose SB belong to this PF */
2302         if (p_hwfn->p_dev->p_iov_info) {
2303                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
2304
2305                 min_vf = p_iov->first_vf_in_pf;
2306                 max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
2307         }
2308
2309         for (igu_sb_id = 0;
2310              igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2311              igu_sb_id++) {
2312                 /* Read current entry; Notice it might not belong to this PF */
2313                 ecore_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2314                 p_block = &p_igu_info->entry[igu_sb_id];
2315
2316                 if ((p_block->is_pf) &&
2317                     (p_block->function_id == p_hwfn->rel_pf_id)) {
2318                         p_block->status = ECORE_IGU_STATUS_PF |
2319                                           ECORE_IGU_STATUS_VALID |
2320                                           ECORE_IGU_STATUS_FREE;
2321
2322                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2323                                 p_igu_info->usage.cnt++;
2324                 } else if (!(p_block->is_pf) &&
2325                            (p_block->function_id >= min_vf) &&
2326                            (p_block->function_id < max_vf)) {
2327                         /* Available for VFs of this PF */
2328                         p_block->status = ECORE_IGU_STATUS_VALID |
2329                                           ECORE_IGU_STATUS_FREE;
2330
2331                         if (p_igu_info->igu_dsb_id != ECORE_SB_INVALID_IDX)
2332                                 p_igu_info->usage.iov_cnt++;
2333                 }
2334
2335                 /* Mark the First entry belonging to the PF or its VFs
2336                  * as the default SB [we'll reset IGU prior to first usage].
2337                  */
2338                 if ((p_block->status & ECORE_IGU_STATUS_VALID) &&
2339                     (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX)) {
2340                         p_igu_info->igu_dsb_id = igu_sb_id;
2341                         p_block->status |= ECORE_IGU_STATUS_DSB;
2342                 }
2343
2344                 /* While this isn't suitable for all clients, limit number
2345                  * of prints by having each PF print only its entries with the
2346                  * exception of PF0 which would print everything.
2347                  */
2348                 if ((p_block->status & ECORE_IGU_STATUS_VALID) ||
2349                     (p_hwfn->abs_pf_id == 0))
2350                         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2351                                    "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2352                                    igu_sb_id, p_block->function_id,
2353                                    p_block->is_pf, p_block->vector_number);
2354         }
2355
2356         if (p_igu_info->igu_dsb_id == ECORE_SB_INVALID_IDX) {
2357                 DP_NOTICE(p_hwfn, true,
2358                           "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2359                           p_igu_info->igu_dsb_id);
2360                 return ECORE_INVAL;
2361         }
2362
2363         /* All non default SB are considered free at this point */
2364         p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2365         p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2366
2367         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2368                    "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2369                    p_igu_info->igu_dsb_id, p_igu_info->usage.cnt,
2370                    p_igu_info->usage.iov_cnt);
2371
2372         return ECORE_SUCCESS;
2373 }
2374
2375 enum _ecore_status_t
2376 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2377                           u16 sb_id, bool b_to_vf)
2378 {
2379         struct ecore_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2380         struct ecore_igu_block *p_block = OSAL_NULL;
2381         u16 igu_sb_id = 0, vf_num = 0;
2382         u32 val = 0;
2383
2384         if (IS_VF(p_hwfn->p_dev) || !IS_PF_SRIOV(p_hwfn))
2385                 return ECORE_INVAL;
2386
2387         if (sb_id == ECORE_SP_SB_ID)
2388                 return ECORE_INVAL;
2389
2390         if (!p_info->b_allow_pf_vf_change) {
2391                 DP_INFO(p_hwfn, "Can't relocate SBs as MFW is too old.\n");
2392                 return ECORE_INVAL;
2393         }
2394
2395         /* If we're moving a SB from PF to VF, the client had to specify
2396          * which vector it wants to move.
2397          */
2398         if (b_to_vf) {
2399                 igu_sb_id = ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
2400                 if (igu_sb_id == ECORE_SB_INVALID_IDX)
2401                         return ECORE_INVAL;
2402         }
2403
2404         /* If we're moving a SB from VF to PF, need to validate there isn't
2405          * already a line configured for that vector.
2406          */
2407         if (!b_to_vf) {
2408                 if (ecore_get_pf_igu_sb_id(p_hwfn, sb_id + 1) !=
2409                     ECORE_SB_INVALID_IDX)
2410                         return ECORE_INVAL;
2411         }
2412
2413         /* We need to validate that the SB can actually be relocated.
2414          * This would also handle the previous case where we've explicitly
2415          * stated which IGU SB needs to move.
2416          */
2417         for (; igu_sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
2418              igu_sb_id++) {
2419                 p_block = &p_info->entry[igu_sb_id];
2420
2421                 if (!(p_block->status & ECORE_IGU_STATUS_VALID) ||
2422                     !(p_block->status & ECORE_IGU_STATUS_FREE) ||
2423                     (!!(p_block->status & ECORE_IGU_STATUS_PF) != b_to_vf)) {
2424                         if (b_to_vf)
2425                                 return ECORE_INVAL;
2426                         else
2427                                 continue;
2428                 }
2429
2430                 break;
2431         }
2432
2433         if (igu_sb_id == ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev)) {
2434                 DP_VERBOSE(p_hwfn, (ECORE_MSG_INTR | ECORE_MSG_IOV),
2435                            "Failed to find a free SB to move\n");
2436                 return ECORE_INVAL;
2437         }
2438
2439         /* At this point, p_block points to the SB we want to relocate */
2440         if (b_to_vf) {
2441                 p_block->status &= ~ECORE_IGU_STATUS_PF;
2442
2443                 /* It doesn't matter which VF number we choose, since we're
2444                  * going to disable the line; But let's keep it in range.
2445                  */
2446                 vf_num = (u16)p_hwfn->p_dev->p_iov_info->first_vf_in_pf;
2447
2448                 p_block->function_id = (u8)vf_num;
2449                 p_block->is_pf = 0;
2450                 p_block->vector_number = 0;
2451
2452                 p_info->usage.cnt--;
2453                 p_info->usage.free_cnt--;
2454                 p_info->usage.iov_cnt++;
2455                 p_info->usage.free_cnt_iov++;
2456
2457                 /* TODO - if SBs aren't really the limiting factor,
2458                  * then it might not be accurate [in the since that
2459                  * we might not need decrement the feature].
2460                  */
2461                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]--;
2462                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]++;
2463         } else {
2464                 p_block->status |= ECORE_IGU_STATUS_PF;
2465                 p_block->function_id = p_hwfn->rel_pf_id;
2466                 p_block->is_pf = 1;
2467                 p_block->vector_number = sb_id + 1;
2468
2469                 p_info->usage.cnt++;
2470                 p_info->usage.free_cnt++;
2471                 p_info->usage.iov_cnt--;
2472                 p_info->usage.free_cnt_iov--;
2473
2474                 p_hwfn->hw_info.feat_num[ECORE_PF_L2_QUE]++;
2475                 p_hwfn->hw_info.feat_num[ECORE_VF_L2_QUE]--;
2476         }
2477
2478         /* Update the IGU and CAU with the new configuration */
2479         SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2480                   p_block->function_id);
2481         SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2482         SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2483         SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2484                   p_block->vector_number);
2485
2486         ecore_wr(p_hwfn, p_ptt,
2487                  IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id,
2488                  val);
2489
2490         ecore_int_cau_conf_sb(p_hwfn, p_ptt, 0,
2491                               igu_sb_id, vf_num,
2492                               p_block->is_pf ? 0 : 1);
2493
2494         DP_VERBOSE(p_hwfn, ECORE_MSG_INTR,
2495                    "Relocation: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2496                    igu_sb_id, p_block->function_id,
2497                    p_block->is_pf, p_block->vector_number);
2498
2499         return ECORE_SUCCESS;
2500 }
2501
2502 /**
2503  * @brief Initialize igu runtime registers
2504  *
2505  * @param p_hwfn
2506  */
2507 void ecore_int_igu_init_rt(struct ecore_hwfn *p_hwfn)
2508 {
2509         u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2510
2511         STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2512 }
2513
2514 #define LSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - \
2515                           IGU_CMD_INT_ACK_BASE)
2516 #define MSB_IGU_CMD_ADDR (IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - \
2517                           IGU_CMD_INT_ACK_BASE)
2518 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn)
2519 {
2520         u32 intr_status_hi = 0, intr_status_lo = 0;
2521         u64 intr_status = 0;
2522
2523         intr_status_lo = REG_RD(p_hwfn,
2524                                 GTT_BAR0_MAP_REG_IGU_CMD +
2525                                 LSB_IGU_CMD_ADDR * 8);
2526         intr_status_hi = REG_RD(p_hwfn,
2527                                 GTT_BAR0_MAP_REG_IGU_CMD +
2528                                 MSB_IGU_CMD_ADDR * 8);
2529         intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2530
2531         return intr_status;
2532 }
2533
2534 static void ecore_int_sp_dpc_setup(struct ecore_hwfn *p_hwfn)
2535 {
2536         OSAL_DPC_INIT(p_hwfn->sp_dpc, p_hwfn);
2537         p_hwfn->b_sp_dpc_enabled = true;
2538 }
2539
2540 static enum _ecore_status_t ecore_int_sp_dpc_alloc(struct ecore_hwfn *p_hwfn)
2541 {
2542         p_hwfn->sp_dpc = OSAL_DPC_ALLOC(p_hwfn);
2543         if (!p_hwfn->sp_dpc)
2544                 return ECORE_NOMEM;
2545
2546         return ECORE_SUCCESS;
2547 }
2548
2549 static void ecore_int_sp_dpc_free(struct ecore_hwfn *p_hwfn)
2550 {
2551         OSAL_FREE(p_hwfn->p_dev, p_hwfn->sp_dpc);
2552 }
2553
2554 enum _ecore_status_t ecore_int_alloc(struct ecore_hwfn *p_hwfn,
2555                                      struct ecore_ptt *p_ptt)
2556 {
2557         enum _ecore_status_t rc = ECORE_SUCCESS;
2558
2559         rc = ecore_int_sp_dpc_alloc(p_hwfn);
2560         if (rc != ECORE_SUCCESS) {
2561                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp dpc mem\n");
2562                 return rc;
2563         }
2564
2565         rc = ecore_int_sp_sb_alloc(p_hwfn, p_ptt);
2566         if (rc != ECORE_SUCCESS) {
2567                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sp sb mem\n");
2568                 return rc;
2569         }
2570
2571         rc = ecore_int_sb_attn_alloc(p_hwfn, p_ptt);
2572         if (rc != ECORE_SUCCESS)
2573                 DP_ERR(p_hwfn->p_dev, "Failed to allocate sb attn mem\n");
2574
2575         return rc;
2576 }
2577
2578 void ecore_int_free(struct ecore_hwfn *p_hwfn)
2579 {
2580         ecore_int_sp_sb_free(p_hwfn);
2581         ecore_int_sb_attn_free(p_hwfn);
2582         ecore_int_sp_dpc_free(p_hwfn);
2583 }
2584
2585 void ecore_int_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
2586 {
2587         if (!p_hwfn || !p_hwfn->p_sp_sb || !p_hwfn->p_sb_attn)
2588                 return;
2589
2590         ecore_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
2591         ecore_int_sb_attn_setup(p_hwfn, p_ptt);
2592         ecore_int_sp_dpc_setup(p_hwfn);
2593 }
2594
2595 void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
2596                            struct ecore_sb_cnt_info *p_sb_cnt_info)
2597 {
2598         struct ecore_igu_info *p_igu_info = p_hwfn->hw_info.p_igu_info;
2599
2600         if (!p_igu_info || !p_sb_cnt_info)
2601                 return;
2602
2603         OSAL_MEMCPY(p_sb_cnt_info, &p_igu_info->usage,
2604                     sizeof(*p_sb_cnt_info));
2605 }
2606
2607 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
2608 {
2609         int i;
2610
2611         for_each_hwfn(p_dev, i)
2612                 p_dev->hwfns[i].b_int_requested = false;
2613 }
2614
2615 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
2616 {
2617         p_dev->attn_clr_en = clr_enable;
2618 }
2619
2620 enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
2621                                              struct ecore_ptt *p_ptt,
2622                                              u8 timer_res, u16 sb_id, bool tx)
2623 {
2624         struct cau_sb_entry sb_entry;
2625         enum _ecore_status_t rc;
2626
2627         if (!p_hwfn->hw_init_done) {
2628                 DP_ERR(p_hwfn, "hardware not initialized yet\n");
2629                 return ECORE_INVAL;
2630         }
2631
2632         rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2633                                  sb_id * sizeof(u64),
2634                                  (u64)(osal_uintptr_t)&sb_entry, 2, 0);
2635         if (rc != ECORE_SUCCESS) {
2636                 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2637                 return rc;
2638         }
2639
2640         if (tx)
2641                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2642         else
2643                 SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
2644
2645         rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
2646                                  (u64)(osal_uintptr_t)&sb_entry,
2647                                  CAU_REG_SB_VAR_MEMORY +
2648                                  sb_id * sizeof(u64), 2, 0);
2649         if (rc != ECORE_SUCCESS) {
2650                 DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2651                 return rc;
2652         }
2653
2654         return rc;
2655 }
2656
2657 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
2658                                           struct ecore_ptt *p_ptt,
2659                                           struct ecore_sb_info *p_sb,
2660                                           struct ecore_sb_info_dbg *p_info)
2661 {
2662         u16 sbid = p_sb->igu_sb_id;
2663         int i;
2664
2665         if (IS_VF(p_hwfn->p_dev))
2666                 return ECORE_INVAL;
2667
2668         if (sbid > NUM_OF_SBS(p_hwfn->p_dev))
2669                 return ECORE_INVAL;
2670
2671         p_info->igu_prod = ecore_rd(p_hwfn, p_ptt,
2672                                     IGU_REG_PRODUCER_MEMORY + sbid * 4);
2673         p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
2674                                     IGU_REG_CONSUMER_MEM + sbid * 4);
2675
2676         for (i = 0; i < PIS_PER_SB_E4; i++)
2677                 p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
2678                                               CAU_REG_PI_MEMORY +
2679                                               sbid * 4 * PIS_PER_SB_E4 +
2680                                               i * 4);
2681
2682         return ECORE_SUCCESS;
2683 }