drivers/net/qede/base/ecore_l2.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10
  11 #include "ecore.h"
  12 #include "ecore_status.h"
  13 #include "ecore_hsi_eth.h"
  14 #include "ecore_chain.h"
  15 #include "ecore_spq.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_cxt.h"
  18 #include "ecore_l2.h"
  19 #include "ecore_sp_commands.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "reg_addr.h"
  23 #include "ecore_int.h"
  24 #include "ecore_hw.h"
  25 #include "ecore_vf.h"
  26 #include "ecore_sriov.h"
  27 #include "ecore_mcp.h"
  28
  29 #define ECORE_MAX_SGES_NUM 16
  30 #define CRC32_POLY 0x1edc6f41
  31
  32 enum _ecore_status_t
  33 ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
  34                          struct ecore_sp_vport_start_params *p_params)
  35 {
  36         struct vport_start_ramrod_data *p_ramrod = OSAL_NULL;
  37         struct ecore_spq_entry *p_ent = OSAL_NULL;
  38         struct ecore_sp_init_data init_data;
  39         u8 abs_vport_id = 0;
  40         enum _ecore_status_t rc = ECORE_NOTIMPL;
  41         u16 rx_mode = 0;
  42
  43         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
  44         if (rc != ECORE_SUCCESS)
  45                 return rc;
  46
  47         /* Get SPQ entry */
  48         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
  49         init_data.cid = ecore_spq_get_cid(p_hwfn);
  50         init_data.opaque_fid = p_params->opaque_fid;
  51         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
  52
  53         rc = ecore_sp_init_request(p_hwfn, &p_ent,
  54                                    ETH_RAMROD_VPORT_START,
  55                                    PROTOCOLID_ETH, &init_data);
  56         if (rc != ECORE_SUCCESS)
  57                 return rc;
  58
  59         p_ramrod = &p_ent->ramrod.vport_start;
  60         p_ramrod->vport_id = abs_vport_id;
  61
  62         p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu);
  63         p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan;
  64         p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts;
  65         p_ramrod->drop_ttl0_en = p_params->drop_ttl0;
  66         p_ramrod->untagged = p_params->only_untagged;
  67         p_ramrod->zero_placement_offset = p_params->zero_placement_offset;
  68
  69         SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1);
  70         SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1);
  71
  72         p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode);
  73
  74         /* TPA related fields */
  75         OSAL_MEMSET(&p_ramrod->tpa_param, 0,
  76                     sizeof(struct eth_vport_tpa_param));
  77         p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
  78
  79         switch (p_params->tpa_mode) {
  80         case ECORE_TPA_MODE_GRO:
  81                 p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
  82                 p_ramrod->tpa_param.tpa_max_size = (u16)-1;
  83                 p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
  84                 p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
  85                 p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
  86                 p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
  87                 p_ramrod->tpa_param.tpa_ipv4_tunn_en_flg = 1;
  88                 p_ramrod->tpa_param.tpa_ipv6_tunn_en_flg = 1;
  89                 p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
  90                 p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
  91                 break;
  92         default:
  93                 break;
  94         }
  95
  96         p_ramrod->tx_switching_en = p_params->tx_switching;
  97 #ifndef ASIC_ONLY
  98         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
  99                 p_ramrod->tx_switching_en = 0;
 100 #endif
 101
 102         p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
 103         p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
 104
 105         /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
 106         p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
 107                                                     p_params->concrete_fid);
 108
 109         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 110 }
 111
 112 enum _ecore_status_t
 113 ecore_sp_vport_start(struct ecore_hwfn *p_hwfn,
 114                      struct ecore_sp_vport_start_params *p_params)
 115 {
 116         if (IS_VF(p_hwfn->p_dev))
 117                 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id,
 118                                                p_params->mtu,
 119                                                p_params->remove_inner_vlan,
 120                                                p_params->tpa_mode,
 121                                                p_params->max_buffers_per_cqe,
 122                                                p_params->only_untagged);
 123
 124         return ecore_sp_eth_vport_start(p_hwfn, p_params);
 125 }
 126
 127 static enum _ecore_status_t
 128 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
 129                           struct vport_update_ramrod_data *p_ramrod,
 130                           struct ecore_rss_params *p_rss)
 131 {
 132         enum _ecore_status_t rc = ECORE_SUCCESS;
 133         struct eth_vport_rss_config *p_config;
 134         u16 abs_l2_queue = 0;
 135         int i;
 136
 137         if (!p_rss) {
 138                 p_ramrod->common.update_rss_flg = 0;
 139                 return rc;
 140         }
 141         p_config = &p_ramrod->rss_config;
 142
 143         OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE !=
 144                           ETH_RSS_IND_TABLE_ENTRIES_NUM);
 145
 146         rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, &p_config->rss_id);
 147         if (rc != ECORE_SUCCESS)
 148                 return rc;
 149
 150         p_ramrod->common.update_rss_flg = p_rss->update_rss_config;
 151         p_config->update_rss_capabilities = p_rss->update_rss_capabilities;
 152         p_config->update_rss_ind_table = p_rss->update_rss_ind_table;
 153         p_config->update_rss_key = p_rss->update_rss_key;
 154
 155         p_config->rss_mode = p_rss->rss_enable ?
 156             ETH_VPORT_RSS_MODE_REGULAR : ETH_VPORT_RSS_MODE_DISABLED;
 157
 158         p_config->capabilities = 0;
 159
 160         SET_FIELD(p_config->capabilities,
 161                   ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY,
 162                   !!(p_rss->rss_caps & ECORE_RSS_IPV4));
 163         SET_FIELD(p_config->capabilities,
 164                   ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY,
 165                   !!(p_rss->rss_caps & ECORE_RSS_IPV6));
 166         SET_FIELD(p_config->capabilities,
 167                   ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY,
 168                   !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP));
 169         SET_FIELD(p_config->capabilities,
 170                   ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY,
 171                   !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP));
 172         SET_FIELD(p_config->capabilities,
 173                   ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY,
 174                   !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP));
 175         SET_FIELD(p_config->capabilities,
 176                   ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY,
 177                   !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP));
 178         p_config->tbl_size = p_rss->rss_table_size_log;
 179         p_config->capabilities = OSAL_CPU_TO_LE16(p_config->capabilities);
 180
 181         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
 182                    "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n",
 183                    p_ramrod->common.update_rss_flg,
 184                    p_config->rss_mode,
 185                    p_config->update_rss_capabilities,
 186                    p_config->capabilities,
 187                    p_config->update_rss_ind_table, p_config->update_rss_key);
 188
 189         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 190                 rc = ecore_fw_l2_queue(p_hwfn,
 191                                        (u8)p_rss->rss_ind_table[i],
 192                                        &abs_l2_queue);
 193                 if (rc != ECORE_SUCCESS)
 194                         return rc;
 195
 196                 p_config->indirection_table[i] = OSAL_CPU_TO_LE16(abs_l2_queue);
 197                 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, "i= %d, queue = %d\n",
 198                            i, p_config->indirection_table[i]);
 199         }
 200
 201         for (i = 0; i < 10; i++)
 202                 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]);
 203
 204         return rc;
 205 }
 206
 207 static void
 208 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
 209                             struct vport_update_ramrod_data *p_ramrod,
 210                             struct ecore_filter_accept_flags accept_flags)
 211 {
 212         p_ramrod->common.update_rx_mode_flg =
 213                                         accept_flags.update_rx_mode_config;
 214         p_ramrod->common.update_tx_mode_flg =
 215                                         accept_flags.update_tx_mode_config;
 216
 217 #ifndef ASIC_ONLY
 218         /* On B0 emulation we cannot enable Tx, since this would cause writes
 219          * to PVFC HW block which isn't implemented in emulation.
 220          */
 221         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
 222                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 223                            "Non-Asic - prevent Tx mode in vport update\n");
 224                 p_ramrod->common.update_tx_mode_flg = 0;
 225         }
 226 #endif
 227
 228         /* Set Rx mode accept flags */
 229         if (p_ramrod->common.update_rx_mode_flg) {
 230                 u8 accept_filter = accept_flags.rx_accept_filter;
 231                 u16 state = 0;
 232
 233                 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
 234                           !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
 235                            !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
 236
 237                 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
 238                           !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
 239
 240                 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
 241                           !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
 242                             !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 243
 244                 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
 245                           (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
 246                            !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 247
 248                 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
 249                           !!(accept_filter & ECORE_ACCEPT_BCAST));
 250
 251                 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
 252                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 253                            "p_ramrod->rx_mode.state = 0x%x\n",
 254                            state);
 255         }
 256
 257         /* Set Tx mode accept flags */
 258         if (p_ramrod->common.update_tx_mode_flg) {
 259                 u8 accept_filter = accept_flags.tx_accept_filter;
 260                 u16 state = 0;
 261
 262                 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
 263                           !!(accept_filter & ECORE_ACCEPT_NONE));
 264
 265                 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
 266                           !!(accept_filter & ECORE_ACCEPT_NONE));
 267
 268                 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
 269                           (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
 270                            !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
 271
 272                 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
 273                           !!(accept_filter & ECORE_ACCEPT_BCAST));
 274
 275                 p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state);
 276                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 277                            "p_ramrod->tx_mode.state = 0x%x\n",
 278                            state);
 279         }
 280 }
 281
 282 static void
 283 ecore_sp_vport_update_sge_tpa(struct ecore_hwfn *p_hwfn,
 284                               struct vport_update_ramrod_data *p_ramrod,
 285                               struct ecore_sge_tpa_params *p_params)
 286 {
 287         struct eth_vport_tpa_param *p_tpa;
 288
 289         if (!p_params) {
 290                 p_ramrod->common.update_tpa_param_flg = 0;
 291                 p_ramrod->common.update_tpa_en_flg = 0;
 292                 p_ramrod->common.update_tpa_param_flg = 0;
 293                 return;
 294         }
 295
 296         p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
 297         p_tpa = &p_ramrod->tpa_param;
 298         p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
 299         p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
 300         p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
 301         p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
 302
 303         p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
 304         p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
 305         p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
 306         p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
 307         p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
 308         p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
 309         p_tpa->tpa_max_size = p_params->tpa_max_size;
 310         p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
 311         p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
 312 }
 313
 314 static void
 315 ecore_sp_update_mcast_bin(struct ecore_hwfn *p_hwfn,
 316                           struct vport_update_ramrod_data *p_ramrod,
 317                           struct ecore_sp_vport_update_params *p_params)
 318 {
 319         int i;
 320
 321         OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0,
 322                     sizeof(p_ramrod->approx_mcast.bins));
 323
 324         if (!p_params->update_approx_mcast_flg)
 325                 return;
 326
 327         p_ramrod->common.update_approx_mcast_flg = 1;
 328         for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
 329                 u32 *p_bins = (u32 *)p_params->bins;
 330
 331                 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
 332         }
 333 }
 334
 335 enum _ecore_status_t
 336 ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
 337                       struct ecore_sp_vport_update_params *p_params,
 338                       enum spq_mode comp_mode,
 339                       struct ecore_spq_comp_cb *p_comp_data)
 340 {
 341         struct ecore_rss_params *p_rss_params = p_params->rss_params;
 342         struct vport_update_ramrod_data_cmn *p_cmn;
 343         struct ecore_sp_init_data init_data;
 344         struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
 345         struct ecore_spq_entry *p_ent = OSAL_NULL;
 346         u8 abs_vport_id = 0, val;
 347         enum _ecore_status_t rc = ECORE_NOTIMPL;
 348
 349         if (IS_VF(p_hwfn->p_dev)) {
 350                 rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
 351                 return rc;
 352         }
 353
 354         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
 355         if (rc != ECORE_SUCCESS)
 356                 return rc;
 357
 358         /* Get SPQ entry */
 359         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 360         init_data.cid = ecore_spq_get_cid(p_hwfn);
 361         init_data.opaque_fid = p_params->opaque_fid;
 362         init_data.comp_mode = comp_mode;
 363         init_data.p_comp_data = p_comp_data;
 364
 365         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 366                                    ETH_RAMROD_VPORT_UPDATE,
 367                                    PROTOCOLID_ETH, &init_data);
 368         if (rc != ECORE_SUCCESS)
 369                 return rc;
 370
 371         /* Copy input params to ramrod according to FW struct */
 372         p_ramrod = &p_ent->ramrod.vport_update;
 373         p_cmn = &p_ramrod->common;
 374
 375         p_cmn->vport_id = abs_vport_id;
 376
 377         p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
 378         p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
 379         p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
 380         p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
 381
 382         p_cmn->accept_any_vlan = p_params->accept_any_vlan;
 383         val = p_params->update_accept_any_vlan_flg;
 384         p_cmn->update_accept_any_vlan_flg = val;
 385
 386         p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
 387         val = p_params->update_inner_vlan_removal_flg;
 388         p_cmn->update_inner_vlan_removal_en_flg = val;
 389
 390         p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
 391         val = p_params->update_default_vlan_enable_flg;
 392         p_cmn->update_default_vlan_en_flg = val;
 393
 394         p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan);
 395         p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
 396
 397         p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
 398
 399         p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
 400
 401 #ifndef ASIC_ONLY
 402         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 403                 if (p_ramrod->common.tx_switching_en ||
 404                     p_ramrod->common.update_tx_switching_en_flg) {
 405                         DP_NOTICE(p_hwfn, false,
 406                                   "FPGA - why are we seeing tx-switching? Overriding it\n");
 407                         p_ramrod->common.tx_switching_en = 0;
 408                         p_ramrod->common.update_tx_switching_en_flg = 1;
 409                 }
 410 #endif
 411         p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
 412
 413         p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
 414         val = p_params->update_anti_spoofing_en_flg;
 415         p_ramrod->common.update_anti_spoofing_en_flg = val;
 416
 417         rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
 418         if (rc != ECORE_SUCCESS) {
 419                 /* Return spq entry which is taken in ecore_sp_init_request()*/
 420                 ecore_spq_return_entry(p_hwfn, p_ent);
 421                 return rc;
 422         }
 423
 424         /* Update mcast bins for VFs, PF doesn't use this functionality */
 425         ecore_sp_update_mcast_bin(p_hwfn, p_ramrod, p_params);
 426
 427         ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags);
 428         ecore_sp_vport_update_sge_tpa(p_hwfn, p_ramrod,
 429                                       p_params->sge_tpa_params);
 430         if (p_params->mtu) {
 431                 p_ramrod->common.update_mtu_flg = 1;
 432                 p_ramrod->common.mtu = OSAL_CPU_TO_LE16(p_params->mtu);
 433         }
 434
 435         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 436 }
 437
 438 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn,
 439                                          u16 opaque_fid, u8 vport_id)
 440 {
 441         struct vport_stop_ramrod_data *p_ramrod;
 442         struct ecore_sp_init_data init_data;
 443         struct ecore_spq_entry *p_ent;
 444         u8 abs_vport_id = 0;
 445         enum _ecore_status_t rc;
 446
 447         if (IS_VF(p_hwfn->p_dev))
 448                 return ecore_vf_pf_vport_stop(p_hwfn);
 449
 450         rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
 451         if (rc != ECORE_SUCCESS)
 452                 return rc;
 453
 454         /* Get SPQ entry */
 455         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 456         init_data.cid = ecore_spq_get_cid(p_hwfn);
 457         init_data.opaque_fid = opaque_fid;
 458         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 459
 460         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 461                                    ETH_RAMROD_VPORT_STOP,
 462                                    PROTOCOLID_ETH, &init_data);
 463         if (rc != ECORE_SUCCESS)
 464                 return rc;
 465
 466         p_ramrod = &p_ent->ramrod.vport_stop;
 467         p_ramrod->vport_id = abs_vport_id;
 468
 469         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 470 }
 471
 472 static enum _ecore_status_t
 473 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn,
 474                          struct ecore_filter_accept_flags *p_accept_flags)
 475 {
 476         struct ecore_sp_vport_update_params s_params;
 477
 478         OSAL_MEMSET(&s_params, 0, sizeof(s_params));
 479         OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags,
 480                     sizeof(struct ecore_filter_accept_flags));
 481
 482         return ecore_vf_pf_vport_update(p_hwfn, &s_params);
 483 }
 484
 485 enum _ecore_status_t
 486 ecore_filter_accept_cmd(struct ecore_dev *p_dev,
 487                         u8 vport,
 488                         struct ecore_filter_accept_flags accept_flags,
 489                         u8 update_accept_any_vlan,
 490                         u8 accept_any_vlan,
 491                         enum spq_mode comp_mode,
 492                         struct ecore_spq_comp_cb *p_comp_data)
 493 {
 494         struct ecore_sp_vport_update_params vport_update_params;
 495         int i, rc;
 496
 497         /* Prepare and send the vport rx_mode change */
 498         OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params));
 499         vport_update_params.vport_id = vport;
 500         vport_update_params.accept_flags = accept_flags;
 501         vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
 502         vport_update_params.accept_any_vlan = accept_any_vlan;
 503
 504         for_each_hwfn(p_dev, i) {
 505                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
 506
 507                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 508
 509                 if (IS_VF(p_dev)) {
 510                         rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
 511                         if (rc != ECORE_SUCCESS)
 512                                 return rc;
 513                         continue;
 514                 }
 515
 516                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
 517                                            comp_mode, p_comp_data);
 518                 if (rc != ECORE_SUCCESS) {
 519                         DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
 520                         return rc;
 521                 }
 522
 523                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 524                            "Accept filter configured, flags = [Rx]%x [Tx]%x\n",
 525                            accept_flags.rx_accept_filter,
 526                            accept_flags.tx_accept_filter);
 527
 528                 if (update_accept_any_vlan)
 529                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 530                                    "accept_any_vlan=%d configured\n",
 531                                    accept_any_vlan);
 532         }
 533
 534         return 0;
 535 }
 536
 537 static void ecore_sp_release_queue_cid(struct ecore_hwfn *p_hwfn,
 538                                        struct ecore_hw_cid_data *p_cid_data)
 539 {
 540         if (!p_cid_data->b_cid_allocated)
 541                 return;
 542
 543         ecore_cxt_release_cid(p_hwfn, p_cid_data->cid);
 544         p_cid_data->b_cid_allocated = false;
 545 }
 546
 547 enum _ecore_status_t
 548 ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
 549                               u16 opaque_fid,
 550                               u32 cid,
 551                               struct ecore_queue_start_common_params *p_params,
 552                               u16 bd_max_bytes,
 553                               dma_addr_t bd_chain_phys_addr,
 554                               dma_addr_t cqe_pbl_addr,
 555                               u16 cqe_pbl_size, bool b_use_zone_a_prod)
 556 {
 557         struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
 558         struct ecore_spq_entry *p_ent = OSAL_NULL;
 559         struct ecore_sp_init_data init_data;
 560         struct ecore_hw_cid_data *p_rx_cid;
 561         u16 abs_rx_q_id = 0;
 562         u8 abs_vport_id = 0;
 563         enum _ecore_status_t rc = ECORE_NOTIMPL;
 564
 565         /* Store information for the stop */
 566         p_rx_cid = &p_hwfn->p_rx_cids[p_params->queue_id];
 567         p_rx_cid->cid = cid;
 568         p_rx_cid->opaque_fid = opaque_fid;
 569         p_rx_cid->vport_id = p_params->vport_id;
 570
 571         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
 572         if (rc != ECORE_SUCCESS)
 573                 return rc;
 574
 575         rc = ecore_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_rx_q_id);
 576         if (rc != ECORE_SUCCESS)
 577                 return rc;
 578
 579         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 580                    "opaque_fid=0x%x, cid=0x%x, rx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
 581                    opaque_fid, cid, p_params->queue_id,
 582                    p_params->vport_id, p_params->sb);
 583
 584         /* Get SPQ entry */
 585         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 586         init_data.cid = cid;
 587         init_data.opaque_fid = opaque_fid;
 588         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 589
 590         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 591                                    ETH_RAMROD_RX_QUEUE_START,
 592                                    PROTOCOLID_ETH, &init_data);
 593         if (rc != ECORE_SUCCESS)
 594                 return rc;
 595
 596         p_ramrod = &p_ent->ramrod.rx_queue_start;
 597
 598         p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_params->sb);
 599         p_ramrod->sb_index = (u8)p_params->sb_idx;
 600         p_ramrod->vport_id = abs_vport_id;
 601         p_ramrod->stats_counter_id = p_params->stats_id;
 602         p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 603         p_ramrod->complete_cqe_flg = 0;
 604         p_ramrod->complete_event_flg = 1;
 605
 606         p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes);
 607         DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr);
 608
 609         p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
 610         DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
 611
 612         if (p_params->vf_qid || b_use_zone_a_prod) {
 613                 p_ramrod->vf_rx_prod_index = (u8)p_params->vf_qid;
 614                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 615                            "Queue%s is meant for VF rxq[%02x]\n",
 616                            b_use_zone_a_prod ? " [legacy]" : "",
 617                            p_params->vf_qid);
 618                 p_ramrod->vf_rx_prod_use_zone_a = b_use_zone_a_prod;
 619         }
 620
 621         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 622 }
 623
 624 enum _ecore_status_t
 625 ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
 626                             u16 opaque_fid,
 627                             struct ecore_queue_start_common_params *p_params,
 628                             u16 bd_max_bytes,
 629                             dma_addr_t bd_chain_phys_addr,
 630                             dma_addr_t cqe_pbl_addr,
 631                             u16 cqe_pbl_size,
 632                             void OSAL_IOMEM * *pp_prod)
 633 {
 634         struct ecore_hw_cid_data *p_rx_cid;
 635         u32 init_prod_val = 0;
 636         u16 abs_l2_queue = 0;
 637         u8 abs_stats_id = 0;
 638         enum _ecore_status_t rc;
 639
 640         if (IS_VF(p_hwfn->p_dev)) {
 641                 return ecore_vf_pf_rxq_start(p_hwfn,
 642                                              p_params->queue_id,
 643                                              p_params->sb,
 644                                              (u8)p_params->sb_idx,
 645                                              bd_max_bytes,
 646                                              bd_chain_phys_addr,
 647                                              cqe_pbl_addr,
 648                                              cqe_pbl_size, pp_prod);
 649         }
 650
 651         rc = ecore_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_l2_queue);
 652         if (rc != ECORE_SUCCESS)
 653                 return rc;
 654
 655         rc = ecore_fw_vport(p_hwfn, p_params->stats_id, &abs_stats_id);
 656         if (rc != ECORE_SUCCESS)
 657                 return rc;
 658
 659         *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview +
 660             GTT_BAR0_MAP_REG_MSDM_RAM +
 661             MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue);
 662
 663         /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
 664         __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
 665                           (u32 *)(&init_prod_val));
 666
 667         /* Allocate a CID for the queue */
 668         p_rx_cid = &p_hwfn->p_rx_cids[p_params->queue_id];
 669         rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
 670                                    &p_rx_cid->cid);
 671         if (rc != ECORE_SUCCESS) {
 672                 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
 673                 return rc;
 674         }
 675         p_rx_cid->b_cid_allocated = true;
 676         p_params->stats_id = abs_stats_id;
 677         p_params->vf_qid = 0;
 678
 679         rc = ecore_sp_eth_rxq_start_ramrod(p_hwfn,
 680                                            opaque_fid,
 681                                            p_rx_cid->cid,
 682                                            p_params,
 683                                            bd_max_bytes,
 684                                            bd_chain_phys_addr,
 685                                            cqe_pbl_addr,
 686                                            cqe_pbl_size,
 687                                            false);
 688
 689         if (rc != ECORE_SUCCESS)
 690                 ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
 691
 692         return rc;
 693 }
 694
 695 enum _ecore_status_t
 696 ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn,
 697                               u16 rx_queue_id,
 698                               u8 num_rxqs,
 699                               u8 complete_cqe_flg,
 700                               u8 complete_event_flg,
 701                               enum spq_mode comp_mode,
 702                               struct ecore_spq_comp_cb *p_comp_data)
 703 {
 704         struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL;
 705         struct ecore_spq_entry *p_ent = OSAL_NULL;
 706         struct ecore_sp_init_data init_data;
 707         struct ecore_hw_cid_data *p_rx_cid;
 708         u16 qid, abs_rx_q_id = 0;
 709         enum _ecore_status_t rc = ECORE_NOTIMPL;
 710         u8 i;
 711
 712         if (IS_VF(p_hwfn->p_dev))
 713                 return ecore_vf_pf_rxqs_update(p_hwfn,
 714                                                rx_queue_id,
 715                                                num_rxqs,
 716                                                complete_cqe_flg,
 717                                                complete_event_flg);
 718
 719         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 720         init_data.comp_mode = comp_mode;
 721         init_data.p_comp_data = p_comp_data;
 722
 723         for (i = 0; i < num_rxqs; i++) {
 724                 qid = rx_queue_id + i;
 725                 p_rx_cid = &p_hwfn->p_rx_cids[qid];
 726
 727                 /* Get SPQ entry */
 728                 init_data.cid = p_rx_cid->cid;
 729                 init_data.opaque_fid = p_rx_cid->opaque_fid;
 730
 731                 rc = ecore_sp_init_request(p_hwfn, &p_ent,
 732                                            ETH_RAMROD_RX_QUEUE_UPDATE,
 733                                            PROTOCOLID_ETH, &init_data);
 734                 if (rc != ECORE_SUCCESS)
 735                         return rc;
 736
 737                 p_ramrod = &p_ent->ramrod.rx_queue_update;
 738
 739                 ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
 740                 ecore_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
 741                 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 742                 p_ramrod->complete_cqe_flg = complete_cqe_flg;
 743                 p_ramrod->complete_event_flg = complete_event_flg;
 744
 745                 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 746                 if (rc)
 747                         return rc;
 748         }
 749
 750         return rc;
 751 }
 752
 753 enum _ecore_status_t
 754 ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
 755                            u16 rx_queue_id,
 756                            bool eq_completion_only, bool cqe_completion)
 757 {
 758         struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
 759         struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
 760         struct ecore_spq_entry *p_ent = OSAL_NULL;
 761         struct ecore_sp_init_data init_data;
 762         u16 abs_rx_q_id = 0;
 763         enum _ecore_status_t rc = ECORE_NOTIMPL;
 764
 765         if (IS_VF(p_hwfn->p_dev))
 766                 return ecore_vf_pf_rxq_stop(p_hwfn, rx_queue_id,
 767                                             cqe_completion);
 768
 769         /* Get SPQ entry */
 770         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 771         init_data.cid = p_rx_cid->cid;
 772         init_data.opaque_fid = p_rx_cid->opaque_fid;
 773         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 774
 775         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 776                                    ETH_RAMROD_RX_QUEUE_STOP,
 777                                    PROTOCOLID_ETH, &init_data);
 778         if (rc != ECORE_SUCCESS)
 779                 return rc;
 780
 781         p_ramrod = &p_ent->ramrod.rx_queue_stop;
 782
 783         ecore_fw_vport(p_hwfn, p_rx_cid->vport_id, &p_ramrod->vport_id);
 784         ecore_fw_l2_queue(p_hwfn, rx_queue_id, &abs_rx_q_id);
 785         p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(abs_rx_q_id);
 786
 787         /* Cleaning the queue requires the completion to arrive there.
 788          * In addition, VFs require the answer to come as eqe to PF.
 789          */
 790         p_ramrod->complete_cqe_flg = (!!(p_rx_cid->opaque_fid ==
 791                                          p_hwfn->hw_info.opaque_fid) &&
 792                                       !eq_completion_only) || cqe_completion;
 793         p_ramrod->complete_event_flg = !(p_rx_cid->opaque_fid ==
 794                                          p_hwfn->hw_info.opaque_fid) ||
 795             eq_completion_only;
 796
 797         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 798         if (rc != ECORE_SUCCESS)
 799                 return rc;
 800
 801         ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
 802
 803         return rc;
 804 }
 805
 806 enum _ecore_status_t
 807 ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
 808                               u16 opaque_fid,
 809                               u32 cid,
 810                               struct ecore_queue_start_common_params *p_params,
 811                               dma_addr_t pbl_addr,
 812                               u16 pbl_size,
 813                               union ecore_qm_pq_params *p_pq_params)
 814 {
 815         struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
 816         struct ecore_spq_entry *p_ent = OSAL_NULL;
 817         struct ecore_sp_init_data init_data;
 818         struct ecore_hw_cid_data *p_tx_cid;
 819         u16 pq_id, abs_tx_q_id = 0;
 820         u8 abs_vport_id;
 821         enum _ecore_status_t rc = ECORE_NOTIMPL;
 822
 823         /* Store information for the stop */
 824         p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
 825         p_tx_cid->cid = cid;
 826         p_tx_cid->opaque_fid = opaque_fid;
 827
 828         rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
 829         if (rc != ECORE_SUCCESS)
 830                 return rc;
 831
 832         rc = ecore_fw_l2_queue(p_hwfn, p_params->queue_id, &abs_tx_q_id);
 833         if (rc != ECORE_SUCCESS)
 834                 return rc;
 835
 836         /* Get SPQ entry */
 837         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 838         init_data.cid = cid;
 839         init_data.opaque_fid = opaque_fid;
 840         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 841
 842         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 843                                    ETH_RAMROD_TX_QUEUE_START,
 844                                    PROTOCOLID_ETH, &init_data);
 845         if (rc != ECORE_SUCCESS)
 846                 return rc;
 847
 848         p_ramrod = &p_ent->ramrod.tx_queue_start;
 849         p_ramrod->vport_id = abs_vport_id;
 850
 851         p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_params->sb);
 852         p_ramrod->sb_index = (u8)p_params->sb_idx;
 853         p_ramrod->stats_counter_id = p_params->stats_id;
 854
 855         p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(abs_tx_q_id);
 856
 857         p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
 858         DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
 859
 860         pq_id = ecore_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
 861         p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
 862
 863         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 864 }
 865
 866 enum _ecore_status_t
 867 ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,
 868                             u16 opaque_fid,
 869                             struct ecore_queue_start_common_params *p_params,
 870                             u8 tc,
 871                             dma_addr_t pbl_addr,
 872                             u16 pbl_size,
 873                             void OSAL_IOMEM * *pp_doorbell)
 874 {
 875         struct ecore_hw_cid_data *p_tx_cid;
 876         union ecore_qm_pq_params pq_params;
 877         u8 abs_stats_id = 0;
 878         enum _ecore_status_t rc;
 879
 880         if (IS_VF(p_hwfn->p_dev)) {
 881                 return ecore_vf_pf_txq_start(p_hwfn,
 882                                              p_params->queue_id,
 883                                              p_params->sb,
 884                                              (u8)p_params->sb_idx,
 885                                              pbl_addr,
 886                                              pbl_size,
 887                                              pp_doorbell);
 888         }
 889
 890         rc = ecore_fw_vport(p_hwfn, p_params->stats_id, &abs_stats_id);
 891         if (rc != ECORE_SUCCESS)
 892                 return rc;
 893
 894         p_tx_cid = &p_hwfn->p_tx_cids[p_params->queue_id];
 895         OSAL_MEMSET(p_tx_cid, 0, sizeof(*p_tx_cid));
 896         OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
 897
 898         pq_params.eth.tc = tc;
 899
 900         /* Allocate a CID for the queue */
 901         rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
 902         if (rc != ECORE_SUCCESS) {
 903                 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
 904                 return rc;
 905         }
 906         p_tx_cid->b_cid_allocated = true;
 907
 908         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 909                    "opaque_fid=0x%x, cid=0x%x, tx_qid=0x%x, vport_id=0x%x, sb_id=0x%x\n",
 910                     opaque_fid, p_tx_cid->cid, p_params->queue_id,
 911                     p_params->vport_id, p_params->sb);
 912
 913         p_params->stats_id = abs_stats_id;
 914
 915         /* TODO - set tc in the pq_params for multi-cos */
 916         rc = ecore_sp_eth_txq_start_ramrod(p_hwfn,
 917                                            opaque_fid,
 918                                            p_tx_cid->cid,
 919                                            p_params,
 920                                            pbl_addr,
 921                                            pbl_size,
 922                                            &pq_params);
 923
 924         *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
 925             DB_ADDR(p_tx_cid->cid, DQ_DEMS_LEGACY);
 926
 927         if (rc != ECORE_SUCCESS)
 928                 ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
 929
 930         return rc;
 931 }
 932
 933 enum _ecore_status_t ecore_sp_eth_tx_queue_update(struct ecore_hwfn *p_hwfn)
 934 {
 935         return ECORE_NOTIMPL;
 936 }
 937
 938 enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
 939                                                 u16 tx_queue_id)
 940 {
 941         struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
 942         struct ecore_spq_entry *p_ent = OSAL_NULL;
 943         struct ecore_sp_init_data init_data;
 944         enum _ecore_status_t rc = ECORE_NOTIMPL;
 945
 946         if (IS_VF(p_hwfn->p_dev))
 947                 return ecore_vf_pf_txq_stop(p_hwfn, tx_queue_id);
 948
 949         /* Get SPQ entry */
 950         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 951         init_data.cid = p_tx_cid->cid;
 952         init_data.opaque_fid = p_tx_cid->opaque_fid;
 953         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 954
 955         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 956                                    ETH_RAMROD_TX_QUEUE_STOP,
 957                                    PROTOCOLID_ETH, &init_data);
 958         if (rc != ECORE_SUCCESS)
 959                 return rc;
 960
 961         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 962         if (rc != ECORE_SUCCESS)
 963                 return rc;
 964
 965         ecore_sp_release_queue_cid(p_hwfn, p_tx_cid);
 966         return rc;
 967 }
 968
 969 static enum eth_filter_action
 970 ecore_filter_action(enum ecore_filter_opcode opcode)
 971 {
 972         enum eth_filter_action action = MAX_ETH_FILTER_ACTION;
 973
 974         switch (opcode) {
 975         case ECORE_FILTER_ADD:
 976                 action = ETH_FILTER_ACTION_ADD;
 977                 break;
 978         case ECORE_FILTER_REMOVE:
 979                 action = ETH_FILTER_ACTION_REMOVE;
 980                 break;
 981         case ECORE_FILTER_FLUSH:
 982                 action = ETH_FILTER_ACTION_REMOVE_ALL;
 983                 break;
 984         default:
 985                 action = MAX_ETH_FILTER_ACTION;
 986         }
 987
 988         return action;
 989 }
 990
 991 static void ecore_set_fw_mac_addr(__le16 *fw_msb,
 992                                   __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
 993 {
 994         ((u8 *)fw_msb)[0] = mac[1];
 995         ((u8 *)fw_msb)[1] = mac[0];
 996         ((u8 *)fw_mid)[0] = mac[3];
 997         ((u8 *)fw_mid)[1] = mac[2];
 998         ((u8 *)fw_lsb)[0] = mac[5];
 999         ((u8 *)fw_lsb)[1] = mac[4];
1000 }
1001
1002 static enum _ecore_status_t
1003 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn,
1004                           u16 opaque_fid,
1005                           struct ecore_filter_ucast *p_filter_cmd,
1006                           struct vport_filter_update_ramrod_data **pp_ramrod,
1007                           struct ecore_spq_entry **pp_ent,
1008                           enum spq_mode comp_mode,
1009                           struct ecore_spq_comp_cb *p_comp_data)
1010 {
1011         u8 vport_to_add_to = 0, vport_to_remove_from = 0;
1012         struct vport_filter_update_ramrod_data *p_ramrod;
1013         struct eth_filter_cmd *p_first_filter;
1014         struct eth_filter_cmd *p_second_filter;
1015         struct ecore_sp_init_data init_data;
1016         enum eth_filter_action action;
1017         enum _ecore_status_t rc;
1018
1019         rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from,
1020                             &vport_to_remove_from);
1021         if (rc != ECORE_SUCCESS)
1022                 return rc;
1023
1024         rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to,
1025                             &vport_to_add_to);
1026         if (rc != ECORE_SUCCESS)
1027                 return rc;
1028
1029         /* Get SPQ entry */
1030         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1031         init_data.cid = ecore_spq_get_cid(p_hwfn);
1032         init_data.opaque_fid = opaque_fid;
1033         init_data.comp_mode = comp_mode;
1034         init_data.p_comp_data = p_comp_data;
1035
1036         rc = ecore_sp_init_request(p_hwfn, pp_ent,
1037                                    ETH_RAMROD_FILTERS_UPDATE,
1038                                    PROTOCOLID_ETH, &init_data);
1039         if (rc != ECORE_SUCCESS)
1040                 return rc;
1041
1042         *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update;
1043         p_ramrod = *pp_ramrod;
1044         p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0;
1045         p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0;
1046
1047 #ifndef ASIC_ONLY
1048         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1049                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1050                            "Non-Asic - prevent Tx filters\n");
1051                 p_ramrod->filter_cmd_hdr.tx = 0;
1052         }
1053 #endif
1054
1055         switch (p_filter_cmd->opcode) {
1056         case ECORE_FILTER_REPLACE:
1057         case ECORE_FILTER_MOVE:
1058                 p_ramrod->filter_cmd_hdr.cmd_cnt = 2;
1059                 break;
1060         default:
1061                 p_ramrod->filter_cmd_hdr.cmd_cnt = 1;
1062                 break;
1063         }
1064
1065         p_first_filter = &p_ramrod->filter_cmds[0];
1066         p_second_filter = &p_ramrod->filter_cmds[1];
1067
1068         switch (p_filter_cmd->type) {
1069         case ECORE_FILTER_MAC:
1070                 p_first_filter->type = ETH_FILTER_TYPE_MAC;
1071                 break;
1072         case ECORE_FILTER_VLAN:
1073                 p_first_filter->type = ETH_FILTER_TYPE_VLAN;
1074                 break;
1075         case ECORE_FILTER_MAC_VLAN:
1076                 p_first_filter->type = ETH_FILTER_TYPE_PAIR;
1077                 break;
1078         case ECORE_FILTER_INNER_MAC:
1079                 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC;
1080                 break;
1081         case ECORE_FILTER_INNER_VLAN:
1082                 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN;
1083                 break;
1084         case ECORE_FILTER_INNER_PAIR:
1085                 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR;
1086                 break;
1087         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1088                 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR;
1089                 break;
1090         case ECORE_FILTER_MAC_VNI_PAIR:
1091                 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR;
1092                 break;
1093         case ECORE_FILTER_VNI:
1094                 p_first_filter->type = ETH_FILTER_TYPE_VNI;
1095                 break;
1096         }
1097
1098         if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) ||
1099             (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1100             (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) ||
1101             (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) ||
1102             (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1103             (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR))
1104                 ecore_set_fw_mac_addr(&p_first_filter->mac_msb,
1105                                       &p_first_filter->mac_mid,
1106                                       &p_first_filter->mac_lsb,
1107                                       (u8 *)p_filter_cmd->mac);
1108
1109         if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) ||
1110             (p_first_filter->type == ETH_FILTER_TYPE_PAIR) ||
1111             (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) ||
1112             (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR))
1113                 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan);
1114
1115         if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) ||
1116             (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) ||
1117             (p_first_filter->type == ETH_FILTER_TYPE_VNI))
1118                 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni);
1119
1120         if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) {
1121                 p_second_filter->type = p_first_filter->type;
1122                 p_second_filter->mac_msb = p_first_filter->mac_msb;
1123                 p_second_filter->mac_mid = p_first_filter->mac_mid;
1124                 p_second_filter->mac_lsb = p_first_filter->mac_lsb;
1125                 p_second_filter->vlan_id = p_first_filter->vlan_id;
1126                 p_second_filter->vni = p_first_filter->vni;
1127
1128                 p_first_filter->action = ETH_FILTER_ACTION_REMOVE;
1129
1130                 p_first_filter->vport_id = vport_to_remove_from;
1131
1132                 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1133                 p_second_filter->vport_id = vport_to_add_to;
1134         } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) {
1135                 p_first_filter->vport_id = vport_to_add_to;
1136                 OSAL_MEMCPY(p_second_filter, p_first_filter,
1137                             sizeof(*p_second_filter));
1138                 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL;
1139                 p_second_filter->action = ETH_FILTER_ACTION_ADD;
1140         } else {
1141                 action = ecore_filter_action(p_filter_cmd->opcode);
1142
1143                 if (action == MAX_ETH_FILTER_ACTION) {
1144                         DP_NOTICE(p_hwfn, true,
1145                                   "%d is not supported yet\n",
1146                                   p_filter_cmd->opcode);
1147                         return ECORE_NOTIMPL;
1148                 }
1149
1150                 p_first_filter->action = action;
1151                 p_first_filter->vport_id =
1152                     (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1153                     vport_to_remove_from : vport_to_add_to;
1154         }
1155
1156         return ECORE_SUCCESS;
1157 }
1158
1159 enum _ecore_status_t
1160 ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn,
1161                           u16 opaque_fid,
1162                           struct ecore_filter_ucast *p_filter_cmd,
1163                           enum spq_mode comp_mode,
1164                           struct ecore_spq_comp_cb *p_comp_data)
1165 {
1166         struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL;
1167         struct ecore_spq_entry *p_ent = OSAL_NULL;
1168         struct eth_filter_cmd_header *p_header;
1169         enum _ecore_status_t rc;
1170
1171         rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd,
1172                                        &p_ramrod, &p_ent,
1173                                        comp_mode, p_comp_data);
1174         if (rc != ECORE_SUCCESS) {
1175                 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc);
1176                 return rc;
1177         }
1178         p_header = &p_ramrod->filter_cmd_hdr;
1179         p_header->assert_on_error = p_filter_cmd->assert_on_error;
1180
1181         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1182         if (rc != ECORE_SUCCESS) {
1183                 DP_ERR(p_hwfn, "Unicast filter ADD command failed %d\n", rc);
1184                 return rc;
1185         }
1186
1187         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1188                    "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n",
1189                    (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" :
1190                    ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ?
1191                     "REMOVE" :
1192                     ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ?
1193                      "MOVE" : "REPLACE")),
1194                    (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" :
1195                    ((p_filter_cmd->type == ECORE_FILTER_VLAN) ?
1196                     "VLAN" : "MAC & VLAN"),
1197                    p_ramrod->filter_cmd_hdr.cmd_cnt,
1198                    p_filter_cmd->is_rx_filter, p_filter_cmd->is_tx_filter);
1199         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1200                    "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n",
1201                    p_filter_cmd->vport_to_add_to,
1202                    p_filter_cmd->vport_to_remove_from,
1203                    p_filter_cmd->mac[0], p_filter_cmd->mac[1],
1204                    p_filter_cmd->mac[2], p_filter_cmd->mac[3],
1205                    p_filter_cmd->mac[4], p_filter_cmd->mac[5],
1206                    p_filter_cmd->vlan);
1207
1208         return ECORE_SUCCESS;
1209 }
1210
1211 /*******************************************************************************
1212  * Description:
1213  *         Calculates crc 32 on a buffer
1214  *         Note: crc32_length MUST be aligned to 8
1215  * Return:
1216  ******************************************************************************/
1217 static u32 ecore_calc_crc32c(u8 *crc32_packet,
1218                              u32 crc32_length, u32 crc32_seed, u8 complement)
1219 {
1220         u32 byte = 0, bit = 0, crc32_result = crc32_seed;
1221         u8 msb = 0, current_byte = 0;
1222
1223         if ((crc32_packet == OSAL_NULL) ||
1224             (crc32_length == 0) || ((crc32_length % 8) != 0)) {
1225                 return crc32_result;
1226         }
1227
1228         for (byte = 0; byte < crc32_length; byte++) {
1229                 current_byte = crc32_packet[byte];
1230                 for (bit = 0; bit < 8; bit++) {
1231                         msb = (u8)(crc32_result >> 31);
1232                         crc32_result = crc32_result << 1;
1233                         if (msb != (0x1 & (current_byte >> bit))) {
1234                                 crc32_result = crc32_result ^ CRC32_POLY;
1235                                 crc32_result |= 1;
1236                         }
1237                 }
1238         }
1239
1240         return crc32_result;
1241 }
1242
1243 static u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
1244 {
1245         u32 packet_buf[2] = { 0 };
1246
1247         OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6);
1248         return ecore_calc_crc32c((u8 *)packet_buf, 8, seed, 0);
1249 }
1250
1251 u8 ecore_mcast_bin_from_mac(u8 *mac)
1252 {
1253         u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED,
1254                                   mac, ETH_ALEN);
1255
1256         return crc & 0xff;
1257 }
1258
1259 static enum _ecore_status_t
1260 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
1261                           u16 opaque_fid,
1262                           struct ecore_filter_mcast *p_filter_cmd,
1263                           enum spq_mode comp_mode,
1264                           struct ecore_spq_comp_cb *p_comp_data)
1265 {
1266         unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
1267         struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
1268         struct ecore_spq_entry *p_ent = OSAL_NULL;
1269         struct ecore_sp_init_data init_data;
1270         u8 abs_vport_id = 0;
1271         enum _ecore_status_t rc;
1272         int i;
1273
1274         if (p_filter_cmd->opcode == ECORE_FILTER_ADD)
1275                 rc = ecore_fw_vport(p_hwfn,
1276                                     p_filter_cmd->vport_to_add_to,
1277                                     &abs_vport_id);
1278         else
1279                 rc = ecore_fw_vport(p_hwfn,
1280                                     p_filter_cmd->vport_to_remove_from,
1281                                     &abs_vport_id);
1282         if (rc != ECORE_SUCCESS)
1283                 return rc;
1284
1285         /* Get SPQ entry */
1286         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
1287         init_data.cid = ecore_spq_get_cid(p_hwfn);
1288         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1289         init_data.comp_mode = comp_mode;
1290         init_data.p_comp_data = p_comp_data;
1291
1292         rc = ecore_sp_init_request(p_hwfn, &p_ent,
1293                                    ETH_RAMROD_VPORT_UPDATE,
1294                                    PROTOCOLID_ETH, &init_data);
1295         if (rc != ECORE_SUCCESS) {
1296                 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc);
1297                 return rc;
1298         }
1299
1300         p_ramrod = &p_ent->ramrod.vport_update;
1301         p_ramrod->common.update_approx_mcast_flg = 1;
1302
1303         /* explicitly clear out the entire vector */
1304         OSAL_MEMSET(&p_ramrod->approx_mcast.bins,
1305                     0, sizeof(p_ramrod->approx_mcast.bins));
1306         OSAL_MEMSET(bins, 0, sizeof(unsigned long) *
1307                     ETH_MULTICAST_MAC_BINS_IN_REGS);
1308         /* filter ADD op is explicit set op and it removes
1309         *  any existing filters for the vport.
1310         */
1311         if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1312                 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1313                         u32 bit;
1314
1315                         bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1316                         OSAL_SET_BIT(bit, bins);
1317                 }
1318
1319                 /* Convert to correct endianity */
1320                 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) {
1321                         struct vport_update_ramrod_mcast *p_ramrod_bins;
1322                         u32 *p_bins = (u32 *)bins;
1323
1324                         p_ramrod_bins = &p_ramrod->approx_mcast;
1325                         p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(p_bins[i]);
1326                 }
1327         }
1328
1329         p_ramrod->common.vport_id = abs_vport_id;
1330
1331         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
1332         if (rc != ECORE_SUCCESS)
1333                 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc);
1334
1335         return rc;
1336 }
1337
1338 enum _ecore_status_t
1339 ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
1340                        struct ecore_filter_mcast *p_filter_cmd,
1341                        enum spq_mode comp_mode,
1342                        struct ecore_spq_comp_cb *p_comp_data)
1343 {
1344         enum _ecore_status_t rc = ECORE_SUCCESS;
1345         int i;
1346
1347         /* only ADD and REMOVE operations are supported for multi-cast */
1348         if ((p_filter_cmd->opcode != ECORE_FILTER_ADD &&
1349              (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) ||
1350             (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) {
1351                 return ECORE_INVAL;
1352         }
1353
1354         for_each_hwfn(p_dev, i) {
1355                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1356                 u16 opaque_fid;
1357
1358                 if (IS_VF(p_dev)) {
1359                         ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
1360                         continue;
1361                 }
1362
1363                 opaque_fid = p_hwfn->hw_info.opaque_fid;
1364                 rc = ecore_sp_eth_filter_mcast(p_hwfn,
1365                                                opaque_fid,
1366                                                p_filter_cmd,
1367                                                comp_mode, p_comp_data);
1368                 if (rc != ECORE_SUCCESS)
1369                         break;
1370         }
1371
1372         return rc;
1373 }
1374
1375 enum _ecore_status_t
1376 ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
1377                        struct ecore_filter_ucast *p_filter_cmd,
1378                        enum spq_mode comp_mode,
1379                        struct ecore_spq_comp_cb *p_comp_data)
1380 {
1381         enum _ecore_status_t rc = ECORE_SUCCESS;
1382         int i;
1383
1384         for_each_hwfn(p_dev, i) {
1385                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1386                 u16 opaque_fid;
1387
1388                 if (IS_VF(p_dev)) {
1389                         rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
1390                         continue;
1391                 }
1392
1393                 opaque_fid = p_hwfn->hw_info.opaque_fid;
1394                 rc = ecore_sp_eth_filter_ucast(p_hwfn,
1395                                                opaque_fid,
1396                                                p_filter_cmd,
1397                                                comp_mode, p_comp_data);
1398                 if (rc != ECORE_SUCCESS)
1399                         break;
1400         }
1401
1402         return rc;
1403 }
1404
1405 /* Statistics related code */
1406 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
1407                                              u32 *p_addr, u32 *p_len,
1408                                              u16 statistics_bin)
1409 {
1410         if (IS_PF(p_hwfn->p_dev)) {
1411                 *p_addr = BAR0_MAP_REG_PSDM_RAM +
1412                     PSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1413                 *p_len = sizeof(struct eth_pstorm_per_queue_stat);
1414         } else {
1415                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1416                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1417
1418                 *p_addr = p_resp->pfdev_info.stats_info.pstats.address;
1419                 *p_len = p_resp->pfdev_info.stats_info.pstats.len;
1420         }
1421 }
1422
1423 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn,
1424                                      struct ecore_ptt *p_ptt,
1425                                      struct ecore_eth_stats *p_stats,
1426                                      u16 statistics_bin)
1427 {
1428         struct eth_pstorm_per_queue_stat pstats;
1429         u32 pstats_addr = 0, pstats_len = 0;
1430
1431         __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len,
1432                                          statistics_bin);
1433
1434         OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1435         ecore_memcpy_from(p_hwfn, p_ptt, &pstats, pstats_addr, pstats_len);
1436
1437         p_stats->tx_ucast_bytes += HILO_64_REGPAIR(pstats.sent_ucast_bytes);
1438         p_stats->tx_mcast_bytes += HILO_64_REGPAIR(pstats.sent_mcast_bytes);
1439         p_stats->tx_bcast_bytes += HILO_64_REGPAIR(pstats.sent_bcast_bytes);
1440         p_stats->tx_ucast_pkts += HILO_64_REGPAIR(pstats.sent_ucast_pkts);
1441         p_stats->tx_mcast_pkts += HILO_64_REGPAIR(pstats.sent_mcast_pkts);
1442         p_stats->tx_bcast_pkts += HILO_64_REGPAIR(pstats.sent_bcast_pkts);
1443         p_stats->tx_err_drop_pkts += HILO_64_REGPAIR(pstats.error_drop_pkts);
1444 }
1445
1446 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn,
1447                                      struct ecore_ptt *p_ptt,
1448                                      struct ecore_eth_stats *p_stats,
1449                                      u16 statistics_bin)
1450 {
1451         struct tstorm_per_port_stat tstats;
1452         u32 tstats_addr, tstats_len;
1453
1454         if (IS_PF(p_hwfn->p_dev)) {
1455                 tstats_addr = BAR0_MAP_REG_TSDM_RAM +
1456                     TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn));
1457                 tstats_len = sizeof(struct tstorm_per_port_stat);
1458         } else {
1459                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1460                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1461
1462                 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address;
1463                 tstats_len = p_resp->pfdev_info.stats_info.tstats.len;
1464         }
1465
1466         OSAL_MEMSET(&tstats, 0, sizeof(tstats));
1467         ecore_memcpy_from(p_hwfn, p_ptt, &tstats, tstats_addr, tstats_len);
1468
1469         p_stats->mftag_filter_discards +=
1470             HILO_64_REGPAIR(tstats.mftag_filter_discard);
1471         p_stats->mac_filter_discards +=
1472             HILO_64_REGPAIR(tstats.eth_mac_filter_discard);
1473 }
1474
1475 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn,
1476                                              u32 *p_addr, u32 *p_len,
1477                                              u16 statistics_bin)
1478 {
1479         if (IS_PF(p_hwfn->p_dev)) {
1480                 *p_addr = BAR0_MAP_REG_USDM_RAM +
1481                     USTORM_QUEUE_STAT_OFFSET(statistics_bin);
1482                 *p_len = sizeof(struct eth_ustorm_per_queue_stat);
1483         } else {
1484                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1485                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1486
1487                 *p_addr = p_resp->pfdev_info.stats_info.ustats.address;
1488                 *p_len = p_resp->pfdev_info.stats_info.ustats.len;
1489         }
1490 }
1491
1492 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn,
1493                                      struct ecore_ptt *p_ptt,
1494                                      struct ecore_eth_stats *p_stats,
1495                                      u16 statistics_bin)
1496 {
1497         struct eth_ustorm_per_queue_stat ustats;
1498         u32 ustats_addr = 0, ustats_len = 0;
1499
1500         __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len,
1501                                          statistics_bin);
1502
1503         OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1504         ecore_memcpy_from(p_hwfn, p_ptt, &ustats, ustats_addr, ustats_len);
1505
1506         p_stats->rx_ucast_bytes += HILO_64_REGPAIR(ustats.rcv_ucast_bytes);
1507         p_stats->rx_mcast_bytes += HILO_64_REGPAIR(ustats.rcv_mcast_bytes);
1508         p_stats->rx_bcast_bytes += HILO_64_REGPAIR(ustats.rcv_bcast_bytes);
1509         p_stats->rx_ucast_pkts += HILO_64_REGPAIR(ustats.rcv_ucast_pkts);
1510         p_stats->rx_mcast_pkts += HILO_64_REGPAIR(ustats.rcv_mcast_pkts);
1511         p_stats->rx_bcast_pkts += HILO_64_REGPAIR(ustats.rcv_bcast_pkts);
1512 }
1513
1514 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn,
1515                                              u32 *p_addr, u32 *p_len,
1516                                              u16 statistics_bin)
1517 {
1518         if (IS_PF(p_hwfn->p_dev)) {
1519                 *p_addr = BAR0_MAP_REG_MSDM_RAM +
1520                     MSTORM_QUEUE_STAT_OFFSET(statistics_bin);
1521                 *p_len = sizeof(struct eth_mstorm_per_queue_stat);
1522         } else {
1523                 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1524                 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp;
1525
1526                 *p_addr = p_resp->pfdev_info.stats_info.mstats.address;
1527                 *p_len = p_resp->pfdev_info.stats_info.mstats.len;
1528         }
1529 }
1530
1531 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn,
1532                                      struct ecore_ptt *p_ptt,
1533                                      struct ecore_eth_stats *p_stats,
1534                                      u16 statistics_bin)
1535 {
1536         struct eth_mstorm_per_queue_stat mstats;
1537         u32 mstats_addr = 0, mstats_len = 0;
1538
1539         __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len,
1540                                          statistics_bin);
1541
1542         OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1543         ecore_memcpy_from(p_hwfn, p_ptt, &mstats, mstats_addr, mstats_len);
1544
1545         p_stats->no_buff_discards += HILO_64_REGPAIR(mstats.no_buff_discard);
1546         p_stats->packet_too_big_discard +=
1547             HILO_64_REGPAIR(mstats.packet_too_big_discard);
1548         p_stats->ttl0_discard += HILO_64_REGPAIR(mstats.ttl0_discard);
1549         p_stats->tpa_coalesced_pkts +=
1550             HILO_64_REGPAIR(mstats.tpa_coalesced_pkts);
1551         p_stats->tpa_coalesced_events +=
1552             HILO_64_REGPAIR(mstats.tpa_coalesced_events);
1553         p_stats->tpa_aborts_num += HILO_64_REGPAIR(mstats.tpa_aborts_num);
1554         p_stats->tpa_coalesced_bytes +=
1555             HILO_64_REGPAIR(mstats.tpa_coalesced_bytes);
1556 }
1557
1558 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn,
1559                                          struct ecore_ptt *p_ptt,
1560                                          struct ecore_eth_stats *p_stats)
1561 {
1562         struct port_stats port_stats;
1563         int j;
1564
1565         OSAL_MEMSET(&port_stats, 0, sizeof(port_stats));
1566
1567         ecore_memcpy_from(p_hwfn, p_ptt, &port_stats,
1568                           p_hwfn->mcp_info->port_addr +
1569                           OFFSETOF(struct public_port, stats),
1570                           sizeof(port_stats));
1571
1572         p_stats->rx_64_byte_packets += port_stats.eth.r64;
1573         p_stats->rx_65_to_127_byte_packets += port_stats.eth.r127;
1574         p_stats->rx_128_to_255_byte_packets += port_stats.eth.r255;
1575         p_stats->rx_256_to_511_byte_packets += port_stats.eth.r511;
1576         p_stats->rx_512_to_1023_byte_packets += port_stats.eth.r1023;
1577         p_stats->rx_1024_to_1518_byte_packets += port_stats.eth.r1518;
1578         p_stats->rx_1519_to_1522_byte_packets += port_stats.eth.r1522;
1579         p_stats->rx_1519_to_2047_byte_packets += port_stats.eth.r2047;
1580         p_stats->rx_2048_to_4095_byte_packets += port_stats.eth.r4095;
1581         p_stats->rx_4096_to_9216_byte_packets += port_stats.eth.r9216;
1582         p_stats->rx_9217_to_16383_byte_packets += port_stats.eth.r16383;
1583         p_stats->rx_crc_errors += port_stats.eth.rfcs;
1584         p_stats->rx_mac_crtl_frames += port_stats.eth.rxcf;
1585         p_stats->rx_pause_frames += port_stats.eth.rxpf;
1586         p_stats->rx_pfc_frames += port_stats.eth.rxpp;
1587         p_stats->rx_align_errors += port_stats.eth.raln;
1588         p_stats->rx_carrier_errors += port_stats.eth.rfcr;
1589         p_stats->rx_oversize_packets += port_stats.eth.rovr;
1590         p_stats->rx_jabbers += port_stats.eth.rjbr;
1591         p_stats->rx_undersize_packets += port_stats.eth.rund;
1592         p_stats->rx_fragments += port_stats.eth.rfrg;
1593         p_stats->tx_64_byte_packets += port_stats.eth.t64;
1594         p_stats->tx_65_to_127_byte_packets += port_stats.eth.t127;
1595         p_stats->tx_128_to_255_byte_packets += port_stats.eth.t255;
1596         p_stats->tx_256_to_511_byte_packets += port_stats.eth.t511;
1597         p_stats->tx_512_to_1023_byte_packets += port_stats.eth.t1023;
1598         p_stats->tx_1024_to_1518_byte_packets += port_stats.eth.t1518;
1599         p_stats->tx_1519_to_2047_byte_packets += port_stats.eth.t2047;
1600         p_stats->tx_2048_to_4095_byte_packets += port_stats.eth.t4095;
1601         p_stats->tx_4096_to_9216_byte_packets += port_stats.eth.t9216;
1602         p_stats->tx_9217_to_16383_byte_packets += port_stats.eth.t16383;
1603         p_stats->tx_pause_frames += port_stats.eth.txpf;
1604         p_stats->tx_pfc_frames += port_stats.eth.txpp;
1605         p_stats->tx_lpi_entry_count += port_stats.eth.tlpiec;
1606         p_stats->tx_total_collisions += port_stats.eth.tncl;
1607         p_stats->rx_mac_bytes += port_stats.eth.rbyte;
1608         p_stats->rx_mac_uc_packets += port_stats.eth.rxuca;
1609         p_stats->rx_mac_mc_packets += port_stats.eth.rxmca;
1610         p_stats->rx_mac_bc_packets += port_stats.eth.rxbca;
1611         p_stats->rx_mac_frames_ok += port_stats.eth.rxpok;
1612         p_stats->tx_mac_bytes += port_stats.eth.tbyte;
1613         p_stats->tx_mac_uc_packets += port_stats.eth.txuca;
1614         p_stats->tx_mac_mc_packets += port_stats.eth.txmca;
1615         p_stats->tx_mac_bc_packets += port_stats.eth.txbca;
1616         p_stats->tx_mac_ctrl_frames += port_stats.eth.txcf;
1617         for (j = 0; j < 8; j++) {
1618                 p_stats->brb_truncates += port_stats.brb.brb_truncate[j];
1619                 p_stats->brb_discards += port_stats.brb.brb_discard[j];
1620         }
1621 }
1622
1623 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn,
1624                              struct ecore_ptt *p_ptt,
1625                              struct ecore_eth_stats *stats,
1626                              u16 statistics_bin, bool b_get_port_stats)
1627 {
1628         __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin);
1629         __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin);
1630         __ecore_get_vport_tstats(p_hwfn, p_ptt, stats, statistics_bin);
1631         __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin);
1632
1633 #ifndef ASIC_ONLY
1634         /* Avoid getting PORT stats for emulation. */
1635         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1636                 return;
1637 #endif
1638
1639         if (b_get_port_stats && p_hwfn->mcp_info)
1640                 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats);
1641 }
1642
1643 static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
1644                                    struct ecore_eth_stats *stats)
1645 {
1646         u8 fw_vport = 0;
1647         int i;
1648
1649         OSAL_MEMSET(stats, 0, sizeof(*stats));
1650
1651         for_each_hwfn(p_dev, i) {
1652                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1653                 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1654                     ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1655
1656                 if (IS_PF(p_dev)) {
1657                         /* The main vport index is relative first */
1658                         if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) {
1659                                 DP_ERR(p_hwfn, "No vport available!\n");
1660                                 goto out;
1661                         }
1662                 }
1663
1664                 if (IS_PF(p_dev) && !p_ptt) {
1665                         DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1666                         continue;
1667                 }
1668
1669                 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1670                                         IS_PF(p_dev) ? true : false);
1671
1672 out:
1673                 if (IS_PF(p_dev) && p_ptt)
1674                         ecore_ptt_release(p_hwfn, p_ptt);
1675         }
1676 }
1677
1678 void ecore_get_vport_stats(struct ecore_dev *p_dev,
1679                            struct ecore_eth_stats *stats)
1680 {
1681         u32 i;
1682
1683         if (!p_dev) {
1684                 OSAL_MEMSET(stats, 0, sizeof(*stats));
1685                 return;
1686         }
1687
1688         _ecore_get_vport_stats(p_dev, stats);
1689
1690         if (!p_dev->reset_stats)
1691                 return;
1692
1693         /* Reduce the statistics baseline */
1694         for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++)
1695                 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i];
1696 }
1697
1698 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */
1699 void ecore_reset_vport_stats(struct ecore_dev *p_dev)
1700 {
1701         int i;
1702
1703         for_each_hwfn(p_dev, i) {
1704                 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
1705                 struct eth_mstorm_per_queue_stat mstats;
1706                 struct eth_ustorm_per_queue_stat ustats;
1707                 struct eth_pstorm_per_queue_stat pstats;
1708                 struct ecore_ptt *p_ptt = IS_PF(p_dev) ?
1709                     ecore_ptt_acquire(p_hwfn) : OSAL_NULL;
1710                 u32 addr = 0, len = 0;
1711
1712                 if (IS_PF(p_dev) && !p_ptt) {
1713                         DP_ERR(p_hwfn, "Failed to acquire ptt\n");
1714                         continue;
1715                 }
1716
1717                 OSAL_MEMSET(&mstats, 0, sizeof(mstats));
1718                 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0);
1719                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len);
1720
1721                 OSAL_MEMSET(&ustats, 0, sizeof(ustats));
1722                 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0);
1723                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len);
1724
1725                 OSAL_MEMSET(&pstats, 0, sizeof(pstats));
1726                 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0);
1727                 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len);
1728
1729                 if (IS_PF(p_dev))
1730                         ecore_ptt_release(p_hwfn, p_ptt);
1731         }
1732
1733         /* PORT statistics are not necessarily reset, so we need to
1734          * read and create a baseline for future statistics.
1735          */
1736         if (!p_dev->reset_stats)
1737                 DP_INFO(p_dev, "Reset stats not allocated\n");
1738         else
1739                 _ecore_get_vport_stats(p_dev, p_dev->reset_stats);
1740 }