drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23
  24 #define CHIP_MCP_RESP_ITER_US 10
  25 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  26
  27 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  28 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  29
  30 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  31         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  32                  _val)
  33
  34 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  35         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  36
  37 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  38         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  39                      OFFSETOF(struct public_drv_mb, _field), _val)
  40
  41 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  42         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  43                      OFFSETOF(struct public_drv_mb, _field))
  44
  45 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  46         DRV_ID_PDA_COMP_VER_SHIFT)
  47
  48 #define MCP_BYTES_PER_MBIT_SHIFT 17
  49
  50 #ifndef ASIC_ONLY
  51 static int loaded;
  52 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  53 #endif
  54
  55 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  56 {
  57         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  58                 return false;
  59         return true;
  60 }
  61
  62 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  63 {
  64         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  65                                         PUBLIC_PORT);
  66         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  67
  68         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  69                                                    MFW_PORT(p_hwfn));
  70         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  71                    "port_addr = 0x%x, port_id 0x%02x\n",
  72                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  73 }
  74
  75 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  76 {
  77         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  78         OSAL_BE32 tmp;
  79         u32 i;
  80
  81 #ifndef ASIC_ONLY
  82         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  83                 return;
  84 #endif
  85
  86         if (!p_hwfn->mcp_info->public_base)
  87                 return;
  88
  89         for (i = 0; i < length; i++) {
  90                 tmp = ecore_rd(p_hwfn, p_ptt,
  91                                p_hwfn->mcp_info->mfw_mb_addr +
  92                                (i << 2) + sizeof(u32));
  93
  94                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  95                     OSAL_BE32_TO_CPU(tmp);
  96         }
  97 }
  98
  99 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 100 {
 101         if (p_hwfn->mcp_info) {
 102                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 103                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 104                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->lock);
 105         }
 106         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 107
 108         return ECORE_SUCCESS;
 109 }
 110
 111 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 112                                                    struct ecore_ptt *p_ptt)
 113 {
 114         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 115         u32 drv_mb_offsize, mfw_mb_offsize;
 116         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 117
 118 #ifndef ASIC_ONLY
 119         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 120                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 121                 p_info->public_base = 0;
 122                 return ECORE_INVAL;
 123         }
 124 #endif
 125
 126         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 127         if (!p_info->public_base)
 128                 return ECORE_INVAL;
 129
 130         p_info->public_base |= GRCBASE_MCP;
 131
 132         /* Calculate the driver and MFW mailbox address */
 133         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 134                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 135                                                        PUBLIC_DRV_MB));
 136         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 137         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 138                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 139                    " mcp_pf_id = 0x%x\n",
 140                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 141
 142         /* Set the MFW MB address */
 143         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 144                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 145                                                        PUBLIC_MFW_MB));
 146         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 147         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 148                                                p_info->mfw_mb_addr);
 149
 150         /* Get the current driver mailbox sequence before sending
 151          * the first command
 152          */
 153         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 154             DRV_MSG_SEQ_NUMBER_MASK;
 155
 156         /* Get current FW pulse sequence */
 157         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 158             DRV_PULSE_SEQ_MASK;
 159
 160         p_info->mcp_hist = (u16)ecore_rd(p_hwfn, p_ptt,
 161                                           MISCS_REG_GENERIC_POR_0);
 162
 163         return ECORE_SUCCESS;
 164 }
 165
 166 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 167                                         struct ecore_ptt *p_ptt)
 168 {
 169         struct ecore_mcp_info *p_info;
 170         u32 size;
 171
 172         /* Allocate mcp_info structure */
 173         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 174                                        sizeof(*p_hwfn->mcp_info));
 175         if (!p_hwfn->mcp_info)
 176                 goto err;
 177         p_info = p_hwfn->mcp_info;
 178
 179         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 180                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 181                 /* Do not free mcp_info here, since public_base indicate that
 182                  * the MCP is not initialized
 183                  */
 184                 return ECORE_SUCCESS;
 185         }
 186
 187         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 188         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 189         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 190         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 191                 goto err;
 192
 193         /* Initialize the MFW spinlock */
 194         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->lock);
 195         OSAL_SPIN_LOCK_INIT(&p_info->lock);
 196
 197         return ECORE_SUCCESS;
 198
 199 err:
 200         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 201         ecore_mcp_free(p_hwfn);
 202         return ECORE_NOMEM;
 203 }
 204
 205 /* Locks the MFW mailbox of a PF to ensure a single access.
 206  * The lock is achieved in most cases by holding a spinlock, causing other
 207  * threads to wait till a previous access is done.
 208  * In some cases (currently when a [UN]LOAD_REQ commands are sent), the single
 209  * access is achieved by setting a blocking flag, which will fail other
 210  * competing contexts to send their mailboxes.
 211  */
 212 static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
 213                                               u32 cmd)
 214 {
 215         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
 216
 217         /* The spinlock shouldn't be acquired when the mailbox command is
 218          * [UN]LOAD_REQ, since the engine is locked by the MFW, and a parallel
 219          * pending [UN]LOAD_REQ command of another PF together with a spinlock
 220          * (i.e. interrupts are disabled) - can lead to a deadlock.
 221          * It is assumed that for a single PF, no other mailbox commands can be
 222          * sent from another context while sending LOAD_REQ, and that any
 223          * parallel commands to UNLOAD_REQ can be cancelled.
 224          */
 225         if (cmd == DRV_MSG_CODE_LOAD_DONE || cmd == DRV_MSG_CODE_UNLOAD_DONE)
 226                 p_hwfn->mcp_info->block_mb_sending = false;
 227
 228         if (p_hwfn->mcp_info->block_mb_sending) {
 229                 DP_NOTICE(p_hwfn, false,
 230                           "Trying to send a MFW mailbox command [0x%x]"
 231                           " in parallel to [UN]LOAD_REQ. Aborting.\n",
 232                           cmd);
 233                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 234                 return ECORE_BUSY;
 235         }
 236
 237         if (cmd == DRV_MSG_CODE_LOAD_REQ || cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 238                 p_hwfn->mcp_info->block_mb_sending = true;
 239                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 240         }
 241
 242         return ECORE_SUCCESS;
 243 }
 244
 245 static void ecore_mcp_mb_unlock(struct ecore_hwfn *p_hwfn, u32 cmd)
 246 {
 247         if (cmd != DRV_MSG_CODE_LOAD_REQ && cmd != DRV_MSG_CODE_UNLOAD_REQ)
 248                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
 249 }
 250
 251 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 252                                      struct ecore_ptt *p_ptt)
 253 {
 254         u32 seq = ++p_hwfn->mcp_info->drv_mb_seq;
 255         u32 delay = CHIP_MCP_RESP_ITER_US;
 256         u32 org_mcp_reset_seq, cnt = 0;
 257         enum _ecore_status_t rc = ECORE_SUCCESS;
 258
 259 #ifndef ASIC_ONLY
 260         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 261                 delay = EMUL_MCP_RESP_ITER_US;
 262 #endif
 263
 264         /* Ensure that only a single thread is accessing the mailbox at a
 265          * certain time.
 266          */
 267         rc = ecore_mcp_mb_lock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 268         if (rc != ECORE_SUCCESS)
 269                 return rc;
 270
 271         /* Set drv command along with the updated sequence */
 272         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 273         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 274
 275         do {
 276                 /* Wait for MFW response */
 277                 OSAL_UDELAY(delay);
 278                 /* Give the FW up to 500 second (50*1000*10usec) */
 279         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 280                                                 MISCS_REG_GENERIC_POR_0)) &&
 281                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 282
 283         if (org_mcp_reset_seq !=
 284             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 285                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 286                            "MCP was reset after %d usec\n", cnt * delay);
 287         } else {
 288                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 289                 rc = ECORE_AGAIN;
 290         }
 291
 292         ecore_mcp_mb_unlock(p_hwfn, DRV_MSG_CODE_MCP_RESET);
 293
 294         return rc;
 295 }
 296
 297 static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
 298                                              struct ecore_ptt *p_ptt,
 299                                              u32 cmd, u32 param,
 300                                              u32 *o_mcp_resp,
 301                                              u32 *o_mcp_param)
 302 {
 303         u32 delay = CHIP_MCP_RESP_ITER_US;
 304         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 305         u32 seq, cnt = 1, actual_mb_seq;
 306         enum _ecore_status_t rc = ECORE_SUCCESS;
 307
 308 #ifndef ASIC_ONLY
 309         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 310                 delay = EMUL_MCP_RESP_ITER_US;
 311         /* There is a built-in delay of 100usec in each MFW response read */
 312         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 313                 max_retries /= 10;
 314 #endif
 315
 316         /* Get actual driver mailbox sequence */
 317         actual_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 318             DRV_MSG_SEQ_NUMBER_MASK;
 319
 320         /* Use MCP history register to check if MCP reset occurred between
 321          * init time and now.
 322          */
 323         if (p_hwfn->mcp_info->mcp_hist !=
 324             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 325                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Rereading MCP offsets\n");
 326                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 327                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 328         }
 329         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 330
 331         /* Set drv param */
 332         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, param);
 333
 334         /* Set drv command along with the updated sequence */
 335         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
 336
 337         do {
 338                 /* Wait for MFW response */
 339                 OSAL_UDELAY(delay);
 340                 *o_mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 341
 342                 /* Give the FW up to 5 second (500*10ms) */
 343         } while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
 344                  (cnt++ < max_retries));
 345
 346         /* Is this a reply to our command? */
 347         if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
 348                 *o_mcp_resp &= FW_MSG_CODE_MASK;
 349                 /* Get the MCP param */
 350                 *o_mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 351         } else {
 352                 /* FW BUG! */
 353                 DP_ERR(p_hwfn, "MFW failed to respond [cmd 0x%x param 0x%x]\n",
 354                        cmd, param);
 355                 *o_mcp_resp = 0;
 356                 rc = ECORE_AGAIN;
 357                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 358         }
 359         return rc;
 360 }
 361
 362 static enum _ecore_status_t
 363 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 364                         struct ecore_ptt *p_ptt,
 365                         struct ecore_mcp_mb_params *p_mb_params)
 366 {
 367         union drv_union_data union_data;
 368         u32 union_data_addr;
 369         enum _ecore_status_t rc;
 370
 371         /* MCP not initialized */
 372         if (!ecore_mcp_is_init(p_hwfn)) {
 373                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 374                 return ECORE_BUSY;
 375         }
 376
 377         if (p_mb_params->data_src_size > sizeof(union_data) ||
 378             p_mb_params->data_dst_size > sizeof(union_data)) {
 379                 DP_ERR(p_hwfn,
 380                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 381                        p_mb_params->data_src_size, p_mb_params->data_dst_size,
 382                        sizeof(union_data));
 383                 return ECORE_INVAL;
 384         }
 385
 386         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 387                           OFFSETOF(struct public_drv_mb, union_data);
 388
 389         /* Ensure that only a single thread is accessing the mailbox at a
 390          * certain time.
 391          */
 392         rc = ecore_mcp_mb_lock(p_hwfn, p_mb_params->cmd);
 393         if (rc != ECORE_SUCCESS)
 394                 return rc;
 395
 396         OSAL_MEM_ZERO(&union_data, sizeof(union_data));
 397         if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
 398                 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
 399                             p_mb_params->data_src_size);
 400         ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 401                         sizeof(union_data));
 402
 403         rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, p_mb_params->cmd,
 404                               p_mb_params->param, &p_mb_params->mcp_resp,
 405                               &p_mb_params->mcp_param);
 406
 407         if (p_mb_params->p_data_dst != OSAL_NULL &&
 408             p_mb_params->data_dst_size)
 409                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 410                                   union_data_addr, p_mb_params->data_dst_size);
 411
 412         ecore_mcp_mb_unlock(p_hwfn, p_mb_params->cmd);
 413
 414         return rc;
 415 }
 416
 417 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 418                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 419                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 420 {
 421         struct ecore_mcp_mb_params mb_params;
 422         enum _ecore_status_t rc;
 423
 424 #ifndef ASIC_ONLY
 425         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 426                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 427                         loaded--;
 428                         loaded_port[p_hwfn->port_id]--;
 429                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 430                                    loaded);
 431                 }
 432                 return ECORE_SUCCESS;
 433         }
 434 #endif
 435
 436         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 437         mb_params.cmd = cmd;
 438         mb_params.param = param;
 439         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 440         if (rc != ECORE_SUCCESS)
 441                 return rc;
 442
 443         *o_mcp_resp = mb_params.mcp_resp;
 444         *o_mcp_param = mb_params.mcp_param;
 445
 446         return ECORE_SUCCESS;
 447 }
 448
 449 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 450                                           struct ecore_ptt *p_ptt,
 451                                           u32 cmd,
 452                                           u32 param,
 453                                           u32 *o_mcp_resp,
 454                                           u32 *o_mcp_param,
 455                                           u32 i_txn_size, u32 *i_buf)
 456 {
 457         struct ecore_mcp_mb_params mb_params;
 458         enum _ecore_status_t rc;
 459
 460         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 461         mb_params.cmd = cmd;
 462         mb_params.param = param;
 463         mb_params.p_data_src = i_buf;
 464         mb_params.data_src_size = (u8)i_txn_size;
 465         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 466         if (rc != ECORE_SUCCESS)
 467                 return rc;
 468
 469         *o_mcp_resp = mb_params.mcp_resp;
 470         *o_mcp_param = mb_params.mcp_param;
 471
 472         return ECORE_SUCCESS;
 473 }
 474
 475 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 476                                           struct ecore_ptt *p_ptt,
 477                                           u32 cmd,
 478                                           u32 param,
 479                                           u32 *o_mcp_resp,
 480                                           u32 *o_mcp_param,
 481                                           u32 *o_txn_size, u32 *o_buf)
 482 {
 483         struct ecore_mcp_mb_params mb_params;
 484         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 485         enum _ecore_status_t rc;
 486
 487         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 488         mb_params.cmd = cmd;
 489         mb_params.param = param;
 490         mb_params.p_data_dst = raw_data;
 491
 492         /* Use the maximal value since the actual one is part of the response */
 493         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 494
 495         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 496         if (rc != ECORE_SUCCESS)
 497                 return rc;
 498
 499         *o_mcp_resp = mb_params.mcp_resp;
 500         *o_mcp_param = mb_params.mcp_param;
 501
 502         *o_txn_size = *o_mcp_param;
 503         /* @DPDK */
 504         OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
 505
 506         return ECORE_SUCCESS;
 507 }
 508
 509 #ifndef ASIC_ONLY
 510 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 511                                     u32 *p_load_code)
 512 {
 513         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 514
 515         if (!loaded)
 516                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 517         else if (!loaded_port[p_hwfn->port_id])
 518                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 519         else
 520                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 521
 522         /* On CMT, always tell that it's engine */
 523         if (p_hwfn->p_dev->num_hwfns > 1)
 524                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 525
 526         *p_load_code = load_phase;
 527         loaded++;
 528         loaded_port[p_hwfn->port_id]++;
 529
 530         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 531                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 532                    *p_load_code, loaded, p_hwfn->port_id,
 533                    loaded_port[p_hwfn->port_id]);
 534 }
 535 #endif
 536
 537 static bool ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role)
 538 {
 539         return (drv_role == DRV_ROLE_OS &&
 540                 exist_drv_role == DRV_ROLE_PREBOOT) ||
 541                (drv_role == DRV_ROLE_KDUMP && exist_drv_role == DRV_ROLE_OS);
 542 }
 543
 544 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
 545                                                       struct ecore_ptt *p_ptt)
 546 {
 547         u32 resp = 0, param = 0;
 548         enum _ecore_status_t rc;
 549
 550         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 551                            &resp, &param);
 552         if (rc != ECORE_SUCCESS)
 553                 DP_NOTICE(p_hwfn, false,
 554                           "Failed to send cancel load request, rc = %d\n", rc);
 555
 556         return rc;
 557 }
 558
 559 #define CONFIG_ECORE_L2_BITMAP_IDX      (0x1 << 0)
 560 #define CONFIG_ECORE_SRIOV_BITMAP_IDX   (0x1 << 1)
 561 #define CONFIG_ECORE_ROCE_BITMAP_IDX    (0x1 << 2)
 562 #define CONFIG_ECORE_IWARP_BITMAP_IDX   (0x1 << 3)
 563 #define CONFIG_ECORE_FCOE_BITMAP_IDX    (0x1 << 4)
 564 #define CONFIG_ECORE_ISCSI_BITMAP_IDX   (0x1 << 5)
 565 #define CONFIG_ECORE_LL2_BITMAP_IDX     (0x1 << 6)
 566
 567 static u32 ecore_get_config_bitmap(void)
 568 {
 569         u32 config_bitmap = 0x0;
 570
 571 #ifdef CONFIG_ECORE_L2
 572         config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
 573 #endif
 574 #ifdef CONFIG_ECORE_SRIOV
 575         config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
 576 #endif
 577 #ifdef CONFIG_ECORE_ROCE
 578         config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
 579 #endif
 580 #ifdef CONFIG_ECORE_IWARP
 581         config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
 582 #endif
 583 #ifdef CONFIG_ECORE_FCOE
 584         config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
 585 #endif
 586 #ifdef CONFIG_ECORE_ISCSI
 587         config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
 588 #endif
 589 #ifdef CONFIG_ECORE_LL2
 590         config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
 591 #endif
 592
 593         return config_bitmap;
 594 }
 595
 596 struct ecore_load_req_in_params {
 597         u8 hsi_ver;
 598 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT  0
 599 #define ECORE_LOAD_REQ_HSI_VER_1        1
 600         u32 drv_ver_0;
 601         u32 drv_ver_1;
 602         u32 fw_ver;
 603         u8 drv_role;
 604         u8 timeout_val;
 605         u8 force_cmd;
 606         bool avoid_eng_reset;
 607 };
 608
 609 struct ecore_load_req_out_params {
 610         u32 load_code;
 611         u32 exist_drv_ver_0;
 612         u32 exist_drv_ver_1;
 613         u32 exist_fw_ver;
 614         u8 exist_drv_role;
 615         u8 mfw_hsi_ver;
 616         bool drv_exists;
 617 };
 618
 619 static enum _ecore_status_t
 620 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 621                      struct ecore_load_req_in_params *p_in_params,
 622                      struct ecore_load_req_out_params *p_out_params)
 623 {
 624         struct ecore_mcp_mb_params mb_params;
 625         struct load_req_stc load_req;
 626         struct load_rsp_stc load_rsp;
 627         u32 hsi_ver;
 628         enum _ecore_status_t rc;
 629
 630         OSAL_MEM_ZERO(&load_req, sizeof(load_req));
 631         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 632         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 633         load_req.fw_ver = p_in_params->fw_ver;
 634         ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE,
 635                             p_in_params->drv_role);
 636         ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 637                             p_in_params->timeout_val);
 638         ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
 639                             p_in_params->force_cmd);
 640         ECORE_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 641                             p_in_params->avoid_eng_reset);
 642
 643         hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
 644                   DRV_ID_MCP_HSI_VER_CURRENT :
 645                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
 646
 647         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 648         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 649         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
 650         mb_params.p_data_src = &load_req;
 651         mb_params.data_src_size = sizeof(load_req);
 652         mb_params.p_data_dst = &load_rsp;
 653         mb_params.data_dst_size = sizeof(load_rsp);
 654
 655         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 656                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 657                    mb_params.param,
 658                    ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 659                    ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 660                    ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 661                    ECORE_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 662
 663         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
 664                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 665                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 666                            load_req.drv_ver_0, load_req.drv_ver_1,
 667                            load_req.fw_ver, load_req.misc0,
 668                            ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 669                            ECORE_MFW_GET_FIELD(load_req.misc0,
 670                                                LOAD_REQ_LOCK_TO),
 671                            ECORE_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 672                            ECORE_MFW_GET_FIELD(load_req.misc0,
 673                                                LOAD_REQ_FLAGS0));
 674
 675         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 676         if (rc != ECORE_SUCCESS) {
 677                 DP_NOTICE(p_hwfn, false,
 678                           "Failed to send load request, rc = %d\n", rc);
 679                 return rc;
 680         }
 681
 682         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 683                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 684         p_out_params->load_code = mb_params.mcp_resp;
 685
 686         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
 687             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 688                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 689                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 690                            load_rsp.drv_ver_0, load_rsp.drv_ver_1,
 691                            load_rsp.fw_ver, load_rsp.misc0,
 692                            ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 693                            ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 694                            ECORE_MFW_GET_FIELD(load_rsp.misc0,
 695                                                LOAD_RSP_FLAGS0));
 696
 697                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 698                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 699                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 700                 p_out_params->exist_drv_role =
 701                         ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 702                 p_out_params->mfw_hsi_ver =
 703                         ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 704                 p_out_params->drv_exists =
 705                         ECORE_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 706                         LOAD_RSP_FLAGS0_DRV_EXISTS;
 707         }
 708
 709         return ECORE_SUCCESS;
 710 }
 711
 712 static enum _ecore_status_t eocre_get_mfw_drv_role(struct ecore_hwfn *p_hwfn,
 713                                                    enum ecore_drv_role drv_role,
 714                                                    u8 *p_mfw_drv_role)
 715 {
 716         switch (drv_role) {
 717         case ECORE_DRV_ROLE_OS:
 718                 *p_mfw_drv_role = DRV_ROLE_OS;
 719                 break;
 720         case ECORE_DRV_ROLE_KDUMP:
 721                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 722                 break;
 723         default:
 724                 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
 725                 return ECORE_INVAL;
 726         }
 727
 728         return ECORE_SUCCESS;
 729 }
 730
 731 enum ecore_load_req_force {
 732         ECORE_LOAD_REQ_FORCE_NONE,
 733         ECORE_LOAD_REQ_FORCE_PF,
 734         ECORE_LOAD_REQ_FORCE_ALL,
 735 };
 736
 737 static enum _ecore_status_t
 738 ecore_get_mfw_force_cmd(struct ecore_hwfn *p_hwfn,
 739                         enum ecore_load_req_force force_cmd,
 740                         u8 *p_mfw_force_cmd)
 741 {
 742         switch (force_cmd) {
 743         case ECORE_LOAD_REQ_FORCE_NONE:
 744                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 745                 break;
 746         case ECORE_LOAD_REQ_FORCE_PF:
 747                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 748                 break;
 749         case ECORE_LOAD_REQ_FORCE_ALL:
 750                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 751                 break;
 752         default:
 753                 DP_ERR(p_hwfn, "Unexpected force value %d\n", force_cmd);
 754                 return ECORE_INVAL;
 755         }
 756
 757         return ECORE_SUCCESS;
 758 }
 759
 760 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 761                                         struct ecore_ptt *p_ptt,
 762                                         struct ecore_load_req_params *p_params)
 763 {
 764         struct ecore_load_req_out_params out_params;
 765         struct ecore_load_req_in_params in_params;
 766         u8 mfw_drv_role, mfw_force_cmd;
 767         enum _ecore_status_t rc;
 768
 769 #ifndef ASIC_ONLY
 770         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 771                 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
 772                 return ECORE_SUCCESS;
 773         }
 774 #endif
 775
 776         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
 777         in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
 778         in_params.drv_ver_0 = ECORE_VERSION;
 779         in_params.drv_ver_1 = ecore_get_config_bitmap();
 780         in_params.fw_ver = STORM_FW_VERSION;
 781         rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
 782         if (rc != ECORE_SUCCESS)
 783                 return rc;
 784
 785         in_params.drv_role = mfw_drv_role;
 786         in_params.timeout_val = p_params->timeout_val;
 787         rc = ecore_get_mfw_force_cmd(p_hwfn, ECORE_LOAD_REQ_FORCE_NONE,
 788                                      &mfw_force_cmd);
 789         if (rc != ECORE_SUCCESS)
 790                 return rc;
 791
 792         in_params.force_cmd = mfw_force_cmd;
 793         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 794
 795         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 796         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 797         if (rc != ECORE_SUCCESS)
 798                 return rc;
 799
 800         /* First handle cases where another load request should/might be sent:
 801          * - MFW expects the old interface [HSI version = 1]
 802          * - MFW responds that a force load request is required
 803          */
 804         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 805                 DP_INFO(p_hwfn,
 806                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
 807
 808                 /* The previous load request set the mailbox blocking */
 809                 p_hwfn->mcp_info->block_mb_sending = false;
 810
 811                 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
 812                 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 813                 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
 814                                           &out_params);
 815                 if (rc != ECORE_SUCCESS)
 816                         return rc;
 817         } else if (out_params.load_code ==
 818                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 819                 /* The previous load request set the mailbox blocking */
 820                 p_hwfn->mcp_info->block_mb_sending = false;
 821
 822                 if (ecore_mcp_can_force_load(in_params.drv_role,
 823                                              out_params.exist_drv_role)) {
 824                         DP_INFO(p_hwfn,
 825                                 "A force load is required [existing: role %d, fw_ver 0x%08x, drv_ver 0x%08x_0x%08x]. Sending a force load request.\n",
 826                                 out_params.exist_drv_role,
 827                                 out_params.exist_fw_ver,
 828                                 out_params.exist_drv_ver_0,
 829                                 out_params.exist_drv_ver_1);
 830
 831                         rc = ecore_get_mfw_force_cmd(p_hwfn,
 832                                                      ECORE_LOAD_REQ_FORCE_ALL,
 833                                                      &mfw_force_cmd);
 834                         if (rc != ECORE_SUCCESS)
 835                                 return rc;
 836
 837                         in_params.force_cmd = mfw_force_cmd;
 838                         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 839                         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
 840                                                   &out_params);
 841                         if (rc != ECORE_SUCCESS)
 842                                 return rc;
 843                 } else {
 844                         DP_NOTICE(p_hwfn, false,
 845                                   "A force load is required [existing: role %d, fw_ver 0x%08x, drv_ver 0x%08x_0x%08x]. Avoiding to prevent disruption of active PFs.\n",
 846                                   out_params.exist_drv_role,
 847                                   out_params.exist_fw_ver,
 848                                   out_params.exist_drv_ver_0,
 849                                   out_params.exist_drv_ver_1);
 850
 851                         ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
 852                         return ECORE_BUSY;
 853                 }
 854         }
 855
 856         /* Now handle the other types of responses.
 857          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
 858          * expected here after the additional revised load requests were sent.
 859          */
 860         switch (out_params.load_code) {
 861         case FW_MSG_CODE_DRV_LOAD_ENGINE:
 862         case FW_MSG_CODE_DRV_LOAD_PORT:
 863         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
 864                 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
 865                     out_params.drv_exists) {
 866                         /* The role and fw/driver version match, but the PF is
 867                          * already loaded and has not been unloaded gracefully.
 868                          * This is unexpected since a quasi-FLR request was
 869                          * previously sent as part of ecore_hw_prepare().
 870                          */
 871                         DP_NOTICE(p_hwfn, false,
 872                                   "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
 873                         return ECORE_INVAL;
 874                 }
 875                 break;
 876         case FW_MSG_CODE_DRV_LOAD_REFUSED_PDA:
 877         case FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG:
 878         case FW_MSG_CODE_DRV_LOAD_REFUSED_HSI:
 879         case FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT:
 880                 DP_NOTICE(p_hwfn, false,
 881                           "MFW refused a load request [resp 0x%08x]. Aborting.\n",
 882                           out_params.load_code);
 883                 return ECORE_BUSY;
 884         default:
 885                 DP_NOTICE(p_hwfn, false,
 886                           "Unexpected response to load request [resp 0x%08x]. Aborting.\n",
 887                           out_params.load_code);
 888                 break;
 889         }
 890
 891         p_params->load_code = out_params.load_code;
 892
 893         return ECORE_SUCCESS;
 894 }
 895
 896 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
 897                                          struct ecore_ptt *p_ptt)
 898 {
 899         u32 resp = 0, param = 0;
 900         enum _ecore_status_t rc;
 901
 902         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
 903                            &param);
 904         if (rc != ECORE_SUCCESS) {
 905                 DP_NOTICE(p_hwfn, false,
 906                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
 907                 return rc;
 908         }
 909
 910 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR     (1 << 0)
 911
 912         /* Check if there is a DID mismatch between nvm-cfg/efuse */
 913         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
 914                 DP_NOTICE(p_hwfn, false,
 915                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
 916
 917         return ECORE_SUCCESS;
 918 }
 919
 920 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
 921                                           struct ecore_ptt *p_ptt)
 922 {
 923         u32 wol_param, mcp_resp, mcp_param;
 924
 925         /* @DPDK */
 926         wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
 927
 928         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
 929                              &mcp_resp, &mcp_param);
 930 }
 931
 932 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
 933                                            struct ecore_ptt *p_ptt)
 934 {
 935         struct ecore_mcp_mb_params mb_params;
 936         struct mcp_mac wol_mac;
 937
 938         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 939         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
 940
 941         return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 942 }
 943
 944 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
 945                                     struct ecore_ptt *p_ptt)
 946 {
 947         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 948                                         PUBLIC_PATH);
 949         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 950         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
 951                                      ECORE_PATH_ID(p_hwfn));
 952         u32 disabled_vfs[VF_MAX_STATIC / 32];
 953         int i;
 954
 955         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 956                    "Reading Disabled VF information from [offset %08x],"
 957                    " path_addr %08x\n",
 958                    mfw_path_offsize, path_addr);
 959
 960         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
 961                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
 962                                            path_addr +
 963                                            OFFSETOF(struct public_path,
 964                                                     mcp_vf_disabled) +
 965                                            sizeof(u32) * i);
 966                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 967                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
 968                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
 969         }
 970
 971         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
 972                 OSAL_VF_FLR_UPDATE(p_hwfn);
 973 }
 974
 975 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
 976                                           struct ecore_ptt *p_ptt,
 977                                           u32 *vfs_to_ack)
 978 {
 979         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
 980                                         PUBLIC_FUNC);
 981         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
 982         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
 983                                      MCP_PF_ID(p_hwfn));
 984         struct ecore_mcp_mb_params mb_params;
 985         enum _ecore_status_t rc;
 986         int i;
 987
 988         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
 989                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
 990                            "Acking VFs [%08x,...,%08x] - %08x\n",
 991                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
 992
 993         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 994         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
 995         mb_params.p_data_src = vfs_to_ack;
 996         mb_params.data_src_size = VF_MAX_STATIC / 8;
 997         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
 998                                      &mb_params);
 999         if (rc != ECORE_SUCCESS) {
1000                 DP_NOTICE(p_hwfn, false,
1001                           "Failed to pass ACK for VF flr to MFW\n");
1002                 return ECORE_TIMEOUT;
1003         }
1004
1005         /* TMP - clear the ACK bits; should be done by MFW */
1006         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1007                 ecore_wr(p_hwfn, p_ptt,
1008                          func_addr +
1009                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1010                          i * sizeof(u32), 0);
1011
1012         return rc;
1013 }
1014
1015 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1016                                                 struct ecore_ptt *p_ptt)
1017 {
1018         u32 transceiver_state;
1019
1020         transceiver_state = ecore_rd(p_hwfn, p_ptt,
1021                                      p_hwfn->mcp_info->port_addr +
1022                                      OFFSETOF(struct public_port,
1023                                               transceiver_data));
1024
1025         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1026                    "Received transceiver state update [0x%08x] from mfw"
1027                    " [Addr 0x%x]\n",
1028                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1029                                             OFFSETOF(struct public_port,
1030                                                      transceiver_data)));
1031
1032         transceiver_state = GET_FIELD(transceiver_state, ETH_TRANSCEIVER_STATE);
1033
1034         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1035                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1036         else
1037                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1038 }
1039
1040 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1041                                          struct ecore_ptt *p_ptt,
1042                                          bool b_reset)
1043 {
1044         struct ecore_mcp_link_state *p_link;
1045         u8 max_bw, min_bw;
1046         u32 status = 0;
1047
1048         p_link = &p_hwfn->mcp_info->link_output;
1049         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1050         if (!b_reset) {
1051                 status = ecore_rd(p_hwfn, p_ptt,
1052                                   p_hwfn->mcp_info->port_addr +
1053                                   OFFSETOF(struct public_port, link_status));
1054                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1055                            "Received link update [0x%08x] from mfw"
1056                            " [Addr 0x%x]\n",
1057                            status, (u32)(p_hwfn->mcp_info->port_addr +
1058                                           OFFSETOF(struct public_port,
1059                                                    link_status)));
1060         } else {
1061                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1062                            "Resetting link indications\n");
1063                 return;
1064         }
1065
1066         if (p_hwfn->b_drv_link_init)
1067                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1068         else
1069                 p_link->link_up = false;
1070
1071         p_link->full_duplex = true;
1072         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1073         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1074                 p_link->speed = 100000;
1075                 break;
1076         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1077                 p_link->speed = 50000;
1078                 break;
1079         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1080                 p_link->speed = 40000;
1081                 break;
1082         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1083                 p_link->speed = 25000;
1084                 break;
1085         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1086                 p_link->speed = 20000;
1087                 break;
1088         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1089                 p_link->speed = 10000;
1090                 break;
1091         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1092                 p_link->full_duplex = false;
1093                 /* Fall-through */
1094         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1095                 p_link->speed = 1000;
1096                 break;
1097         default:
1098                 p_link->speed = 0;
1099         }
1100
1101         /* We never store total line speed as p_link->speed is
1102          * again changes according to bandwidth allocation.
1103          */
1104         if (p_link->link_up && p_link->speed)
1105                 p_link->line_speed = p_link->speed;
1106         else
1107                 p_link->line_speed = 0;
1108
1109         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1110         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1111
1112         /* Max bandwidth configuration */
1113         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1114                                            p_link, max_bw);
1115
1116         /* Mintz bandwidth configuration */
1117         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1118                                            p_link, min_bw);
1119         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,
1120                                               p_link->min_pf_rate);
1121
1122         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1123         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1124         p_link->parallel_detection = !!(status &
1125                                          LINK_STATUS_PARALLEL_DETECTION_USED);
1126         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1127
1128         p_link->partner_adv_speed |=
1129             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1130             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1131         p_link->partner_adv_speed |=
1132             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1133             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1134         p_link->partner_adv_speed |=
1135             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1136             ECORE_LINK_PARTNER_SPEED_10G : 0;
1137         p_link->partner_adv_speed |=
1138             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1139             ECORE_LINK_PARTNER_SPEED_20G : 0;
1140         p_link->partner_adv_speed |=
1141             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1142             ECORE_LINK_PARTNER_SPEED_25G : 0;
1143         p_link->partner_adv_speed |=
1144             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1145             ECORE_LINK_PARTNER_SPEED_40G : 0;
1146         p_link->partner_adv_speed |=
1147             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1148             ECORE_LINK_PARTNER_SPEED_50G : 0;
1149         p_link->partner_adv_speed |=
1150             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1151             ECORE_LINK_PARTNER_SPEED_100G : 0;
1152
1153         p_link->partner_tx_flow_ctrl_en =
1154             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1155         p_link->partner_rx_flow_ctrl_en =
1156             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1157
1158         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1159         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1160                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1161                 break;
1162         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1163                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1164                 break;
1165         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1166                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1167                 break;
1168         default:
1169                 p_link->partner_adv_pause = 0;
1170         }
1171
1172         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1173
1174         OSAL_LINK_UPDATE(p_hwfn);
1175 }
1176
1177 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1178                                         struct ecore_ptt *p_ptt, bool b_up)
1179 {
1180         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1181         struct ecore_mcp_mb_params mb_params;
1182         struct eth_phy_cfg phy_cfg;
1183         enum _ecore_status_t rc = ECORE_SUCCESS;
1184         u32 cmd;
1185
1186 #ifndef ASIC_ONLY
1187         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1188                 return ECORE_SUCCESS;
1189 #endif
1190
1191         /* Set the shmem configuration according to params */
1192         OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1193         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1194         if (!params->speed.autoneg)
1195                 phy_cfg.speed = params->speed.forced_speed;
1196         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1197         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1198         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1199         phy_cfg.adv_speed = params->speed.advertised_speeds;
1200         phy_cfg.loopback_mode = params->loopback_mode;
1201         p_hwfn->b_drv_link_init = b_up;
1202
1203         if (b_up)
1204                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1205                            "Configuring Link: Speed 0x%08x, Pause 0x%08x,"
1206                            " adv_speed 0x%08x, loopback 0x%08x\n",
1207                            phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1208                            phy_cfg.loopback_mode);
1209         else
1210                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1211
1212         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1213         mb_params.cmd = cmd;
1214         mb_params.p_data_src = &phy_cfg;
1215         mb_params.data_src_size = sizeof(phy_cfg);
1216         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1217
1218         /* if mcp fails to respond we must abort */
1219         if (rc != ECORE_SUCCESS) {
1220                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1221                 return rc;
1222         }
1223
1224         /* Reset the link status if needed */
1225         if (!b_up)
1226                 ecore_mcp_handle_link_change(p_hwfn, p_ptt, true);
1227
1228         return rc;
1229 }
1230
1231 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1232                                    struct ecore_ptt *p_ptt)
1233 {
1234         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1235
1236         /* TODO - Add support for VFs */
1237         if (IS_VF(p_hwfn->p_dev))
1238                 return ECORE_INVAL;
1239
1240         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1241                                                  PUBLIC_PATH);
1242         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1243         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1244
1245         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1246                                  path_addr +
1247                                  OFFSETOF(struct public_path, process_kill)) &
1248             PROCESS_KILL_COUNTER_MASK;
1249
1250         return proc_kill_cnt;
1251 }
1252
1253 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1254                                           struct ecore_ptt *p_ptt)
1255 {
1256         struct ecore_dev *p_dev = p_hwfn->p_dev;
1257         u32 proc_kill_cnt;
1258
1259         /* Prevent possible attentions/interrupts during the recovery handling
1260          * and till its load phase, during which they will be re-enabled.
1261          */
1262         ecore_int_igu_disable_int(p_hwfn, p_ptt);
1263
1264         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1265
1266         /* The following operations should be done once, and thus in CMT mode
1267          * are carried out by only the first HW function.
1268          */
1269         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1270                 return;
1271
1272         if (p_dev->recov_in_prog) {
1273                 DP_NOTICE(p_hwfn, false,
1274                           "Ignoring the indication since a recovery"
1275                           " process is already in progress\n");
1276                 return;
1277         }
1278
1279         p_dev->recov_in_prog = true;
1280
1281         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1282         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1283
1284         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1285 }
1286
1287 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1288                                           struct ecore_ptt *p_ptt,
1289                                           enum MFW_DRV_MSG_TYPE type)
1290 {
1291         enum ecore_mcp_protocol_type stats_type;
1292         union ecore_mcp_protocol_stats stats;
1293         struct ecore_mcp_mb_params mb_params;
1294         u32 hsi_param;
1295         enum _ecore_status_t rc;
1296
1297         switch (type) {
1298         case MFW_DRV_MSG_GET_LAN_STATS:
1299                 stats_type = ECORE_MCP_LAN_STATS;
1300                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1301                 break;
1302         default:
1303                 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1304                 return;
1305         }
1306
1307         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1308
1309         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1310         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1311         mb_params.param = hsi_param;
1312         mb_params.p_data_src = &stats;
1313         mb_params.data_src_size = sizeof(stats);
1314         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1315         if (rc != ECORE_SUCCESS)
1316                 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1317 }
1318
1319 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1320                                     struct public_func *p_shmem_info)
1321 {
1322         struct ecore_mcp_function_info *p_info;
1323
1324         p_info = &p_hwfn->mcp_info->func_info;
1325
1326         /* TODO - bandwidth min/max should have valid values of 1-100,
1327          * as well as some indication that the feature is disabled.
1328          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1329          * limit and correct value to min `1' and max `100' if limit isn't in
1330          * range.
1331          */
1332         p_info->bandwidth_min = (p_shmem_info->config &
1333                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1334             FUNC_MF_CFG_MIN_BW_SHIFT;
1335         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1336                 DP_INFO(p_hwfn,
1337                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1338                         p_info->bandwidth_min);
1339                 p_info->bandwidth_min = 1;
1340         }
1341
1342         p_info->bandwidth_max = (p_shmem_info->config &
1343                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1344             FUNC_MF_CFG_MAX_BW_SHIFT;
1345         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1346                 DP_INFO(p_hwfn,
1347                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1348                         p_info->bandwidth_max);
1349                 p_info->bandwidth_max = 100;
1350         }
1351 }
1352
1353 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1354                                     struct ecore_ptt *p_ptt,
1355                                     struct public_func *p_data,
1356                                     int pfid)
1357 {
1358         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1359                                         PUBLIC_FUNC);
1360         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1361         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1362         u32 i, size;
1363
1364         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1365
1366         size = OSAL_MIN_T(u32, sizeof(*p_data),
1367                           SECTION_SIZE(mfw_path_offsize));
1368         for (i = 0; i < size / sizeof(u32); i++)
1369                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1370                                               func_addr + (i << 2));
1371
1372         return size;
1373 }
1374
1375 static void
1376 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1377 {
1378         struct ecore_mcp_function_info *p_info;
1379         struct public_func shmem_info;
1380         u32 resp = 0, param = 0;
1381
1382         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1383
1384         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1385
1386         p_info = &p_hwfn->mcp_info->func_info;
1387
1388         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1389
1390         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1391
1392         /* Acknowledge the MFW */
1393         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1394                       &param);
1395 }
1396
1397 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn,
1398                                          struct ecore_ptt *p_ptt)
1399 {
1400         /* A single notification should be sent to upper driver in CMT mode */
1401         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1402                 return;
1403
1404         DP_NOTICE(p_hwfn, false,
1405                   "Fan failure was detected on the network interface card"
1406                   " and it's going to be shut down.\n");
1407
1408         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1409 }
1410
1411 struct ecore_mdump_cmd_params {
1412         u32 cmd;
1413         void *p_data_src;
1414         u8 data_src_size;
1415         void *p_data_dst;
1416         u8 data_dst_size;
1417         u32 mcp_resp;
1418 };
1419
1420 static enum _ecore_status_t
1421 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1422                     struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1423 {
1424         struct ecore_mcp_mb_params mb_params;
1425         enum _ecore_status_t rc;
1426
1427         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1428         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1429         mb_params.param = p_mdump_cmd_params->cmd;
1430         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1431         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1432         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1433         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1434         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1435         if (rc != ECORE_SUCCESS)
1436                 return rc;
1437
1438         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1439         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1440                 DP_NOTICE(p_hwfn, false,
1441                           "MFW claims that the mdump command is illegal [mdump_cmd 0x%x]\n",
1442                           p_mdump_cmd_params->cmd);
1443                 rc = ECORE_INVAL;
1444         }
1445
1446         return rc;
1447 }
1448
1449 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1450                                                 struct ecore_ptt *p_ptt)
1451 {
1452         struct ecore_mdump_cmd_params mdump_cmd_params;
1453
1454         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1455         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1456
1457         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1458 }
1459
1460 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1461                                                 struct ecore_ptt *p_ptt,
1462                                                 u32 epoch)
1463 {
1464         struct ecore_mdump_cmd_params mdump_cmd_params;
1465
1466         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1467         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1468         mdump_cmd_params.p_data_src = &epoch;
1469         mdump_cmd_params.data_src_size = sizeof(epoch);
1470
1471         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1472 }
1473
1474 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1475                                              struct ecore_ptt *p_ptt)
1476 {
1477         struct ecore_mdump_cmd_params mdump_cmd_params;
1478
1479         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1480         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1481
1482         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1483 }
1484
1485 static enum _ecore_status_t
1486 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1487                            struct mdump_config_stc *p_mdump_config)
1488 {
1489         struct ecore_mdump_cmd_params mdump_cmd_params;
1490         enum _ecore_status_t rc;
1491
1492         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1493         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1494         mdump_cmd_params.p_data_dst = p_mdump_config;
1495         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1496
1497         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1498         if (rc != ECORE_SUCCESS)
1499                 return rc;
1500
1501         if (mdump_cmd_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1502                 DP_INFO(p_hwfn,
1503                         "The mdump command is not supported by the MFW\n");
1504                 return ECORE_NOTIMPL;
1505         }
1506
1507         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1508                 DP_NOTICE(p_hwfn, false,
1509                           "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1510                           mdump_cmd_params.mcp_resp);
1511                 rc = ECORE_UNKNOWN_ERROR;
1512         }
1513
1514         return rc;
1515 }
1516
1517 enum _ecore_status_t
1518 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1519                          struct ecore_mdump_info *p_mdump_info)
1520 {
1521         u32 addr, global_offsize, global_addr;
1522         struct mdump_config_stc mdump_config;
1523         enum _ecore_status_t rc;
1524
1525         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1526
1527         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1528                                     PUBLIC_GLOBAL);
1529         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1530         global_addr = SECTION_ADDR(global_offsize, 0);
1531         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1532                                         global_addr +
1533                                         OFFSETOF(struct public_global,
1534                                                  mdump_reason));
1535
1536         if (p_mdump_info->reason) {
1537                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1538                 if (rc != ECORE_SUCCESS)
1539                         return rc;
1540
1541                 p_mdump_info->version = mdump_config.version;
1542                 p_mdump_info->config = mdump_config.config;
1543                 p_mdump_info->epoch = mdump_config.epoc;
1544                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1545                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1546
1547                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1548                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1549                            p_mdump_info->reason, p_mdump_info->version,
1550                            p_mdump_info->config, p_mdump_info->epoch,
1551                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1552         } else {
1553                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1554                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1555         }
1556
1557         return ECORE_SUCCESS;
1558 }
1559
1560 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1561                                                 struct ecore_ptt *p_ptt)
1562 {
1563         struct ecore_mdump_cmd_params mdump_cmd_params;
1564
1565         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1566         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1567
1568         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1569 }
1570
1571 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1572                                             struct ecore_ptt *p_ptt)
1573 {
1574         /* In CMT mode - no need for more than a single acknowledgment to the
1575          * MFW, and no more than a single notification to the upper driver.
1576          */
1577         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1578                 return;
1579
1580         DP_NOTICE(p_hwfn, false,
1581                   "Received a critical error notification from the MFW!\n");
1582
1583         if (p_hwfn->p_dev->allow_mdump) {
1584                 DP_NOTICE(p_hwfn, false,
1585                           "Not acknowledging the notification to allow the MFW crash dump\n");
1586                 return;
1587         }
1588
1589         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1590         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1591 }
1592
1593 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1594                                              struct ecore_ptt *p_ptt)
1595 {
1596         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1597         enum _ecore_status_t rc = ECORE_SUCCESS;
1598         bool found = false;
1599         u16 i;
1600
1601         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1602
1603         /* Read Messages from MFW */
1604         ecore_mcp_read_mb(p_hwfn, p_ptt);
1605
1606         /* Compare current messages to old ones */
1607         for (i = 0; i < info->mfw_mb_length; i++) {
1608                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1609                         continue;
1610
1611                 found = true;
1612
1613                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1614                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1615                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1616
1617                 switch (i) {
1618                 case MFW_DRV_MSG_LINK_CHANGE:
1619                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1620                         break;
1621                 case MFW_DRV_MSG_VF_DISABLED:
1622                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1623                         break;
1624                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1625                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1626                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1627                         break;
1628                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1629                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1630                                                     ECORE_DCBX_REMOTE_MIB);
1631                         break;
1632                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1633                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1634                                                     ECORE_DCBX_OPERATIONAL_MIB);
1635                         break;
1636                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1637                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1638                         break;
1639                 case MFW_DRV_MSG_ERROR_RECOVERY:
1640                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1641                         break;
1642                 case MFW_DRV_MSG_GET_LAN_STATS:
1643                 case MFW_DRV_MSG_GET_FCOE_STATS:
1644                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1645                 case MFW_DRV_MSG_GET_RDMA_STATS:
1646                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1647                         break;
1648                 case MFW_DRV_MSG_BW_UPDATE:
1649                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1650                         break;
1651                 case MFW_DRV_MSG_FAILURE_DETECTED:
1652                         ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
1653                         break;
1654                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1655                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1656                         break;
1657                 default:
1658                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1659                         rc = ECORE_INVAL;
1660                 }
1661         }
1662
1663         /* ACK everything */
1664         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1665                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1666
1667                 /* MFW expect answer in BE, so we force write in that format */
1668                 ecore_wr(p_hwfn, p_ptt,
1669                          info->mfw_mb_addr + sizeof(u32) +
1670                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1671                          sizeof(u32) + i * sizeof(u32), val);
1672         }
1673
1674         if (!found) {
1675                 DP_NOTICE(p_hwfn, false,
1676                           "Received an MFW message indication but no"
1677                           " new message!\n");
1678                 rc = ECORE_INVAL;
1679         }
1680
1681         /* Copy the new mfw messages into the shadow */
1682         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1683
1684         return rc;
1685 }
1686
1687 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1688                                            struct ecore_ptt *p_ptt,
1689                                            u32 *p_mfw_ver,
1690                                            u32 *p_running_bundle_id)
1691 {
1692         u32 global_offsize;
1693
1694 #ifndef ASIC_ONLY
1695         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1696                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1697                 return ECORE_SUCCESS;
1698         }
1699 #endif
1700
1701         if (IS_VF(p_hwfn->p_dev)) {
1702                 if (p_hwfn->vf_iov_info) {
1703                         struct pfvf_acquire_resp_tlv *p_resp;
1704
1705                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1706                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1707                         return ECORE_SUCCESS;
1708                 } else {
1709                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1710                                    "VF requested MFW version prior to ACQUIRE\n");
1711                         return ECORE_INVAL;
1712                 }
1713         }
1714
1715         global_offsize = ecore_rd(p_hwfn, p_ptt,
1716                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1717                                                        public_base,
1718                                                        PUBLIC_GLOBAL));
1719         *p_mfw_ver =
1720             ecore_rd(p_hwfn, p_ptt,
1721                      SECTION_ADDR(global_offsize,
1722                                   0) + OFFSETOF(struct public_global, mfw_ver));
1723
1724         if (p_running_bundle_id != OSAL_NULL) {
1725                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1726                                                 SECTION_ADDR(global_offsize,
1727                                                              0) +
1728                                                 OFFSETOF(struct public_global,
1729                                                          running_bundle_id));
1730         }
1731
1732         return ECORE_SUCCESS;
1733 }
1734
1735 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_dev *p_dev,
1736                                               u32 *p_media_type)
1737 {
1738         struct ecore_hwfn *p_hwfn = &p_dev->hwfns[0];
1739         struct ecore_ptt *p_ptt;
1740
1741         /* TODO - Add support for VFs */
1742         if (IS_VF(p_dev))
1743                 return ECORE_INVAL;
1744
1745         if (!ecore_mcp_is_init(p_hwfn)) {
1746                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
1747                 return ECORE_BUSY;
1748         }
1749
1750         *p_media_type = MEDIA_UNSPECIFIED;
1751
1752         p_ptt = ecore_ptt_acquire(p_hwfn);
1753         if (!p_ptt)
1754                 return ECORE_BUSY;
1755
1756         *p_media_type = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1757                                  OFFSETOF(struct public_port, media_type));
1758
1759         ecore_ptt_release(p_hwfn, p_ptt);
1760
1761         return ECORE_SUCCESS;
1762 }
1763
1764 /* @DPDK */
1765 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1766 static void
1767 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
1768                                  enum ecore_pci_personality *p_proto)
1769 {
1770         *p_proto = ECORE_PCI_ETH;
1771
1772         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1773                    "According to Legacy capabilities, L2 personality is %08x\n",
1774                    (u32)*p_proto);
1775 }
1776
1777 /* @DPDK */
1778 static enum _ecore_status_t
1779 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
1780                               struct ecore_ptt *p_ptt,
1781                               enum ecore_pci_personality *p_proto)
1782 {
1783         u32 resp = 0, param = 0;
1784         enum _ecore_status_t rc;
1785
1786         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
1787                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1788                    (u32)*p_proto, resp, param);
1789         return ECORE_SUCCESS;
1790 }
1791
1792 static enum _ecore_status_t
1793 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
1794                           struct public_func *p_info,
1795                           struct ecore_ptt *p_ptt,
1796                           enum ecore_pci_personality *p_proto)
1797 {
1798         enum _ecore_status_t rc = ECORE_SUCCESS;
1799
1800         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1801         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1802                 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
1803                     ECORE_SUCCESS)
1804                         ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1805                 break;
1806         default:
1807                 rc = ECORE_INVAL;
1808         }
1809
1810         return rc;
1811 }
1812
1813 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
1814                                                     struct ecore_ptt *p_ptt)
1815 {
1816         struct ecore_mcp_function_info *info;
1817         struct public_func shmem_info;
1818
1819         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1820         info = &p_hwfn->mcp_info->func_info;
1821
1822         info->pause_on_host = (shmem_info.config &
1823                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1824
1825         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1826                                       &info->protocol)) {
1827                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1828                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1829                 return ECORE_INVAL;
1830         }
1831
1832         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1833
1834         if (shmem_info.mac_upper || shmem_info.mac_lower) {
1835                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1836                 info->mac[1] = (u8)(shmem_info.mac_upper);
1837                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1838                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1839                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1840                 info->mac[5] = (u8)(shmem_info.mac_lower);
1841         } else {
1842                 /* TODO - are there protocols for which there's no MAC? */
1843                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
1844         }
1845
1846         /* TODO - are these calculations true for BE machine? */
1847         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
1848                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
1849         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
1850                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
1851
1852         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1853
1854         info->mtu = (u16)shmem_info.mtu_size;
1855
1856         if (info->mtu == 0)
1857                 info->mtu = 1500;
1858
1859         info->mtu = (u16)shmem_info.mtu_size;
1860
1861         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
1862                    "Read configuration from shmem: pause_on_host %02x"
1863                     " protocol %02x BW [%02x - %02x]"
1864                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
1865                     " node %lx ovlan %04x\n",
1866                    info->pause_on_host, info->protocol,
1867                    info->bandwidth_min, info->bandwidth_max,
1868                    info->mac[0], info->mac[1], info->mac[2],
1869                    info->mac[3], info->mac[4], info->mac[5],
1870                    (unsigned long)info->wwn_port,
1871                    (unsigned long)info->wwn_node, info->ovlan);
1872
1873         return ECORE_SUCCESS;
1874 }
1875
1876 struct ecore_mcp_link_params
1877 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
1878 {
1879         if (!p_hwfn || !p_hwfn->mcp_info)
1880                 return OSAL_NULL;
1881         return &p_hwfn->mcp_info->link_input;
1882 }
1883
1884 struct ecore_mcp_link_state
1885 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
1886 {
1887         if (!p_hwfn || !p_hwfn->mcp_info)
1888                 return OSAL_NULL;
1889
1890 #ifndef ASIC_ONLY
1891         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
1892                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
1893                 p_hwfn->mcp_info->link_output.link_up = true;
1894         }
1895 #endif
1896
1897         return &p_hwfn->mcp_info->link_output;
1898 }
1899
1900 struct ecore_mcp_link_capabilities
1901 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
1902 {
1903         if (!p_hwfn || !p_hwfn->mcp_info)
1904                 return OSAL_NULL;
1905         return &p_hwfn->mcp_info->link_capabilities;
1906 }
1907
1908 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
1909                                      struct ecore_ptt *p_ptt)
1910 {
1911         u32 resp = 0, param = 0;
1912         enum _ecore_status_t rc;
1913
1914         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
1915                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1916
1917         /* Wait for the drain to complete before returning */
1918         OSAL_MSLEEP(1020);
1919
1920         return rc;
1921 }
1922
1923 const struct ecore_mcp_function_info
1924 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
1925 {
1926         if (!p_hwfn || !p_hwfn->mcp_info)
1927                 return OSAL_NULL;
1928         return &p_hwfn->mcp_info->func_info;
1929 }
1930
1931 enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
1932                                            struct ecore_ptt *p_ptt,
1933                                            struct ecore_mcp_nvm_params *params)
1934 {
1935         enum _ecore_status_t rc;
1936
1937         switch (params->type) {
1938         case ECORE_MCP_NVM_RD:
1939                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1940                                           params->nvm_common.offset,
1941                                           &params->nvm_common.resp,
1942                                           &params->nvm_common.param,
1943                                           params->nvm_rd.buf_size,
1944                                           params->nvm_rd.buf);
1945                 break;
1946         case ECORE_MCP_CMD:
1947                 rc = ecore_mcp_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1948                                    params->nvm_common.offset,
1949                                    &params->nvm_common.resp,
1950                                    &params->nvm_common.param);
1951                 break;
1952         case ECORE_MCP_NVM_WR:
1953                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, params->nvm_common.cmd,
1954                                           params->nvm_common.offset,
1955                                           &params->nvm_common.resp,
1956                                           &params->nvm_common.param,
1957                                           params->nvm_wr.buf_size,
1958                                           params->nvm_wr.buf);
1959                 break;
1960         default:
1961                 rc = ECORE_NOTIMPL;
1962                 break;
1963         }
1964         return rc;
1965 }
1966
1967 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
1968                                   struct ecore_ptt *p_ptt, u32 personalities)
1969 {
1970         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
1971         struct public_func shmem_info;
1972         int i, count = 0, num_pfs;
1973
1974         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
1975
1976         for (i = 0; i < num_pfs; i++) {
1977                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1978                                          MCP_PF_ID_BY_REL(p_hwfn, i));
1979                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
1980                         continue;
1981
1982                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1983                                               &protocol) !=
1984                     ECORE_SUCCESS)
1985                         continue;
1986
1987                 if ((1 << ((u32)protocol)) & personalities)
1988                         count++;
1989         }
1990
1991         return count;
1992 }
1993
1994 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
1995                                               struct ecore_ptt *p_ptt,
1996                                               u32 *p_flash_size)
1997 {
1998         u32 flash_size;
1999
2000 #ifndef ASIC_ONLY
2001         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2002                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2003                 return ECORE_INVAL;
2004         }
2005 #endif
2006
2007         if (IS_VF(p_hwfn->p_dev))
2008                 return ECORE_INVAL;
2009
2010         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2011         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2012             MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2013         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
2014
2015         *p_flash_size = flash_size;
2016
2017         return ECORE_SUCCESS;
2018 }
2019
2020 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2021                                                   struct ecore_ptt *p_ptt)
2022 {
2023         struct ecore_dev *p_dev = p_hwfn->p_dev;
2024
2025         if (p_dev->recov_in_prog) {
2026                 DP_NOTICE(p_hwfn, false,
2027                           "Avoid triggering a recovery since such a process"
2028                           " is already in progress\n");
2029                 return ECORE_AGAIN;
2030         }
2031
2032         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2033         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2034
2035         return ECORE_SUCCESS;
2036 }
2037
2038 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2039                                               struct ecore_ptt *p_ptt,
2040                                               u8 vf_id, u8 num)
2041 {
2042         u32 resp = 0, param = 0, rc_param = 0;
2043         enum _ecore_status_t rc;
2044
2045 /* Only Leader can configure MSIX, and need to take CMT into account */
2046
2047         if (!IS_LEAD_HWFN(p_hwfn))
2048                 return ECORE_SUCCESS;
2049         num *= p_hwfn->p_dev->num_hwfns;
2050
2051         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
2052             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2053         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
2054             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2055
2056         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2057                            &resp, &rc_param);
2058
2059         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2060                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2061                           vf_id);
2062                 rc = ECORE_INVAL;
2063         } else {
2064                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2065                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2066                             num, vf_id);
2067         }
2068
2069         return rc;
2070 }
2071
2072 enum _ecore_status_t
2073 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2074                            struct ecore_mcp_drv_version *p_ver)
2075 {
2076         struct ecore_mcp_mb_params mb_params;
2077         struct drv_version_stc drv_version;
2078         u32 num_words, i;
2079         void *p_name;
2080         OSAL_BE32 val;
2081         enum _ecore_status_t rc;
2082
2083 #ifndef ASIC_ONLY
2084         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2085                 return ECORE_SUCCESS;
2086 #endif
2087
2088         OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2089         drv_version.version = p_ver->version;
2090         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2091         for (i = 0; i < num_words; i++) {
2092                 /* The driver name is expected to be in a big-endian format */
2093                 p_name = &p_ver->name[i * sizeof(u32)];
2094                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2095                 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2096         }
2097
2098         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2099         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2100         mb_params.p_data_src = &drv_version;
2101         mb_params.data_src_size = sizeof(drv_version);
2102         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2103         if (rc != ECORE_SUCCESS)
2104                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2105
2106         return rc;
2107 }
2108
2109 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2110                                     struct ecore_ptt *p_ptt)
2111 {
2112         enum _ecore_status_t rc;
2113         u32 resp = 0, param = 0;
2114
2115         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2116                            &param);
2117         if (rc != ECORE_SUCCESS)
2118                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2119
2120         return rc;
2121 }
2122
2123 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2124                                       struct ecore_ptt *p_ptt)
2125 {
2126         u32 value, cpu_mode;
2127
2128         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2129
2130         value = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2131         value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2132         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2133         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2134
2135         return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -1 : 0;
2136 }
2137
2138 enum _ecore_status_t
2139 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2140                                    struct ecore_ptt *p_ptt,
2141                                    enum ecore_ov_client client)
2142 {
2143         enum _ecore_status_t rc;
2144         u32 resp = 0, param = 0;
2145         u32 drv_mb_param;
2146
2147         switch (client) {
2148         case ECORE_OV_CLIENT_DRV:
2149                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2150                 break;
2151         case ECORE_OV_CLIENT_USER:
2152                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2153                 break;
2154         case ECORE_OV_CLIENT_VENDOR_SPEC:
2155                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2156                 break;
2157         default:
2158                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2159                 return ECORE_INVAL;
2160         }
2161
2162         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2163                            drv_mb_param, &resp, &param);
2164         if (rc != ECORE_SUCCESS)
2165                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2166
2167         return rc;
2168 }
2169
2170 enum _ecore_status_t
2171 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2172                                  struct ecore_ptt *p_ptt,
2173                                  enum ecore_ov_driver_state drv_state)
2174 {
2175         enum _ecore_status_t rc;
2176         u32 resp = 0, param = 0;
2177         u32 drv_mb_param;
2178
2179         switch (drv_state) {
2180         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2181                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2182                 break;
2183         case ECORE_OV_DRIVER_STATE_DISABLED:
2184                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2185                 break;
2186         case ECORE_OV_DRIVER_STATE_ACTIVE:
2187                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2188                 break;
2189         default:
2190                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2191                 return ECORE_INVAL;
2192         }
2193
2194         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2195                            drv_mb_param, &resp, &param);
2196         if (rc != ECORE_SUCCESS)
2197                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2198
2199         return rc;
2200 }
2201
2202 enum _ecore_status_t
2203 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2204                          struct ecore_fc_npiv_tbl *p_table)
2205 {
2206         return 0;
2207 }
2208
2209 enum _ecore_status_t
2210 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2211                         struct ecore_ptt *p_ptt, u16 mtu)
2212 {
2213         return 0;
2214 }
2215
2216 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2217                                        struct ecore_ptt *p_ptt,
2218                                        enum ecore_led_mode mode)
2219 {
2220         u32 resp = 0, param = 0, drv_mb_param;
2221         enum _ecore_status_t rc;
2222
2223         switch (mode) {
2224         case ECORE_LED_MODE_ON:
2225                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2226                 break;
2227         case ECORE_LED_MODE_OFF:
2228                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2229                 break;
2230         case ECORE_LED_MODE_RESTORE:
2231                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2232                 break;
2233         default:
2234                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2235                 return ECORE_INVAL;
2236         }
2237
2238         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2239                            drv_mb_param, &resp, &param);
2240         if (rc != ECORE_SUCCESS)
2241                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2242
2243         return rc;
2244 }
2245
2246 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2247                                              struct ecore_ptt *p_ptt,
2248                                              u32 mask_parities)
2249 {
2250         enum _ecore_status_t rc;
2251         u32 resp = 0, param = 0;
2252
2253         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2254                            mask_parities, &resp, &param);
2255
2256         if (rc != ECORE_SUCCESS) {
2257                 DP_ERR(p_hwfn,
2258                        "MCP response failure for mask parities, aborting\n");
2259         } else if (resp != FW_MSG_CODE_OK) {
2260                 DP_ERR(p_hwfn,
2261                        "MCP did not ack mask parity request. Old MFW?\n");
2262                 rc = ECORE_INVAL;
2263         }
2264
2265         return rc;
2266 }
2267
2268 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2269                                         u8 *p_buf, u32 len)
2270 {
2271         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2272         u32 bytes_left, offset, bytes_to_copy, buf_size;
2273         struct ecore_mcp_nvm_params params;
2274         struct ecore_ptt *p_ptt;
2275         enum _ecore_status_t rc = ECORE_SUCCESS;
2276
2277         p_ptt = ecore_ptt_acquire(p_hwfn);
2278         if (!p_ptt)
2279                 return ECORE_BUSY;
2280
2281         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2282         bytes_left = len;
2283         offset = 0;
2284         params.type = ECORE_MCP_NVM_RD;
2285         params.nvm_rd.buf_size = &buf_size;
2286         params.nvm_common.cmd = DRV_MSG_CODE_NVM_READ_NVRAM;
2287         while (bytes_left > 0) {
2288                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2289                                            MCP_DRV_NVM_BUF_LEN);
2290                 params.nvm_common.offset = (addr + offset) |
2291                     (bytes_to_copy << DRV_MB_PARAM_NVM_LEN_SHIFT);
2292                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2293                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2294                 if (rc != ECORE_SUCCESS || (params.nvm_common.resp !=
2295                                             FW_MSG_CODE_NVM_OK)) {
2296                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2297                         break;
2298                 }
2299
2300                 /* This can be a lengthy process, and it's possible scheduler
2301                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2302                  */
2303                 if (bytes_left % 0x1000 <
2304                     (bytes_left - *params.nvm_rd.buf_size) % 0x1000)
2305                         OSAL_MSLEEP(1);
2306
2307                 offset += *params.nvm_rd.buf_size;
2308                 bytes_left -= *params.nvm_rd.buf_size;
2309         }
2310
2311         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2312         ecore_ptt_release(p_hwfn, p_ptt);
2313
2314         return rc;
2315 }
2316
2317 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2318                                         u32 addr, u8 *p_buf, u32 len)
2319 {
2320         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2321         struct ecore_mcp_nvm_params params;
2322         struct ecore_ptt *p_ptt;
2323         enum _ecore_status_t rc;
2324
2325         p_ptt = ecore_ptt_acquire(p_hwfn);
2326         if (!p_ptt)
2327                 return ECORE_BUSY;
2328
2329         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2330         params.type = ECORE_MCP_NVM_RD;
2331         params.nvm_rd.buf_size = &len;
2332         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_READ) ?
2333             DRV_MSG_CODE_PHY_CORE_READ : DRV_MSG_CODE_PHY_RAW_READ;
2334         params.nvm_common.offset = addr;
2335         params.nvm_rd.buf = (u32 *)p_buf;
2336         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2337         if (rc != ECORE_SUCCESS)
2338                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2339
2340         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2341         ecore_ptt_release(p_hwfn, p_ptt);
2342
2343         return rc;
2344 }
2345
2346 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2347 {
2348         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2349         struct ecore_mcp_nvm_params params;
2350         struct ecore_ptt *p_ptt;
2351
2352         p_ptt = ecore_ptt_acquire(p_hwfn);
2353         if (!p_ptt)
2354                 return ECORE_BUSY;
2355
2356         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2357         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2358         ecore_ptt_release(p_hwfn, p_ptt);
2359
2360         return ECORE_SUCCESS;
2361 }
2362
2363 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2364 {
2365         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2366         struct ecore_mcp_nvm_params params;
2367         struct ecore_ptt *p_ptt;
2368         enum _ecore_status_t rc;
2369
2370         p_ptt = ecore_ptt_acquire(p_hwfn);
2371         if (!p_ptt)
2372                 return ECORE_BUSY;
2373         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2374         params.type = ECORE_MCP_CMD;
2375         params.nvm_common.cmd = DRV_MSG_CODE_NVM_DEL_FILE;
2376         params.nvm_common.offset = addr;
2377         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2378         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2379         ecore_ptt_release(p_hwfn, p_ptt);
2380
2381         return rc;
2382 }
2383
2384 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2385                                                   u32 addr)
2386 {
2387         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2388         struct ecore_mcp_nvm_params params;
2389         struct ecore_ptt *p_ptt;
2390         enum _ecore_status_t rc;
2391
2392         p_ptt = ecore_ptt_acquire(p_hwfn);
2393         if (!p_ptt)
2394                 return ECORE_BUSY;
2395         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2396         params.type = ECORE_MCP_CMD;
2397         params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN;
2398         params.nvm_common.offset = addr;
2399         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2400         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2401         ecore_ptt_release(p_hwfn, p_ptt);
2402
2403         return rc;
2404 }
2405
2406 /* rc receives ECORE_INVAL as default parameter because
2407  * it might not enter the while loop if the len is 0
2408  */
2409 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2410                                          u32 addr, u8 *p_buf, u32 len)
2411 {
2412         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2413         enum _ecore_status_t rc = ECORE_INVAL;
2414         struct ecore_mcp_nvm_params params;
2415         struct ecore_ptt *p_ptt;
2416         u32 buf_idx, buf_size;
2417
2418         p_ptt = ecore_ptt_acquire(p_hwfn);
2419         if (!p_ptt)
2420                 return ECORE_BUSY;
2421
2422         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2423         params.type = ECORE_MCP_NVM_WR;
2424         if (cmd == ECORE_PUT_FILE_DATA)
2425                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2426         else
2427                 params.nvm_common.cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2428         buf_idx = 0;
2429         while (buf_idx < len) {
2430                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2431                                       MCP_DRV_NVM_BUF_LEN);
2432                 params.nvm_common.offset = ((buf_size <<
2433                                              DRV_MB_PARAM_NVM_LEN_SHIFT)
2434                                             | addr) + buf_idx;
2435                 params.nvm_wr.buf_size = buf_size;
2436                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2437                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2438                 if (rc != ECORE_SUCCESS ||
2439                     ((params.nvm_common.resp != FW_MSG_CODE_NVM_OK) &&
2440                      (params.nvm_common.resp !=
2441                       FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
2442                         DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2443
2444                 /* This can be a lengthy process, and it's possible scheduler
2445                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2446                  */
2447                 if (buf_idx % 0x1000 >
2448                     (buf_idx + buf_size) % 0x1000)
2449                         OSAL_MSLEEP(1);
2450
2451                 buf_idx += buf_size;
2452         }
2453
2454         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2455         ecore_ptt_release(p_hwfn, p_ptt);
2456
2457         return rc;
2458 }
2459
2460 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2461                                          u32 addr, u8 *p_buf, u32 len)
2462 {
2463         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2464         struct ecore_mcp_nvm_params params;
2465         struct ecore_ptt *p_ptt;
2466         enum _ecore_status_t rc;
2467
2468         p_ptt = ecore_ptt_acquire(p_hwfn);
2469         if (!p_ptt)
2470                 return ECORE_BUSY;
2471
2472         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2473         params.type = ECORE_MCP_NVM_WR;
2474         params.nvm_wr.buf_size = len;
2475         params.nvm_common.cmd = (cmd == ECORE_PHY_CORE_WRITE) ?
2476             DRV_MSG_CODE_PHY_CORE_WRITE : DRV_MSG_CODE_PHY_RAW_WRITE;
2477         params.nvm_common.offset = addr;
2478         params.nvm_wr.buf = (u32 *)p_buf;
2479         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2480         if (rc != ECORE_SUCCESS)
2481                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2482         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2483         ecore_ptt_release(p_hwfn, p_ptt);
2484
2485         return rc;
2486 }
2487
2488 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2489                                                    u32 addr)
2490 {
2491         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2492         struct ecore_mcp_nvm_params params;
2493         struct ecore_ptt *p_ptt;
2494         enum _ecore_status_t rc;
2495
2496         p_ptt = ecore_ptt_acquire(p_hwfn);
2497         if (!p_ptt)
2498                 return ECORE_BUSY;
2499
2500         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2501         params.type = ECORE_MCP_CMD;
2502         params.nvm_common.cmd = DRV_MSG_CODE_SET_SECURE_MODE;
2503         params.nvm_common.offset = addr;
2504         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2505         p_dev->mcp_nvm_resp = params.nvm_common.resp;
2506         ecore_ptt_release(p_hwfn, p_ptt);
2507
2508         return rc;
2509 }
2510
2511 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2512                                             struct ecore_ptt *p_ptt,
2513                                             u32 port, u32 addr, u32 offset,
2514                                             u32 len, u8 *p_buf)
2515 {
2516         struct ecore_mcp_nvm_params params;
2517         enum _ecore_status_t rc;
2518         u32 bytes_left, bytes_to_copy, buf_size;
2519
2520         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2521         params.nvm_common.offset =
2522                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2523                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2524         addr = offset;
2525         offset = 0;
2526         bytes_left = len;
2527         params.type = ECORE_MCP_NVM_RD;
2528         params.nvm_rd.buf_size = &buf_size;
2529         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_READ;
2530         while (bytes_left > 0) {
2531                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2532                                            MAX_I2C_TRANSACTION_SIZE);
2533                 params.nvm_rd.buf = (u32 *)(p_buf + offset);
2534                 params.nvm_common.offset &=
2535                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2536                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2537                 params.nvm_common.offset |=
2538                         ((addr + offset) <<
2539                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2540                 params.nvm_common.offset |=
2541                         (bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2542                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2543                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2544                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2545                         return ECORE_NODEV;
2546                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2547                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2548                         return ECORE_UNKNOWN_ERROR;
2549
2550                 offset += *params.nvm_rd.buf_size;
2551                 bytes_left -= *params.nvm_rd.buf_size;
2552         }
2553
2554         return ECORE_SUCCESS;
2555 }
2556
2557 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2558                                              struct ecore_ptt *p_ptt,
2559                                              u32 port, u32 addr, u32 offset,
2560                                              u32 len, u8 *p_buf)
2561 {
2562         struct ecore_mcp_nvm_params params;
2563         enum _ecore_status_t rc;
2564         u32 buf_idx, buf_size;
2565
2566         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2567         params.nvm_common.offset =
2568                 (port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
2569                 (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
2570         params.type = ECORE_MCP_NVM_WR;
2571         params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
2572         buf_idx = 0;
2573         while (buf_idx < len) {
2574                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2575                                       MAX_I2C_TRANSACTION_SIZE);
2576                 params.nvm_common.offset &=
2577                         (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2578                          DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2579                 params.nvm_common.offset |=
2580                         ((offset + buf_idx) <<
2581                          DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
2582                 params.nvm_common.offset |=
2583                         (buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
2584                 params.nvm_wr.buf_size = buf_size;
2585                 params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
2586                 rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2587                 if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
2588                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2589                         return ECORE_NODEV;
2590                 } else if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2591                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2592                         return ECORE_UNKNOWN_ERROR;
2593
2594                 buf_idx += buf_size;
2595         }
2596
2597         return ECORE_SUCCESS;
2598 }
2599
2600 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2601                                          struct ecore_ptt *p_ptt,
2602                                          u16 gpio, u32 *gpio_val)
2603 {
2604         enum _ecore_status_t rc = ECORE_SUCCESS;
2605         u32 drv_mb_param = 0, rsp;
2606
2607         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
2608
2609         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2610                            drv_mb_param, &rsp, gpio_val);
2611
2612         if (rc != ECORE_SUCCESS)
2613                 return rc;
2614
2615         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2616                 return ECORE_UNKNOWN_ERROR;
2617
2618         return ECORE_SUCCESS;
2619 }
2620
2621 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2622                                           struct ecore_ptt *p_ptt,
2623                                           u16 gpio, u16 gpio_val)
2624 {
2625         enum _ecore_status_t rc = ECORE_SUCCESS;
2626         u32 drv_mb_param = 0, param, rsp;
2627
2628         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
2629                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
2630
2631         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2632                            drv_mb_param, &rsp, &param);
2633
2634         if (rc != ECORE_SUCCESS)
2635                 return rc;
2636
2637         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2638                 return ECORE_UNKNOWN_ERROR;
2639
2640         return ECORE_SUCCESS;
2641 }
2642
2643 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2644                                          struct ecore_ptt *p_ptt,
2645                                          u16 gpio, u32 *gpio_direction,
2646                                          u32 *gpio_ctrl)
2647 {
2648         u32 drv_mb_param = 0, rsp, val = 0;
2649         enum _ecore_status_t rc = ECORE_SUCCESS;
2650
2651         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT;
2652
2653         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2654                            drv_mb_param, &rsp, &val);
2655         if (rc != ECORE_SUCCESS)
2656                 return rc;
2657
2658         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2659                            DRV_MB_PARAM_GPIO_DIRECTION_SHIFT;
2660         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2661                       DRV_MB_PARAM_GPIO_CTRL_SHIFT;
2662
2663         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2664                 return ECORE_UNKNOWN_ERROR;
2665
2666         return ECORE_SUCCESS;
2667 }
2668
2669 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2670                                                   struct ecore_ptt *p_ptt)
2671 {
2672         u32 drv_mb_param = 0, rsp, param;
2673         enum _ecore_status_t rc = ECORE_SUCCESS;
2674
2675         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2676                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2677
2678         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2679                            drv_mb_param, &rsp, &param);
2680
2681         if (rc != ECORE_SUCCESS)
2682                 return rc;
2683
2684         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2685             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2686                 rc = ECORE_UNKNOWN_ERROR;
2687
2688         return rc;
2689 }
2690
2691 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2692                                                struct ecore_ptt *p_ptt)
2693 {
2694         u32 drv_mb_param, rsp, param;
2695         enum _ecore_status_t rc = ECORE_SUCCESS;
2696
2697         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2698                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2699
2700         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2701                            drv_mb_param, &rsp, &param);
2702
2703         if (rc != ECORE_SUCCESS)
2704                 return rc;
2705
2706         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2707             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2708                 rc = ECORE_UNKNOWN_ERROR;
2709
2710         return rc;
2711 }
2712
2713 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
2714         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
2715 {
2716         u32 drv_mb_param = 0, rsp;
2717         enum _ecore_status_t rc = ECORE_SUCCESS;
2718
2719         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2720                         DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2721
2722         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2723                            drv_mb_param, &rsp, num_images);
2724
2725         if (rc != ECORE_SUCCESS)
2726                 return rc;
2727
2728         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2729                 rc = ECORE_UNKNOWN_ERROR;
2730
2731         return rc;
2732 }
2733
2734 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
2735         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2736         struct bist_nvm_image_att *p_image_att, u32 image_index)
2737 {
2738         struct ecore_mcp_nvm_params params;
2739         enum _ecore_status_t rc;
2740         u32 buf_size;
2741
2742         OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
2743         params.nvm_common.offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2744                                     DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2745         params.nvm_common.offset |= (image_index <<
2746                                     DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT);
2747
2748         params.type = ECORE_MCP_NVM_RD;
2749         params.nvm_rd.buf_size = &buf_size;
2750         params.nvm_common.cmd = DRV_MSG_CODE_BIST_TEST;
2751         params.nvm_rd.buf = (u32 *)p_image_att;
2752
2753         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2754         if (rc != ECORE_SUCCESS)
2755                 return rc;
2756
2757         if (((params.nvm_common.resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2758             (p_image_att->return_code != 1))
2759                 rc = ECORE_UNKNOWN_ERROR;
2760
2761         return rc;
2762 }
2763
2764 enum _ecore_status_t
2765 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
2766                                struct ecore_ptt *p_ptt,
2767                                struct ecore_temperature_info *p_temp_info)
2768 {
2769         struct ecore_temperature_sensor *p_temp_sensor;
2770         struct temperature_status_stc mfw_temp_info;
2771         struct ecore_mcp_mb_params mb_params;
2772         u32 val;
2773         enum _ecore_status_t rc;
2774         u8 i;
2775
2776         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2777         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
2778         mb_params.p_data_dst = &mfw_temp_info;
2779         mb_params.data_dst_size = sizeof(mfw_temp_info);
2780         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2781         if (rc != ECORE_SUCCESS)
2782                 return rc;
2783
2784         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
2785         p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
2786                                               ECORE_MAX_NUM_OF_SENSORS);
2787         for (i = 0; i < p_temp_info->num_sensors; i++) {
2788                 val = mfw_temp_info.sensor[i];
2789                 p_temp_sensor = &p_temp_info->sensors[i];
2790                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
2791                                                  SENSOR_LOCATION_SHIFT;
2792                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
2793                                                 THRESHOLD_HIGH_SHIFT;
2794                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
2795                                           CRITICAL_TEMPERATURE_SHIFT;
2796                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
2797                                               CURRENT_TEMP_SHIFT;
2798         }
2799
2800         return ECORE_SUCCESS;
2801 }
2802
2803 enum _ecore_status_t ecore_mcp_get_mba_versions(
2804         struct ecore_hwfn *p_hwfn,
2805         struct ecore_ptt *p_ptt,
2806         struct ecore_mba_vers *p_mba_vers)
2807 {
2808         struct ecore_mcp_nvm_params params;
2809         enum _ecore_status_t rc;
2810         u32 buf_size;
2811
2812         OSAL_MEM_ZERO(&params, sizeof(params));
2813         params.type = ECORE_MCP_NVM_RD;
2814         params.nvm_common.cmd = DRV_MSG_CODE_GET_MBA_VERSION;
2815         params.nvm_common.offset = 0;
2816         params.nvm_rd.buf = &p_mba_vers->mba_vers[0];
2817         params.nvm_rd.buf_size = &buf_size;
2818         rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
2819
2820         if (rc != ECORE_SUCCESS)
2821                 return rc;
2822
2823         if ((params.nvm_common.resp & FW_MSG_CODE_MASK) !=
2824             FW_MSG_CODE_NVM_OK)
2825                 rc = ECORE_UNKNOWN_ERROR;
2826
2827         if (buf_size != MCP_DRV_NVM_BUF_LEN)
2828                 rc = ECORE_UNKNOWN_ERROR;
2829
2830         return rc;
2831 }
2832
2833 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
2834                                               struct ecore_ptt *p_ptt,
2835                                               u64 *num_events)
2836 {
2837         u32 rsp;
2838
2839         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
2840                              0, &rsp, (u32 *)num_events);
2841 }
2842
2843 static enum resource_id_enum
2844 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
2845 {
2846         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2847
2848         switch (res_id) {
2849         case ECORE_SB:
2850                 mfw_res_id = RESOURCE_NUM_SB_E;
2851                 break;
2852         case ECORE_L2_QUEUE:
2853                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2854                 break;
2855         case ECORE_VPORT:
2856                 mfw_res_id = RESOURCE_NUM_VPORT_E;
2857                 break;
2858         case ECORE_RSS_ENG:
2859                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2860                 break;
2861         case ECORE_PQ:
2862                 mfw_res_id = RESOURCE_NUM_PQ_E;
2863                 break;
2864         case ECORE_RL:
2865                 mfw_res_id = RESOURCE_NUM_RL_E;
2866                 break;
2867         case ECORE_MAC:
2868         case ECORE_VLAN:
2869                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2870                 mfw_res_id = RESOURCE_VFC_FILTER_E;
2871                 break;
2872         case ECORE_ILT:
2873                 mfw_res_id = RESOURCE_ILT_E;
2874                 break;
2875         case ECORE_LL2_QUEUE:
2876                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2877                 break;
2878         case ECORE_RDMA_CNQ_RAM:
2879         case ECORE_CMDQS_CQS:
2880                 /* CNQ/CMDQS are the same resource */
2881                 mfw_res_id = RESOURCE_CQS_E;
2882                 break;
2883         case ECORE_RDMA_STATS_QUEUE:
2884                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2885                 break;
2886         case ECORE_BDQ:
2887                 mfw_res_id = RESOURCE_BDQ_E;
2888                 break;
2889         default:
2890                 break;
2891         }
2892
2893         return mfw_res_id;
2894 }
2895
2896 #define ECORE_RESC_ALLOC_VERSION_MAJOR  2
2897 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
2898 #define ECORE_RESC_ALLOC_VERSION                                \
2899         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
2900           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) |    \
2901          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
2902           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2903
2904 struct ecore_resc_alloc_in_params {
2905         u32 cmd;
2906         enum ecore_resources res_id;
2907         u32 resc_max_val;
2908 };
2909
2910 struct ecore_resc_alloc_out_params {
2911         u32 mcp_resp;
2912         u32 mcp_param;
2913         u32 resc_num;
2914         u32 resc_start;
2915         u32 vf_resc_num;
2916         u32 vf_resc_start;
2917         u32 flags;
2918 };
2919
2920 #define ECORE_RECOVERY_PROLOG_SLEEP_MS  100
2921
2922 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
2923 {
2924         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2925         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
2926         enum _ecore_status_t rc;
2927
2928         /* Allow ongoing PCIe transactions to complete */
2929         OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
2930
2931         /* Clear the PF's internal FID_enable in the PXP */
2932         rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
2933         if (rc != ECORE_SUCCESS)
2934                 DP_NOTICE(p_hwfn, false,
2935                           "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
2936                           rc);
2937
2938         return rc;
2939 }
2940
2941 static enum _ecore_status_t
2942 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
2943                               struct ecore_ptt *p_ptt,
2944                               struct ecore_resc_alloc_in_params *p_in_params,
2945                               struct ecore_resc_alloc_out_params *p_out_params)
2946 {
2947         struct ecore_mcp_mb_params mb_params;
2948         struct resource_info mfw_resc_info;
2949         enum _ecore_status_t rc;
2950
2951         OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
2952
2953         mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
2954         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
2955                 DP_ERR(p_hwfn,
2956                        "Failed to match resource %d [%s] with the MFW resources\n",
2957                        p_in_params->res_id,
2958                        ecore_hw_get_resc_name(p_in_params->res_id));
2959                 return ECORE_INVAL;
2960         }
2961
2962         switch (p_in_params->cmd) {
2963         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
2964                 mfw_resc_info.size = p_in_params->resc_max_val;
2965                 /* Fallthrough */
2966         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
2967                 break;
2968         default:
2969                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
2970                        p_in_params->cmd);
2971                 return ECORE_INVAL;
2972         }
2973
2974         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2975         mb_params.cmd = p_in_params->cmd;
2976         mb_params.param = ECORE_RESC_ALLOC_VERSION;
2977         mb_params.p_data_src = &mfw_resc_info;
2978         mb_params.data_src_size = sizeof(mfw_resc_info);
2979         mb_params.p_data_dst = mb_params.p_data_src;
2980         mb_params.data_dst_size = mb_params.data_src_size;
2981
2982         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
2983                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
2984                    p_in_params->cmd, p_in_params->res_id,
2985                    ecore_hw_get_resc_name(p_in_params->res_id),
2986                    ECORE_MFW_GET_FIELD(mb_params.param,
2987                            DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2988                    ECORE_MFW_GET_FIELD(mb_params.param,
2989                            DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2990                    p_in_params->resc_max_val);
2991
2992         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2993         if (rc != ECORE_SUCCESS)
2994                 return rc;
2995
2996         p_out_params->mcp_resp = mb_params.mcp_resp;
2997         p_out_params->mcp_param = mb_params.mcp_param;
2998         p_out_params->resc_num = mfw_resc_info.size;
2999         p_out_params->resc_start = mfw_resc_info.offset;
3000         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3001         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3002         p_out_params->flags = mfw_resc_info.flags;
3003
3004         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3005                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3006                    ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3007                            FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3008                    ECORE_MFW_GET_FIELD(p_out_params->mcp_param,
3009                            FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3010                    p_out_params->resc_num, p_out_params->resc_start,
3011                    p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3012                    p_out_params->flags);
3013
3014         return ECORE_SUCCESS;
3015 }
3016
3017 enum _ecore_status_t
3018 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3019                            enum ecore_resources res_id, u32 resc_max_val,
3020                            u32 *p_mcp_resp)
3021 {
3022         struct ecore_resc_alloc_out_params out_params;
3023         struct ecore_resc_alloc_in_params in_params;
3024         enum _ecore_status_t rc;
3025
3026         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3027         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3028         in_params.res_id = res_id;
3029         in_params.resc_max_val = resc_max_val;
3030         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3031         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3032                                            &out_params);
3033         if (rc != ECORE_SUCCESS)
3034                 return rc;
3035
3036         *p_mcp_resp = out_params.mcp_resp;
3037
3038         return ECORE_SUCCESS;
3039 }
3040
3041 enum _ecore_status_t
3042 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3043                         enum ecore_resources res_id, u32 *p_mcp_resp,
3044                         u32 *p_resc_num, u32 *p_resc_start)
3045 {
3046         struct ecore_resc_alloc_out_params out_params;
3047         struct ecore_resc_alloc_in_params in_params;
3048         enum _ecore_status_t rc;
3049
3050         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3051         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3052         in_params.res_id = res_id;
3053         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3054         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3055                                            &out_params);
3056         if (rc != ECORE_SUCCESS)
3057                 return rc;
3058
3059         *p_mcp_resp = out_params.mcp_resp;
3060
3061         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3062                 *p_resc_num = out_params.resc_num;
3063                 *p_resc_start = out_params.resc_start;
3064         }
3065
3066         return ECORE_SUCCESS;
3067 }
3068
3069 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3070                                                struct ecore_ptt *p_ptt)
3071 {
3072         u32 mcp_resp, mcp_param;
3073
3074         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3075                              &mcp_resp, &mcp_param);
3076 }
3077
3078 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3079                                                    struct ecore_ptt *p_ptt,
3080                                                    u32 param, u32 *p_mcp_resp,
3081                                                    u32 *p_mcp_param)
3082 {
3083         enum _ecore_status_t rc;
3084
3085         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3086                            p_mcp_resp, p_mcp_param);
3087         if (rc != ECORE_SUCCESS)
3088                 return rc;
3089
3090         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3091                 DP_INFO(p_hwfn,
3092                         "The resource command is unsupported by the MFW\n");
3093                 return ECORE_NOTIMPL;
3094         }
3095
3096         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3097                 u8 opcode = ECORE_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3098
3099                 DP_NOTICE(p_hwfn, false,
3100                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3101                           param, opcode);
3102                 return ECORE_INVAL;
3103         }
3104
3105         return rc;
3106 }
3107
3108 enum _ecore_status_t
3109 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3110                       struct ecore_resc_lock_params *p_params)
3111 {
3112         u32 param = 0, mcp_resp, mcp_param;
3113         u8 opcode;
3114         enum _ecore_status_t rc;
3115
3116         switch (p_params->timeout) {
3117         case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3118                 opcode = RESOURCE_OPCODE_REQ;
3119                 p_params->timeout = 0;
3120                 break;
3121         case ECORE_MCP_RESC_LOCK_TO_NONE:
3122                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3123                 p_params->timeout = 0;
3124                 break;
3125         default:
3126                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3127                 break;
3128         }
3129
3130         ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3131         ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3132         ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3133
3134         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3135                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3136                    param, p_params->timeout, opcode, p_params->resource);
3137
3138         /* Attempt to acquire the resource */
3139         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3140                                     &mcp_param);
3141         if (rc != ECORE_SUCCESS)
3142                 return rc;
3143
3144         /* Analyze the response */
3145         p_params->owner = ECORE_MFW_GET_FIELD(mcp_param,
3146                                              RESOURCE_CMD_RSP_OWNER);
3147         opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3148
3149         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3150                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3151                    mcp_param, opcode, p_params->owner);
3152
3153         switch (opcode) {
3154         case RESOURCE_OPCODE_GNT:
3155                 p_params->b_granted = true;
3156                 break;
3157         case RESOURCE_OPCODE_BUSY:
3158                 p_params->b_granted = false;
3159                 break;
3160         default:
3161                 DP_NOTICE(p_hwfn, false,
3162                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3163                           mcp_param, opcode);
3164                 return ECORE_INVAL;
3165         }
3166
3167         return ECORE_SUCCESS;
3168 }
3169
3170 enum _ecore_status_t
3171 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3172                     struct ecore_resc_lock_params *p_params)
3173 {
3174         u32 retry_cnt = 0;
3175         enum _ecore_status_t rc;
3176
3177         do {
3178                 /* No need for an interval before the first iteration */
3179                 if (retry_cnt) {
3180                         if (p_params->sleep_b4_retry) {
3181                                 u16 retry_interval_in_ms =
3182                                         DIV_ROUND_UP(p_params->retry_interval,
3183                                                      1000);
3184
3185                                 OSAL_MSLEEP(retry_interval_in_ms);
3186                         } else {
3187                                 OSAL_UDELAY(p_params->retry_interval);
3188                         }
3189                 }
3190
3191                 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3192                 if (rc != ECORE_SUCCESS)
3193                         return rc;
3194
3195                 if (p_params->b_granted)
3196                         break;
3197         } while (retry_cnt++ < p_params->retry_num);
3198
3199         return ECORE_SUCCESS;
3200 }
3201
3202 enum _ecore_status_t
3203 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3204                       struct ecore_resc_unlock_params *p_params)
3205 {
3206         u32 param = 0, mcp_resp, mcp_param;
3207         u8 opcode;
3208         enum _ecore_status_t rc;
3209
3210         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3211                                    : RESOURCE_OPCODE_RELEASE;
3212         ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3213         ECORE_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3214
3215         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3216                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3217                    param, opcode, p_params->resource);
3218
3219         /* Attempt to release the resource */
3220         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3221                                     &mcp_param);
3222         if (rc != ECORE_SUCCESS)
3223                 return rc;
3224
3225         /* Analyze the response */
3226         opcode = ECORE_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3227
3228         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3229                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3230                    mcp_param, opcode);
3231
3232         switch (opcode) {
3233         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3234                 DP_INFO(p_hwfn,
3235                         "Resource unlock request for an already released resource [%d]\n",
3236                         p_params->resource);
3237                 /* Fallthrough */
3238         case RESOURCE_OPCODE_RELEASED:
3239                 p_params->b_released = true;
3240                 break;
3241         case RESOURCE_OPCODE_WRONG_OWNER:
3242                 p_params->b_released = false;
3243                 break;
3244         default:
3245                 DP_NOTICE(p_hwfn, false,
3246                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3247                           mcp_param, opcode);
3248                 return ECORE_INVAL;
3249         }
3250
3251         return ECORE_SUCCESS;
3252 }