drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23 #include "ecore_sp_commands.h"
  24 #include "ecore_cxt.h"
  25
  26 #define CHIP_MCP_RESP_ITER_US 10
  27 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  28
  29 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  30 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  31
  32 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  33         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  34                  _val)
  35
  36 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  37         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  38
  39 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  40         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  41                      OFFSETOF(struct public_drv_mb, _field), _val)
  42
  43 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  44         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  45                      OFFSETOF(struct public_drv_mb, _field))
  46
  47 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  48         DRV_ID_PDA_COMP_VER_OFFSET)
  49
  50 #define MCP_BYTES_PER_MBIT_OFFSET 17
  51
  52 #ifndef ASIC_ONLY
  53 static int loaded;
  54 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  55 #endif
  56
  57 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  58 {
  59         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  60                 return false;
  61         return true;
  62 }
  63
  64 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  65 {
  66         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  67                                         PUBLIC_PORT);
  68         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  69
  70         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  71                                                    MFW_PORT(p_hwfn));
  72         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  73                    "port_addr = 0x%x, port_id 0x%02x\n",
  74                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  75 }
  76
  77 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  78 {
  79         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  80         OSAL_BE32 tmp;
  81         u32 i;
  82
  83 #ifndef ASIC_ONLY
  84         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  85                 return;
  86 #endif
  87
  88         if (!p_hwfn->mcp_info->public_base)
  89                 return;
  90
  91         for (i = 0; i < length; i++) {
  92                 tmp = ecore_rd(p_hwfn, p_ptt,
  93                                p_hwfn->mcp_info->mfw_mb_addr +
  94                                (i << 2) + sizeof(u32));
  95
  96                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  97                     OSAL_BE32_TO_CPU(tmp);
  98         }
  99 }
 100
 101 struct ecore_mcp_cmd_elem {
 102         osal_list_entry_t list;
 103         struct ecore_mcp_mb_params *p_mb_params;
 104         u16 expected_seq_num;
 105         bool b_is_completed;
 106 };
 107
 108 /* Must be called while cmd_lock is acquired */
 109 static struct ecore_mcp_cmd_elem *
 110 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
 111                        struct ecore_mcp_mb_params *p_mb_params,
 112                        u16 expected_seq_num)
 113 {
 114         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 115
 116         p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
 117                                  sizeof(*p_cmd_elem));
 118         if (!p_cmd_elem) {
 119                 DP_NOTICE(p_hwfn, false,
 120                           "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
 121                 goto out;
 122         }
 123
 124         p_cmd_elem->p_mb_params = p_mb_params;
 125         p_cmd_elem->expected_seq_num = expected_seq_num;
 126         OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 127 out:
 128         return p_cmd_elem;
 129 }
 130
 131 /* Must be called while cmd_lock is acquired */
 132 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
 133                                    struct ecore_mcp_cmd_elem *p_cmd_elem)
 134 {
 135         OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 136         OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
 137 }
 138
 139 /* Must be called while cmd_lock is acquired */
 140 static struct ecore_mcp_cmd_elem *
 141 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
 142 {
 143         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 144
 145         OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
 146                                  struct ecore_mcp_cmd_elem) {
 147                 if (p_cmd_elem->expected_seq_num == seq_num)
 148                         return p_cmd_elem;
 149         }
 150
 151         return OSAL_NULL;
 152 }
 153
 154 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 155 {
 156         if (p_hwfn->mcp_info) {
 157                 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
 158
 159                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 160                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 161
 162                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 163                 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
 164                                               &p_hwfn->mcp_info->cmd_list, list,
 165                                               struct ecore_mcp_cmd_elem) {
 166                         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 167                 }
 168                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 169
 170 #ifdef CONFIG_ECORE_LOCK_ALLOC
 171                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
 172                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
 173 #endif
 174         }
 175
 176         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 177
 178         return ECORE_SUCCESS;
 179 }
 180
 181 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 182                                                    struct ecore_ptt *p_ptt)
 183 {
 184         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 185         u32 drv_mb_offsize, mfw_mb_offsize;
 186         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 187
 188 #ifndef ASIC_ONLY
 189         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 190                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 191                 p_info->public_base = 0;
 192                 return ECORE_INVAL;
 193         }
 194 #endif
 195
 196         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 197         if (!p_info->public_base)
 198                 return ECORE_INVAL;
 199
 200         p_info->public_base |= GRCBASE_MCP;
 201
 202         /* Calculate the driver and MFW mailbox address */
 203         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 204                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 205                                                        PUBLIC_DRV_MB));
 206         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 207         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 208                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 209                    " mcp_pf_id = 0x%x\n",
 210                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 211
 212         /* Set the MFW MB address */
 213         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 214                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 215                                                        PUBLIC_MFW_MB));
 216         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 217         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 218                                                p_info->mfw_mb_addr);
 219
 220         /* Get the current driver mailbox sequence before sending
 221          * the first command
 222          */
 223         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 224             DRV_MSG_SEQ_NUMBER_MASK;
 225
 226         /* Get current FW pulse sequence */
 227         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 228             DRV_PULSE_SEQ_MASK;
 229
 230         p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 231
 232         return ECORE_SUCCESS;
 233 }
 234
 235 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 236                                         struct ecore_ptt *p_ptt)
 237 {
 238         struct ecore_mcp_info *p_info;
 239         u32 size;
 240
 241         /* Allocate mcp_info structure */
 242         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 243                                        sizeof(*p_hwfn->mcp_info));
 244         if (!p_hwfn->mcp_info)
 245                 goto err;
 246         p_info = p_hwfn->mcp_info;
 247
 248         /* Initialize the MFW spinlocks */
 249 #ifdef CONFIG_ECORE_LOCK_ALLOC
 250         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
 251         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
 252 #endif
 253         OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
 254         OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
 255
 256         OSAL_LIST_INIT(&p_info->cmd_list);
 257
 258         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 259                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 260                 /* Do not free mcp_info here, since public_base indicate that
 261                  * the MCP is not initialized
 262                  */
 263                 return ECORE_SUCCESS;
 264         }
 265
 266         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 267         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 268         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 269         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 270                 goto err;
 271
 272         return ECORE_SUCCESS;
 273
 274 err:
 275         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 276         ecore_mcp_free(p_hwfn);
 277         return ECORE_NOMEM;
 278 }
 279
 280 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
 281                                      struct ecore_ptt *p_ptt)
 282 {
 283         u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 284
 285         /* Use MCP history register to check if MCP reset occurred between init
 286          * time and now.
 287          */
 288         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 289                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 290                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 291                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 292
 293                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 294                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 295         }
 296 }
 297
 298 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 299                                      struct ecore_ptt *p_ptt)
 300 {
 301         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 302         enum _ecore_status_t rc = ECORE_SUCCESS;
 303
 304 #ifndef ASIC_ONLY
 305         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 306                 delay = EMUL_MCP_RESP_ITER_US;
 307 #endif
 308
 309         if (p_hwfn->mcp_info->b_block_cmd) {
 310                 DP_NOTICE(p_hwfn, false,
 311                           "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
 312                 return ECORE_ABORTED;
 313         }
 314
 315         /* Ensure that only a single thread is accessing the mailbox */
 316         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 317
 318         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 319
 320         /* Set drv command along with the updated sequence */
 321         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 322         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 323         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 324
 325         do {
 326                 /* Wait for MFW response */
 327                 OSAL_UDELAY(delay);
 328                 /* Give the FW up to 500 second (50*1000*10usec) */
 329         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 330                                                 MISCS_REG_GENERIC_POR_0)) &&
 331                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 332
 333         if (org_mcp_reset_seq !=
 334             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 335                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 336                            "MCP was reset after %d usec\n", cnt * delay);
 337         } else {
 338                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 339                 rc = ECORE_AGAIN;
 340         }
 341
 342         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 343
 344         return rc;
 345 }
 346
 347 /* Must be called while cmd_lock is acquired */
 348 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
 349 {
 350         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 351
 352         /* There is at most one pending command at a certain time, and if it
 353          * exists - it is placed at the HEAD of the list.
 354          */
 355         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
 356                 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
 357                                                    struct ecore_mcp_cmd_elem,
 358                                                    list);
 359                 return !p_cmd_elem->b_is_completed;
 360         }
 361
 362         return false;
 363 }
 364
 365 /* Must be called while cmd_lock is acquired */
 366 static enum _ecore_status_t
 367 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 368 {
 369         struct ecore_mcp_mb_params *p_mb_params;
 370         struct ecore_mcp_cmd_elem *p_cmd_elem;
 371         u32 mcp_resp;
 372         u16 seq_num;
 373
 374         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 375         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 376
 377         /* Return if no new non-handled response has been received */
 378         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 379                 return ECORE_AGAIN;
 380
 381         p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
 382         if (!p_cmd_elem) {
 383                 DP_ERR(p_hwfn,
 384                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 385                        seq_num);
 386                 return ECORE_UNKNOWN_ERROR;
 387         }
 388
 389         p_mb_params = p_cmd_elem->p_mb_params;
 390
 391         /* Get the MFW response along with the sequence number */
 392         p_mb_params->mcp_resp = mcp_resp;
 393
 394         /* Get the MFW param */
 395         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 396
 397         /* Get the union data */
 398         if (p_mb_params->p_data_dst != OSAL_NULL &&
 399             p_mb_params->data_dst_size) {
 400                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 401                                       OFFSETOF(struct public_drv_mb,
 402                                                union_data);
 403                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 404                                   union_data_addr, p_mb_params->data_dst_size);
 405         }
 406
 407         p_cmd_elem->b_is_completed = true;
 408
 409         return ECORE_SUCCESS;
 410 }
 411
 412 /* Must be called while cmd_lock is acquired */
 413 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 414                                       struct ecore_ptt *p_ptt,
 415                                       struct ecore_mcp_mb_params *p_mb_params,
 416                                       u16 seq_num)
 417 {
 418         union drv_union_data union_data;
 419         u32 union_data_addr;
 420
 421         /* Set the union data */
 422         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 423                           OFFSETOF(struct public_drv_mb, union_data);
 424         OSAL_MEM_ZERO(&union_data, sizeof(union_data));
 425         if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
 426                 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
 427                             p_mb_params->data_src_size);
 428         ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 429                         sizeof(union_data));
 430
 431         /* Set the drv param */
 432         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 433
 434         /* Set the drv command along with the sequence number */
 435         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 436
 437         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 438                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 439                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 440 }
 441
 442 static void ecore_mcp_cmd_set_blocking(struct ecore_hwfn *p_hwfn,
 443                                        bool block_cmd)
 444 {
 445         p_hwfn->mcp_info->b_block_cmd = block_cmd;
 446
 447         DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
 448                 block_cmd ? "Block" : "Unblock");
 449 }
 450
 451 void ecore_mcp_print_cpu_info(struct ecore_hwfn *p_hwfn,
 452                               struct ecore_ptt *p_ptt)
 453 {
 454         u32 cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2;
 455
 456         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
 457         cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
 458         cpu_pc_0 = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 459         OSAL_UDELAY(CHIP_MCP_RESP_ITER_US);
 460         cpu_pc_1 = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 461         OSAL_UDELAY(CHIP_MCP_RESP_ITER_US);
 462         cpu_pc_2 = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
 463
 464         DP_NOTICE(p_hwfn, false,
 465                   "MCP CPU info: mode 0x%08x, state 0x%08x, pc {0x%08x, 0x%08x, 0x%08x}\n",
 466                   cpu_mode, cpu_state, cpu_pc_0, cpu_pc_1, cpu_pc_2);
 467 }
 468
 469 static enum _ecore_status_t
 470 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 471                          struct ecore_mcp_mb_params *p_mb_params,
 472                          u32 max_retries, u32 delay)
 473 {
 474         struct ecore_mcp_cmd_elem *p_cmd_elem;
 475         u32 cnt = 0;
 476         u16 seq_num;
 477         enum _ecore_status_t rc = ECORE_SUCCESS;
 478
 479         /* Wait until the mailbox is non-occupied */
 480         do {
 481                 /* Exit the loop if there is no pending command, or if the
 482                  * pending command is completed during this iteration.
 483                  * The spinlock stays locked until the command is sent.
 484                  */
 485
 486                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 487
 488                 if (!ecore_mcp_has_pending_cmd(p_hwfn))
 489                         break;
 490
 491                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 492                 if (rc == ECORE_SUCCESS)
 493                         break;
 494                 else if (rc != ECORE_AGAIN)
 495                         goto err;
 496
 497                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 498                 OSAL_UDELAY(delay);
 499                 OSAL_MFW_CMD_PREEMPT(p_hwfn);
 500         } while (++cnt < max_retries);
 501
 502         if (cnt >= max_retries) {
 503                 DP_NOTICE(p_hwfn, false,
 504                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 505                           p_mb_params->cmd, p_mb_params->param);
 506                 return ECORE_AGAIN;
 507         }
 508
 509         /* Send the mailbox command */
 510         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 511         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 512         p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 513         if (!p_cmd_elem) {
 514                 rc = ECORE_NOMEM;
 515                 goto err;
 516         }
 517
 518         __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 519         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 520
 521         /* Wait for the MFW response */
 522         do {
 523                 /* Exit the loop if the command is already completed, or if the
 524                  * command is completed during this iteration.
 525                  * The spinlock stays locked until the list element is removed.
 526                  */
 527
 528                 OSAL_UDELAY(delay);
 529                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 530
 531                 if (p_cmd_elem->b_is_completed)
 532                         break;
 533
 534                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 535                 if (rc == ECORE_SUCCESS)
 536                         break;
 537                 else if (rc != ECORE_AGAIN)
 538                         goto err;
 539
 540                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 541                 OSAL_MFW_CMD_PREEMPT(p_hwfn);
 542         } while (++cnt < max_retries);
 543
 544         if (cnt >= max_retries) {
 545                 DP_NOTICE(p_hwfn, false,
 546                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 547                           p_mb_params->cmd, p_mb_params->param);
 548                 ecore_mcp_print_cpu_info(p_hwfn, p_ptt);
 549
 550                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 551                 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 552                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 553
 554                 ecore_mcp_cmd_set_blocking(p_hwfn, true);
 555                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 556                 return ECORE_AGAIN;
 557         }
 558
 559         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 560         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 561
 562         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 563                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 564                    p_mb_params->mcp_resp, p_mb_params->mcp_param,
 565                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 566
 567         /* Clear the sequence number from the MFW response */
 568         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 569
 570         return ECORE_SUCCESS;
 571
 572 err:
 573         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 574         return rc;
 575 }
 576
 577 static enum _ecore_status_t
 578 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 579                         struct ecore_ptt *p_ptt,
 580                         struct ecore_mcp_mb_params *p_mb_params)
 581 {
 582         osal_size_t union_data_size = sizeof(union drv_union_data);
 583         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 584         u32 delay = CHIP_MCP_RESP_ITER_US;
 585
 586 #ifndef ASIC_ONLY
 587         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 588                 delay = EMUL_MCP_RESP_ITER_US;
 589         /* There is a built-in delay of 100usec in each MFW response read */
 590         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 591                 max_retries /= 10;
 592 #endif
 593
 594         /* MCP not initialized */
 595         if (!ecore_mcp_is_init(p_hwfn)) {
 596                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 597                 return ECORE_BUSY;
 598         }
 599
 600         if (p_mb_params->data_src_size > union_data_size ||
 601             p_mb_params->data_dst_size > union_data_size) {
 602                 DP_ERR(p_hwfn,
 603                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 604                        p_mb_params->data_src_size, p_mb_params->data_dst_size,
 605                        union_data_size);
 606                 return ECORE_INVAL;
 607         }
 608
 609         if (p_hwfn->mcp_info->b_block_cmd) {
 610                 DP_NOTICE(p_hwfn, false,
 611                           "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
 612                           p_mb_params->cmd, p_mb_params->param);
 613                 return ECORE_ABORTED;
 614         }
 615
 616         return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 617                                         delay);
 618 }
 619
 620 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 621                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 622                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 623 {
 624         struct ecore_mcp_mb_params mb_params;
 625         enum _ecore_status_t rc;
 626
 627 #ifndef ASIC_ONLY
 628         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 629                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 630                         loaded--;
 631                         loaded_port[p_hwfn->port_id]--;
 632                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 633                                    loaded);
 634                 }
 635                 return ECORE_SUCCESS;
 636         }
 637 #endif
 638
 639         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 640         mb_params.cmd = cmd;
 641         mb_params.param = param;
 642         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 643         if (rc != ECORE_SUCCESS)
 644                 return rc;
 645
 646         *o_mcp_resp = mb_params.mcp_resp;
 647         *o_mcp_param = mb_params.mcp_param;
 648
 649         return ECORE_SUCCESS;
 650 }
 651
 652 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 653                                           struct ecore_ptt *p_ptt,
 654                                           u32 cmd,
 655                                           u32 param,
 656                                           u32 *o_mcp_resp,
 657                                           u32 *o_mcp_param,
 658                                           u32 i_txn_size, u32 *i_buf)
 659 {
 660         struct ecore_mcp_mb_params mb_params;
 661         enum _ecore_status_t rc;
 662
 663         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 664         mb_params.cmd = cmd;
 665         mb_params.param = param;
 666         mb_params.p_data_src = i_buf;
 667         mb_params.data_src_size = (u8)i_txn_size;
 668         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 669         if (rc != ECORE_SUCCESS)
 670                 return rc;
 671
 672         *o_mcp_resp = mb_params.mcp_resp;
 673         *o_mcp_param = mb_params.mcp_param;
 674
 675         return ECORE_SUCCESS;
 676 }
 677
 678 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 679                                           struct ecore_ptt *p_ptt,
 680                                           u32 cmd,
 681                                           u32 param,
 682                                           u32 *o_mcp_resp,
 683                                           u32 *o_mcp_param,
 684                                           u32 *o_txn_size, u32 *o_buf)
 685 {
 686         struct ecore_mcp_mb_params mb_params;
 687         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 688         enum _ecore_status_t rc;
 689
 690         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 691         mb_params.cmd = cmd;
 692         mb_params.param = param;
 693         mb_params.p_data_dst = raw_data;
 694
 695         /* Use the maximal value since the actual one is part of the response */
 696         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 697
 698         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 699         if (rc != ECORE_SUCCESS)
 700                 return rc;
 701
 702         *o_mcp_resp = mb_params.mcp_resp;
 703         *o_mcp_param = mb_params.mcp_param;
 704
 705         *o_txn_size = *o_mcp_param;
 706         /* @DPDK */
 707         OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
 708
 709         return ECORE_SUCCESS;
 710 }
 711
 712 #ifndef ASIC_ONLY
 713 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 714                                     u32 *p_load_code)
 715 {
 716         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 717
 718         if (!loaded)
 719                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 720         else if (!loaded_port[p_hwfn->port_id])
 721                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 722         else
 723                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 724
 725         /* On CMT, always tell that it's engine */
 726         if (ECORE_IS_CMT(p_hwfn->p_dev))
 727                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 728
 729         *p_load_code = load_phase;
 730         loaded++;
 731         loaded_port[p_hwfn->port_id]++;
 732
 733         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 734                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 735                    *p_load_code, loaded, p_hwfn->port_id,
 736                    loaded_port[p_hwfn->port_id]);
 737 }
 738 #endif
 739
 740 static bool
 741 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
 742                          enum ecore_override_force_load override_force_load)
 743 {
 744         bool can_force_load = false;
 745
 746         switch (override_force_load) {
 747         case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
 748                 can_force_load = true;
 749                 break;
 750         case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
 751                 can_force_load = false;
 752                 break;
 753         default:
 754                 can_force_load = (drv_role == DRV_ROLE_OS &&
 755                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 756                                  (drv_role == DRV_ROLE_KDUMP &&
 757                                   exist_drv_role == DRV_ROLE_OS);
 758                 break;
 759         }
 760
 761         return can_force_load;
 762 }
 763
 764 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
 765                                                       struct ecore_ptt *p_ptt)
 766 {
 767         u32 resp = 0, param = 0;
 768         enum _ecore_status_t rc;
 769
 770         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 771                            &resp, &param);
 772         if (rc != ECORE_SUCCESS)
 773                 DP_NOTICE(p_hwfn, false,
 774                           "Failed to send cancel load request, rc = %d\n", rc);
 775
 776         return rc;
 777 }
 778
 779 #define CONFIG_ECORE_L2_BITMAP_IDX      (0x1 << 0)
 780 #define CONFIG_ECORE_SRIOV_BITMAP_IDX   (0x1 << 1)
 781 #define CONFIG_ECORE_ROCE_BITMAP_IDX    (0x1 << 2)
 782 #define CONFIG_ECORE_IWARP_BITMAP_IDX   (0x1 << 3)
 783 #define CONFIG_ECORE_FCOE_BITMAP_IDX    (0x1 << 4)
 784 #define CONFIG_ECORE_ISCSI_BITMAP_IDX   (0x1 << 5)
 785 #define CONFIG_ECORE_LL2_BITMAP_IDX     (0x1 << 6)
 786
 787 static u32 ecore_get_config_bitmap(void)
 788 {
 789         u32 config_bitmap = 0x0;
 790
 791 #ifdef CONFIG_ECORE_L2
 792         config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
 793 #endif
 794 #ifdef CONFIG_ECORE_SRIOV
 795         config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
 796 #endif
 797 #ifdef CONFIG_ECORE_ROCE
 798         config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
 799 #endif
 800 #ifdef CONFIG_ECORE_IWARP
 801         config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
 802 #endif
 803 #ifdef CONFIG_ECORE_FCOE
 804         config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
 805 #endif
 806 #ifdef CONFIG_ECORE_ISCSI
 807         config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
 808 #endif
 809 #ifdef CONFIG_ECORE_LL2
 810         config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
 811 #endif
 812
 813         return config_bitmap;
 814 }
 815
 816 struct ecore_load_req_in_params {
 817         u8 hsi_ver;
 818 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT  0
 819 #define ECORE_LOAD_REQ_HSI_VER_1        1
 820         u32 drv_ver_0;
 821         u32 drv_ver_1;
 822         u32 fw_ver;
 823         u8 drv_role;
 824         u8 timeout_val;
 825         u8 force_cmd;
 826         bool avoid_eng_reset;
 827 };
 828
 829 struct ecore_load_req_out_params {
 830         u32 load_code;
 831         u32 exist_drv_ver_0;
 832         u32 exist_drv_ver_1;
 833         u32 exist_fw_ver;
 834         u8 exist_drv_role;
 835         u8 mfw_hsi_ver;
 836         bool drv_exists;
 837 };
 838
 839 static enum _ecore_status_t
 840 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 841                      struct ecore_load_req_in_params *p_in_params,
 842                      struct ecore_load_req_out_params *p_out_params)
 843 {
 844         struct ecore_mcp_mb_params mb_params;
 845         struct load_req_stc load_req;
 846         struct load_rsp_stc load_rsp;
 847         u32 hsi_ver;
 848         enum _ecore_status_t rc;
 849
 850         OSAL_MEM_ZERO(&load_req, sizeof(load_req));
 851         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 852         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 853         load_req.fw_ver = p_in_params->fw_ver;
 854         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 855         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 856                       p_in_params->timeout_val);
 857         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
 858         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 859                       p_in_params->avoid_eng_reset);
 860
 861         hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
 862                   DRV_ID_MCP_HSI_VER_CURRENT :
 863                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
 864
 865         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 866         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 867         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
 868         mb_params.p_data_src = &load_req;
 869         mb_params.data_src_size = sizeof(load_req);
 870         mb_params.p_data_dst = &load_rsp;
 871         mb_params.data_dst_size = sizeof(load_rsp);
 872
 873         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 874                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 875                    mb_params.param,
 876                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 877                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 878                    GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 879                    GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 880
 881         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
 882                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 883                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 884                            load_req.drv_ver_0, load_req.drv_ver_1,
 885                            load_req.fw_ver, load_req.misc0,
 886                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 887                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
 888                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 889                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 890
 891         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 892         if (rc != ECORE_SUCCESS) {
 893                 DP_NOTICE(p_hwfn, false,
 894                           "Failed to send load request, rc = %d\n", rc);
 895                 return rc;
 896         }
 897
 898         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 899                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 900         p_out_params->load_code = mb_params.mcp_resp;
 901
 902         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
 903             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 904                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 905                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 906                            load_rsp.drv_ver_0, load_rsp.drv_ver_1,
 907                            load_rsp.fw_ver, load_rsp.misc0,
 908                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 909                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 910                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 911
 912                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 913                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 914                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 915                 p_out_params->exist_drv_role =
 916                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 917                 p_out_params->mfw_hsi_ver =
 918                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 919                 p_out_params->drv_exists =
 920                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 921                         LOAD_RSP_FLAGS0_DRV_EXISTS;
 922         }
 923
 924         return ECORE_SUCCESS;
 925 }
 926
 927 static void ecore_get_mfw_drv_role(enum ecore_drv_role drv_role,
 928                                    u8 *p_mfw_drv_role)
 929 {
 930         switch (drv_role) {
 931         case ECORE_DRV_ROLE_OS:
 932                 *p_mfw_drv_role = DRV_ROLE_OS;
 933                 break;
 934         case ECORE_DRV_ROLE_KDUMP:
 935                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 936                 break;
 937         }
 938 }
 939
 940 enum ecore_load_req_force {
 941         ECORE_LOAD_REQ_FORCE_NONE,
 942         ECORE_LOAD_REQ_FORCE_PF,
 943         ECORE_LOAD_REQ_FORCE_ALL,
 944 };
 945
 946 static void ecore_get_mfw_force_cmd(enum ecore_load_req_force force_cmd,
 947                                     u8 *p_mfw_force_cmd)
 948 {
 949         switch (force_cmd) {
 950         case ECORE_LOAD_REQ_FORCE_NONE:
 951                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 952                 break;
 953         case ECORE_LOAD_REQ_FORCE_PF:
 954                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 955                 break;
 956         case ECORE_LOAD_REQ_FORCE_ALL:
 957                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 958                 break;
 959         }
 960 }
 961
 962 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 963                                         struct ecore_ptt *p_ptt,
 964                                         struct ecore_load_req_params *p_params)
 965 {
 966         struct ecore_load_req_out_params out_params;
 967         struct ecore_load_req_in_params in_params;
 968         u8 mfw_drv_role = 0, mfw_force_cmd;
 969         enum _ecore_status_t rc;
 970
 971 #ifndef ASIC_ONLY
 972         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 973                 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
 974                 return ECORE_SUCCESS;
 975         }
 976 #endif
 977
 978         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
 979         in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
 980         in_params.drv_ver_0 = ECORE_VERSION;
 981         in_params.drv_ver_1 = ecore_get_config_bitmap();
 982         in_params.fw_ver = STORM_FW_VERSION;
 983         ecore_get_mfw_drv_role(p_params->drv_role, &mfw_drv_role);
 984         in_params.drv_role = mfw_drv_role;
 985         in_params.timeout_val = p_params->timeout_val;
 986         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 987         in_params.force_cmd = mfw_force_cmd;
 988         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 989
 990         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 991         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 992         if (rc != ECORE_SUCCESS)
 993                 return rc;
 994
 995         /* First handle cases where another load request should/might be sent:
 996          * - MFW expects the old interface [HSI version = 1]
 997          * - MFW responds that a force load request is required
 998          */
 999         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
1000                 DP_INFO(p_hwfn,
1001                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
1002
1003                 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
1004                 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
1005                 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
1006                                           &out_params);
1007                 if (rc != ECORE_SUCCESS)
1008                         return rc;
1009         } else if (out_params.load_code ==
1010                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
1011                 if (ecore_mcp_can_force_load(in_params.drv_role,
1012                                              out_params.exist_drv_role,
1013                                              p_params->override_force_load)) {
1014                         DP_INFO(p_hwfn,
1015                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
1016                                 in_params.drv_role, in_params.fw_ver,
1017                                 in_params.drv_ver_0, in_params.drv_ver_1,
1018                                 out_params.exist_drv_role,
1019                                 out_params.exist_fw_ver,
1020                                 out_params.exist_drv_ver_0,
1021                                 out_params.exist_drv_ver_1);
1022
1023                         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_ALL,
1024                                                 &mfw_force_cmd);
1025
1026                         in_params.force_cmd = mfw_force_cmd;
1027                         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
1028                         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
1029                                                   &out_params);
1030                         if (rc != ECORE_SUCCESS)
1031                                 return rc;
1032                 } else {
1033                         DP_NOTICE(p_hwfn, false,
1034                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1035                                   in_params.drv_role, in_params.fw_ver,
1036                                   in_params.drv_ver_0, in_params.drv_ver_1,
1037                                   out_params.exist_drv_role,
1038                                   out_params.exist_fw_ver,
1039                                   out_params.exist_drv_ver_0,
1040                                   out_params.exist_drv_ver_1);
1041
1042                         ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1043                         return ECORE_BUSY;
1044                 }
1045         }
1046
1047         /* Now handle the other types of responses.
1048          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1049          * expected here after the additional revised load requests were sent.
1050          */
1051         switch (out_params.load_code) {
1052         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1053         case FW_MSG_CODE_DRV_LOAD_PORT:
1054         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1055                 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1056                     out_params.drv_exists) {
1057                         /* The role and fw/driver version match, but the PF is
1058                          * already loaded and has not been unloaded gracefully.
1059                          * This is unexpected since a quasi-FLR request was
1060                          * previously sent as part of ecore_hw_prepare().
1061                          */
1062                         DP_NOTICE(p_hwfn, false,
1063                                   "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1064                         return ECORE_INVAL;
1065                 }
1066                 break;
1067         default:
1068                 DP_NOTICE(p_hwfn, false,
1069                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1070                           out_params.load_code);
1071                 return ECORE_BUSY;
1072         }
1073
1074         p_params->load_code = out_params.load_code;
1075
1076         return ECORE_SUCCESS;
1077 }
1078
1079 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1080                                          struct ecore_ptt *p_ptt)
1081 {
1082         u32 resp = 0, param = 0;
1083         enum _ecore_status_t rc;
1084
1085         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1086                            &param);
1087         if (rc != ECORE_SUCCESS) {
1088                 DP_NOTICE(p_hwfn, false,
1089                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1090                 return rc;
1091         }
1092
1093         /* Check if there is a DID mismatch between nvm-cfg/efuse */
1094         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1095                 DP_NOTICE(p_hwfn, false,
1096                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1097
1098         return ECORE_SUCCESS;
1099 }
1100
1101 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1102                                           struct ecore_ptt *p_ptt)
1103 {
1104         u32 wol_param, mcp_resp, mcp_param;
1105
1106         /* @DPDK */
1107         wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1108
1109         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1110                              &mcp_resp, &mcp_param);
1111 }
1112
1113 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1114                                            struct ecore_ptt *p_ptt)
1115 {
1116         struct ecore_mcp_mb_params mb_params;
1117         struct mcp_mac wol_mac;
1118
1119         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1120         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1121
1122         return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1123 }
1124
1125 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1126                                     struct ecore_ptt *p_ptt)
1127 {
1128         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1129                                         PUBLIC_PATH);
1130         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1131         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1132                                      ECORE_PATH_ID(p_hwfn));
1133         u32 disabled_vfs[VF_MAX_STATIC / 32];
1134         int i;
1135
1136         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1137                    "Reading Disabled VF information from [offset %08x],"
1138                    " path_addr %08x\n",
1139                    mfw_path_offsize, path_addr);
1140
1141         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1142                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1143                                            path_addr +
1144                                            OFFSETOF(struct public_path,
1145                                                     mcp_vf_disabled) +
1146                                            sizeof(u32) * i);
1147                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1148                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1149                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1150         }
1151
1152         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1153                 OSAL_VF_FLR_UPDATE(p_hwfn);
1154 }
1155
1156 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1157                                           struct ecore_ptt *p_ptt,
1158                                           u32 *vfs_to_ack)
1159 {
1160         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1161                                         PUBLIC_FUNC);
1162         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1163         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1164                                      MCP_PF_ID(p_hwfn));
1165         struct ecore_mcp_mb_params mb_params;
1166         enum _ecore_status_t rc;
1167         int i;
1168
1169         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1170                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1171                            "Acking VFs [%08x,...,%08x] - %08x\n",
1172                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1173
1174         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1175         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1176         mb_params.p_data_src = vfs_to_ack;
1177         mb_params.data_src_size = VF_MAX_STATIC / 8;
1178         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1179                                      &mb_params);
1180         if (rc != ECORE_SUCCESS) {
1181                 DP_NOTICE(p_hwfn, false,
1182                           "Failed to pass ACK for VF flr to MFW\n");
1183                 return ECORE_TIMEOUT;
1184         }
1185
1186         /* TMP - clear the ACK bits; should be done by MFW */
1187         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1188                 ecore_wr(p_hwfn, p_ptt,
1189                          func_addr +
1190                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1191                          i * sizeof(u32), 0);
1192
1193         return rc;
1194 }
1195
1196 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1197                                                 struct ecore_ptt *p_ptt)
1198 {
1199         u32 transceiver_state;
1200
1201         transceiver_state = ecore_rd(p_hwfn, p_ptt,
1202                                      p_hwfn->mcp_info->port_addr +
1203                                      OFFSETOF(struct public_port,
1204                                               transceiver_data));
1205
1206         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1207                    "Received transceiver state update [0x%08x] from mfw"
1208                    " [Addr 0x%x]\n",
1209                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1210                                             OFFSETOF(struct public_port,
1211                                                      transceiver_data)));
1212
1213         transceiver_state = GET_MFW_FIELD(transceiver_state,
1214                                           ETH_TRANSCEIVER_STATE);
1215
1216         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1217                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1218         else
1219                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1220
1221         OSAL_TRANSCEIVER_UPDATE(p_hwfn);
1222 }
1223
1224 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1225                                       struct ecore_ptt *p_ptt,
1226                                       struct ecore_mcp_link_state *p_link)
1227 {
1228         u32 eee_status, val;
1229
1230         p_link->eee_adv_caps = 0;
1231         p_link->eee_lp_adv_caps = 0;
1232         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1233                                      OFFSETOF(struct public_port, eee_status));
1234         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1235         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1236         if (val & EEE_1G_ADV)
1237                 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1238         if (val & EEE_10G_ADV)
1239                 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1240         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1241         if (val & EEE_1G_ADV)
1242                 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1243         if (val & EEE_10G_ADV)
1244                 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1245 }
1246
1247 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1248                                     struct ecore_ptt *p_ptt,
1249                                     struct public_func *p_data,
1250                                     int pfid)
1251 {
1252         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1253                                         PUBLIC_FUNC);
1254         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1255         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1256         u32 i, size;
1257
1258         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1259
1260         size = OSAL_MIN_T(u32, sizeof(*p_data),
1261                           SECTION_SIZE(mfw_path_offsize));
1262         for (i = 0; i < size / sizeof(u32); i++)
1263                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1264                                               func_addr + (i << 2));
1265
1266         return size;
1267 }
1268
1269 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1270                                          struct ecore_ptt *p_ptt,
1271                                          bool b_reset)
1272 {
1273         struct ecore_mcp_link_state *p_link;
1274         u8 max_bw, min_bw;
1275         u32 status = 0;
1276
1277         /* Prevent SW/attentions from doing this at the same time */
1278         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1279
1280         p_link = &p_hwfn->mcp_info->link_output;
1281         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1282         if (!b_reset) {
1283                 status = ecore_rd(p_hwfn, p_ptt,
1284                                   p_hwfn->mcp_info->port_addr +
1285                                   OFFSETOF(struct public_port, link_status));
1286                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1287                            "Received link update [0x%08x] from mfw"
1288                            " [Addr 0x%x]\n",
1289                            status, (u32)(p_hwfn->mcp_info->port_addr +
1290                                           OFFSETOF(struct public_port,
1291                                                    link_status)));
1292         } else {
1293                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1294                            "Resetting link indications\n");
1295                 goto out;
1296         }
1297
1298         if (p_hwfn->b_drv_link_init) {
1299                 /* Link indication with modern MFW arrives as per-PF
1300                  * indication.
1301                  */
1302                 if (p_hwfn->mcp_info->capabilities &
1303                     FW_MB_PARAM_FEATURE_SUPPORT_VLINK) {
1304                         struct public_func shmem_info;
1305
1306                         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1307                                                  MCP_PF_ID(p_hwfn));
1308                         p_link->link_up = !!(shmem_info.status &
1309                                              FUNC_STATUS_VIRTUAL_LINK_UP);
1310                 } else {
1311                         p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1312                 }
1313         } else {
1314                 p_link->link_up = false;
1315         }
1316
1317         p_link->full_duplex = true;
1318         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1319         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1320                 p_link->speed = 100000;
1321                 break;
1322         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1323                 p_link->speed = 50000;
1324                 break;
1325         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1326                 p_link->speed = 40000;
1327                 break;
1328         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1329                 p_link->speed = 25000;
1330                 break;
1331         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1332                 p_link->speed = 20000;
1333                 break;
1334         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1335                 p_link->speed = 10000;
1336                 break;
1337         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1338                 p_link->full_duplex = false;
1339                 /* Fall-through */
1340         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1341                 p_link->speed = 1000;
1342                 break;
1343         default:
1344                 p_link->speed = 0;
1345         }
1346
1347         /* We never store total line speed as p_link->speed is
1348          * again changes according to bandwidth allocation.
1349          */
1350         if (p_link->link_up && p_link->speed)
1351                 p_link->line_speed = p_link->speed;
1352         else
1353                 p_link->line_speed = 0;
1354
1355         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1356         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1357
1358         /* Max bandwidth configuration */
1359         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1360                                            p_link, max_bw);
1361
1362         /* Min bandwidth configuration */
1363         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1364                                            p_link, min_bw);
1365         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1366                                               p_link->min_pf_rate);
1367
1368         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1369         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1370         p_link->parallel_detection = !!(status &
1371                                          LINK_STATUS_PARALLEL_DETECTION_USED);
1372         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1373
1374         p_link->partner_adv_speed |=
1375             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1376             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1377         p_link->partner_adv_speed |=
1378             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1379             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1380         p_link->partner_adv_speed |=
1381             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1382             ECORE_LINK_PARTNER_SPEED_10G : 0;
1383         p_link->partner_adv_speed |=
1384             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1385             ECORE_LINK_PARTNER_SPEED_20G : 0;
1386         p_link->partner_adv_speed |=
1387             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1388             ECORE_LINK_PARTNER_SPEED_25G : 0;
1389         p_link->partner_adv_speed |=
1390             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1391             ECORE_LINK_PARTNER_SPEED_40G : 0;
1392         p_link->partner_adv_speed |=
1393             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1394             ECORE_LINK_PARTNER_SPEED_50G : 0;
1395         p_link->partner_adv_speed |=
1396             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1397             ECORE_LINK_PARTNER_SPEED_100G : 0;
1398
1399         p_link->partner_tx_flow_ctrl_en =
1400             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1401         p_link->partner_rx_flow_ctrl_en =
1402             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1403
1404         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1405         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1406                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1407                 break;
1408         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1409                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1410                 break;
1411         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1412                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1413                 break;
1414         default:
1415                 p_link->partner_adv_pause = 0;
1416         }
1417
1418         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1419
1420         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1421                 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1422
1423         OSAL_LINK_UPDATE(p_hwfn);
1424 out:
1425         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1426 }
1427
1428 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1429                                         struct ecore_ptt *p_ptt, bool b_up)
1430 {
1431         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1432         struct ecore_mcp_mb_params mb_params;
1433         struct eth_phy_cfg phy_cfg;
1434         enum _ecore_status_t rc = ECORE_SUCCESS;
1435         u32 cmd;
1436
1437 #ifndef ASIC_ONLY
1438         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1439                 return ECORE_SUCCESS;
1440 #endif
1441
1442         /* Set the shmem configuration according to params */
1443         OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1444         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1445         if (!params->speed.autoneg)
1446                 phy_cfg.speed = params->speed.forced_speed;
1447         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1448         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1449         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1450         phy_cfg.adv_speed = params->speed.advertised_speeds;
1451         phy_cfg.loopback_mode = params->loopback_mode;
1452
1453         /* There are MFWs that share this capability regardless of whether
1454          * this is feasible or not. And given that at the very least adv_caps
1455          * would be set internally by ecore, we want to make sure LFA would
1456          * still work.
1457          */
1458         if ((p_hwfn->mcp_info->capabilities &
1459              FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1460             params->eee.enable) {
1461                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1462                 if (params->eee.tx_lpi_enable)
1463                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1464                 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1465                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1466                 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1467                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1468                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1469                                     EEE_TX_TIMER_USEC_OFFSET) &
1470                                         EEE_TX_TIMER_USEC_MASK;
1471         }
1472
1473         p_hwfn->b_drv_link_init = b_up;
1474
1475         if (b_up)
1476                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1477                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1478                            phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1479                            phy_cfg.loopback_mode);
1480         else
1481                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1482
1483         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1484         mb_params.cmd = cmd;
1485         mb_params.p_data_src = &phy_cfg;
1486         mb_params.data_src_size = sizeof(phy_cfg);
1487         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1488
1489         /* if mcp fails to respond we must abort */
1490         if (rc != ECORE_SUCCESS) {
1491                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1492                 return rc;
1493         }
1494
1495         /* Mimic link-change attention, done for several reasons:
1496          *  - On reset, there's no guarantee MFW would trigger
1497          *    an attention.
1498          *  - On initialization, older MFWs might not indicate link change
1499          *    during LFA, so we'll never get an UP indication.
1500          */
1501         ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1502
1503         return ECORE_SUCCESS;
1504 }
1505
1506 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1507                                    struct ecore_ptt *p_ptt)
1508 {
1509         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1510
1511         /* TODO - Add support for VFs */
1512         if (IS_VF(p_hwfn->p_dev))
1513                 return ECORE_INVAL;
1514
1515         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1516                                                  PUBLIC_PATH);
1517         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1518         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1519
1520         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1521                                  path_addr +
1522                                  OFFSETOF(struct public_path, process_kill)) &
1523             PROCESS_KILL_COUNTER_MASK;
1524
1525         return proc_kill_cnt;
1526 }
1527
1528 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1529                                           struct ecore_ptt *p_ptt)
1530 {
1531         struct ecore_dev *p_dev = p_hwfn->p_dev;
1532         u32 proc_kill_cnt;
1533
1534         /* Prevent possible attentions/interrupts during the recovery handling
1535          * and till its load phase, during which they will be re-enabled.
1536          */
1537         ecore_int_igu_disable_int(p_hwfn, p_ptt);
1538
1539         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1540
1541         /* The following operations should be done once, and thus in CMT mode
1542          * are carried out by only the first HW function.
1543          */
1544         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1545                 return;
1546
1547         if (p_dev->recov_in_prog) {
1548                 DP_NOTICE(p_hwfn, false,
1549                           "Ignoring the indication since a recovery"
1550                           " process is already in progress\n");
1551                 return;
1552         }
1553
1554         p_dev->recov_in_prog = true;
1555
1556         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1557         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1558
1559         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1560 }
1561
1562 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1563                                           struct ecore_ptt *p_ptt,
1564                                           enum MFW_DRV_MSG_TYPE type)
1565 {
1566         enum ecore_mcp_protocol_type stats_type;
1567         union ecore_mcp_protocol_stats stats;
1568         struct ecore_mcp_mb_params mb_params;
1569         u32 hsi_param;
1570         enum _ecore_status_t rc;
1571
1572         switch (type) {
1573         case MFW_DRV_MSG_GET_LAN_STATS:
1574                 stats_type = ECORE_MCP_LAN_STATS;
1575                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1576                 break;
1577         default:
1578                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1579                            "Invalid protocol type %d\n", type);
1580                 return;
1581         }
1582
1583         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1584
1585         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1586         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1587         mb_params.param = hsi_param;
1588         mb_params.p_data_src = &stats;
1589         mb_params.data_src_size = sizeof(stats);
1590         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1591         if (rc != ECORE_SUCCESS)
1592                 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1593 }
1594
1595 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1596                                     struct public_func *p_shmem_info)
1597 {
1598         struct ecore_mcp_function_info *p_info;
1599
1600         p_info = &p_hwfn->mcp_info->func_info;
1601
1602         /* TODO - bandwidth min/max should have valid values of 1-100,
1603          * as well as some indication that the feature is disabled.
1604          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1605          * limit and correct value to min `1' and max `100' if limit isn't in
1606          * range.
1607          */
1608         p_info->bandwidth_min = (p_shmem_info->config &
1609                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1610             FUNC_MF_CFG_MIN_BW_OFFSET;
1611         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1612                 DP_INFO(p_hwfn,
1613                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1614                         p_info->bandwidth_min);
1615                 p_info->bandwidth_min = 1;
1616         }
1617
1618         p_info->bandwidth_max = (p_shmem_info->config &
1619                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1620             FUNC_MF_CFG_MAX_BW_OFFSET;
1621         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1622                 DP_INFO(p_hwfn,
1623                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1624                         p_info->bandwidth_max);
1625                 p_info->bandwidth_max = 100;
1626         }
1627 }
1628
1629 static void
1630 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1631 {
1632         struct ecore_mcp_function_info *p_info;
1633         struct public_func shmem_info;
1634         u32 resp = 0, param = 0;
1635
1636         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1637
1638         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1639
1640         p_info = &p_hwfn->mcp_info->func_info;
1641
1642         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1643
1644         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1645
1646         /* Acknowledge the MFW */
1647         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1648                       &param);
1649 }
1650
1651 static void ecore_mcp_update_stag(struct ecore_hwfn *p_hwfn,
1652                                   struct ecore_ptt *p_ptt)
1653 {
1654         struct public_func shmem_info;
1655         u32 resp = 0, param = 0;
1656
1657         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1658                                  MCP_PF_ID(p_hwfn));
1659
1660         p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
1661                                                  FUNC_MF_CFG_OV_STAG_MASK;
1662         p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
1663         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) {
1664                 if (p_hwfn->hw_info.ovlan != ECORE_MCP_VLAN_UNSET) {
1665                         ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE,
1666                                  p_hwfn->hw_info.ovlan);
1667                         ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1);
1668
1669                         /* Configure DB to add external vlan to EDPM packets */
1670                         ecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);
1671                         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2,
1672                                  p_hwfn->hw_info.ovlan);
1673                 } else {
1674                         ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0);
1675                         ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0);
1676
1677                         /* Configure DB to add external vlan to EDPM packets */
1678                         ecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0);
1679                         ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0);
1680                 }
1681
1682                 ecore_sp_pf_update_stag(p_hwfn);
1683         }
1684
1685         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "ovlan  = %d hw_mode = 0x%x\n",
1686                    p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode);
1687         OSAL_HW_INFO_CHANGE(p_hwfn, ECORE_HW_INFO_CHANGE_OVLAN);
1688
1689         /* Acknowledge the MFW */
1690         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
1691                       &resp, &param);
1692 }
1693
1694 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn)
1695 {
1696         /* A single notification should be sent to upper driver in CMT mode */
1697         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1698                 return;
1699
1700         DP_NOTICE(p_hwfn, false,
1701                   "Fan failure was detected on the network interface card"
1702                   " and it's going to be shut down.\n");
1703
1704         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1705 }
1706
1707 struct ecore_mdump_cmd_params {
1708         u32 cmd;
1709         void *p_data_src;
1710         u8 data_src_size;
1711         void *p_data_dst;
1712         u8 data_dst_size;
1713         u32 mcp_resp;
1714 };
1715
1716 static enum _ecore_status_t
1717 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1718                     struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1719 {
1720         struct ecore_mcp_mb_params mb_params;
1721         enum _ecore_status_t rc;
1722
1723         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1724         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1725         mb_params.param = p_mdump_cmd_params->cmd;
1726         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1727         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1728         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1729         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1730         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1731         if (rc != ECORE_SUCCESS)
1732                 return rc;
1733
1734         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1735
1736         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1737                 DP_INFO(p_hwfn,
1738                         "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1739                         p_mdump_cmd_params->cmd);
1740                 rc = ECORE_NOTIMPL;
1741         } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1742                 DP_INFO(p_hwfn,
1743                         "The mdump command is not supported by the MFW\n");
1744                 rc = ECORE_NOTIMPL;
1745         }
1746
1747         return rc;
1748 }
1749
1750 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1751                                                 struct ecore_ptt *p_ptt)
1752 {
1753         struct ecore_mdump_cmd_params mdump_cmd_params;
1754
1755         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1756         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1757
1758         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1759 }
1760
1761 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1762                                                 struct ecore_ptt *p_ptt,
1763                                                 u32 epoch)
1764 {
1765         struct ecore_mdump_cmd_params mdump_cmd_params;
1766
1767         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1768         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1769         mdump_cmd_params.p_data_src = &epoch;
1770         mdump_cmd_params.data_src_size = sizeof(epoch);
1771
1772         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1773 }
1774
1775 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1776                                              struct ecore_ptt *p_ptt)
1777 {
1778         struct ecore_mdump_cmd_params mdump_cmd_params;
1779
1780         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1781         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1782
1783         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1784 }
1785
1786 static enum _ecore_status_t
1787 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1788                            struct mdump_config_stc *p_mdump_config)
1789 {
1790         struct ecore_mdump_cmd_params mdump_cmd_params;
1791         enum _ecore_status_t rc;
1792
1793         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1794         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1795         mdump_cmd_params.p_data_dst = p_mdump_config;
1796         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1797
1798         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1799         if (rc != ECORE_SUCCESS)
1800                 return rc;
1801
1802         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1803                 DP_INFO(p_hwfn,
1804                         "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1805                         mdump_cmd_params.mcp_resp);
1806                 rc = ECORE_UNKNOWN_ERROR;
1807         }
1808
1809         return rc;
1810 }
1811
1812 enum _ecore_status_t
1813 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1814                          struct ecore_mdump_info *p_mdump_info)
1815 {
1816         u32 addr, global_offsize, global_addr;
1817         struct mdump_config_stc mdump_config;
1818         enum _ecore_status_t rc;
1819
1820         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1821
1822         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1823                                     PUBLIC_GLOBAL);
1824         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1825         global_addr = SECTION_ADDR(global_offsize, 0);
1826         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1827                                         global_addr +
1828                                         OFFSETOF(struct public_global,
1829                                                  mdump_reason));
1830
1831         if (p_mdump_info->reason) {
1832                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1833                 if (rc != ECORE_SUCCESS)
1834                         return rc;
1835
1836                 p_mdump_info->version = mdump_config.version;
1837                 p_mdump_info->config = mdump_config.config;
1838                 p_mdump_info->epoch = mdump_config.epoc;
1839                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1840                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1841
1842                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1843                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1844                            p_mdump_info->reason, p_mdump_info->version,
1845                            p_mdump_info->config, p_mdump_info->epoch,
1846                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1847         } else {
1848                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1849                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1850         }
1851
1852         return ECORE_SUCCESS;
1853 }
1854
1855 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1856                                                 struct ecore_ptt *p_ptt)
1857 {
1858         struct ecore_mdump_cmd_params mdump_cmd_params;
1859
1860         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1861         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1862
1863         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1864 }
1865
1866 enum _ecore_status_t
1867 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1868                            struct ecore_mdump_retain_data *p_mdump_retain)
1869 {
1870         struct ecore_mdump_cmd_params mdump_cmd_params;
1871         struct mdump_retain_data_stc mfw_mdump_retain;
1872         enum _ecore_status_t rc;
1873
1874         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1875         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1876         mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1877         mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1878
1879         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1880         if (rc != ECORE_SUCCESS)
1881                 return rc;
1882
1883         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1884                 DP_INFO(p_hwfn,
1885                         "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1886                         mdump_cmd_params.mcp_resp);
1887                 return ECORE_UNKNOWN_ERROR;
1888         }
1889
1890         p_mdump_retain->valid = mfw_mdump_retain.valid;
1891         p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1892         p_mdump_retain->pf = mfw_mdump_retain.pf;
1893         p_mdump_retain->status = mfw_mdump_retain.status;
1894
1895         return ECORE_SUCCESS;
1896 }
1897
1898 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1899                                                 struct ecore_ptt *p_ptt)
1900 {
1901         struct ecore_mdump_cmd_params mdump_cmd_params;
1902
1903         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1904         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1905
1906         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1907 }
1908
1909 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1910                                             struct ecore_ptt *p_ptt)
1911 {
1912         struct ecore_mdump_retain_data mdump_retain;
1913         enum _ecore_status_t rc;
1914
1915         /* In CMT mode - no need for more than a single acknowledgment to the
1916          * MFW, and no more than a single notification to the upper driver.
1917          */
1918         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1919                 return;
1920
1921         rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1922         if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1923                 DP_NOTICE(p_hwfn, false,
1924                           "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1925                           mdump_retain.epoch, mdump_retain.pf,
1926                           mdump_retain.status);
1927         } else {
1928                 DP_NOTICE(p_hwfn, false,
1929                           "The MFW notified that a critical error occurred in the device\n");
1930         }
1931
1932         if (p_hwfn->p_dev->allow_mdump) {
1933                 DP_NOTICE(p_hwfn, false,
1934                           "Not acknowledging the notification to allow the MFW crash dump\n");
1935                 return;
1936         }
1937
1938         DP_NOTICE(p_hwfn, false,
1939                   "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1940         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1941         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1942 }
1943
1944 void
1945 ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1946 {
1947         struct public_func shmem_info;
1948         u32 port_cfg, val;
1949
1950         if (!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
1951                 return;
1952
1953         OSAL_MEMSET(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1954         port_cfg = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1955                             OFFSETOF(struct public_port, oem_cfg_port));
1956         val = GET_MFW_FIELD(port_cfg, OEM_CFG_CHANNEL_TYPE);
1957         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1958                 DP_NOTICE(p_hwfn, false, "Incorrect UFP Channel type  %d\n",
1959                           val);
1960
1961         val = GET_MFW_FIELD(port_cfg, OEM_CFG_SCHED_TYPE);
1962         if (val == OEM_CFG_SCHED_TYPE_ETS)
1963                 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_ETS;
1964         else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW)
1965                 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_VNIC_BW;
1966         else
1967                 DP_NOTICE(p_hwfn, false, "Unknown UFP scheduling mode %d\n",
1968                           val);
1969
1970         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1971                                  MCP_PF_ID(p_hwfn));
1972         val = GET_MFW_FIELD(shmem_info.oem_cfg_func, OEM_CFG_FUNC_TC);
1973         p_hwfn->ufp_info.tc = (u8)val;
1974         val = GET_MFW_FIELD(shmem_info.oem_cfg_func,
1975                             OEM_CFG_FUNC_HOST_PRI_CTRL);
1976         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC)
1977                 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_VNIC;
1978         else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS)
1979                 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_OS;
1980         else
1981                 DP_NOTICE(p_hwfn, false, "Unknown Host priority control %d\n",
1982                           val);
1983
1984         DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1985                    "UFP shmem config: mode = %d tc = %d pri_type = %d\n",
1986                    p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc,
1987                    p_hwfn->ufp_info.pri_type);
1988 }
1989
1990 static enum _ecore_status_t
1991 ecore_mcp_handle_ufp_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1992 {
1993         ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
1994
1995         if (p_hwfn->ufp_info.mode == ECORE_UFP_MODE_VNIC_BW) {
1996                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1997                 p_hwfn->hw_info.offload_tc = p_hwfn->ufp_info.tc;
1998
1999                 ecore_qm_reconf(p_hwfn, p_ptt);
2000         } else {
2001                 /* Merge UFP TC with the dcbx TC data */
2002                 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
2003                                             ECORE_DCBX_OPERATIONAL_MIB);
2004         }
2005
2006         /* update storm FW with negotiation results */
2007         ecore_sp_pf_update_ufp(p_hwfn);
2008
2009         return ECORE_SUCCESS;
2010 }
2011
2012 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
2013                                              struct ecore_ptt *p_ptt)
2014 {
2015         struct ecore_mcp_info *info = p_hwfn->mcp_info;
2016         enum _ecore_status_t rc = ECORE_SUCCESS;
2017         bool found = false;
2018         u16 i;
2019
2020         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
2021
2022         /* Read Messages from MFW */
2023         ecore_mcp_read_mb(p_hwfn, p_ptt);
2024
2025         /* Compare current messages to old ones */
2026         for (i = 0; i < info->mfw_mb_length; i++) {
2027                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
2028                         continue;
2029
2030                 found = true;
2031
2032                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
2033                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
2034                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
2035
2036                 switch (i) {
2037                 case MFW_DRV_MSG_LINK_CHANGE:
2038                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
2039                         break;
2040                 case MFW_DRV_MSG_VF_DISABLED:
2041                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
2042                         break;
2043                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
2044                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
2045                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
2046                         break;
2047                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
2048                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
2049                                                     ECORE_DCBX_REMOTE_MIB);
2050                         break;
2051                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
2052                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
2053                                                     ECORE_DCBX_OPERATIONAL_MIB);
2054                         /* clear the user-config cache */
2055                         OSAL_MEMSET(&p_hwfn->p_dcbx_info->set, 0,
2056                                     sizeof(struct ecore_dcbx_set));
2057                         break;
2058                 case MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED:
2059                         ecore_lldp_mib_update_event(p_hwfn, p_ptt);
2060                         break;
2061                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
2062                         ecore_mcp_handle_ufp_event(p_hwfn, p_ptt);
2063                         break;
2064                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
2065                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
2066                         break;
2067                 case MFW_DRV_MSG_ERROR_RECOVERY:
2068                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
2069                         break;
2070                 case MFW_DRV_MSG_GET_LAN_STATS:
2071                 case MFW_DRV_MSG_GET_FCOE_STATS:
2072                 case MFW_DRV_MSG_GET_ISCSI_STATS:
2073                 case MFW_DRV_MSG_GET_RDMA_STATS:
2074                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
2075                         break;
2076                 case MFW_DRV_MSG_BW_UPDATE:
2077                         ecore_mcp_update_bw(p_hwfn, p_ptt);
2078                         break;
2079                 case MFW_DRV_MSG_S_TAG_UPDATE:
2080                         ecore_mcp_update_stag(p_hwfn, p_ptt);
2081                         break;
2082                 case MFW_DRV_MSG_FAILURE_DETECTED:
2083                         ecore_mcp_handle_fan_failure(p_hwfn);
2084                         break;
2085                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
2086                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
2087                         break;
2088                 default:
2089                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
2090                         rc = ECORE_INVAL;
2091                 }
2092         }
2093
2094         /* ACK everything */
2095         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
2096                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
2097
2098                 /* MFW expect answer in BE, so we force write in that format */
2099                 ecore_wr(p_hwfn, p_ptt,
2100                          info->mfw_mb_addr + sizeof(u32) +
2101                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
2102                          sizeof(u32) + i * sizeof(u32), val);
2103         }
2104
2105         if (!found) {
2106                 DP_NOTICE(p_hwfn, false,
2107                           "Received an MFW message indication but no"
2108                           " new message!\n");
2109                 rc = ECORE_INVAL;
2110         }
2111
2112         /* Copy the new mfw messages into the shadow */
2113         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
2114
2115         return rc;
2116 }
2117
2118 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
2119                                            struct ecore_ptt *p_ptt,
2120                                            u32 *p_mfw_ver,
2121                                            u32 *p_running_bundle_id)
2122 {
2123         u32 global_offsize;
2124
2125 #ifndef ASIC_ONLY
2126         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2127                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
2128                 return ECORE_SUCCESS;
2129         }
2130 #endif
2131
2132         if (IS_VF(p_hwfn->p_dev)) {
2133                 if (p_hwfn->vf_iov_info) {
2134                         struct pfvf_acquire_resp_tlv *p_resp;
2135
2136                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
2137                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
2138                         return ECORE_SUCCESS;
2139                 } else {
2140                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2141                                    "VF requested MFW version prior to ACQUIRE\n");
2142                         return ECORE_INVAL;
2143                 }
2144         }
2145
2146         global_offsize = ecore_rd(p_hwfn, p_ptt,
2147                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
2148                                                        public_base,
2149                                                        PUBLIC_GLOBAL));
2150         *p_mfw_ver =
2151             ecore_rd(p_hwfn, p_ptt,
2152                      SECTION_ADDR(global_offsize,
2153                                   0) + OFFSETOF(struct public_global, mfw_ver));
2154
2155         if (p_running_bundle_id != OSAL_NULL) {
2156                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
2157                                                 SECTION_ADDR(global_offsize,
2158                                                              0) +
2159                                                 OFFSETOF(struct public_global,
2160                                                          running_bundle_id));
2161         }
2162
2163         return ECORE_SUCCESS;
2164 }
2165
2166 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
2167                                               struct ecore_ptt *p_ptt,
2168                                               u32 *p_media_type)
2169 {
2170
2171         /* TODO - Add support for VFs */
2172         if (IS_VF(p_hwfn->p_dev))
2173                 return ECORE_INVAL;
2174
2175         if (!ecore_mcp_is_init(p_hwfn)) {
2176                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
2177                 return ECORE_BUSY;
2178         }
2179
2180         if (!p_ptt) {
2181                 *p_media_type = MEDIA_UNSPECIFIED;
2182                 return ECORE_INVAL;
2183         } else {
2184                 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2185                                          p_hwfn->mcp_info->port_addr +
2186                                          OFFSETOF(struct public_port,
2187                                                   media_type));
2188         }
2189
2190         return ECORE_SUCCESS;
2191 }
2192
2193 /* @DPDK */
2194 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2195 static void
2196 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2197                                  enum ecore_pci_personality *p_proto)
2198 {
2199         *p_proto = ECORE_PCI_ETH;
2200
2201         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2202                    "According to Legacy capabilities, L2 personality is %08x\n",
2203                    (u32)*p_proto);
2204 }
2205
2206 /* @DPDK */
2207 static enum _ecore_status_t
2208 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2209                               struct ecore_ptt *p_ptt,
2210                               enum ecore_pci_personality *p_proto)
2211 {
2212         u32 resp = 0, param = 0;
2213         enum _ecore_status_t rc;
2214
2215         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2216                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2217                    (u32)*p_proto, resp, param);
2218         return ECORE_SUCCESS;
2219 }
2220
2221 static enum _ecore_status_t
2222 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2223                           struct public_func *p_info,
2224                           struct ecore_ptt *p_ptt,
2225                           enum ecore_pci_personality *p_proto)
2226 {
2227         enum _ecore_status_t rc = ECORE_SUCCESS;
2228
2229         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2230         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2231                 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2232                     ECORE_SUCCESS)
2233                         ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2234                 break;
2235         default:
2236                 rc = ECORE_INVAL;
2237         }
2238
2239         return rc;
2240 }
2241
2242 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2243                                                     struct ecore_ptt *p_ptt)
2244 {
2245         struct ecore_mcp_function_info *info;
2246         struct public_func shmem_info;
2247
2248         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2249         info = &p_hwfn->mcp_info->func_info;
2250
2251         info->pause_on_host = (shmem_info.config &
2252                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2253
2254         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2255                                       &info->protocol)) {
2256                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2257                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2258                 return ECORE_INVAL;
2259         }
2260
2261         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2262
2263         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2264                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2265                 info->mac[1] = (u8)(shmem_info.mac_upper);
2266                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2267                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2268                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2269                 info->mac[5] = (u8)(shmem_info.mac_lower);
2270         } else {
2271                 /* TODO - are there protocols for which there's no MAC? */
2272                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2273         }
2274
2275         /* TODO - are these calculations true for BE machine? */
2276         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2277                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2278         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2279                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2280
2281         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2282
2283         info->mtu = (u16)shmem_info.mtu_size;
2284
2285         if (info->mtu == 0)
2286                 info->mtu = 1500;
2287
2288         info->mtu = (u16)shmem_info.mtu_size;
2289
2290         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2291                    "Read configuration from shmem: pause_on_host %02x"
2292                     " protocol %02x BW [%02x - %02x]"
2293                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2294                     " node %lx ovlan %04x\n",
2295                    info->pause_on_host, info->protocol,
2296                    info->bandwidth_min, info->bandwidth_max,
2297                    info->mac[0], info->mac[1], info->mac[2],
2298                    info->mac[3], info->mac[4], info->mac[5],
2299                    (unsigned long)info->wwn_port,
2300                    (unsigned long)info->wwn_node, info->ovlan);
2301
2302         return ECORE_SUCCESS;
2303 }
2304
2305 struct ecore_mcp_link_params
2306 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2307 {
2308         if (!p_hwfn || !p_hwfn->mcp_info)
2309                 return OSAL_NULL;
2310         return &p_hwfn->mcp_info->link_input;
2311 }
2312
2313 struct ecore_mcp_link_state
2314 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2315 {
2316         if (!p_hwfn || !p_hwfn->mcp_info)
2317                 return OSAL_NULL;
2318
2319 #ifndef ASIC_ONLY
2320         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2321                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2322                 p_hwfn->mcp_info->link_output.link_up = true;
2323         }
2324 #endif
2325
2326         return &p_hwfn->mcp_info->link_output;
2327 }
2328
2329 struct ecore_mcp_link_capabilities
2330 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2331 {
2332         if (!p_hwfn || !p_hwfn->mcp_info)
2333                 return OSAL_NULL;
2334         return &p_hwfn->mcp_info->link_capabilities;
2335 }
2336
2337 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2338                                      struct ecore_ptt *p_ptt)
2339 {
2340         u32 resp = 0, param = 0;
2341         enum _ecore_status_t rc;
2342
2343         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2344                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2345
2346         /* Wait for the drain to complete before returning */
2347         OSAL_MSLEEP(1020);
2348
2349         return rc;
2350 }
2351
2352 const struct ecore_mcp_function_info
2353 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2354 {
2355         if (!p_hwfn || !p_hwfn->mcp_info)
2356                 return OSAL_NULL;
2357         return &p_hwfn->mcp_info->func_info;
2358 }
2359
2360 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2361                                   struct ecore_ptt *p_ptt, u32 personalities)
2362 {
2363         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2364         struct public_func shmem_info;
2365         int i, count = 0, num_pfs;
2366
2367         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2368
2369         for (i = 0; i < num_pfs; i++) {
2370                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2371                                          MCP_PF_ID_BY_REL(p_hwfn, i));
2372                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2373                         continue;
2374
2375                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2376                                               &protocol) !=
2377                     ECORE_SUCCESS)
2378                         continue;
2379
2380                 if ((1 << ((u32)protocol)) & personalities)
2381                         count++;
2382         }
2383
2384         return count;
2385 }
2386
2387 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2388                                               struct ecore_ptt *p_ptt,
2389                                               u32 *p_flash_size)
2390 {
2391         u32 flash_size;
2392
2393 #ifndef ASIC_ONLY
2394         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2395                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2396                 return ECORE_INVAL;
2397         }
2398 #endif
2399
2400         if (IS_VF(p_hwfn->p_dev))
2401                 return ECORE_INVAL;
2402
2403         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2404         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2405                      MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2406         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2407
2408         *p_flash_size = flash_size;
2409
2410         return ECORE_SUCCESS;
2411 }
2412
2413 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2414                                                   struct ecore_ptt *p_ptt)
2415 {
2416         struct ecore_dev *p_dev = p_hwfn->p_dev;
2417
2418         if (p_dev->recov_in_prog) {
2419                 DP_NOTICE(p_hwfn, false,
2420                           "Avoid triggering a recovery since such a process"
2421                           " is already in progress\n");
2422                 return ECORE_AGAIN;
2423         }
2424
2425         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2426         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2427
2428         return ECORE_SUCCESS;
2429 }
2430
2431 static enum _ecore_status_t
2432 ecore_mcp_config_vf_msix_bb(struct ecore_hwfn *p_hwfn,
2433                             struct ecore_ptt *p_ptt,
2434                             u8 vf_id, u8 num)
2435 {
2436         u32 resp = 0, param = 0, rc_param = 0;
2437         enum _ecore_status_t rc;
2438
2439 /* Only Leader can configure MSIX, and need to take CMT into account */
2440
2441         if (!IS_LEAD_HWFN(p_hwfn))
2442                 return ECORE_SUCCESS;
2443         num *= p_hwfn->p_dev->num_hwfns;
2444
2445         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2446             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2447         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2448             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2449
2450         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2451                            &resp, &rc_param);
2452
2453         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2454                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2455                           vf_id);
2456                 rc = ECORE_INVAL;
2457         } else {
2458                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2459                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2460                             num, vf_id);
2461         }
2462
2463         return rc;
2464 }
2465
2466 static enum _ecore_status_t
2467 ecore_mcp_config_vf_msix_ah(struct ecore_hwfn *p_hwfn,
2468                             struct ecore_ptt *p_ptt,
2469                             u8 num)
2470 {
2471         u32 resp = 0, param = num, rc_param = 0;
2472         enum _ecore_status_t rc;
2473
2474         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2475                            param, &resp, &rc_param);
2476
2477         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2478                 DP_NOTICE(p_hwfn, true, "MFW failed to set MSI-X for VFs\n");
2479                 rc = ECORE_INVAL;
2480         } else {
2481                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2482                            "Requested 0x%02x MSI-x interrupts for VFs\n",
2483                            num);
2484         }
2485
2486         return rc;
2487 }
2488
2489 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2490                                               struct ecore_ptt *p_ptt,
2491                                               u8 vf_id, u8 num)
2492 {
2493         if (ECORE_IS_BB(p_hwfn->p_dev))
2494                 return ecore_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2495         else
2496                 return ecore_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2497 }
2498
2499 enum _ecore_status_t
2500 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2501                            struct ecore_mcp_drv_version *p_ver)
2502 {
2503         struct ecore_mcp_mb_params mb_params;
2504         struct drv_version_stc drv_version;
2505         u32 num_words, i;
2506         void *p_name;
2507         OSAL_BE32 val;
2508         enum _ecore_status_t rc;
2509
2510 #ifndef ASIC_ONLY
2511         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2512                 return ECORE_SUCCESS;
2513 #endif
2514
2515         OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2516         drv_version.version = p_ver->version;
2517         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2518         for (i = 0; i < num_words; i++) {
2519                 /* The driver name is expected to be in a big-endian format */
2520                 p_name = &p_ver->name[i * sizeof(u32)];
2521                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2522                 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2523         }
2524
2525         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2526         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2527         mb_params.p_data_src = &drv_version;
2528         mb_params.data_src_size = sizeof(drv_version);
2529         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2530         if (rc != ECORE_SUCCESS)
2531                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2532
2533         return rc;
2534 }
2535
2536 /* A maximal 100 msec waiting time for the MCP to halt */
2537 #define ECORE_MCP_HALT_SLEEP_MS         10
2538 #define ECORE_MCP_HALT_MAX_RETRIES      10
2539
2540 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2541                                     struct ecore_ptt *p_ptt)
2542 {
2543         u32 resp = 0, param = 0, cpu_state, cnt = 0;
2544         enum _ecore_status_t rc;
2545
2546         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2547                            &param);
2548         if (rc != ECORE_SUCCESS) {
2549                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2550                 return rc;
2551         }
2552
2553         do {
2554                 OSAL_MSLEEP(ECORE_MCP_HALT_SLEEP_MS);
2555                 cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2556                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2557                         break;
2558         } while (++cnt < ECORE_MCP_HALT_MAX_RETRIES);
2559
2560         if (cnt == ECORE_MCP_HALT_MAX_RETRIES) {
2561                 DP_NOTICE(p_hwfn, false,
2562                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2563                           ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2564                 return ECORE_BUSY;
2565         }
2566
2567         ecore_mcp_cmd_set_blocking(p_hwfn, true);
2568
2569         return ECORE_SUCCESS;
2570 }
2571
2572 #define ECORE_MCP_RESUME_SLEEP_MS       10
2573
2574 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2575                                       struct ecore_ptt *p_ptt)
2576 {
2577         u32 cpu_mode, cpu_state;
2578
2579         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2580
2581         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2582         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2583         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2584
2585         OSAL_MSLEEP(ECORE_MCP_RESUME_SLEEP_MS);
2586         cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2587
2588         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2589                 DP_NOTICE(p_hwfn, false,
2590                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2591                           cpu_mode, cpu_state);
2592                 return ECORE_BUSY;
2593         }
2594
2595         ecore_mcp_cmd_set_blocking(p_hwfn, false);
2596
2597         return ECORE_SUCCESS;
2598 }
2599
2600 enum _ecore_status_t
2601 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2602                                    struct ecore_ptt *p_ptt,
2603                                    enum ecore_ov_client client)
2604 {
2605         u32 resp = 0, param = 0;
2606         u32 drv_mb_param;
2607         enum _ecore_status_t rc;
2608
2609         switch (client) {
2610         case ECORE_OV_CLIENT_DRV:
2611                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2612                 break;
2613         case ECORE_OV_CLIENT_USER:
2614                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2615                 break;
2616         case ECORE_OV_CLIENT_VENDOR_SPEC:
2617                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2618                 break;
2619         default:
2620                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2621                 return ECORE_INVAL;
2622         }
2623
2624         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2625                            drv_mb_param, &resp, &param);
2626         if (rc != ECORE_SUCCESS)
2627                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2628
2629         return rc;
2630 }
2631
2632 enum _ecore_status_t
2633 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2634                                  struct ecore_ptt *p_ptt,
2635                                  enum ecore_ov_driver_state drv_state)
2636 {
2637         u32 resp = 0, param = 0;
2638         u32 drv_mb_param;
2639         enum _ecore_status_t rc;
2640
2641         switch (drv_state) {
2642         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2643                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2644                 break;
2645         case ECORE_OV_DRIVER_STATE_DISABLED:
2646                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2647                 break;
2648         case ECORE_OV_DRIVER_STATE_ACTIVE:
2649                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2650                 break;
2651         default:
2652                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2653                 return ECORE_INVAL;
2654         }
2655
2656         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2657                            drv_mb_param, &resp, &param);
2658         if (rc != ECORE_SUCCESS)
2659                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2660
2661         return rc;
2662 }
2663
2664 enum _ecore_status_t
2665 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2666                          struct ecore_fc_npiv_tbl *p_table)
2667 {
2668         return 0;
2669 }
2670
2671 enum _ecore_status_t
2672 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2673                         struct ecore_ptt *p_ptt, u16 mtu)
2674 {
2675         return 0;
2676 }
2677
2678 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2679                                        struct ecore_ptt *p_ptt,
2680                                        enum ecore_led_mode mode)
2681 {
2682         u32 resp = 0, param = 0, drv_mb_param;
2683         enum _ecore_status_t rc;
2684
2685         switch (mode) {
2686         case ECORE_LED_MODE_ON:
2687                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2688                 break;
2689         case ECORE_LED_MODE_OFF:
2690                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2691                 break;
2692         case ECORE_LED_MODE_RESTORE:
2693                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2694                 break;
2695         default:
2696                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2697                 return ECORE_INVAL;
2698         }
2699
2700         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2701                            drv_mb_param, &resp, &param);
2702         if (rc != ECORE_SUCCESS)
2703                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2704
2705         return rc;
2706 }
2707
2708 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2709                                              struct ecore_ptt *p_ptt,
2710                                              u32 mask_parities)
2711 {
2712         u32 resp = 0, param = 0;
2713         enum _ecore_status_t rc;
2714
2715         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2716                            mask_parities, &resp, &param);
2717
2718         if (rc != ECORE_SUCCESS) {
2719                 DP_ERR(p_hwfn,
2720                        "MCP response failure for mask parities, aborting\n");
2721         } else if (resp != FW_MSG_CODE_OK) {
2722                 DP_ERR(p_hwfn,
2723                        "MCP did not ack mask parity request. Old MFW?\n");
2724                 rc = ECORE_INVAL;
2725         }
2726
2727         return rc;
2728 }
2729
2730 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2731                                         u8 *p_buf, u32 len)
2732 {
2733         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2734         u32 bytes_left, offset, bytes_to_copy, buf_size;
2735         u32 nvm_offset, resp, param;
2736         struct ecore_ptt *p_ptt;
2737         enum _ecore_status_t rc = ECORE_SUCCESS;
2738
2739         p_ptt = ecore_ptt_acquire(p_hwfn);
2740         if (!p_ptt)
2741                 return ECORE_BUSY;
2742
2743         bytes_left = len;
2744         offset = 0;
2745         while (bytes_left > 0) {
2746                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2747                                            MCP_DRV_NVM_BUF_LEN);
2748                 nvm_offset = (addr + offset) | (bytes_to_copy <<
2749                                                 DRV_MB_PARAM_NVM_LEN_OFFSET);
2750                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2751                                           DRV_MSG_CODE_NVM_READ_NVRAM,
2752                                           nvm_offset, &resp, &param, &buf_size,
2753                                           (u32 *)(p_buf + offset));
2754                 if (rc != ECORE_SUCCESS) {
2755                         DP_NOTICE(p_dev, false,
2756                                   "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2757                                   rc);
2758                         resp = FW_MSG_CODE_ERROR;
2759                         break;
2760                 }
2761
2762                 if (resp != FW_MSG_CODE_NVM_OK) {
2763                         DP_NOTICE(p_dev, false,
2764                                   "nvm read failed, resp = 0x%08x\n", resp);
2765                         rc = ECORE_UNKNOWN_ERROR;
2766                         break;
2767                 }
2768
2769                 /* This can be a lengthy process, and it's possible scheduler
2770                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2771                  */
2772                 if (bytes_left % 0x1000 <
2773                     (bytes_left - buf_size) % 0x1000)
2774                         OSAL_MSLEEP(1);
2775
2776                 offset += buf_size;
2777                 bytes_left -= buf_size;
2778         }
2779
2780         p_dev->mcp_nvm_resp = resp;
2781         ecore_ptt_release(p_hwfn, p_ptt);
2782
2783         return rc;
2784 }
2785
2786 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2787                                         u32 addr, u8 *p_buf, u32 len)
2788 {
2789         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2790         struct ecore_ptt *p_ptt;
2791         u32 resp, param;
2792         enum _ecore_status_t rc;
2793
2794         p_ptt = ecore_ptt_acquire(p_hwfn);
2795         if (!p_ptt)
2796                 return ECORE_BUSY;
2797
2798         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2799                                   (cmd == ECORE_PHY_CORE_READ) ?
2800                                   DRV_MSG_CODE_PHY_CORE_READ :
2801                                   DRV_MSG_CODE_PHY_RAW_READ,
2802                                   addr, &resp, &param, &len, (u32 *)p_buf);
2803         if (rc != ECORE_SUCCESS)
2804                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2805
2806         p_dev->mcp_nvm_resp = resp;
2807         ecore_ptt_release(p_hwfn, p_ptt);
2808
2809         return rc;
2810 }
2811
2812 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2813 {
2814         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2815         struct ecore_ptt *p_ptt;
2816
2817         p_ptt = ecore_ptt_acquire(p_hwfn);
2818         if (!p_ptt)
2819                 return ECORE_BUSY;
2820
2821         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2822         ecore_ptt_release(p_hwfn, p_ptt);
2823
2824         return ECORE_SUCCESS;
2825 }
2826
2827 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2828 {
2829         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2830         struct ecore_ptt *p_ptt;
2831         u32 resp, param;
2832         enum _ecore_status_t rc;
2833
2834         p_ptt = ecore_ptt_acquire(p_hwfn);
2835         if (!p_ptt)
2836                 return ECORE_BUSY;
2837         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2838                            &resp, &param);
2839         p_dev->mcp_nvm_resp = resp;
2840         ecore_ptt_release(p_hwfn, p_ptt);
2841
2842         return rc;
2843 }
2844
2845 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2846                                                   u32 addr)
2847 {
2848         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2849         struct ecore_ptt *p_ptt;
2850         u32 resp, param;
2851         enum _ecore_status_t rc;
2852
2853         p_ptt = ecore_ptt_acquire(p_hwfn);
2854         if (!p_ptt)
2855                 return ECORE_BUSY;
2856         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2857                            &resp, &param);
2858         p_dev->mcp_nvm_resp = resp;
2859         ecore_ptt_release(p_hwfn, p_ptt);
2860
2861         return rc;
2862 }
2863
2864 /* rc receives ECORE_INVAL as default parameter because
2865  * it might not enter the while loop if the len is 0
2866  */
2867 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2868                                          u32 addr, u8 *p_buf, u32 len)
2869 {
2870         u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2871         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2872         enum _ecore_status_t rc = ECORE_INVAL;
2873         struct ecore_ptt *p_ptt;
2874
2875         p_ptt = ecore_ptt_acquire(p_hwfn);
2876         if (!p_ptt)
2877                 return ECORE_BUSY;
2878
2879         switch (cmd) {
2880         case ECORE_PUT_FILE_DATA:
2881                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2882                 break;
2883         case ECORE_NVM_WRITE_NVRAM:
2884                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2885                 break;
2886         case ECORE_EXT_PHY_FW_UPGRADE:
2887                 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2888                 break;
2889         default:
2890                 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2891                           cmd);
2892                 rc = ECORE_INVAL;
2893                 goto out;
2894         }
2895
2896         buf_idx = 0;
2897         while (buf_idx < len) {
2898                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2899                                       MCP_DRV_NVM_BUF_LEN);
2900                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2901                               addr) +
2902                              buf_idx;
2903                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2904                                           &resp, &param, buf_size,
2905                                           (u32 *)&p_buf[buf_idx]);
2906                 if (rc != ECORE_SUCCESS) {
2907                         DP_NOTICE(p_dev, false,
2908                                   "ecore_mcp_nvm_write() failed, rc = %d\n",
2909                                   rc);
2910                         resp = FW_MSG_CODE_ERROR;
2911                         break;
2912                 }
2913
2914                 if (resp != FW_MSG_CODE_OK &&
2915                     resp != FW_MSG_CODE_NVM_OK &&
2916                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2917                         DP_NOTICE(p_dev, false,
2918                                   "nvm write failed, resp = 0x%08x\n", resp);
2919                         rc = ECORE_UNKNOWN_ERROR;
2920                         break;
2921                 }
2922
2923                 /* This can be a lengthy process, and it's possible scheduler
2924                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2925                  */
2926                 if (buf_idx % 0x1000 >
2927                     (buf_idx + buf_size) % 0x1000)
2928                         OSAL_MSLEEP(1);
2929
2930                 buf_idx += buf_size;
2931         }
2932
2933         p_dev->mcp_nvm_resp = resp;
2934 out:
2935         ecore_ptt_release(p_hwfn, p_ptt);
2936
2937         return rc;
2938 }
2939
2940 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2941                                          u32 addr, u8 *p_buf, u32 len)
2942 {
2943         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2944         struct ecore_ptt *p_ptt;
2945         u32 resp, param, nvm_cmd;
2946         enum _ecore_status_t rc;
2947
2948         p_ptt = ecore_ptt_acquire(p_hwfn);
2949         if (!p_ptt)
2950                 return ECORE_BUSY;
2951
2952         nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ?  DRV_MSG_CODE_PHY_CORE_WRITE :
2953                         DRV_MSG_CODE_PHY_RAW_WRITE;
2954         rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2955                                   &resp, &param, len, (u32 *)p_buf);
2956         if (rc != ECORE_SUCCESS)
2957                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2958         p_dev->mcp_nvm_resp = resp;
2959         ecore_ptt_release(p_hwfn, p_ptt);
2960
2961         return rc;
2962 }
2963
2964 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2965                                                    u32 addr)
2966 {
2967         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2968         struct ecore_ptt *p_ptt;
2969         u32 resp, param;
2970         enum _ecore_status_t rc;
2971
2972         p_ptt = ecore_ptt_acquire(p_hwfn);
2973         if (!p_ptt)
2974                 return ECORE_BUSY;
2975
2976         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2977                            &resp, &param);
2978         p_dev->mcp_nvm_resp = resp;
2979         ecore_ptt_release(p_hwfn, p_ptt);
2980
2981         return rc;
2982 }
2983
2984 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2985                                             struct ecore_ptt *p_ptt,
2986                                             u32 port, u32 addr, u32 offset,
2987                                             u32 len, u8 *p_buf)
2988 {
2989         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2990         u32 resp, param;
2991         enum _ecore_status_t rc;
2992
2993         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2994                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2995         addr = offset;
2996         offset = 0;
2997         bytes_left = len;
2998         while (bytes_left > 0) {
2999                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
3000                                            MAX_I2C_TRANSACTION_SIZE);
3001                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
3002                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
3003                 nvm_offset |= ((addr + offset) <<
3004                                 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
3005                 nvm_offset |= (bytes_to_copy <<
3006                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
3007                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
3008                                           DRV_MSG_CODE_TRANSCEIVER_READ,
3009                                           nvm_offset, &resp, &param, &buf_size,
3010                                           (u32 *)(p_buf + offset));
3011                 if (rc != ECORE_SUCCESS) {
3012                         DP_NOTICE(p_hwfn, false,
3013                                   "Failed to send a transceiver read command to the MFW. rc = %d.\n",
3014                                   rc);
3015                         return rc;
3016                 }
3017
3018                 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT)
3019                         return ECORE_NODEV;
3020                 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
3021                         return ECORE_UNKNOWN_ERROR;
3022
3023                 offset += buf_size;
3024                 bytes_left -= buf_size;
3025         }
3026
3027         return ECORE_SUCCESS;
3028 }
3029
3030 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
3031                                              struct ecore_ptt *p_ptt,
3032                                              u32 port, u32 addr, u32 offset,
3033                                              u32 len, u8 *p_buf)
3034 {
3035         u32 buf_idx, buf_size, nvm_offset, resp, param;
3036         enum _ecore_status_t rc;
3037
3038         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
3039                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
3040         buf_idx = 0;
3041         while (buf_idx < len) {
3042                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
3043                                       MAX_I2C_TRANSACTION_SIZE);
3044                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
3045                                  DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
3046                 nvm_offset |= ((offset + buf_idx) <<
3047                                  DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
3048                 nvm_offset |= (buf_size <<
3049                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
3050                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
3051                                           DRV_MSG_CODE_TRANSCEIVER_WRITE,
3052                                           nvm_offset, &resp, &param, buf_size,
3053                                           (u32 *)&p_buf[buf_idx]);
3054                 if (rc != ECORE_SUCCESS) {
3055                         DP_NOTICE(p_hwfn, false,
3056                                   "Failed to send a transceiver write command to the MFW. rc = %d.\n",
3057                                   rc);
3058                         return rc;
3059                 }
3060
3061                 if (resp == FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT)
3062                         return ECORE_NODEV;
3063                 else if (resp != FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
3064                         return ECORE_UNKNOWN_ERROR;
3065
3066                 buf_idx += buf_size;
3067         }
3068
3069         return ECORE_SUCCESS;
3070 }
3071
3072 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
3073                                          struct ecore_ptt *p_ptt,
3074                                          u16 gpio, u32 *gpio_val)
3075 {
3076         enum _ecore_status_t rc = ECORE_SUCCESS;
3077         u32 drv_mb_param = 0, rsp;
3078
3079         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
3080
3081         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
3082                            drv_mb_param, &rsp, gpio_val);
3083
3084         if (rc != ECORE_SUCCESS)
3085                 return rc;
3086
3087         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3088                 return ECORE_UNKNOWN_ERROR;
3089
3090         return ECORE_SUCCESS;
3091 }
3092
3093 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
3094                                           struct ecore_ptt *p_ptt,
3095                                           u16 gpio, u16 gpio_val)
3096 {
3097         enum _ecore_status_t rc = ECORE_SUCCESS;
3098         u32 drv_mb_param = 0, param, rsp;
3099
3100         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
3101                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
3102
3103         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
3104                            drv_mb_param, &rsp, &param);
3105
3106         if (rc != ECORE_SUCCESS)
3107                 return rc;
3108
3109         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3110                 return ECORE_UNKNOWN_ERROR;
3111
3112         return ECORE_SUCCESS;
3113 }
3114
3115 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
3116                                          struct ecore_ptt *p_ptt,
3117                                          u16 gpio, u32 *gpio_direction,
3118                                          u32 *gpio_ctrl)
3119 {
3120         u32 drv_mb_param = 0, rsp, val = 0;
3121         enum _ecore_status_t rc = ECORE_SUCCESS;
3122
3123         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
3124
3125         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
3126                            drv_mb_param, &rsp, &val);
3127         if (rc != ECORE_SUCCESS)
3128                 return rc;
3129
3130         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
3131                            DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
3132         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
3133                       DRV_MB_PARAM_GPIO_CTRL_OFFSET;
3134
3135         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3136                 return ECORE_UNKNOWN_ERROR;
3137
3138         return ECORE_SUCCESS;
3139 }
3140
3141 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
3142                                                   struct ecore_ptt *p_ptt)
3143 {
3144         u32 drv_mb_param = 0, rsp, param;
3145         enum _ecore_status_t rc = ECORE_SUCCESS;
3146
3147         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
3148                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3149
3150         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3151                            drv_mb_param, &rsp, &param);
3152
3153         if (rc != ECORE_SUCCESS)
3154                 return rc;
3155
3156         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3157             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3158                 rc = ECORE_UNKNOWN_ERROR;
3159
3160         return rc;
3161 }
3162
3163 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
3164                                                struct ecore_ptt *p_ptt)
3165 {
3166         u32 drv_mb_param, rsp, param;
3167         enum _ecore_status_t rc = ECORE_SUCCESS;
3168
3169         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
3170                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3171
3172         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3173                            drv_mb_param, &rsp, &param);
3174
3175         if (rc != ECORE_SUCCESS)
3176                 return rc;
3177
3178         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3179             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3180                 rc = ECORE_UNKNOWN_ERROR;
3181
3182         return rc;
3183 }
3184
3185 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
3186         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
3187 {
3188         u32 drv_mb_param = 0, rsp;
3189         enum _ecore_status_t rc = ECORE_SUCCESS;
3190
3191         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
3192                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3193
3194         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3195                            drv_mb_param, &rsp, num_images);
3196
3197         if (rc != ECORE_SUCCESS)
3198                 return rc;
3199
3200         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
3201                 rc = ECORE_UNKNOWN_ERROR;
3202
3203         return rc;
3204 }
3205
3206 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
3207         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3208         struct bist_nvm_image_att *p_image_att, u32 image_index)
3209 {
3210         u32 buf_size, nvm_offset, resp, param;
3211         enum _ecore_status_t rc;
3212
3213         nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
3214                                     DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3215         nvm_offset |= (image_index <<
3216                        DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
3217         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3218                                   nvm_offset, &resp, &param, &buf_size,
3219                                   (u32 *)p_image_att);
3220         if (rc != ECORE_SUCCESS)
3221                 return rc;
3222
3223         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3224             (p_image_att->return_code != 1))
3225                 rc = ECORE_UNKNOWN_ERROR;
3226
3227         return rc;
3228 }
3229
3230 enum _ecore_status_t
3231 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
3232                                struct ecore_ptt *p_ptt,
3233                                struct ecore_temperature_info *p_temp_info)
3234 {
3235         struct ecore_temperature_sensor *p_temp_sensor;
3236         struct temperature_status_stc mfw_temp_info;
3237         struct ecore_mcp_mb_params mb_params;
3238         u32 val;
3239         enum _ecore_status_t rc;
3240         u8 i;
3241
3242         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3243         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
3244         mb_params.p_data_dst = &mfw_temp_info;
3245         mb_params.data_dst_size = sizeof(mfw_temp_info);
3246         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3247         if (rc != ECORE_SUCCESS)
3248                 return rc;
3249
3250         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
3251         p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
3252                                               ECORE_MAX_NUM_OF_SENSORS);
3253         for (i = 0; i < p_temp_info->num_sensors; i++) {
3254                 val = mfw_temp_info.sensor[i];
3255                 p_temp_sensor = &p_temp_info->sensors[i];
3256                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
3257                                                  SENSOR_LOCATION_OFFSET;
3258                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3259                                                 THRESHOLD_HIGH_OFFSET;
3260                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3261                                           CRITICAL_TEMPERATURE_OFFSET;
3262                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3263                                               CURRENT_TEMP_OFFSET;
3264         }
3265
3266         return ECORE_SUCCESS;
3267 }
3268
3269 enum _ecore_status_t ecore_mcp_get_mba_versions(
3270         struct ecore_hwfn *p_hwfn,
3271         struct ecore_ptt *p_ptt,
3272         struct ecore_mba_vers *p_mba_vers)
3273 {
3274         u32 buf_size, resp, param;
3275         enum _ecore_status_t rc;
3276
3277         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3278                                   0, &resp, &param, &buf_size,
3279                                   &p_mba_vers->mba_vers[0]);
3280
3281         if (rc != ECORE_SUCCESS)
3282                 return rc;
3283
3284         if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3285                 rc = ECORE_UNKNOWN_ERROR;
3286
3287         if (buf_size != MCP_DRV_NVM_BUF_LEN)
3288                 rc = ECORE_UNKNOWN_ERROR;
3289
3290         return rc;
3291 }
3292
3293 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3294                                               struct ecore_ptt *p_ptt,
3295                                               u64 *num_events)
3296 {
3297         u32 rsp;
3298
3299         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3300                              0, &rsp, (u32 *)num_events);
3301 }
3302
3303 static enum resource_id_enum
3304 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3305 {
3306         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3307
3308         switch (res_id) {
3309         case ECORE_SB:
3310                 mfw_res_id = RESOURCE_NUM_SB_E;
3311                 break;
3312         case ECORE_L2_QUEUE:
3313                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3314                 break;
3315         case ECORE_VPORT:
3316                 mfw_res_id = RESOURCE_NUM_VPORT_E;
3317                 break;
3318         case ECORE_RSS_ENG:
3319                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3320                 break;
3321         case ECORE_PQ:
3322                 mfw_res_id = RESOURCE_NUM_PQ_E;
3323                 break;
3324         case ECORE_RL:
3325                 mfw_res_id = RESOURCE_NUM_RL_E;
3326                 break;
3327         case ECORE_MAC:
3328         case ECORE_VLAN:
3329                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3330                 mfw_res_id = RESOURCE_VFC_FILTER_E;
3331                 break;
3332         case ECORE_ILT:
3333                 mfw_res_id = RESOURCE_ILT_E;
3334                 break;
3335         case ECORE_LL2_QUEUE:
3336                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3337                 break;
3338         case ECORE_RDMA_CNQ_RAM:
3339         case ECORE_CMDQS_CQS:
3340                 /* CNQ/CMDQS are the same resource */
3341                 mfw_res_id = RESOURCE_CQS_E;
3342                 break;
3343         case ECORE_RDMA_STATS_QUEUE:
3344                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3345                 break;
3346         case ECORE_BDQ:
3347                 mfw_res_id = RESOURCE_BDQ_E;
3348                 break;
3349         default:
3350                 break;
3351         }
3352
3353         return mfw_res_id;
3354 }
3355
3356 #define ECORE_RESC_ALLOC_VERSION_MAJOR  2
3357 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
3358 #define ECORE_RESC_ALLOC_VERSION                                \
3359         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
3360           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) |   \
3361          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
3362           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3363
3364 struct ecore_resc_alloc_in_params {
3365         u32 cmd;
3366         enum ecore_resources res_id;
3367         u32 resc_max_val;
3368 };
3369
3370 struct ecore_resc_alloc_out_params {
3371         u32 mcp_resp;
3372         u32 mcp_param;
3373         u32 resc_num;
3374         u32 resc_start;
3375         u32 vf_resc_num;
3376         u32 vf_resc_start;
3377         u32 flags;
3378 };
3379
3380 #define ECORE_RECOVERY_PROLOG_SLEEP_MS  100
3381
3382 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3383 {
3384         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3385         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3386         enum _ecore_status_t rc;
3387
3388         /* Allow ongoing PCIe transactions to complete */
3389         OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3390
3391         /* Clear the PF's internal FID_enable in the PXP */
3392         rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3393         if (rc != ECORE_SUCCESS)
3394                 DP_NOTICE(p_hwfn, false,
3395                           "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3396                           rc);
3397
3398         return rc;
3399 }
3400
3401 static enum _ecore_status_t
3402 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3403                               struct ecore_ptt *p_ptt,
3404                               struct ecore_resc_alloc_in_params *p_in_params,
3405                               struct ecore_resc_alloc_out_params *p_out_params)
3406 {
3407         struct ecore_mcp_mb_params mb_params;
3408         struct resource_info mfw_resc_info;
3409         enum _ecore_status_t rc;
3410
3411         OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3412
3413         mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3414         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3415                 DP_ERR(p_hwfn,
3416                        "Failed to match resource %d [%s] with the MFW resources\n",
3417                        p_in_params->res_id,
3418                        ecore_hw_get_resc_name(p_in_params->res_id));
3419                 return ECORE_INVAL;
3420         }
3421
3422         switch (p_in_params->cmd) {
3423         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3424                 mfw_resc_info.size = p_in_params->resc_max_val;
3425                 /* Fallthrough */
3426         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3427                 break;
3428         default:
3429                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3430                        p_in_params->cmd);
3431                 return ECORE_INVAL;
3432         }
3433
3434         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3435         mb_params.cmd = p_in_params->cmd;
3436         mb_params.param = ECORE_RESC_ALLOC_VERSION;
3437         mb_params.p_data_src = &mfw_resc_info;
3438         mb_params.data_src_size = sizeof(mfw_resc_info);
3439         mb_params.p_data_dst = mb_params.p_data_src;
3440         mb_params.data_dst_size = mb_params.data_src_size;
3441
3442         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3443                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3444                    p_in_params->cmd, p_in_params->res_id,
3445                    ecore_hw_get_resc_name(p_in_params->res_id),
3446                    GET_MFW_FIELD(mb_params.param,
3447                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3448                    GET_MFW_FIELD(mb_params.param,
3449                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3450                    p_in_params->resc_max_val);
3451
3452         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3453         if (rc != ECORE_SUCCESS)
3454                 return rc;
3455
3456         p_out_params->mcp_resp = mb_params.mcp_resp;
3457         p_out_params->mcp_param = mb_params.mcp_param;
3458         p_out_params->resc_num = mfw_resc_info.size;
3459         p_out_params->resc_start = mfw_resc_info.offset;
3460         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3461         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3462         p_out_params->flags = mfw_resc_info.flags;
3463
3464         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3465                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3466                    GET_MFW_FIELD(p_out_params->mcp_param,
3467                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3468                    GET_MFW_FIELD(p_out_params->mcp_param,
3469                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3470                    p_out_params->resc_num, p_out_params->resc_start,
3471                    p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3472                    p_out_params->flags);
3473
3474         return ECORE_SUCCESS;
3475 }
3476
3477 enum _ecore_status_t
3478 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3479                            enum ecore_resources res_id, u32 resc_max_val,
3480                            u32 *p_mcp_resp)
3481 {
3482         struct ecore_resc_alloc_out_params out_params;
3483         struct ecore_resc_alloc_in_params in_params;
3484         enum _ecore_status_t rc;
3485
3486         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3487         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3488         in_params.res_id = res_id;
3489         in_params.resc_max_val = resc_max_val;
3490         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3491         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3492                                            &out_params);
3493         if (rc != ECORE_SUCCESS)
3494                 return rc;
3495
3496         *p_mcp_resp = out_params.mcp_resp;
3497
3498         return ECORE_SUCCESS;
3499 }
3500
3501 enum _ecore_status_t
3502 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3503                         enum ecore_resources res_id, u32 *p_mcp_resp,
3504                         u32 *p_resc_num, u32 *p_resc_start)
3505 {
3506         struct ecore_resc_alloc_out_params out_params;
3507         struct ecore_resc_alloc_in_params in_params;
3508         enum _ecore_status_t rc;
3509
3510         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3511         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3512         in_params.res_id = res_id;
3513         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3514         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3515                                            &out_params);
3516         if (rc != ECORE_SUCCESS)
3517                 return rc;
3518
3519         *p_mcp_resp = out_params.mcp_resp;
3520
3521         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3522                 *p_resc_num = out_params.resc_num;
3523                 *p_resc_start = out_params.resc_start;
3524         }
3525
3526         return ECORE_SUCCESS;
3527 }
3528
3529 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3530                                                struct ecore_ptt *p_ptt)
3531 {
3532         u32 mcp_resp, mcp_param;
3533
3534         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3535                              &mcp_resp, &mcp_param);
3536 }
3537
3538 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3539                                                    struct ecore_ptt *p_ptt,
3540                                                    u32 param, u32 *p_mcp_resp,
3541                                                    u32 *p_mcp_param)
3542 {
3543         enum _ecore_status_t rc;
3544
3545         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3546                            p_mcp_resp, p_mcp_param);
3547         if (rc != ECORE_SUCCESS)
3548                 return rc;
3549
3550         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3551                 DP_INFO(p_hwfn,
3552                         "The resource command is unsupported by the MFW\n");
3553                 return ECORE_NOTIMPL;
3554         }
3555
3556         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3557                 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3558
3559                 DP_NOTICE(p_hwfn, false,
3560                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3561                           param, opcode);
3562                 return ECORE_INVAL;
3563         }
3564
3565         return rc;
3566 }
3567
3568 enum _ecore_status_t
3569 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3570                       struct ecore_resc_lock_params *p_params)
3571 {
3572         u32 param = 0, mcp_resp, mcp_param;
3573         u8 opcode;
3574         enum _ecore_status_t rc;
3575
3576         switch (p_params->timeout) {
3577         case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3578                 opcode = RESOURCE_OPCODE_REQ;
3579                 p_params->timeout = 0;
3580                 break;
3581         case ECORE_MCP_RESC_LOCK_TO_NONE:
3582                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3583                 p_params->timeout = 0;
3584                 break;
3585         default:
3586                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3587                 break;
3588         }
3589
3590         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3591         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3592         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3593
3594         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3595                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3596                    param, p_params->timeout, opcode, p_params->resource);
3597
3598         /* Attempt to acquire the resource */
3599         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3600                                     &mcp_param);
3601         if (rc != ECORE_SUCCESS)
3602                 return rc;
3603
3604         /* Analyze the response */
3605         p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3606         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3607
3608         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3609                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3610                    mcp_param, opcode, p_params->owner);
3611
3612         switch (opcode) {
3613         case RESOURCE_OPCODE_GNT:
3614                 p_params->b_granted = true;
3615                 break;
3616         case RESOURCE_OPCODE_BUSY:
3617                 p_params->b_granted = false;
3618                 break;
3619         default:
3620                 DP_NOTICE(p_hwfn, false,
3621                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3622                           mcp_param, opcode);
3623                 return ECORE_INVAL;
3624         }
3625
3626         return ECORE_SUCCESS;
3627 }
3628
3629 enum _ecore_status_t
3630 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3631                     struct ecore_resc_lock_params *p_params)
3632 {
3633         u32 retry_cnt = 0;
3634         enum _ecore_status_t rc;
3635
3636         do {
3637                 /* No need for an interval before the first iteration */
3638                 if (retry_cnt) {
3639                         if (p_params->sleep_b4_retry) {
3640                                 u16 retry_interval_in_ms =
3641                                         DIV_ROUND_UP(p_params->retry_interval,
3642                                                      1000);
3643
3644                                 OSAL_MSLEEP(retry_interval_in_ms);
3645                         } else {
3646                                 OSAL_UDELAY(p_params->retry_interval);
3647                         }
3648                 }
3649
3650                 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3651                 if (rc != ECORE_SUCCESS)
3652                         return rc;
3653
3654                 if (p_params->b_granted)
3655                         break;
3656         } while (retry_cnt++ < p_params->retry_num);
3657
3658         return ECORE_SUCCESS;
3659 }
3660
3661 void ecore_mcp_resc_lock_default_init(struct ecore_resc_lock_params *p_lock,
3662                                       struct ecore_resc_unlock_params *p_unlock,
3663                                       enum ecore_resc_lock resource,
3664                                       bool b_is_permanent)
3665 {
3666         if (p_lock != OSAL_NULL) {
3667                 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3668
3669                 /* Permanent resources don't require aging, and there's no
3670                  * point in trying to acquire them more than once since it's
3671                  * unexpected another entity would release them.
3672                  */
3673                 if (b_is_permanent) {
3674                         p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3675                 } else {
3676                         p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3677                         p_lock->retry_interval =
3678                                         ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3679                         p_lock->sleep_b4_retry = true;
3680                 }
3681
3682                 p_lock->resource = resource;
3683         }
3684
3685         if (p_unlock != OSAL_NULL) {
3686                 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3687                 p_unlock->resource = resource;
3688         }
3689 }
3690
3691 enum _ecore_status_t
3692 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3693                       struct ecore_resc_unlock_params *p_params)
3694 {
3695         u32 param = 0, mcp_resp, mcp_param;
3696         u8 opcode;
3697         enum _ecore_status_t rc;
3698
3699         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3700                                    : RESOURCE_OPCODE_RELEASE;
3701         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3702         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3703
3704         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3705                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3706                    param, opcode, p_params->resource);
3707
3708         /* Attempt to release the resource */
3709         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3710                                     &mcp_param);
3711         if (rc != ECORE_SUCCESS)
3712                 return rc;
3713
3714         /* Analyze the response */
3715         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3716
3717         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3718                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3719                    mcp_param, opcode);
3720
3721         switch (opcode) {
3722         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3723                 DP_INFO(p_hwfn,
3724                         "Resource unlock request for an already released resource [%d]\n",
3725                         p_params->resource);
3726                 /* Fallthrough */
3727         case RESOURCE_OPCODE_RELEASED:
3728                 p_params->b_released = true;
3729                 break;
3730         case RESOURCE_OPCODE_WRONG_OWNER:
3731                 p_params->b_released = false;
3732                 break;
3733         default:
3734                 DP_NOTICE(p_hwfn, false,
3735                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3736                           mcp_param, opcode);
3737                 return ECORE_INVAL;
3738         }
3739
3740         return ECORE_SUCCESS;
3741 }
3742
3743 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3744 {
3745         return !!(p_hwfn->mcp_info->capabilities &
3746                   FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3747 }
3748
3749 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3750                                                 struct ecore_ptt *p_ptt)
3751 {
3752         u32 mcp_resp;
3753         enum _ecore_status_t rc;
3754
3755         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3756                            0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3757         if (rc == ECORE_SUCCESS)
3758                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3759                            "MFW supported features: %08x\n",
3760                            p_hwfn->mcp_info->capabilities);
3761
3762         return rc;
3763 }
3764
3765 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3766                                                 struct ecore_ptt *p_ptt)
3767 {
3768         u32 mcp_resp, mcp_param, features;
3769
3770         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3771                    DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE |
3772                    DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK;
3773
3774         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3775                              features, &mcp_resp, &mcp_param);
3776 }
3777
3778 enum _ecore_status_t
3779 ecore_mcp_drv_attribute(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3780                         struct ecore_mcp_drv_attr *p_drv_attr)
3781 {
3782         struct attribute_cmd_write_stc attr_cmd_write;
3783         enum _attribute_commands_e mfw_attr_cmd;
3784         struct ecore_mcp_mb_params mb_params;
3785         enum _ecore_status_t rc;
3786
3787         switch (p_drv_attr->attr_cmd) {
3788         case ECORE_MCP_DRV_ATTR_CMD_READ:
3789                 mfw_attr_cmd = ATTRIBUTE_CMD_READ;
3790                 break;
3791         case ECORE_MCP_DRV_ATTR_CMD_WRITE:
3792                 mfw_attr_cmd = ATTRIBUTE_CMD_WRITE;
3793                 break;
3794         case ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR:
3795                 mfw_attr_cmd = ATTRIBUTE_CMD_READ_CLEAR;
3796                 break;
3797         case ECORE_MCP_DRV_ATTR_CMD_CLEAR:
3798                 mfw_attr_cmd = ATTRIBUTE_CMD_CLEAR;
3799                 break;
3800         default:
3801                 DP_NOTICE(p_hwfn, false, "Unknown attribute command %d\n",
3802                           p_drv_attr->attr_cmd);
3803                 return ECORE_INVAL;
3804         }
3805
3806         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3807         mb_params.cmd = DRV_MSG_CODE_ATTRIBUTE;
3808         SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_KEY,
3809                       p_drv_attr->attr_num);
3810         SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_CMD,
3811                       mfw_attr_cmd);
3812         if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_WRITE) {
3813                 OSAL_MEM_ZERO(&attr_cmd_write, sizeof(attr_cmd_write));
3814                 attr_cmd_write.val = p_drv_attr->val;
3815                 attr_cmd_write.mask = p_drv_attr->mask;
3816                 attr_cmd_write.offset = p_drv_attr->offset;
3817
3818                 mb_params.p_data_src = &attr_cmd_write;
3819                 mb_params.data_src_size = sizeof(attr_cmd_write);
3820         }
3821
3822         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3823         if (rc != ECORE_SUCCESS)
3824                 return rc;
3825
3826         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3827                 DP_INFO(p_hwfn,
3828                         "The attribute command is not supported by the MFW\n");
3829                 return ECORE_NOTIMPL;
3830         } else if (mb_params.mcp_resp != FW_MSG_CODE_OK) {
3831                 DP_INFO(p_hwfn,
3832                         "Failed to send an attribute command [mcp_resp 0x%x, attr_cmd %d, attr_num %d]\n",
3833                         mb_params.mcp_resp, p_drv_attr->attr_cmd,
3834                         p_drv_attr->attr_num);
3835                 return ECORE_INVAL;
3836         }
3837
3838         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3839                    "Attribute Command: cmd %d [mfw_cmd %d], num %d, in={val 0x%08x, mask 0x%08x, offset 0x%08x}, out={val 0x%08x}\n",
3840                    p_drv_attr->attr_cmd, mfw_attr_cmd, p_drv_attr->attr_num,
3841                    p_drv_attr->val, p_drv_attr->mask, p_drv_attr->offset,
3842                    mb_params.mcp_param);
3843
3844         if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ ||
3845             p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR)
3846                 p_drv_attr->val = mb_params.mcp_param;
3847
3848         return ECORE_SUCCESS;
3849 }
3850
3851 void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3852                       u32 offset, u32 val)
3853 {
3854         struct ecore_mcp_mb_params mb_params = {0};
3855         enum _ecore_status_t       rc = ECORE_SUCCESS;
3856         u32                        dword = val;
3857
3858         mb_params.cmd = DRV_MSG_CODE_WRITE_WOL_REG;
3859         mb_params.param = offset;
3860         mb_params.p_data_src = &dword;
3861         mb_params.data_src_size = sizeof(dword);
3862
3863         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3864         if (rc != ECORE_SUCCESS) {
3865                 DP_NOTICE(p_hwfn, false,
3866                           "Failed to wol write request, rc = %d\n", rc);
3867         }
3868
3869         if (mb_params.mcp_resp != FW_MSG_CODE_WOL_READ_WRITE_OK) {
3870                 DP_NOTICE(p_hwfn, false,
3871                           "Failed to write value 0x%x to offset 0x%x [mcp_resp 0x%x]\n",
3872                           val, offset, mb_params.mcp_resp);
3873                 rc = ECORE_UNKNOWN_ERROR;
3874         }
3875 }