drivers/net/qede/base/ecore_sp_commands.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10
  11 #include "ecore.h"
  12 #include "ecore_status.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_spq.h"
  15 #include "ecore_init_fw_funcs.h"
  16 #include "ecore_cxt.h"
  17 #include "ecore_sp_commands.h"
  18 #include "ecore_gtt_reg_addr.h"
  19 #include "ecore_iro.h"
  20 #include "reg_addr.h"
  21 #include "ecore_int.h"
  22 #include "ecore_hw.h"
  23 #include "ecore_dcbx.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26
  27 enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
  28                                            struct ecore_spq_entry **pp_ent,
  29                                            u8 cmd,
  30                                            u8 protocol,
  31                                            struct ecore_sp_init_data *p_data)
  32 {
  33         u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
  34         struct ecore_spq_entry *p_ent = OSAL_NULL;
  35         enum _ecore_status_t rc;
  36
  37         if (!pp_ent)
  38                 return ECORE_INVAL;
  39
  40         /* Get an SPQ entry */
  41         rc = ecore_spq_get_entry(p_hwfn, pp_ent);
  42         if (rc != ECORE_SUCCESS)
  43                 return rc;
  44
  45         /* Fill the SPQ entry */
  46         p_ent = *pp_ent;
  47         p_ent->elem.hdr.cid = OSAL_CPU_TO_LE32(opaque_cid);
  48         p_ent->elem.hdr.cmd_id = cmd;
  49         p_ent->elem.hdr.protocol_id = protocol;
  50         p_ent->priority = ECORE_SPQ_PRIORITY_NORMAL;
  51         p_ent->comp_mode = p_data->comp_mode;
  52         p_ent->comp_done.done = 0;
  53
  54         switch (p_ent->comp_mode) {
  55         case ECORE_SPQ_MODE_EBLOCK:
  56                 p_ent->comp_cb.cookie = &p_ent->comp_done;
  57                 break;
  58
  59         case ECORE_SPQ_MODE_BLOCK:
  60                 if (!p_data->p_comp_data)
  61                         return ECORE_INVAL;
  62
  63                 p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
  64                 break;
  65
  66         case ECORE_SPQ_MODE_CB:
  67                 if (!p_data->p_comp_data)
  68                         p_ent->comp_cb.function = OSAL_NULL;
  69                 else
  70                         p_ent->comp_cb = *p_data->p_comp_data;
  71                 break;
  72
  73         default:
  74                 DP_NOTICE(p_hwfn, true, "Unknown SPQE completion mode %d\n",
  75                           p_ent->comp_mode);
  76                 return ECORE_INVAL;
  77         }
  78
  79         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
  80                    "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
  81                    opaque_cid, cmd, protocol,
  82                    (unsigned long)&p_ent->ramrod,
  83                    D_TRINE(p_ent->comp_mode, ECORE_SPQ_MODE_EBLOCK,
  84                            ECORE_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
  85                            "MODE_CB"));
  86
  87         OSAL_MEMSET(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
  88
  89         return ECORE_SUCCESS;
  90 }
  91
  92 static enum tunnel_clss ecore_tunn_clss_to_fw_clss(u8 type)
  93 {
  94         switch (type) {
  95         case ECORE_TUNN_CLSS_MAC_VLAN:
  96                 return TUNNEL_CLSS_MAC_VLAN;
  97         case ECORE_TUNN_CLSS_MAC_VNI:
  98                 return TUNNEL_CLSS_MAC_VNI;
  99         case ECORE_TUNN_CLSS_INNER_MAC_VLAN:
 100                 return TUNNEL_CLSS_INNER_MAC_VLAN;
 101         case ECORE_TUNN_CLSS_INNER_MAC_VNI:
 102                 return TUNNEL_CLSS_INNER_MAC_VNI;
 103         case ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
 104                 return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
 105         default:
 106                 return TUNNEL_CLSS_MAC_VLAN;
 107         }
 108 }
 109
 110 static void
 111 ecore_set_pf_update_tunn_mode(struct ecore_tunnel_info *p_tun,
 112                               struct ecore_tunnel_info *p_src,
 113                               bool b_pf_start)
 114 {
 115         if (p_src->vxlan.b_update_mode || b_pf_start)
 116                 p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled;
 117
 118         if (p_src->l2_gre.b_update_mode || b_pf_start)
 119                 p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled;
 120
 121         if (p_src->ip_gre.b_update_mode || b_pf_start)
 122                 p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled;
 123
 124         if (p_src->l2_geneve.b_update_mode || b_pf_start)
 125                 p_tun->l2_geneve.b_mode_enabled =
 126                                 p_src->l2_geneve.b_mode_enabled;
 127
 128         if (p_src->ip_geneve.b_update_mode || b_pf_start)
 129                 p_tun->ip_geneve.b_mode_enabled =
 130                                 p_src->ip_geneve.b_mode_enabled;
 131 }
 132
 133 static void ecore_set_tunn_cls_info(struct ecore_tunnel_info *p_tun,
 134                                     struct ecore_tunnel_info *p_src)
 135 {
 136         enum tunnel_clss type;
 137
 138         p_tun->b_update_rx_cls = p_src->b_update_rx_cls;
 139         p_tun->b_update_tx_cls = p_src->b_update_tx_cls;
 140
 141         /* @DPDK - typecast tunnul class */
 142         type = ecore_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls);
 143         p_tun->vxlan.tun_cls = (enum ecore_tunn_clss)type;
 144         type = ecore_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls);
 145         p_tun->l2_gre.tun_cls = (enum ecore_tunn_clss)type;
 146         type = ecore_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls);
 147         p_tun->ip_gre.tun_cls = (enum ecore_tunn_clss)type;
 148         type = ecore_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls);
 149         p_tun->l2_geneve.tun_cls = (enum ecore_tunn_clss)type;
 150         type = ecore_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls);
 151         p_tun->ip_geneve.tun_cls = (enum ecore_tunn_clss)type;
 152 }
 153
 154 static void ecore_set_tunn_ports(struct ecore_tunnel_info *p_tun,
 155                                  struct ecore_tunnel_info *p_src)
 156 {
 157         p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port;
 158         p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port;
 159
 160         if (p_src->geneve_port.b_update_port)
 161                 p_tun->geneve_port.port = p_src->geneve_port.port;
 162
 163         if (p_src->vxlan_port.b_update_port)
 164                 p_tun->vxlan_port.port = p_src->vxlan_port.port;
 165 }
 166
 167 static void
 168 __ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls,
 169                                 struct ecore_tunn_update_type *tun_type)
 170 {
 171         *p_tunn_cls = tun_type->tun_cls;
 172 }
 173
 174 static void
 175 ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls,
 176                               struct ecore_tunn_update_type *tun_type,
 177                               u8 *p_update_port, __le16 *p_port,
 178                               struct ecore_tunn_update_udp_port *p_udp_port)
 179 {
 180         __ecore_set_ramrod_tunnel_param(p_tunn_cls, tun_type);
 181         if (p_udp_port->b_update_port) {
 182                 *p_update_port = 1;
 183                 *p_port = OSAL_CPU_TO_LE16(p_udp_port->port);
 184         }
 185 }
 186
 187 static void
 188 ecore_tunn_set_pf_update_params(struct ecore_hwfn               *p_hwfn,
 189                                 struct ecore_tunnel_info *p_src,
 190                                 struct pf_update_tunnel_config  *p_tunn_cfg)
 191 {
 192         struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
 193
 194         ecore_set_pf_update_tunn_mode(p_tun, p_src, false);
 195         ecore_set_tunn_cls_info(p_tun, p_src);
 196         ecore_set_tunn_ports(p_tun, p_src);
 197
 198         ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
 199                                       &p_tun->vxlan,
 200                                       &p_tunn_cfg->set_vxlan_udp_port_flg,
 201                                       &p_tunn_cfg->vxlan_udp_port,
 202                                       &p_tun->vxlan_port);
 203
 204         ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
 205                                       &p_tun->l2_geneve,
 206                                       &p_tunn_cfg->set_geneve_udp_port_flg,
 207                                       &p_tunn_cfg->geneve_udp_port,
 208                                       &p_tun->geneve_port);
 209
 210         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
 211                                         &p_tun->ip_geneve);
 212
 213         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
 214                                         &p_tun->l2_gre);
 215
 216         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
 217                                         &p_tun->ip_gre);
 218
 219         p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
 220 }
 221
 222 static void ecore_set_hw_tunn_mode(struct ecore_hwfn *p_hwfn,
 223                                    struct ecore_ptt *p_ptt,
 224                                    struct ecore_tunnel_info *p_tun)
 225 {
 226         ecore_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled,
 227                              p_tun->ip_gre.b_mode_enabled);
 228         ecore_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled);
 229
 230         ecore_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled,
 231                                 p_tun->ip_geneve.b_mode_enabled);
 232 }
 233
 234 static void ecore_set_hw_tunn_mode_port(struct ecore_hwfn *p_hwfn,
 235                                         struct ecore_ptt  *p_ptt,
 236                                         struct ecore_tunnel_info *p_tunn)
 237 {
 238         if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
 239                 DP_NOTICE(p_hwfn, true,
 240                           "A0 chip: tunnel hw config is not supported\n");
 241                 return;
 242         }
 243
 244         if (p_tunn->vxlan_port.b_update_port)
 245                 ecore_set_vxlan_dest_port(p_hwfn, p_ptt,
 246                                           p_tunn->vxlan_port.port);
 247
 248         if (p_tunn->geneve_port.b_update_port)
 249                 ecore_set_geneve_dest_port(p_hwfn, p_ptt,
 250                                            p_tunn->geneve_port.port);
 251
 252         ecore_set_hw_tunn_mode(p_hwfn, p_ptt, p_tunn);
 253 }
 254
 255 static void
 256 ecore_tunn_set_pf_start_params(struct ecore_hwfn *p_hwfn,
 257                                struct ecore_tunnel_info         *p_src,
 258                                struct pf_start_tunnel_config *p_tunn_cfg)
 259 {
 260         struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
 261
 262         if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
 263                 DP_NOTICE(p_hwfn, true,
 264                           "A0 chip: tunnel pf start config is not supported\n");
 265                 return;
 266         }
 267
 268         if (!p_src)
 269                 return;
 270
 271         ecore_set_pf_update_tunn_mode(p_tun, p_src, true);
 272         ecore_set_tunn_cls_info(p_tun, p_src);
 273         ecore_set_tunn_ports(p_tun, p_src);
 274
 275         ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
 276                                       &p_tun->vxlan,
 277                                       &p_tunn_cfg->set_vxlan_udp_port_flg,
 278                                       &p_tunn_cfg->vxlan_udp_port,
 279                                       &p_tun->vxlan_port);
 280
 281         ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
 282                                       &p_tun->l2_geneve,
 283                                       &p_tunn_cfg->set_geneve_udp_port_flg,
 284                                       &p_tunn_cfg->geneve_udp_port,
 285                                       &p_tun->geneve_port);
 286
 287         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
 288                                         &p_tun->ip_geneve);
 289
 290         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
 291                                         &p_tun->l2_gre);
 292
 293         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
 294                                         &p_tun->ip_gre);
 295 }
 296
 297 #define ETH_P_8021Q 0x8100
 298 #define ETH_P_8021AD 0x88A8 /* 802.1ad Service VLAN         */
 299
 300 enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
 301                                        struct ecore_ptt *p_ptt,
 302                                        struct ecore_tunnel_info *p_tunn,
 303                                        bool allow_npar_tx_switch)
 304 {
 305         struct pf_start_ramrod_data *p_ramrod = OSAL_NULL;
 306         u16 sb = ecore_int_get_sp_sb_id(p_hwfn);
 307         u8 sb_index = p_hwfn->p_eq->eq_sb_index;
 308         struct ecore_spq_entry *p_ent = OSAL_NULL;
 309         struct ecore_sp_init_data init_data;
 310         enum _ecore_status_t rc = ECORE_NOTIMPL;
 311         u8 page_cnt;
 312         u8 i;
 313
 314         /* update initial eq producer */
 315         ecore_eq_prod_update(p_hwfn,
 316                              ecore_chain_get_prod_idx(&p_hwfn->p_eq->chain));
 317
 318         /* Initialize the SPQ entry for the ramrod */
 319         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 320         init_data.cid = ecore_spq_get_cid(p_hwfn);
 321         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 322         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 323
 324         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 325                                    COMMON_RAMROD_PF_START,
 326                                    PROTOCOLID_COMMON, &init_data);
 327         if (rc != ECORE_SUCCESS)
 328                 return rc;
 329
 330         /* Fill the ramrod data */
 331         p_ramrod = &p_ent->ramrod.pf_start;
 332         p_ramrod->event_ring_sb_id = OSAL_CPU_TO_LE16(sb);
 333         p_ramrod->event_ring_sb_index = sb_index;
 334         p_ramrod->path_id = ECORE_PATH_ID(p_hwfn);
 335
 336         /* For easier debugging */
 337         p_ramrod->dont_log_ramrods = 0;
 338         p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0x8f);
 339
 340         if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
 341                 p_ramrod->mf_mode = MF_OVLAN;
 342         else
 343                 p_ramrod->mf_mode = MF_NPAR;
 344
 345         p_ramrod->outer_tag_config.outer_tag.tci =
 346                 OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan);
 347         if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, &p_hwfn->p_dev->mf_bits)) {
 348                 p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q;
 349         } else if (OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
 350                  &p_hwfn->p_dev->mf_bits)) {
 351                 p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD;
 352                 p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
 353         }
 354
 355         p_ramrod->outer_tag_config.pri_map_valid = 1;
 356         for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++)
 357                 p_ramrod->outer_tag_config.inner_to_outer_pri_map[i] = i;
 358
 359         /* enable_stag_pri_change should be set if port is in BD mode or,
 360          * UFP with Host Control mode or, UFP with DCB over base interface.
 361          */
 362         if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) {
 363                 if ((p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS) ||
 364                     (p_hwfn->p_dcbx_info->results.dcbx_enabled))
 365                         p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
 366                 else
 367                         p_ramrod->outer_tag_config.enable_stag_pri_change = 0;
 368         }
 369
 370         /* Place EQ address in RAMROD */
 371         DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
 372                        p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
 373         page_cnt = (u8)ecore_chain_get_page_cnt(&p_hwfn->p_eq->chain);
 374         p_ramrod->event_ring_num_pages = page_cnt;
 375         DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
 376                        p_hwfn->p_consq->chain.pbl_sp.p_phys_table);
 377
 378         ecore_tunn_set_pf_start_params(p_hwfn, p_tunn,
 379                                        &p_ramrod->tunnel_config);
 380
 381         if (OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH,
 382                           &p_hwfn->p_dev->mf_bits))
 383                 p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
 384
 385         switch (p_hwfn->hw_info.personality) {
 386         case ECORE_PCI_ETH:
 387                 p_ramrod->personality = PERSONALITY_ETH;
 388                 break;
 389         default:
 390                 DP_NOTICE(p_hwfn, true, "Unknown personality %d\n",
 391                          p_hwfn->hw_info.personality);
 392                 p_ramrod->personality = PERSONALITY_ETH;
 393         }
 394
 395         if (p_hwfn->p_dev->p_iov_info) {
 396                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
 397
 398                 p_ramrod->base_vf_id = (u8)p_iov->first_vf_in_pf;
 399                 p_ramrod->num_vfs = (u8)p_iov->total_vfs;
 400         }
 401         /* @@@TBD - update also the "ROCE_VER_KEY" entries when the FW RoCE HSI
 402          * version is available.
 403          */
 404         p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
 405         p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
 406
 407         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
 408                    "Setting event_ring_sb [id %04x index %02x], outer_tag.tpid [%d], outer_tag.tci [%d]\n",
 409                    sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tpid,
 410                    p_ramrod->outer_tag_config.outer_tag.tci);
 411
 412         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 413
 414         if (p_tunn)
 415                 ecore_set_hw_tunn_mode_port(p_hwfn, p_ptt,
 416                                             &p_hwfn->p_dev->tunnel);
 417
 418         return rc;
 419 }
 420
 421 enum _ecore_status_t ecore_sp_pf_update_dcbx(struct ecore_hwfn *p_hwfn)
 422 {
 423         struct ecore_spq_entry *p_ent = OSAL_NULL;
 424         struct ecore_sp_init_data init_data;
 425         enum _ecore_status_t rc = ECORE_NOTIMPL;
 426
 427         /* Get SPQ entry */
 428         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 429         init_data.cid = ecore_spq_get_cid(p_hwfn);
 430         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 431         init_data.comp_mode = ECORE_SPQ_MODE_CB;
 432
 433         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 434                                    COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
 435                                    &init_data);
 436         if (rc != ECORE_SUCCESS)
 437                 return rc;
 438
 439         ecore_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
 440                                         &p_ent->ramrod.pf_update);
 441
 442         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 443 }
 444
 445 enum _ecore_status_t ecore_sp_pf_update_ufp(struct ecore_hwfn *p_hwfn)
 446 {
 447         struct ecore_spq_entry *p_ent = OSAL_NULL;
 448         struct ecore_sp_init_data init_data;
 449         enum _ecore_status_t rc = ECORE_NOTIMPL;
 450
 451         /* Get SPQ entry */
 452         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 453         init_data.cid = ecore_spq_get_cid(p_hwfn);
 454         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 455         init_data.comp_mode = ECORE_SPQ_MODE_CB;
 456
 457         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 458                                    COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
 459                                    &init_data);
 460         if (rc != ECORE_SUCCESS)
 461                 return rc;
 462
 463         p_ent->ramrod.pf_update.update_enable_stag_pri_change = true;
 464         if ((p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS) ||
 465             (p_hwfn->p_dcbx_info->results.dcbx_enabled))
 466                 p_ent->ramrod.pf_update.enable_stag_pri_change = 1;
 467         else
 468                 p_ent->ramrod.pf_update.enable_stag_pri_change = 0;
 469
 470         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 471 }
 472
 473
 474 /* QM rate limiter resolution is 1.6Mbps */
 475 #define QM_RL_RESOLUTION(mb_val)        ((mb_val) * 10 / 16)
 476
 477 /* FW uses 1/64k to express gd */
 478 #define FW_GD_RESOLUTION(gd)            (64 * 1024 / (gd))
 479
 480 u16 ecore_sp_rl_mb_to_qm(u32 mb_val)
 481 {
 482         return (u16)OSAL_MIN_T(u32, (u16)(~0U), QM_RL_RESOLUTION(mb_val));
 483 }
 484
 485 u16 ecore_sp_rl_gd_denom(u32 gd)
 486 {
 487         return gd ? (u16)OSAL_MIN_T(u32, (u16)(~0U), FW_GD_RESOLUTION(gd)) : 0;
 488 }
 489
 490 enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
 491                                         struct ecore_rl_update_params *params)
 492 {
 493         struct ecore_spq_entry *p_ent = OSAL_NULL;
 494         enum _ecore_status_t rc = ECORE_NOTIMPL;
 495         struct rl_update_ramrod_data *rl_update;
 496         struct ecore_sp_init_data init_data;
 497
 498         /* Get SPQ entry */
 499         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 500         init_data.cid = ecore_spq_get_cid(p_hwfn);
 501         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 502         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 503
 504         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 505                                    COMMON_RAMROD_RL_UPDATE, PROTOCOLID_COMMON,
 506                                    &init_data);
 507         if (rc != ECORE_SUCCESS)
 508                 return rc;
 509
 510         rl_update = &p_ent->ramrod.rl_update;
 511
 512         rl_update->qcn_update_param_flg = params->qcn_update_param_flg;
 513         rl_update->dcqcn_update_param_flg = params->dcqcn_update_param_flg;
 514         rl_update->rl_init_flg = params->rl_init_flg;
 515         rl_update->rl_start_flg = params->rl_start_flg;
 516         rl_update->rl_stop_flg = params->rl_stop_flg;
 517         rl_update->rl_id_first = params->rl_id_first;
 518         rl_update->rl_id_last = params->rl_id_last;
 519         rl_update->rl_dc_qcn_flg = params->rl_dc_qcn_flg;
 520         rl_update->rl_bc_rate = OSAL_CPU_TO_LE32(params->rl_bc_rate);
 521         rl_update->rl_max_rate =
 522                 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_max_rate));
 523         rl_update->rl_r_ai =
 524                 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_r_ai));
 525         rl_update->rl_r_hai =
 526                 OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_r_hai));
 527         rl_update->dcqcn_g =
 528                 OSAL_CPU_TO_LE16(ecore_sp_rl_gd_denom(params->dcqcn_gd));
 529         rl_update->dcqcn_k_us = OSAL_CPU_TO_LE32(params->dcqcn_k_us);
 530         rl_update->dcqcn_timeuot_us =
 531                 OSAL_CPU_TO_LE32(params->dcqcn_timeuot_us);
 532         rl_update->qcn_timeuot_us = OSAL_CPU_TO_LE32(params->qcn_timeuot_us);
 533
 534         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "rl_params: qcn_update_param_flg %x, dcqcn_update_param_flg %x, rl_init_flg %x, rl_start_flg %x, rl_stop_flg %x, rl_id_first %x, rl_id_last %x, rl_dc_qcn_flg %x, rl_bc_rate %x, rl_max_rate %x, rl_r_ai %x, rl_r_hai %x, dcqcn_g %x, dcqcn_k_us %x, dcqcn_timeuot_us %x, qcn_timeuot_us %x\n",
 535                    rl_update->qcn_update_param_flg,
 536                    rl_update->dcqcn_update_param_flg,
 537                    rl_update->rl_init_flg, rl_update->rl_start_flg,
 538                    rl_update->rl_stop_flg, rl_update->rl_id_first,
 539                    rl_update->rl_id_last, rl_update->rl_dc_qcn_flg,
 540                    rl_update->rl_bc_rate, rl_update->rl_max_rate,
 541                    rl_update->rl_r_ai, rl_update->rl_r_hai,
 542                    rl_update->dcqcn_g, rl_update->dcqcn_k_us,
 543                    rl_update->dcqcn_timeuot_us, rl_update->qcn_timeuot_us);
 544
 545         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 546 }
 547
 548 /* Set pf update ramrod command params */
 549 enum _ecore_status_t
 550 ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn,
 551                             struct ecore_ptt *p_ptt,
 552                             struct ecore_tunnel_info *p_tunn,
 553                             enum spq_mode comp_mode,
 554                             struct ecore_spq_comp_cb *p_comp_data)
 555 {
 556         struct ecore_spq_entry *p_ent = OSAL_NULL;
 557         struct ecore_sp_init_data init_data;
 558         enum _ecore_status_t rc = ECORE_NOTIMPL;
 559
 560         if (IS_VF(p_hwfn->p_dev))
 561                 return ecore_vf_pf_tunnel_param_update(p_hwfn, p_tunn);
 562
 563         if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
 564                 DP_NOTICE(p_hwfn, true,
 565                           "A0 chip: tunnel pf update config is not supported\n");
 566                 return rc;
 567         }
 568
 569         if (!p_tunn)
 570                 return ECORE_INVAL;
 571
 572         /* Get SPQ entry */
 573         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 574         init_data.cid = ecore_spq_get_cid(p_hwfn);
 575         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 576         init_data.comp_mode = comp_mode;
 577         init_data.p_comp_data = p_comp_data;
 578
 579         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 580                                    COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
 581                                    &init_data);
 582         if (rc != ECORE_SUCCESS)
 583                 return rc;
 584
 585         ecore_tunn_set_pf_update_params(p_hwfn, p_tunn,
 586                                         &p_ent->ramrod.pf_update.tunnel_config);
 587
 588         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 589         if (rc != ECORE_SUCCESS)
 590                 return rc;
 591
 592         ecore_set_hw_tunn_mode_port(p_hwfn, p_ptt, &p_hwfn->p_dev->tunnel);
 593
 594         return rc;
 595 }
 596
 597 enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn)
 598 {
 599         struct ecore_spq_entry *p_ent = OSAL_NULL;
 600         struct ecore_sp_init_data init_data;
 601         enum _ecore_status_t rc = ECORE_NOTIMPL;
 602
 603         /* Get SPQ entry */
 604         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 605         init_data.cid = ecore_spq_get_cid(p_hwfn);
 606         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 607         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 608
 609         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 610                                    COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
 611                                    &init_data);
 612         if (rc != ECORE_SUCCESS)
 613                 return rc;
 614
 615         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 616 }
 617
 618 enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn)
 619 {
 620         struct ecore_spq_entry *p_ent = OSAL_NULL;
 621         struct ecore_sp_init_data init_data;
 622         enum _ecore_status_t rc;
 623
 624         /* Get SPQ entry */
 625         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 626         init_data.cid = ecore_spq_get_cid(p_hwfn);
 627         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 628         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 629
 630         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 631                                    COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
 632                                    &init_data);
 633         if (rc != ECORE_SUCCESS)
 634                 return rc;
 635
 636         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 637 }
 638
 639 enum _ecore_status_t ecore_sp_pf_update_stag(struct ecore_hwfn *p_hwfn)
 640 {
 641         struct ecore_spq_entry *p_ent = OSAL_NULL;
 642         struct ecore_sp_init_data init_data;
 643         enum _ecore_status_t rc = ECORE_NOTIMPL;
 644
 645         /* Get SPQ entry */
 646         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 647         init_data.cid = ecore_spq_get_cid(p_hwfn);
 648         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 649         init_data.comp_mode = ECORE_SPQ_MODE_CB;
 650
 651         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 652                                    COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
 653                                    &init_data);
 654         if (rc != ECORE_SUCCESS)
 655                 return rc;
 656
 657         p_ent->ramrod.pf_update.update_mf_vlan_flag = true;
 658         p_ent->ramrod.pf_update.mf_vlan =
 659                                 OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan);
 660
 661         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 662 }