drivers/net/qede/base/ecore_sp_commands.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10
  11 #include "ecore.h"
  12 #include "ecore_status.h"
  13 #include "ecore_chain.h"
  14 #include "ecore_spq.h"
  15 #include "ecore_init_fw_funcs.h"
  16 #include "ecore_cxt.h"
  17 #include "ecore_sp_commands.h"
  18 #include "ecore_gtt_reg_addr.h"
  19 #include "ecore_iro.h"
  20 #include "reg_addr.h"
  21 #include "ecore_int.h"
  22 #include "ecore_hw.h"
  23 #include "ecore_dcbx.h"
  24 #include "ecore_sriov.h"
  25 #include "ecore_vf.h"
  26
  27 enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
  28                                            struct ecore_spq_entry **pp_ent,
  29                                            u8 cmd,
  30                                            u8 protocol,
  31                                            struct ecore_sp_init_data *p_data)
  32 {
  33         u32 opaque_cid = p_data->opaque_fid << 16 | p_data->cid;
  34         struct ecore_spq_entry *p_ent = OSAL_NULL;
  35         enum _ecore_status_t rc;
  36
  37         if (!pp_ent)
  38                 return ECORE_INVAL;
  39
  40         /* Get an SPQ entry */
  41         rc = ecore_spq_get_entry(p_hwfn, pp_ent);
  42         if (rc != ECORE_SUCCESS)
  43                 return rc;
  44
  45         /* Fill the SPQ entry */
  46         p_ent = *pp_ent;
  47         p_ent->elem.hdr.cid = OSAL_CPU_TO_LE32(opaque_cid);
  48         p_ent->elem.hdr.cmd_id = cmd;
  49         p_ent->elem.hdr.protocol_id = protocol;
  50         p_ent->priority = ECORE_SPQ_PRIORITY_NORMAL;
  51         p_ent->comp_mode = p_data->comp_mode;
  52         p_ent->comp_done.done = 0;
  53
  54         switch (p_ent->comp_mode) {
  55         case ECORE_SPQ_MODE_EBLOCK:
  56                 p_ent->comp_cb.cookie = &p_ent->comp_done;
  57                 break;
  58
  59         case ECORE_SPQ_MODE_BLOCK:
  60                 if (!p_data->p_comp_data)
  61                         return ECORE_INVAL;
  62
  63                 p_ent->comp_cb.cookie = p_data->p_comp_data->cookie;
  64                 break;
  65
  66         case ECORE_SPQ_MODE_CB:
  67                 if (!p_data->p_comp_data)
  68                         p_ent->comp_cb.function = OSAL_NULL;
  69                 else
  70                         p_ent->comp_cb = *p_data->p_comp_data;
  71                 break;
  72
  73         default:
  74                 DP_NOTICE(p_hwfn, true, "Unknown SPQE completion mode %d\n",
  75                           p_ent->comp_mode);
  76                 return ECORE_INVAL;
  77         }
  78
  79         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
  80                    "Initialized: CID %08x cmd %02x protocol %02x data_addr %lu comp_mode [%s]\n",
  81                    opaque_cid, cmd, protocol,
  82                    (unsigned long)&p_ent->ramrod,
  83                    D_TRINE(p_ent->comp_mode, ECORE_SPQ_MODE_EBLOCK,
  84                            ECORE_SPQ_MODE_BLOCK, "MODE_EBLOCK", "MODE_BLOCK",
  85                            "MODE_CB"));
  86
  87         OSAL_MEMSET(&p_ent->ramrod, 0, sizeof(p_ent->ramrod));
  88
  89         return ECORE_SUCCESS;
  90 }
  91
  92 static enum tunnel_clss ecore_tunn_clss_to_fw_clss(u8 type)
  93 {
  94         switch (type) {
  95         case ECORE_TUNN_CLSS_MAC_VLAN:
  96                 return TUNNEL_CLSS_MAC_VLAN;
  97         case ECORE_TUNN_CLSS_MAC_VNI:
  98                 return TUNNEL_CLSS_MAC_VNI;
  99         case ECORE_TUNN_CLSS_INNER_MAC_VLAN:
 100                 return TUNNEL_CLSS_INNER_MAC_VLAN;
 101         case ECORE_TUNN_CLSS_INNER_MAC_VNI:
 102                 return TUNNEL_CLSS_INNER_MAC_VNI;
 103         case ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
 104                 return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
 105         default:
 106                 return TUNNEL_CLSS_MAC_VLAN;
 107         }
 108 }
 109
 110 static void
 111 ecore_set_pf_update_tunn_mode(struct ecore_tunnel_info *p_tun,
 112                               struct ecore_tunnel_info *p_src,
 113                               bool b_pf_start)
 114 {
 115         if (p_src->vxlan.b_update_mode || b_pf_start)
 116                 p_tun->vxlan.b_mode_enabled = p_src->vxlan.b_mode_enabled;
 117
 118         if (p_src->l2_gre.b_update_mode || b_pf_start)
 119                 p_tun->l2_gre.b_mode_enabled = p_src->l2_gre.b_mode_enabled;
 120
 121         if (p_src->ip_gre.b_update_mode || b_pf_start)
 122                 p_tun->ip_gre.b_mode_enabled = p_src->ip_gre.b_mode_enabled;
 123
 124         if (p_src->l2_geneve.b_update_mode || b_pf_start)
 125                 p_tun->l2_geneve.b_mode_enabled =
 126                                 p_src->l2_geneve.b_mode_enabled;
 127
 128         if (p_src->ip_geneve.b_update_mode || b_pf_start)
 129                 p_tun->ip_geneve.b_mode_enabled =
 130                                 p_src->ip_geneve.b_mode_enabled;
 131 }
 132
 133 static void ecore_set_tunn_cls_info(struct ecore_tunnel_info *p_tun,
 134                                     struct ecore_tunnel_info *p_src)
 135 {
 136         enum tunnel_clss type;
 137
 138         p_tun->b_update_rx_cls = p_src->b_update_rx_cls;
 139         p_tun->b_update_tx_cls = p_src->b_update_tx_cls;
 140
 141         /* @DPDK - typecast tunnul class */
 142         type = ecore_tunn_clss_to_fw_clss(p_src->vxlan.tun_cls);
 143         p_tun->vxlan.tun_cls = (enum ecore_tunn_clss)type;
 144         type = ecore_tunn_clss_to_fw_clss(p_src->l2_gre.tun_cls);
 145         p_tun->l2_gre.tun_cls = (enum ecore_tunn_clss)type;
 146         type = ecore_tunn_clss_to_fw_clss(p_src->ip_gre.tun_cls);
 147         p_tun->ip_gre.tun_cls = (enum ecore_tunn_clss)type;
 148         type = ecore_tunn_clss_to_fw_clss(p_src->l2_geneve.tun_cls);
 149         p_tun->l2_geneve.tun_cls = (enum ecore_tunn_clss)type;
 150         type = ecore_tunn_clss_to_fw_clss(p_src->ip_geneve.tun_cls);
 151         p_tun->ip_geneve.tun_cls = (enum ecore_tunn_clss)type;
 152 }
 153
 154 static void ecore_set_tunn_ports(struct ecore_tunnel_info *p_tun,
 155                                  struct ecore_tunnel_info *p_src)
 156 {
 157         p_tun->geneve_port.b_update_port = p_src->geneve_port.b_update_port;
 158         p_tun->vxlan_port.b_update_port = p_src->vxlan_port.b_update_port;
 159
 160         if (p_src->geneve_port.b_update_port)
 161                 p_tun->geneve_port.port = p_src->geneve_port.port;
 162
 163         if (p_src->vxlan_port.b_update_port)
 164                 p_tun->vxlan_port.port = p_src->vxlan_port.port;
 165 }
 166
 167 static void
 168 __ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls, u8 *p_enable_tx_clas,
 169                                 struct ecore_tunn_update_type *tun_type)
 170 {
 171         *p_tunn_cls = tun_type->tun_cls;
 172
 173         if (tun_type->b_mode_enabled)
 174                 *p_enable_tx_clas = 1;
 175 }
 176
 177 static void
 178 ecore_set_ramrod_tunnel_param(u8 *p_tunn_cls, u8 *p_enable_tx_clas,
 179                               struct ecore_tunn_update_type *tun_type,
 180                               u8 *p_update_port, __le16 *p_port,
 181                               struct ecore_tunn_update_udp_port *p_udp_port)
 182 {
 183         __ecore_set_ramrod_tunnel_param(p_tunn_cls, p_enable_tx_clas,
 184                                         tun_type);
 185         if (p_udp_port->b_update_port) {
 186                 *p_update_port = 1;
 187                 *p_port = OSAL_CPU_TO_LE16(p_udp_port->port);
 188         }
 189 }
 190
 191 static void
 192 ecore_tunn_set_pf_update_params(struct ecore_hwfn               *p_hwfn,
 193                                 struct ecore_tunnel_info *p_src,
 194                                 struct pf_update_tunnel_config  *p_tunn_cfg)
 195 {
 196         struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
 197
 198         ecore_set_pf_update_tunn_mode(p_tun, p_src, false);
 199         ecore_set_tunn_cls_info(p_tun, p_src);
 200         ecore_set_tunn_ports(p_tun, p_src);
 201
 202         ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
 203                                       &p_tunn_cfg->tx_enable_vxlan,
 204                                       &p_tun->vxlan,
 205                                       &p_tunn_cfg->set_vxlan_udp_port_flg,
 206                                       &p_tunn_cfg->vxlan_udp_port,
 207                                       &p_tun->vxlan_port);
 208
 209         ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
 210                                       &p_tunn_cfg->tx_enable_l2geneve,
 211                                       &p_tun->l2_geneve,
 212                                       &p_tunn_cfg->set_geneve_udp_port_flg,
 213                                       &p_tunn_cfg->geneve_udp_port,
 214                                       &p_tun->geneve_port);
 215
 216         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
 217                                         &p_tunn_cfg->tx_enable_ipgeneve,
 218                                         &p_tun->ip_geneve);
 219
 220         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
 221                                         &p_tunn_cfg->tx_enable_l2gre,
 222                                         &p_tun->l2_gre);
 223
 224         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
 225                                         &p_tunn_cfg->tx_enable_ipgre,
 226                                         &p_tun->ip_gre);
 227
 228         p_tunn_cfg->update_rx_pf_clss = p_tun->b_update_rx_cls;
 229         p_tunn_cfg->update_tx_pf_clss = p_tun->b_update_tx_cls;
 230 }
 231
 232 static void ecore_set_hw_tunn_mode(struct ecore_hwfn *p_hwfn,
 233                                    struct ecore_ptt *p_ptt,
 234                                    struct ecore_tunnel_info *p_tun)
 235 {
 236         ecore_set_gre_enable(p_hwfn, p_ptt, p_tun->l2_gre.b_mode_enabled,
 237                              p_tun->ip_gre.b_mode_enabled);
 238         ecore_set_vxlan_enable(p_hwfn, p_ptt, p_tun->vxlan.b_mode_enabled);
 239
 240         ecore_set_geneve_enable(p_hwfn, p_ptt, p_tun->l2_geneve.b_mode_enabled,
 241                                 p_tun->ip_geneve.b_mode_enabled);
 242 }
 243
 244 static void ecore_set_hw_tunn_mode_port(struct ecore_hwfn *p_hwfn,
 245                                         struct ecore_tunnel_info *p_tunn)
 246 {
 247         if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
 248                 DP_NOTICE(p_hwfn, true,
 249                           "A0 chip: tunnel hw config is not supported\n");
 250                 return;
 251         }
 252
 253         if (p_tunn->vxlan_port.b_update_port)
 254                 ecore_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
 255                                           p_tunn->vxlan_port.port);
 256
 257         if (p_tunn->geneve_port.b_update_port)
 258                 ecore_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
 259                                            p_tunn->geneve_port.port);
 260
 261         ecore_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn);
 262 }
 263
 264 static void
 265 ecore_tunn_set_pf_start_params(struct ecore_hwfn *p_hwfn,
 266                                struct ecore_tunnel_info         *p_src,
 267                                struct pf_start_tunnel_config *p_tunn_cfg)
 268 {
 269         struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
 270
 271         if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
 272                 DP_NOTICE(p_hwfn, true,
 273                           "A0 chip: tunnel pf start config is not supported\n");
 274                 return;
 275         }
 276
 277         if (!p_src)
 278                 return;
 279
 280         ecore_set_pf_update_tunn_mode(p_tun, p_src, true);
 281         ecore_set_tunn_cls_info(p_tun, p_src);
 282         ecore_set_tunn_ports(p_tun, p_src);
 283
 284         ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_vxlan,
 285                                       &p_tunn_cfg->tx_enable_vxlan,
 286                                       &p_tun->vxlan,
 287                                       &p_tunn_cfg->set_vxlan_udp_port_flg,
 288                                       &p_tunn_cfg->vxlan_udp_port,
 289                                       &p_tun->vxlan_port);
 290
 291         ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2geneve,
 292                                       &p_tunn_cfg->tx_enable_l2geneve,
 293                                       &p_tun->l2_geneve,
 294                                       &p_tunn_cfg->set_geneve_udp_port_flg,
 295                                       &p_tunn_cfg->geneve_udp_port,
 296                                       &p_tun->geneve_port);
 297
 298         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgeneve,
 299                                         &p_tunn_cfg->tx_enable_ipgeneve,
 300                                         &p_tun->ip_geneve);
 301
 302         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_l2gre,
 303                                         &p_tunn_cfg->tx_enable_l2gre,
 304                                         &p_tun->l2_gre);
 305
 306         __ecore_set_ramrod_tunnel_param(&p_tunn_cfg->tunnel_clss_ipgre,
 307                                         &p_tunn_cfg->tx_enable_ipgre,
 308                                         &p_tun->ip_gre);
 309 }
 310
 311 enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
 312                                        struct ecore_tunnel_info *p_tunn,
 313                                        enum ecore_mf_mode mode,
 314                                        bool allow_npar_tx_switch)
 315 {
 316         struct pf_start_ramrod_data *p_ramrod = OSAL_NULL;
 317         u16 sb = ecore_int_get_sp_sb_id(p_hwfn);
 318         u8 sb_index = p_hwfn->p_eq->eq_sb_index;
 319         struct ecore_spq_entry *p_ent = OSAL_NULL;
 320         struct ecore_sp_init_data init_data;
 321         enum _ecore_status_t rc = ECORE_NOTIMPL;
 322         u8 page_cnt;
 323
 324         /* update initial eq producer */
 325         ecore_eq_prod_update(p_hwfn,
 326                              ecore_chain_get_prod_idx(&p_hwfn->p_eq->chain));
 327
 328         /* Initialize the SPQ entry for the ramrod */
 329         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 330         init_data.cid = ecore_spq_get_cid(p_hwfn);
 331         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 332         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 333
 334         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 335                                    COMMON_RAMROD_PF_START,
 336                                    PROTOCOLID_COMMON, &init_data);
 337         if (rc != ECORE_SUCCESS)
 338                 return rc;
 339
 340         /* Fill the ramrod data */
 341         p_ramrod = &p_ent->ramrod.pf_start;
 342         p_ramrod->event_ring_sb_id = OSAL_CPU_TO_LE16(sb);
 343         p_ramrod->event_ring_sb_index = sb_index;
 344         p_ramrod->path_id = ECORE_PATH_ID(p_hwfn);
 345
 346         /* For easier debugging */
 347         p_ramrod->dont_log_ramrods = 0;
 348         p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0xf);
 349
 350         switch (mode) {
 351         case ECORE_MF_DEFAULT:
 352         case ECORE_MF_NPAR:
 353                 p_ramrod->mf_mode = MF_NPAR;
 354                 break;
 355         case ECORE_MF_OVLAN:
 356                 p_ramrod->mf_mode = MF_OVLAN;
 357                 break;
 358         default:
 359                 DP_NOTICE(p_hwfn, true,
 360                           "Unsupported MF mode, init as DEFAULT\n");
 361                 p_ramrod->mf_mode = MF_NPAR;
 362         }
 363         p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
 364
 365         /* Place EQ address in RAMROD */
 366         DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
 367                        p_hwfn->p_eq->chain.pbl_sp.p_phys_table);
 368         page_cnt = (u8)ecore_chain_get_page_cnt(&p_hwfn->p_eq->chain);
 369         p_ramrod->event_ring_num_pages = page_cnt;
 370         DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
 371                        p_hwfn->p_consq->chain.pbl_sp.p_phys_table);
 372
 373         ecore_tunn_set_pf_start_params(p_hwfn, p_tunn,
 374                                        &p_ramrod->tunnel_config);
 375
 376         if (IS_MF_SI(p_hwfn))
 377                 p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
 378
 379         switch (p_hwfn->hw_info.personality) {
 380         case ECORE_PCI_ETH:
 381                 p_ramrod->personality = PERSONALITY_ETH;
 382                 break;
 383         default:
 384                 DP_NOTICE(p_hwfn, true, "Unknown personality %d\n",
 385                          p_hwfn->hw_info.personality);
 386                 p_ramrod->personality = PERSONALITY_ETH;
 387         }
 388
 389         if (p_hwfn->p_dev->p_iov_info) {
 390                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
 391
 392                 p_ramrod->base_vf_id = (u8)p_iov->first_vf_in_pf;
 393                 p_ramrod->num_vfs = (u8)p_iov->total_vfs;
 394         }
 395         /* @@@TBD - update also the "ROCE_VER_KEY" entries when the FW RoCE HSI
 396          * version is available.
 397          */
 398         p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
 399         p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
 400
 401         DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
 402                    "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
 403                    sb, sb_index, p_ramrod->outer_tag);
 404
 405         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 406
 407         if (p_tunn)
 408                 ecore_set_hw_tunn_mode_port(p_hwfn, &p_hwfn->p_dev->tunnel);
 409
 410         return rc;
 411 }
 412
 413 enum _ecore_status_t ecore_sp_pf_update(struct ecore_hwfn *p_hwfn)
 414 {
 415         struct ecore_spq_entry *p_ent = OSAL_NULL;
 416         struct ecore_sp_init_data init_data;
 417         enum _ecore_status_t rc = ECORE_NOTIMPL;
 418
 419         /* Get SPQ entry */
 420         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 421         init_data.cid = ecore_spq_get_cid(p_hwfn);
 422         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 423         init_data.comp_mode = ECORE_SPQ_MODE_CB;
 424
 425         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 426                                    COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
 427                                    &init_data);
 428         if (rc != ECORE_SUCCESS)
 429                 return rc;
 430
 431         ecore_dcbx_set_pf_update_params(&p_hwfn->p_dcbx_info->results,
 432                                         &p_ent->ramrod.pf_update);
 433
 434         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 435 }
 436
 437 enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
 438                                         struct ecore_rl_update_params *params)
 439 {
 440         struct ecore_spq_entry *p_ent = OSAL_NULL;
 441         enum _ecore_status_t rc = ECORE_NOTIMPL;
 442         struct rl_update_ramrod_data *rl_update;
 443         struct ecore_sp_init_data init_data;
 444
 445         /* Get SPQ entry */
 446         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 447         init_data.cid = ecore_spq_get_cid(p_hwfn);
 448         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 449         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 450
 451         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 452                                    COMMON_RAMROD_RL_UPDATE, PROTOCOLID_COMMON,
 453                                    &init_data);
 454         if (rc != ECORE_SUCCESS)
 455                 return rc;
 456
 457         rl_update = &p_ent->ramrod.rl_update;
 458
 459         rl_update->qcn_update_param_flg = params->qcn_update_param_flg;
 460         rl_update->dcqcn_update_param_flg = params->dcqcn_update_param_flg;
 461         rl_update->rl_init_flg = params->rl_init_flg;
 462         rl_update->rl_start_flg = params->rl_start_flg;
 463         rl_update->rl_stop_flg = params->rl_stop_flg;
 464         rl_update->rl_id_first = params->rl_id_first;
 465         rl_update->rl_id_last = params->rl_id_last;
 466         rl_update->rl_dc_qcn_flg = params->rl_dc_qcn_flg;
 467         rl_update->rl_bc_rate = OSAL_CPU_TO_LE32(params->rl_bc_rate);
 468         rl_update->rl_max_rate = OSAL_CPU_TO_LE16(params->rl_max_rate);
 469         rl_update->rl_r_ai = OSAL_CPU_TO_LE16(params->rl_r_ai);
 470         rl_update->rl_r_hai = OSAL_CPU_TO_LE16(params->rl_r_hai);
 471         rl_update->dcqcn_g = OSAL_CPU_TO_LE16(params->dcqcn_g);
 472         rl_update->dcqcn_k_us = OSAL_CPU_TO_LE32(params->dcqcn_k_us);
 473         rl_update->dcqcn_timeuot_us = OSAL_CPU_TO_LE32(
 474                 params->dcqcn_timeuot_us);
 475         rl_update->qcn_timeuot_us = OSAL_CPU_TO_LE32(params->qcn_timeuot_us);
 476
 477         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 478 }
 479
 480 /* Set pf update ramrod command params */
 481 enum _ecore_status_t
 482 ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn,
 483                             struct ecore_tunnel_info *p_tunn,
 484                             enum spq_mode comp_mode,
 485                             struct ecore_spq_comp_cb *p_comp_data)
 486 {
 487         struct ecore_spq_entry *p_ent = OSAL_NULL;
 488         struct ecore_sp_init_data init_data;
 489         enum _ecore_status_t rc = ECORE_NOTIMPL;
 490
 491         if (IS_VF(p_hwfn->p_dev))
 492                 return ecore_vf_pf_tunnel_param_update(p_hwfn, p_tunn);
 493
 494         if (ECORE_IS_BB_A0(p_hwfn->p_dev)) {
 495                 DP_NOTICE(p_hwfn, true,
 496                           "A0 chip: tunnel pf update config is not supported\n");
 497                 return rc;
 498         }
 499
 500         if (!p_tunn)
 501                 return ECORE_INVAL;
 502
 503         /* Get SPQ entry */
 504         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 505         init_data.cid = ecore_spq_get_cid(p_hwfn);
 506         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 507         init_data.comp_mode = comp_mode;
 508         init_data.p_comp_data = p_comp_data;
 509
 510         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 511                                    COMMON_RAMROD_PF_UPDATE, PROTOCOLID_COMMON,
 512                                    &init_data);
 513         if (rc != ECORE_SUCCESS)
 514                 return rc;
 515
 516         ecore_tunn_set_pf_update_params(p_hwfn, p_tunn,
 517                                         &p_ent->ramrod.pf_update.tunnel_config);
 518
 519         rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 520         if (rc != ECORE_SUCCESS)
 521                 return rc;
 522
 523         ecore_set_hw_tunn_mode_port(p_hwfn, &p_hwfn->p_dev->tunnel);
 524
 525         return rc;
 526 }
 527
 528 enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn)
 529 {
 530         struct ecore_spq_entry *p_ent = OSAL_NULL;
 531         struct ecore_sp_init_data init_data;
 532         enum _ecore_status_t rc = ECORE_NOTIMPL;
 533
 534         /* Get SPQ entry */
 535         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 536         init_data.cid = ecore_spq_get_cid(p_hwfn);
 537         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 538         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 539
 540         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 541                                    COMMON_RAMROD_PF_STOP, PROTOCOLID_COMMON,
 542                                    &init_data);
 543         if (rc != ECORE_SUCCESS)
 544                 return rc;
 545
 546         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 547 }
 548
 549 enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn)
 550 {
 551         struct ecore_spq_entry *p_ent = OSAL_NULL;
 552         struct ecore_sp_init_data init_data;
 553         enum _ecore_status_t rc;
 554
 555         /* Get SPQ entry */
 556         OSAL_MEMSET(&init_data, 0, sizeof(init_data));
 557         init_data.cid = ecore_spq_get_cid(p_hwfn);
 558         init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
 559         init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
 560
 561         rc = ecore_sp_init_request(p_hwfn, &p_ent,
 562                                    COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
 563                                    &init_data);
 564         if (rc != ECORE_SUCCESS)
 565                 return rc;
 566
 567         return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 568 }