2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
14 static const struct qed_eth_ops *qed_ops;
15 static const char *drivername = "qede pmd";
16 static int64_t timer_period = 1;
18 struct rte_qede_xstats_name_off {
19 char name[RTE_ETH_XSTATS_NAME_SIZE];
23 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
24 {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
25 {"rx_multicast_bytes",
26 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
27 {"rx_broadcast_bytes",
28 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
29 {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
30 {"rx_multicast_packets",
31 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
32 {"rx_broadcast_packets",
33 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
35 {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
36 {"tx_multicast_bytes",
37 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
38 {"tx_broadcast_bytes",
39 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
40 {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
41 {"tx_multicast_packets",
42 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
43 {"tx_broadcast_packets",
44 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
46 {"rx_64_byte_packets",
47 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
48 {"rx_65_to_127_byte_packets",
49 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
50 {"rx_128_to_255_byte_packets",
51 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
52 {"rx_256_to_511_byte_packets",
53 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
54 {"rx_512_to_1023_byte_packets",
55 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
56 {"rx_1024_to_1518_byte_packets",
57 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
58 {"rx_1519_to_1522_byte_packets",
59 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
60 {"rx_1519_to_2047_byte_packets",
61 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
62 {"rx_2048_to_4095_byte_packets",
63 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
64 {"rx_4096_to_9216_byte_packets",
65 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
66 {"rx_9217_to_16383_byte_packets",
67 offsetof(struct ecore_eth_stats,
68 rx_9217_to_16383_byte_packets)},
69 {"tx_64_byte_packets",
70 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
71 {"tx_65_to_127_byte_packets",
72 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
73 {"tx_128_to_255_byte_packets",
74 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
75 {"tx_256_to_511_byte_packets",
76 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
77 {"tx_512_to_1023_byte_packets",
78 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
79 {"tx_1024_to_1518_byte_packets",
80 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
81 {"trx_1519_to_1522_byte_packets",
82 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
83 {"tx_2048_to_4095_byte_packets",
84 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
85 {"tx_4096_to_9216_byte_packets",
86 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
87 {"tx_9217_to_16383_byte_packets",
88 offsetof(struct ecore_eth_stats,
89 tx_9217_to_16383_byte_packets)},
91 {"rx_mac_crtl_frames",
92 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
93 {"tx_mac_control_frames",
94 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
95 {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
96 {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
97 {"rx_priority_flow_control_frames",
98 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
99 {"tx_priority_flow_control_frames",
100 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
102 {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
103 {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
104 {"rx_carrier_errors",
105 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
106 {"rx_oversize_packet_errors",
107 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
108 {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
109 {"rx_undersize_packet_errors",
110 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
111 {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
112 {"rx_host_buffer_not_available",
113 offsetof(struct ecore_eth_stats, no_buff_discards)},
114 /* Number of packets discarded because they are bigger than MTU */
115 {"rx_packet_too_big_discards",
116 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
117 {"rx_ttl_zero_discards",
118 offsetof(struct ecore_eth_stats, ttl0_discard)},
119 {"rx_multi_function_tag_filter_discards",
120 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
121 {"rx_mac_filter_discards",
122 offsetof(struct ecore_eth_stats, mac_filter_discards)},
123 {"rx_hw_buffer_truncates",
124 offsetof(struct ecore_eth_stats, brb_truncates)},
125 {"rx_hw_buffer_discards",
126 offsetof(struct ecore_eth_stats, brb_discards)},
127 {"tx_lpi_entry_count",
128 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
129 {"tx_total_collisions",
130 offsetof(struct ecore_eth_stats, tx_total_collisions)},
131 {"tx_error_drop_packets",
132 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
134 {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
135 {"rx_mac_unicast_packets",
136 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
137 {"rx_mac_multicast_packets",
138 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
139 {"rx_mac_broadcast_packets",
140 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
142 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
143 {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
144 {"tx_mac_unicast_packets",
145 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
146 {"tx_mac_multicast_packets",
147 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
148 {"tx_mac_broadcast_packets",
149 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
151 {"lro_coalesced_packets",
152 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
153 {"lro_coalesced_events",
154 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
156 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
157 {"lro_not_coalesced_packets",
158 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
159 {"lro_coalesced_bytes",
160 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
163 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
165 offsetof(struct qede_rx_queue, rx_segs)},
167 offsetof(struct qede_rx_queue, rx_hw_errors)},
168 {"rx_q_allocation_errors",
169 offsetof(struct qede_rx_queue, rx_alloc_errors)}
172 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
174 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
178 qede_interrupt_handler(__rte_unused struct rte_intr_handle *handle, void *param)
180 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
181 struct qede_dev *qdev = eth_dev->data->dev_private;
182 struct ecore_dev *edev = &qdev->edev;
184 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
185 if (rte_intr_enable(ð_dev->pci_dev->intr_handle))
186 DP_ERR(edev, "rte_intr_enable failed\n");
190 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
192 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
193 qdev->num_tc = qdev->dev_info.num_tc;
197 static void qede_print_adapter_info(struct qede_dev *qdev)
199 struct ecore_dev *edev = &qdev->edev;
200 struct qed_dev_info *info = &qdev->dev_info.common;
201 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
202 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
204 DP_INFO(edev, "*********************************\n");
205 DP_INFO(edev, " DPDK version:%s\n", rte_version());
206 DP_INFO(edev, " Chip details : %s %c%d\n",
207 ECORE_IS_BB(edev) ? "BB" : "AH",
208 'A' + edev->chip_rev,
209 (int)edev->chip_metal);
210 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
211 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
212 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
213 ver_str, QEDE_PMD_VERSION);
214 DP_INFO(edev, " Driver version : %s\n", drv_ver);
215 DP_INFO(edev, " Firmware version : %s\n", ver_str);
217 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
219 (info->mfw_rev >> 24) & 0xff,
220 (info->mfw_rev >> 16) & 0xff,
221 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
222 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
223 DP_INFO(edev, " Firmware file : %s\n", fw_file);
224 DP_INFO(edev, "*********************************\n");
227 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
229 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
230 ucast->is_rx_filter = true;
231 ucast->is_tx_filter = true;
232 /* ucast->assert_on_error = true; - For debug */
236 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
239 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
240 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
241 struct qede_ucast_entry *tmp = NULL;
242 struct qede_ucast_entry *u;
243 struct ether_addr *mac_addr;
245 mac_addr = (struct ether_addr *)ucast->mac;
247 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
248 if ((memcmp(mac_addr, &tmp->mac,
249 ETHER_ADDR_LEN) == 0) &&
250 ucast->vlan == tmp->vlan) {
251 DP_ERR(edev, "Unicast MAC is already added"
252 " with vlan = %u, vni = %u\n",
253 ucast->vlan, ucast->vni);
257 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
258 RTE_CACHE_LINE_SIZE);
260 DP_ERR(edev, "Did not allocate memory for ucast\n");
263 ether_addr_copy(mac_addr, &u->mac);
264 u->vlan = ucast->vlan;
265 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
268 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
269 if ((memcmp(mac_addr, &tmp->mac,
270 ETHER_ADDR_LEN) == 0) &&
271 ucast->vlan == tmp->vlan)
275 DP_INFO(edev, "Unicast MAC is not found\n");
278 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
285 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
287 #ifdef RTE_LIBRTE_QEDE_DEBUG_DRIVER
288 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
290 unsigned int i = 0, j = 0, qid;
291 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
292 struct qede_tx_queue *txq;
294 DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
296 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
297 RTE_ETHDEV_QUEUE_STAT_CNTRS);
298 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
299 RTE_ETHDEV_QUEUE_STAT_CNTRS);
301 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
302 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
303 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
304 offsetof(struct qede_rx_queue, rcv_pkts), 0,
306 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
307 offsetof(struct qede_rx_queue, rx_hw_errors), 0,
309 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
310 offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
315 j < RTE_DIM(qede_rxq_xstats_strings); j++)
316 OSAL_MEMSET((((char *)
317 (qdev->fp_array[qid].rxq)) +
318 qede_rxq_xstats_strings[j].offset),
323 if (i == rxq_stat_cntrs)
330 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
331 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
332 txq = qdev->fp_array[(qid)].txqs[0];
334 OSAL_MEMSET((uint64_t *)(uintptr_t)
335 (((uint64_t)(uintptr_t)(txq)) +
336 offsetof(struct qede_tx_queue, xmit_pkts)), 0,
340 if (i == txq_stat_cntrs)
347 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
350 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
351 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
352 struct ether_addr *mac_addr;
353 struct qede_mcast_entry *tmp = NULL;
354 struct qede_mcast_entry *m;
356 mac_addr = (struct ether_addr *)mcast->mac;
358 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
359 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
361 "Multicast MAC is already added\n");
365 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
366 RTE_CACHE_LINE_SIZE);
369 "Did not allocate memory for mcast\n");
372 ether_addr_copy(mac_addr, &m->mac);
373 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
376 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
377 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
381 DP_INFO(edev, "Multicast mac is not found\n");
384 SLIST_REMOVE(&qdev->mc_list_head, tmp,
385 qede_mcast_entry, list);
392 static enum _ecore_status_t
393 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
396 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
397 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
398 enum _ecore_status_t rc;
399 struct ecore_filter_mcast mcast;
400 struct qede_mcast_entry *tmp;
404 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
406 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
408 "Mcast filter table limit exceeded, "
409 "Please enable mcast promisc mode\n");
413 rc = qede_mcast_filter(eth_dev, ucast, add);
415 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
416 memset(&mcast, 0, sizeof(mcast));
417 mcast.num_mc_addrs = qdev->num_mc_addr;
418 mcast.opcode = ECORE_FILTER_ADD;
419 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
420 ether_addr_copy(&tmp->mac,
421 (struct ether_addr *)&mcast.mac[j]);
424 rc = ecore_filter_mcast_cmd(edev, &mcast,
425 ECORE_SPQ_MODE_CB, NULL);
427 if (rc != ECORE_SUCCESS) {
428 DP_ERR(edev, "Failed to add multicast filter"
429 " rc = %d, op = %d\n", rc, add);
431 } else { /* Unicast */
433 if (qdev->num_uc_addr >= qdev->dev_info.num_mac_addrs) {
435 "Ucast filter table limit exceeded,"
436 " Please enable promisc mode\n");
440 rc = qede_ucast_filter(eth_dev, ucast, add);
442 rc = ecore_filter_ucast_cmd(edev, ucast,
443 ECORE_SPQ_MODE_CB, NULL);
444 if (rc != ECORE_SUCCESS) {
445 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
454 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
455 uint32_t index, __rte_unused uint32_t pool)
457 struct ecore_filter_ucast ucast;
459 qede_set_ucast_cmn_params(&ucast);
460 ucast.type = ECORE_FILTER_MAC;
461 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
462 (void)qede_mac_int_ops(eth_dev, &ucast, 1);
466 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
468 struct qede_dev *qdev = eth_dev->data->dev_private;
469 struct ecore_dev *edev = &qdev->edev;
470 struct ether_addr mac_addr;
471 struct ecore_filter_ucast ucast;
474 PMD_INIT_FUNC_TRACE(edev);
476 if (index >= qdev->dev_info.num_mac_addrs) {
477 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
478 index, qdev->dev_info.num_mac_addrs);
482 qede_set_ucast_cmn_params(&ucast);
483 ucast.opcode = ECORE_FILTER_REMOVE;
484 ucast.type = ECORE_FILTER_MAC;
486 /* Use the index maintained by rte */
487 ether_addr_copy(ð_dev->data->mac_addrs[index],
488 (struct ether_addr *)&ucast.mac);
490 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
494 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
496 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
497 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
499 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
500 mac_addr->addr_bytes)) {
501 DP_ERR(edev, "Setting MAC address is not allowed\n");
502 ether_addr_copy(&qdev->primary_mac,
503 ð_dev->data->mac_addrs[0]);
507 qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
510 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
512 struct ecore_dev *edev = &qdev->edev;
513 struct qed_update_vport_params params = {
515 .accept_any_vlan = action,
516 .update_accept_any_vlan_flg = 1,
520 /* Proceed only if action actually needs to be performed */
521 if (qdev->accept_any_vlan == action)
524 rc = qdev->ops->vport_update(edev, ¶ms);
526 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
527 action ? "enable" : "disable");
529 DP_INFO(edev, "%s accept-any-vlan\n",
530 action ? "enabled" : "disabled");
531 qdev->accept_any_vlan = action;
535 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
537 struct qed_update_vport_params vport_update_params;
538 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
539 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
542 memset(&vport_update_params, 0, sizeof(vport_update_params));
543 vport_update_params.vport_id = 0;
544 vport_update_params.update_inner_vlan_removal_flg = 1;
545 vport_update_params.inner_vlan_removal_flg = set_stripping;
546 rc = qdev->ops->vport_update(edev, &vport_update_params);
548 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
555 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
557 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
558 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
559 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
561 if (mask & ETH_VLAN_STRIP_MASK) {
562 if (rxmode->hw_vlan_strip)
563 (void)qede_vlan_stripping(eth_dev, 1);
565 (void)qede_vlan_stripping(eth_dev, 0);
568 if (mask & ETH_VLAN_FILTER_MASK) {
569 /* VLAN filtering kicks in when a VLAN is added */
570 if (rxmode->hw_vlan_filter) {
571 qede_vlan_filter_set(eth_dev, 0, 1);
573 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
574 DP_NOTICE(edev, false,
575 " Please remove existing VLAN filters"
576 " before disabling VLAN filtering\n");
577 /* Signal app that VLAN filtering is still
580 rxmode->hw_vlan_filter = true;
582 qede_vlan_filter_set(eth_dev, 0, 0);
587 if (mask & ETH_VLAN_EXTEND_MASK)
588 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
589 " and classification is based on outer tag only\n");
591 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
592 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
595 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
596 uint16_t vlan_id, int on)
598 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
599 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
600 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
601 struct qede_vlan_entry *tmp = NULL;
602 struct qede_vlan_entry *vlan;
603 struct ecore_filter_ucast ucast;
607 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
608 DP_INFO(edev, "Reached max VLAN filter limit"
609 " enabling accept_any_vlan\n");
610 qede_config_accept_any_vlan(qdev, true);
614 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
615 if (tmp->vid == vlan_id) {
616 DP_ERR(edev, "VLAN %u already configured\n",
622 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
623 RTE_CACHE_LINE_SIZE);
626 DP_ERR(edev, "Did not allocate memory for VLAN\n");
630 qede_set_ucast_cmn_params(&ucast);
631 ucast.opcode = ECORE_FILTER_ADD;
632 ucast.type = ECORE_FILTER_VLAN;
633 ucast.vlan = vlan_id;
634 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
637 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
642 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
643 qdev->configured_vlans++;
644 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
645 vlan_id, qdev->configured_vlans);
648 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
649 if (tmp->vid == vlan_id)
654 if (qdev->configured_vlans == 0) {
656 "No VLAN filters configured yet\n");
660 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
664 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
666 qede_set_ucast_cmn_params(&ucast);
667 ucast.opcode = ECORE_FILTER_REMOVE;
668 ucast.type = ECORE_FILTER_VLAN;
669 ucast.vlan = vlan_id;
670 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
673 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
676 qdev->configured_vlans--;
677 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
678 vlan_id, qdev->configured_vlans);
685 static int qede_init_vport(struct qede_dev *qdev)
687 struct ecore_dev *edev = &qdev->edev;
688 struct qed_start_vport_params start = {0};
691 start.remove_inner_vlan = 1;
692 start.gro_enable = 0;
693 start.mtu = qdev->mtu;
695 start.drop_ttl0 = false;
696 start.clear_stats = 1;
697 start.handle_ptp_pkts = 0;
699 rc = qdev->ops->vport_start(edev, &start);
701 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
706 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
707 start.vport_id, ETHER_MTU);
712 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
714 struct qede_dev *qdev = eth_dev->data->dev_private;
715 struct ecore_dev *edev = &qdev->edev;
716 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
719 PMD_INIT_FUNC_TRACE(edev);
721 /* Check requirements for 100G mode */
722 if (edev->num_hwfns > 1) {
723 if (eth_dev->data->nb_rx_queues < 2 ||
724 eth_dev->data->nb_tx_queues < 2) {
725 DP_NOTICE(edev, false,
726 "100G mode needs min. 2 RX/TX queues\n");
730 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
731 (eth_dev->data->nb_tx_queues % 2 != 0)) {
732 DP_NOTICE(edev, false,
733 "100G mode needs even no. of RX/TX queues\n");
738 /* We need to have min 1 RX queue.There is no min check in
739 * rte_eth_dev_configure(), so we are checking it here.
741 if (eth_dev->data->nb_rx_queues == 0) {
742 DP_ERR(edev, "Minimum one RX queue is required\n");
746 /* Sanity checks and throw warnings */
747 if (rxmode->enable_scatter == 1)
748 eth_dev->data->scattered_rx = 1;
750 if (rxmode->enable_lro == 1) {
751 DP_INFO(edev, "LRO is not supported\n");
755 if (!rxmode->hw_strip_crc)
756 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
758 if (!rxmode->hw_ip_checksum)
759 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
762 /* Check for the port restart case */
763 if (qdev->state != QEDE_DEV_INIT) {
764 rc = qdev->ops->vport_stop(edev, 0);
767 qede_dealloc_fp_resc(eth_dev);
770 qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
771 qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
772 qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
774 /* Fastpath status block should be initialized before sending
775 * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
777 rc = qede_alloc_fp_resc(qdev);
781 /* If jumbo enabled adjust MTU */
782 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
784 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
785 ETHER_HDR_LEN - ETHER_CRC_LEN;
787 qdev->mtu = eth_dev->data->mtu;
789 /* Issue VPORT-START with default config values to allow
790 * other port configurations early on.
792 rc = qede_init_vport(qdev);
796 SLIST_INIT(&qdev->vlan_list_head);
798 /* Enable VLAN offloads by default */
799 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
800 ETH_VLAN_FILTER_MASK |
801 ETH_VLAN_EXTEND_MASK);
803 qdev->state = QEDE_DEV_CONFIG;
805 DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
806 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
812 /* Info about HW descriptor ring limitations */
813 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
814 .nb_max = NUM_RX_BDS_MAX,
816 .nb_align = 128 /* lowest common multiple */
819 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
820 .nb_max = NUM_TX_BDS_MAX,
826 qede_dev_info_get(struct rte_eth_dev *eth_dev,
827 struct rte_eth_dev_info *dev_info)
829 struct qede_dev *qdev = eth_dev->data->dev_private;
830 struct ecore_dev *edev = &qdev->edev;
831 struct qed_link_output link;
832 uint32_t speed_cap = 0;
834 PMD_INIT_FUNC_TRACE(edev);
836 dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
837 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
838 dev_info->rx_desc_lim = qede_rx_desc_lim;
839 dev_info->tx_desc_lim = qede_tx_desc_lim;
840 dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev);
841 dev_info->max_tx_queues = dev_info->max_rx_queues;
842 dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs;
844 dev_info->max_vfs = 0;
846 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev);
847 dev_info->driver_name = qdev->drv_ver;
848 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
849 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
851 dev_info->default_txconf = (struct rte_eth_txconf) {
852 .txq_flags = QEDE_TXQ_FLAGS,
855 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
856 DEV_RX_OFFLOAD_IPV4_CKSUM |
857 DEV_RX_OFFLOAD_UDP_CKSUM |
858 DEV_RX_OFFLOAD_TCP_CKSUM);
859 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
860 DEV_TX_OFFLOAD_IPV4_CKSUM |
861 DEV_TX_OFFLOAD_UDP_CKSUM |
862 DEV_TX_OFFLOAD_TCP_CKSUM);
864 memset(&link, 0, sizeof(struct qed_link_output));
865 qdev->ops->common->get_link(edev, &link);
866 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
867 speed_cap |= ETH_LINK_SPEED_1G;
868 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
869 speed_cap |= ETH_LINK_SPEED_10G;
870 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
871 speed_cap |= ETH_LINK_SPEED_25G;
872 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
873 speed_cap |= ETH_LINK_SPEED_40G;
874 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
875 speed_cap |= ETH_LINK_SPEED_50G;
876 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
877 speed_cap |= ETH_LINK_SPEED_100G;
878 dev_info->speed_capa = speed_cap;
881 /* return 0 means link status changed, -1 means not changed */
883 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
885 struct qede_dev *qdev = eth_dev->data->dev_private;
886 struct ecore_dev *edev = &qdev->edev;
887 uint16_t link_duplex;
888 struct qed_link_output link;
889 struct rte_eth_link *curr = ð_dev->data->dev_link;
891 memset(&link, 0, sizeof(struct qed_link_output));
892 qdev->ops->common->get_link(edev, &link);
895 curr->link_speed = link.speed;
898 switch (link.duplex) {
899 case QEDE_DUPLEX_HALF:
900 link_duplex = ETH_LINK_HALF_DUPLEX;
902 case QEDE_DUPLEX_FULL:
903 link_duplex = ETH_LINK_FULL_DUPLEX;
905 case QEDE_DUPLEX_UNKNOWN:
909 curr->link_duplex = link_duplex;
912 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
915 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
916 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
918 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
919 curr->link_speed, curr->link_duplex,
920 curr->link_autoneg, curr->link_status);
922 /* return 0 means link status changed, -1 means not changed */
923 return ((curr->link_status == link.link_up) ? -1 : 0);
926 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
928 struct qede_dev *qdev = eth_dev->data->dev_private;
929 struct ecore_dev *edev = &qdev->edev;
931 PMD_INIT_FUNC_TRACE(edev);
933 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
935 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
936 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
938 qed_configure_filter_rx_mode(eth_dev, type);
941 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
943 struct qede_dev *qdev = eth_dev->data->dev_private;
944 struct ecore_dev *edev = &qdev->edev;
946 PMD_INIT_FUNC_TRACE(edev);
948 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
949 qed_configure_filter_rx_mode(eth_dev,
950 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
952 qed_configure_filter_rx_mode(eth_dev,
953 QED_FILTER_RX_MODE_TYPE_REGULAR);
956 static void qede_poll_sp_sb_cb(void *param)
958 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
959 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
960 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
963 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
964 qede_interrupt_action(&edev->hwfns[1]);
966 rc = rte_eal_alarm_set(timer_period * US_PER_S,
970 DP_ERR(edev, "Unable to start periodic"
971 " timer rc %d\n", rc);
972 assert(false && "Unable to start periodic timer");
976 static void qede_dev_close(struct rte_eth_dev *eth_dev)
978 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
979 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
982 PMD_INIT_FUNC_TRACE(edev);
984 /* dev_stop() shall cleanup fp resources in hw but without releasing
985 * dma memories and sw structures so that dev_start() can be called
986 * by the app without reconfiguration. However, in dev_close() we
987 * can release all the resources and device can be brought up newly
989 if (qdev->state != QEDE_DEV_STOP)
990 qede_dev_stop(eth_dev);
992 DP_INFO(edev, "Device is already stopped\n");
994 rc = qdev->ops->vport_stop(edev, 0);
996 DP_ERR(edev, "Failed to stop VPORT\n");
998 qede_dealloc_fp_resc(eth_dev);
1000 qdev->ops->common->slowpath_stop(edev);
1002 qdev->ops->common->remove(edev);
1004 rte_intr_disable(ð_dev->pci_dev->intr_handle);
1006 rte_intr_callback_unregister(ð_dev->pci_dev->intr_handle,
1007 qede_interrupt_handler, (void *)eth_dev);
1009 if (edev->num_hwfns > 1)
1010 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1012 qdev->state = QEDE_DEV_INIT; /* Go back to init state */
1016 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1018 struct qede_dev *qdev = eth_dev->data->dev_private;
1019 struct ecore_dev *edev = &qdev->edev;
1020 struct ecore_eth_stats stats;
1021 unsigned int i = 0, j = 0, qid;
1022 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1023 struct qede_tx_queue *txq;
1025 qdev->ops->get_vport_stats(edev, &stats);
1028 eth_stats->ipackets = stats.rx_ucast_pkts +
1029 stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1031 eth_stats->ibytes = stats.rx_ucast_bytes +
1032 stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1034 eth_stats->ierrors = stats.rx_crc_errors +
1035 stats.rx_align_errors +
1036 stats.rx_carrier_errors +
1037 stats.rx_oversize_packets +
1038 stats.rx_jabbers + stats.rx_undersize_packets;
1040 eth_stats->rx_nombuf = stats.no_buff_discards;
1042 eth_stats->imissed = stats.mftag_filter_discards +
1043 stats.mac_filter_discards +
1044 stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1047 eth_stats->opackets = stats.tx_ucast_pkts +
1048 stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1050 eth_stats->obytes = stats.tx_ucast_bytes +
1051 stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1053 eth_stats->oerrors = stats.tx_err_drop_pkts;
1056 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1057 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1058 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1059 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1060 if ((rxq_stat_cntrs != QEDE_RSS_COUNT(qdev)) ||
1061 (txq_stat_cntrs != QEDE_TSS_COUNT(qdev)))
1062 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1063 "Not all the queue stats will be displayed. Set"
1064 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1065 " appropriately and retry.\n");
1067 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1068 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1069 eth_stats->q_ipackets[i] =
1071 ((char *)(qdev->fp_array[(qid)].rxq)) +
1072 offsetof(struct qede_rx_queue,
1074 eth_stats->q_errors[i] =
1076 ((char *)(qdev->fp_array[(qid)].rxq)) +
1077 offsetof(struct qede_rx_queue,
1080 ((char *)(qdev->fp_array[(qid)].rxq)) +
1081 offsetof(struct qede_rx_queue,
1085 if (i == rxq_stat_cntrs)
1089 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1090 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1091 txq = qdev->fp_array[(qid)].txqs[0];
1092 eth_stats->q_opackets[j] =
1093 *((uint64_t *)(uintptr_t)
1094 (((uint64_t)(uintptr_t)(txq)) +
1095 offsetof(struct qede_tx_queue,
1099 if (j == txq_stat_cntrs)
1105 qede_get_xstats_count(struct qede_dev *qdev) {
1106 return RTE_DIM(qede_xstats_strings) +
1107 (RTE_DIM(qede_rxq_xstats_strings) *
1108 RTE_MIN(QEDE_RSS_COUNT(qdev),
1109 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1113 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1114 struct rte_eth_xstat_name *xstats_names, unsigned limit)
1116 struct qede_dev *qdev = dev->data->dev_private;
1117 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1118 unsigned int i, qid, stat_idx = 0;
1119 unsigned int rxq_stat_cntrs;
1121 if (xstats_names != NULL) {
1122 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1123 snprintf(xstats_names[stat_idx].name,
1124 sizeof(xstats_names[stat_idx].name),
1126 qede_xstats_strings[i].name);
1130 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1131 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1132 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1133 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1134 snprintf(xstats_names[stat_idx].name,
1135 sizeof(xstats_names[stat_idx].name),
1137 qede_rxq_xstats_strings[i].name, qid,
1138 qede_rxq_xstats_strings[i].name + 4);
1148 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1151 struct qede_dev *qdev = dev->data->dev_private;
1152 struct ecore_dev *edev = &qdev->edev;
1153 struct ecore_eth_stats stats;
1154 const unsigned int num = qede_get_xstats_count(qdev);
1155 unsigned int i, qid, stat_idx = 0;
1156 unsigned int rxq_stat_cntrs;
1161 qdev->ops->get_vport_stats(edev, &stats);
1163 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1164 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1165 qede_xstats_strings[i].offset);
1166 xstats[stat_idx].id = stat_idx;
1170 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1171 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1172 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1173 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1174 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1175 xstats[stat_idx].value = *(uint64_t *)(
1176 ((char *)(qdev->fp_array[(qid)].rxq)) +
1177 qede_rxq_xstats_strings[i].offset);
1178 xstats[stat_idx].id = stat_idx;
1188 qede_reset_xstats(struct rte_eth_dev *dev)
1190 struct qede_dev *qdev = dev->data->dev_private;
1191 struct ecore_dev *edev = &qdev->edev;
1193 ecore_reset_vport_stats(edev);
1194 qede_reset_queue_stats(qdev, true);
1197 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1199 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1200 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1201 struct qed_link_params link_params;
1204 DP_INFO(edev, "setting link state %d\n", link_up);
1205 memset(&link_params, 0, sizeof(link_params));
1206 link_params.link_up = link_up;
1207 rc = qdev->ops->common->set_link(edev, &link_params);
1208 if (rc != ECORE_SUCCESS)
1209 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1214 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1216 return qede_dev_set_link_state(eth_dev, true);
1219 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1221 return qede_dev_set_link_state(eth_dev, false);
1224 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1226 struct qede_dev *qdev = eth_dev->data->dev_private;
1227 struct ecore_dev *edev = &qdev->edev;
1229 ecore_reset_vport_stats(edev);
1230 qede_reset_queue_stats(qdev, false);
1233 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1235 enum qed_filter_rx_mode_type type =
1236 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1238 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1239 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1241 qed_configure_filter_rx_mode(eth_dev, type);
1244 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1246 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1247 qed_configure_filter_rx_mode(eth_dev,
1248 QED_FILTER_RX_MODE_TYPE_PROMISC);
1250 qed_configure_filter_rx_mode(eth_dev,
1251 QED_FILTER_RX_MODE_TYPE_REGULAR);
1254 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1255 struct rte_eth_fc_conf *fc_conf)
1257 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1258 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1259 struct qed_link_output current_link;
1260 struct qed_link_params params;
1262 memset(¤t_link, 0, sizeof(current_link));
1263 qdev->ops->common->get_link(edev, ¤t_link);
1265 memset(¶ms, 0, sizeof(params));
1266 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1267 if (fc_conf->autoneg) {
1268 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1269 DP_ERR(edev, "Autoneg not supported\n");
1272 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1275 /* Pause is assumed to be supported (SUPPORTED_Pause) */
1276 if (fc_conf->mode == RTE_FC_FULL)
1277 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1278 QED_LINK_PAUSE_RX_ENABLE);
1279 if (fc_conf->mode == RTE_FC_TX_PAUSE)
1280 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1281 if (fc_conf->mode == RTE_FC_RX_PAUSE)
1282 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1284 params.link_up = true;
1285 (void)qdev->ops->common->set_link(edev, ¶ms);
1290 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1291 struct rte_eth_fc_conf *fc_conf)
1293 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1294 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1295 struct qed_link_output current_link;
1297 memset(¤t_link, 0, sizeof(current_link));
1298 qdev->ops->common->get_link(edev, ¤t_link);
1300 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1301 fc_conf->autoneg = true;
1303 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1304 QED_LINK_PAUSE_TX_ENABLE))
1305 fc_conf->mode = RTE_FC_FULL;
1306 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1307 fc_conf->mode = RTE_FC_RX_PAUSE;
1308 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1309 fc_conf->mode = RTE_FC_TX_PAUSE;
1311 fc_conf->mode = RTE_FC_NONE;
1316 static const uint32_t *
1317 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1319 static const uint32_t ptypes[] = {
1325 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1331 void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1334 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
1335 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
1336 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
1337 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
1338 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
1339 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
1340 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
1341 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
1344 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1345 struct rte_eth_rss_conf *rss_conf)
1347 struct qed_update_vport_params vport_update_params;
1348 struct qede_dev *qdev = eth_dev->data->dev_private;
1349 struct ecore_dev *edev = &qdev->edev;
1350 uint32_t *key = (uint32_t *)rss_conf->rss_key;
1351 uint64_t hf = rss_conf->rss_hf;
1354 memset(&vport_update_params, 0, sizeof(vport_update_params));
1358 qede_init_rss_caps(&qdev->rss_params.rss_caps, hf);
1359 memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1360 sizeof(vport_update_params.rss_params));
1362 memcpy(qdev->rss_params.rss_key, rss_conf->rss_key,
1363 rss_conf->rss_key_len);
1364 vport_update_params.update_rss_flg = 1;
1365 qdev->rss_enabled = 1;
1368 qdev->rss_enabled = 0;
1371 /* If the mapping doesn't fit any supported, return */
1372 if (qdev->rss_params.rss_caps == 0 && hf != 0)
1375 DP_INFO(edev, "%s\n", (vport_update_params.update_rss_flg) ?
1376 "Enabling RSS" : "Disabling RSS");
1378 vport_update_params.vport_id = 0;
1380 return qdev->ops->vport_update(edev, &vport_update_params);
1383 int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1384 struct rte_eth_rss_conf *rss_conf)
1386 struct qede_dev *qdev = eth_dev->data->dev_private;
1389 if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key))
1392 if (rss_conf->rss_key)
1393 memcpy(rss_conf->rss_key, qdev->rss_params.rss_key,
1394 sizeof(qdev->rss_params.rss_key));
1397 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4) ?
1399 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6) ?
1401 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6) ?
1402 ETH_RSS_IPV6_EX : 0;
1403 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ?
1404 ETH_RSS_NONFRAG_IPV4_TCP : 0;
1405 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1406 ETH_RSS_NONFRAG_IPV6_TCP : 0;
1407 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1408 ETH_RSS_IPV6_TCP_EX : 0;
1410 rss_conf->rss_hf = hf;
1415 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1416 struct rte_eth_rss_reta_entry64 *reta_conf,
1419 struct qed_update_vport_params vport_update_params;
1420 struct qede_dev *qdev = eth_dev->data->dev_private;
1421 struct ecore_dev *edev = &qdev->edev;
1422 uint16_t i, idx, shift;
1424 if (reta_size > ETH_RSS_RETA_SIZE_128) {
1425 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1430 memset(&vport_update_params, 0, sizeof(vport_update_params));
1431 memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1432 sizeof(vport_update_params.rss_params));
1434 for (i = 0; i < reta_size; i++) {
1435 idx = i / RTE_RETA_GROUP_SIZE;
1436 shift = i % RTE_RETA_GROUP_SIZE;
1437 if (reta_conf[idx].mask & (1ULL << shift)) {
1438 uint8_t entry = reta_conf[idx].reta[shift];
1439 qdev->rss_params.rss_ind_table[i] = entry;
1443 vport_update_params.update_rss_flg = 1;
1444 vport_update_params.vport_id = 0;
1446 return qdev->ops->vport_update(edev, &vport_update_params);
1449 int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1450 struct rte_eth_rss_reta_entry64 *reta_conf,
1453 struct qede_dev *qdev = eth_dev->data->dev_private;
1454 uint16_t i, idx, shift;
1456 if (reta_size > ETH_RSS_RETA_SIZE_128) {
1457 struct ecore_dev *edev = &qdev->edev;
1458 DP_ERR(edev, "reta_size %d is not supported\n",
1462 for (i = 0; i < reta_size; i++) {
1463 idx = i / RTE_RETA_GROUP_SIZE;
1464 shift = i % RTE_RETA_GROUP_SIZE;
1465 if (reta_conf[idx].mask & (1ULL << shift)) {
1466 uint8_t entry = qdev->rss_params.rss_ind_table[i];
1467 reta_conf[idx].reta[shift] = entry;
1474 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1476 struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
1477 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1478 struct rte_eth_dev_info dev_info = {0};
1479 struct qede_fastpath *fp;
1480 uint32_t max_rx_pkt_len;
1481 uint32_t frame_size;
1482 uint16_t rx_buf_size;
1484 bool restart = false;
1487 PMD_INIT_FUNC_TRACE(edev);
1490 qede_dev_info_get(dev, &dev_info);
1491 max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1492 frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
1493 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
1494 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
1495 mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
1496 ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
1499 if (!dev->data->scattered_rx &&
1500 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
1501 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
1502 dev->data->min_rx_buf_size);
1505 /* Temporarily replace I/O functions with dummy ones. It cannot
1506 * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1508 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
1509 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
1510 if (dev->data->dev_started) {
1511 dev->data->dev_started = 0;
1517 /* Fix up RX buf size for all queues of the port */
1519 fp = &qdev->fp_array[i];
1520 if ((fp->type & QEDE_FASTPATH_RX) && (fp->rxq != NULL)) {
1521 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
1522 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
1523 if (dev->data->scattered_rx)
1524 rx_buf_size = bufsz + ETHER_HDR_LEN +
1525 ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
1527 rx_buf_size = frame_size;
1528 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
1529 fp->rxq->rx_buf_size = rx_buf_size;
1530 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
1533 if (max_rx_pkt_len > ETHER_MAX_LEN)
1534 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1536 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1537 if (!dev->data->dev_started && restart) {
1538 qede_dev_start(dev);
1539 dev->data->dev_started = 1;
1541 /* update max frame size */
1542 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
1544 dev->rx_pkt_burst = qede_recv_pkts;
1545 dev->tx_pkt_burst = qede_xmit_pkts;
1550 static const struct eth_dev_ops qede_eth_dev_ops = {
1551 .dev_configure = qede_dev_configure,
1552 .dev_infos_get = qede_dev_info_get,
1553 .rx_queue_setup = qede_rx_queue_setup,
1554 .rx_queue_release = qede_rx_queue_release,
1555 .tx_queue_setup = qede_tx_queue_setup,
1556 .tx_queue_release = qede_tx_queue_release,
1557 .dev_start = qede_dev_start,
1558 .dev_set_link_up = qede_dev_set_link_up,
1559 .dev_set_link_down = qede_dev_set_link_down,
1560 .link_update = qede_link_update,
1561 .promiscuous_enable = qede_promiscuous_enable,
1562 .promiscuous_disable = qede_promiscuous_disable,
1563 .allmulticast_enable = qede_allmulticast_enable,
1564 .allmulticast_disable = qede_allmulticast_disable,
1565 .dev_stop = qede_dev_stop,
1566 .dev_close = qede_dev_close,
1567 .stats_get = qede_get_stats,
1568 .stats_reset = qede_reset_stats,
1569 .xstats_get = qede_get_xstats,
1570 .xstats_reset = qede_reset_xstats,
1571 .xstats_get_names = qede_get_xstats_names,
1572 .mac_addr_add = qede_mac_addr_add,
1573 .mac_addr_remove = qede_mac_addr_remove,
1574 .mac_addr_set = qede_mac_addr_set,
1575 .vlan_offload_set = qede_vlan_offload_set,
1576 .vlan_filter_set = qede_vlan_filter_set,
1577 .flow_ctrl_set = qede_flow_ctrl_set,
1578 .flow_ctrl_get = qede_flow_ctrl_get,
1579 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1580 .rss_hash_update = qede_rss_hash_update,
1581 .rss_hash_conf_get = qede_rss_hash_conf_get,
1582 .reta_update = qede_rss_reta_update,
1583 .reta_query = qede_rss_reta_query,
1584 .mtu_set = qede_set_mtu,
1587 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
1588 .dev_configure = qede_dev_configure,
1589 .dev_infos_get = qede_dev_info_get,
1590 .rx_queue_setup = qede_rx_queue_setup,
1591 .rx_queue_release = qede_rx_queue_release,
1592 .tx_queue_setup = qede_tx_queue_setup,
1593 .tx_queue_release = qede_tx_queue_release,
1594 .dev_start = qede_dev_start,
1595 .dev_set_link_up = qede_dev_set_link_up,
1596 .dev_set_link_down = qede_dev_set_link_down,
1597 .link_update = qede_link_update,
1598 .promiscuous_enable = qede_promiscuous_enable,
1599 .promiscuous_disable = qede_promiscuous_disable,
1600 .allmulticast_enable = qede_allmulticast_enable,
1601 .allmulticast_disable = qede_allmulticast_disable,
1602 .dev_stop = qede_dev_stop,
1603 .dev_close = qede_dev_close,
1604 .stats_get = qede_get_stats,
1605 .stats_reset = qede_reset_stats,
1606 .xstats_get = qede_get_xstats,
1607 .xstats_reset = qede_reset_xstats,
1608 .xstats_get_names = qede_get_xstats_names,
1609 .vlan_offload_set = qede_vlan_offload_set,
1610 .vlan_filter_set = qede_vlan_filter_set,
1611 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1612 .rss_hash_update = qede_rss_hash_update,
1613 .rss_hash_conf_get = qede_rss_hash_conf_get,
1614 .reta_update = qede_rss_reta_update,
1615 .reta_query = qede_rss_reta_query,
1616 .mtu_set = qede_set_mtu,
1619 static void qede_update_pf_params(struct ecore_dev *edev)
1621 struct ecore_pf_params pf_params;
1623 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
1624 pf_params.eth_pf_params.num_cons = 64;
1625 qed_ops->common->update_pf_params(edev, &pf_params);
1628 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
1630 struct rte_pci_device *pci_dev;
1631 struct rte_pci_addr pci_addr;
1632 struct qede_dev *adapter;
1633 struct ecore_dev *edev;
1634 struct qed_dev_eth_info dev_info;
1635 struct qed_slowpath_params params;
1636 static bool do_once = true;
1637 uint8_t bulletin_change;
1638 uint8_t vf_mac[ETHER_ADDR_LEN];
1639 uint8_t is_mac_forced;
1641 /* Fix up ecore debug level */
1642 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
1643 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
1644 uint32_t max_mac_addrs;
1647 /* Extract key data structures */
1648 adapter = eth_dev->data->dev_private;
1649 edev = &adapter->edev;
1650 pci_addr = eth_dev->pci_dev->addr;
1652 PMD_INIT_FUNC_TRACE(edev);
1654 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
1655 pci_addr.bus, pci_addr.devid, pci_addr.function,
1656 eth_dev->data->port_id);
1658 eth_dev->rx_pkt_burst = qede_recv_pkts;
1659 eth_dev->tx_pkt_burst = qede_xmit_pkts;
1661 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1662 DP_NOTICE(edev, false,
1663 "Skipping device init from secondary process\n");
1667 pci_dev = eth_dev->pci_dev;
1669 rte_eth_copy_pci_info(eth_dev, pci_dev);
1672 edev->vendor_id = pci_dev->id.vendor_id;
1673 edev->device_id = pci_dev->id.device_id;
1675 qed_ops = qed_get_eth_ops();
1677 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
1681 DP_INFO(edev, "Starting qede probe\n");
1683 rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
1684 dp_module, dp_level, is_vf);
1687 DP_ERR(edev, "qede probe failed rc %d\n", rc);
1691 qede_update_pf_params(edev);
1693 rte_intr_callback_register(ð_dev->pci_dev->intr_handle,
1694 qede_interrupt_handler, (void *)eth_dev);
1696 if (rte_intr_enable(ð_dev->pci_dev->intr_handle)) {
1697 DP_ERR(edev, "rte_intr_enable() failed\n");
1701 /* Start the Slowpath-process */
1702 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
1703 params.int_mode = ECORE_INT_MODE_MSIX;
1704 params.drv_major = QEDE_PMD_VERSION_MAJOR;
1705 params.drv_minor = QEDE_PMD_VERSION_MINOR;
1706 params.drv_rev = QEDE_PMD_VERSION_REVISION;
1707 params.drv_eng = QEDE_PMD_VERSION_PATCH;
1708 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
1709 QEDE_PMD_DRV_VER_STR_SIZE);
1711 /* For CMT mode device do periodic polling for slowpath events.
1712 * This is required since uio device uses only one MSI-x
1713 * interrupt vector but we need one for each engine.
1715 if (edev->num_hwfns > 1 && IS_PF(edev)) {
1716 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1720 DP_ERR(edev, "Unable to start periodic"
1721 " timer rc %d\n", rc);
1726 rc = qed_ops->common->slowpath_start(edev, ¶ms);
1728 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
1729 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1734 rc = qed_ops->fill_dev_info(edev, &dev_info);
1736 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
1737 qed_ops->common->slowpath_stop(edev);
1738 qed_ops->common->remove(edev);
1739 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1744 qede_alloc_etherdev(adapter, &dev_info);
1746 adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION);
1749 adapter->dev_info.num_mac_addrs =
1750 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
1753 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
1754 &adapter->dev_info.num_mac_addrs);
1756 /* Allocate memory for storing MAC addr */
1757 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
1759 adapter->dev_info.num_mac_addrs),
1760 RTE_CACHE_LINE_SIZE);
1762 if (eth_dev->data->mac_addrs == NULL) {
1763 DP_ERR(edev, "Failed to allocate MAC address\n");
1764 qed_ops->common->slowpath_stop(edev);
1765 qed_ops->common->remove(edev);
1766 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1772 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
1773 hw_info.hw_mac_addr,
1774 ð_dev->data->mac_addrs[0]);
1775 ether_addr_copy(ð_dev->data->mac_addrs[0],
1776 &adapter->primary_mac);
1778 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
1780 if (bulletin_change) {
1782 ecore_vf_bulletin_get_forced_mac(
1783 ECORE_LEADING_HWFN(edev),
1786 if (is_mac_exist && is_mac_forced) {
1787 DP_INFO(edev, "VF macaddr received from PF\n");
1788 ether_addr_copy((struct ether_addr *)&vf_mac,
1789 ð_dev->data->mac_addrs[0]);
1790 ether_addr_copy(ð_dev->data->mac_addrs[0],
1791 &adapter->primary_mac);
1793 DP_NOTICE(edev, false,
1794 "No VF macaddr assigned\n");
1799 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
1802 qede_print_adapter_info(adapter);
1806 adapter->state = QEDE_DEV_INIT;
1808 DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
1809 adapter->primary_mac.addr_bytes[0],
1810 adapter->primary_mac.addr_bytes[1],
1811 adapter->primary_mac.addr_bytes[2],
1812 adapter->primary_mac.addr_bytes[3],
1813 adapter->primary_mac.addr_bytes[4],
1814 adapter->primary_mac.addr_bytes[5]);
1819 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
1821 return qede_common_dev_init(eth_dev, 1);
1824 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
1826 return qede_common_dev_init(eth_dev, 0);
1829 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
1831 /* only uninitialize in the primary process */
1832 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1835 /* safe to close dev here */
1836 qede_dev_close(eth_dev);
1838 eth_dev->dev_ops = NULL;
1839 eth_dev->rx_pkt_burst = NULL;
1840 eth_dev->tx_pkt_burst = NULL;
1842 if (eth_dev->data->mac_addrs)
1843 rte_free(eth_dev->data->mac_addrs);
1845 eth_dev->data->mac_addrs = NULL;
1850 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1852 return qede_dev_common_uninit(eth_dev);
1855 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1857 return qede_dev_common_uninit(eth_dev);
1860 static struct rte_pci_id pci_id_qedevf_map[] = {
1861 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1863 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF)
1866 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV)
1871 static struct rte_pci_id pci_id_qede_map[] = {
1872 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1874 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E)
1877 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S)
1880 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40)
1883 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25)
1886 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100)
1891 static struct eth_driver rte_qedevf_pmd = {
1893 .id_table = pci_id_qedevf_map,
1895 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1896 .probe = rte_eth_dev_pci_probe,
1897 .remove = rte_eth_dev_pci_remove,
1899 .eth_dev_init = qedevf_eth_dev_init,
1900 .eth_dev_uninit = qedevf_eth_dev_uninit,
1901 .dev_private_size = sizeof(struct qede_dev),
1904 static struct eth_driver rte_qede_pmd = {
1906 .id_table = pci_id_qede_map,
1908 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1909 .probe = rte_eth_dev_pci_probe,
1910 .remove = rte_eth_dev_pci_remove,
1912 .eth_dev_init = qede_eth_dev_init,
1913 .eth_dev_uninit = qede_eth_dev_uninit,
1914 .dev_private_size = sizeof(struct qede_dev),
1917 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv);
1918 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
1919 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv);
1920 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);