drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static const char *drivername = "qede pmd";
  16 static int64_t timer_period = 1;
  17
  18 struct rte_qede_xstats_name_off {
  19         char name[RTE_ETH_XSTATS_NAME_SIZE];
  20         uint64_t offset;
  21 };
  22
  23 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  24         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
  25         {"rx_multicast_bytes",
  26                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
  27         {"rx_broadcast_bytes",
  28                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
  29         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
  30         {"rx_multicast_packets",
  31                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
  32         {"rx_broadcast_packets",
  33                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
  34
  35         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
  36         {"tx_multicast_bytes",
  37                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
  38         {"tx_broadcast_bytes",
  39                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
  40         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
  41         {"tx_multicast_packets",
  42                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
  43         {"tx_broadcast_packets",
  44                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
  45
  46         {"rx_64_byte_packets",
  47                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
  48         {"rx_65_to_127_byte_packets",
  49                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
  50         {"rx_128_to_255_byte_packets",
  51                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
  52         {"rx_256_to_511_byte_packets",
  53                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
  54         {"rx_512_to_1023_byte_packets",
  55                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
  56         {"rx_1024_to_1518_byte_packets",
  57                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
  58         {"rx_1519_to_1522_byte_packets",
  59                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
  60         {"rx_1519_to_2047_byte_packets",
  61                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
  62         {"rx_2048_to_4095_byte_packets",
  63                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
  64         {"rx_4096_to_9216_byte_packets",
  65                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
  66         {"rx_9217_to_16383_byte_packets",
  67                 offsetof(struct ecore_eth_stats,
  68                          rx_9217_to_16383_byte_packets)},
  69         {"tx_64_byte_packets",
  70                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
  71         {"tx_65_to_127_byte_packets",
  72                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
  73         {"tx_128_to_255_byte_packets",
  74                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
  75         {"tx_256_to_511_byte_packets",
  76                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
  77         {"tx_512_to_1023_byte_packets",
  78                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
  79         {"tx_1024_to_1518_byte_packets",
  80                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
  81         {"trx_1519_to_1522_byte_packets",
  82                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
  83         {"tx_2048_to_4095_byte_packets",
  84                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
  85         {"tx_4096_to_9216_byte_packets",
  86                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
  87         {"tx_9217_to_16383_byte_packets",
  88                 offsetof(struct ecore_eth_stats,
  89                          tx_9217_to_16383_byte_packets)},
  90
  91         {"rx_mac_crtl_frames",
  92                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
  93         {"tx_mac_control_frames",
  94                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
  95         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
  96         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
  97         {"rx_priority_flow_control_frames",
  98                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
  99         {"tx_priority_flow_control_frames",
 100                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 101
 102         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 103         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 104         {"rx_carrier_errors",
 105                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 106         {"rx_oversize_packet_errors",
 107                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 108         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 109         {"rx_undersize_packet_errors",
 110                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 111         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 112         {"rx_host_buffer_not_available",
 113                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 114         /* Number of packets discarded because they are bigger than MTU */
 115         {"rx_packet_too_big_discards",
 116                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 117         {"rx_ttl_zero_discards",
 118                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 119         {"rx_multi_function_tag_filter_discards",
 120                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 121         {"rx_mac_filter_discards",
 122                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 123         {"rx_hw_buffer_truncates",
 124                 offsetof(struct ecore_eth_stats, brb_truncates)},
 125         {"rx_hw_buffer_discards",
 126                 offsetof(struct ecore_eth_stats, brb_discards)},
 127         {"tx_lpi_entry_count",
 128                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 129         {"tx_total_collisions",
 130                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 131         {"tx_error_drop_packets",
 132                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 133
 134         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 135         {"rx_mac_unicast_packets",
 136                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 137         {"rx_mac_multicast_packets",
 138                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 139         {"rx_mac_broadcast_packets",
 140                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 141         {"rx_mac_frames_ok",
 142                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 143         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 144         {"tx_mac_unicast_packets",
 145                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 146         {"tx_mac_multicast_packets",
 147                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 148         {"tx_mac_broadcast_packets",
 149                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 150
 151         {"lro_coalesced_packets",
 152                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 153         {"lro_coalesced_events",
 154                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 155         {"lro_aborts_num",
 156                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 157         {"lro_not_coalesced_packets",
 158                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 159         {"lro_coalesced_bytes",
 160                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 161 };
 162
 163 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 164         {"rx_q_segments",
 165                 offsetof(struct qede_rx_queue, rx_segs)},
 166         {"rx_q_hw_errors",
 167                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 168         {"rx_q_allocation_errors",
 169                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 170 };
 171
 172 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 173 {
 174         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 175 }
 176
 177 static void
 178 qede_interrupt_handler(__rte_unused struct rte_intr_handle *handle, void *param)
 179 {
 180         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 181         struct qede_dev *qdev = eth_dev->data->dev_private;
 182         struct ecore_dev *edev = &qdev->edev;
 183
 184         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 185         if (rte_intr_enable(&eth_dev->pci_dev->intr_handle))
 186                 DP_ERR(edev, "rte_intr_enable failed\n");
 187 }
 188
 189 static void
 190 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 191 {
 192         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 193         qdev->num_tc = qdev->dev_info.num_tc;
 194         qdev->ops = qed_ops;
 195 }
 196
 197 static void qede_print_adapter_info(struct qede_dev *qdev)
 198 {
 199         struct ecore_dev *edev = &qdev->edev;
 200         struct qed_dev_info *info = &qdev->dev_info.common;
 201         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 202         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 203
 204         DP_INFO(edev, "*********************************\n");
 205         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 206         DP_INFO(edev, " Chip details : %s %c%d\n",
 207                   ECORE_IS_BB(edev) ? "BB" : "AH",
 208                   'A' + edev->chip_rev,
 209                   (int)edev->chip_metal);
 210         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 211                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 212         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 213                  ver_str, QEDE_PMD_VERSION);
 214         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 215         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 216
 217         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 218                  "%d.%d.%d.%d",
 219                 (info->mfw_rev >> 24) & 0xff,
 220                 (info->mfw_rev >> 16) & 0xff,
 221                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 222         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 223         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 224         DP_INFO(edev, "*********************************\n");
 225 }
 226
 227 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 228 {
 229         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 230         ucast->is_rx_filter = true;
 231         ucast->is_tx_filter = true;
 232         /* ucast->assert_on_error = true; - For debug */
 233 }
 234
 235 static int
 236 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 237                   bool add)
 238 {
 239         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 240         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 241         struct qede_ucast_entry *tmp = NULL;
 242         struct qede_ucast_entry *u;
 243         struct ether_addr *mac_addr;
 244
 245         mac_addr  = (struct ether_addr *)ucast->mac;
 246         if (add) {
 247                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 248                         if ((memcmp(mac_addr, &tmp->mac,
 249                                     ETHER_ADDR_LEN) == 0) &&
 250                              ucast->vlan == tmp->vlan) {
 251                                 DP_INFO(edev, "Unicast MAC is already added"
 252                                         " with vlan = %u, vni = %u\n",
 253                                         ucast->vlan,  ucast->vni);
 254                                         return 0;
 255                         }
 256                 }
 257                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 258                                RTE_CACHE_LINE_SIZE);
 259                 if (!u) {
 260                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 261                         return -ENOMEM;
 262                 }
 263                 ether_addr_copy(mac_addr, &u->mac);
 264                 u->vlan = ucast->vlan;
 265                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 266                 qdev->num_uc_addr++;
 267         } else {
 268                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 269                         if ((memcmp(mac_addr, &tmp->mac,
 270                                     ETHER_ADDR_LEN) == 0) &&
 271                             ucast->vlan == tmp->vlan)
 272                         break;
 273                 }
 274                 if (tmp == NULL) {
 275                         DP_INFO(edev, "Unicast MAC is not found\n");
 276                         return -EINVAL;
 277                 }
 278                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 279                 qdev->num_uc_addr--;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 286 {
 287 #ifdef RTE_LIBRTE_QEDE_DEBUG_DRIVER
 288         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 289 #endif
 290         unsigned int i = 0, j = 0, qid;
 291         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 292         struct qede_tx_queue *txq;
 293
 294         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 295
 296         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 297                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 298         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 299                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 300
 301         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
 302                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
 303                         OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 304                             offsetof(struct qede_rx_queue, rcv_pkts), 0,
 305                             sizeof(uint64_t));
 306                         OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 307                             offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 308                             sizeof(uint64_t));
 309                         OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 310                             offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 311                             sizeof(uint64_t));
 312
 313                         if (xstats)
 314                                 for (j = 0;
 315                                      j < RTE_DIM(qede_rxq_xstats_strings); j++)
 316                                         OSAL_MEMSET((((char *)
 317                                             (qdev->fp_array[qid].rxq)) +
 318                                             qede_rxq_xstats_strings[j].offset),
 319                                             0,
 320                                             sizeof(uint64_t));
 321
 322                         i++;
 323                         if (i == rxq_stat_cntrs)
 324                                 break;
 325                 }
 326         }
 327
 328         i = 0;
 329
 330         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
 331                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
 332                         txq = qdev->fp_array[(qid)].txqs[0];
 333
 334                         OSAL_MEMSET((uint64_t *)(uintptr_t)
 335                                 (((uint64_t)(uintptr_t)(txq)) +
 336                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 337                             sizeof(uint64_t));
 338
 339                         i++;
 340                         if (i == txq_stat_cntrs)
 341                                 break;
 342                 }
 343         }
 344 }
 345
 346 static int
 347 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 348                   bool add)
 349 {
 350         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 351         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 352         struct ether_addr *mac_addr;
 353         struct qede_mcast_entry *tmp = NULL;
 354         struct qede_mcast_entry *m;
 355
 356         mac_addr  = (struct ether_addr *)mcast->mac;
 357         if (add) {
 358                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 359                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 360                                 DP_ERR(edev,
 361                                         "Multicast MAC is already added\n");
 362                                 return -EEXIST;
 363                         }
 364                 }
 365                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 366                         RTE_CACHE_LINE_SIZE);
 367                 if (!m) {
 368                         DP_ERR(edev,
 369                                 "Did not allocate memory for mcast\n");
 370                         return -ENOMEM;
 371                 }
 372                 ether_addr_copy(mac_addr, &m->mac);
 373                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 374                 qdev->num_mc_addr++;
 375         } else {
 376                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 377                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 378                                 break;
 379                 }
 380                 if (tmp == NULL) {
 381                         DP_INFO(edev, "Multicast mac is not found\n");
 382                         return -EINVAL;
 383                 }
 384                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 385                              qede_mcast_entry, list);
 386                 qdev->num_mc_addr--;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static enum _ecore_status_t
 393 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 394                  bool add)
 395 {
 396         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 397         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 398         enum _ecore_status_t rc;
 399         struct ecore_filter_mcast mcast;
 400         struct qede_mcast_entry *tmp;
 401         uint16_t j = 0;
 402
 403         /* Multicast */
 404         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 405                 if (add) {
 406                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 407                                 DP_ERR(edev,
 408                                        "Mcast filter table limit exceeded, "
 409                                        "Please enable mcast promisc mode\n");
 410                                 return -ECORE_INVAL;
 411                         }
 412                 }
 413                 rc = qede_mcast_filter(eth_dev, ucast, add);
 414                 if (rc == 0) {
 415                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 416                         memset(&mcast, 0, sizeof(mcast));
 417                         mcast.num_mc_addrs = qdev->num_mc_addr;
 418                         mcast.opcode = ECORE_FILTER_ADD;
 419                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 420                                 ether_addr_copy(&tmp->mac,
 421                                         (struct ether_addr *)&mcast.mac[j]);
 422                                 j++;
 423                         }
 424                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 425                                                     ECORE_SPQ_MODE_CB, NULL);
 426                 }
 427                 if (rc != ECORE_SUCCESS) {
 428                         DP_ERR(edev, "Failed to add multicast filter"
 429                                " rc = %d, op = %d\n", rc, add);
 430                 }
 431         } else { /* Unicast */
 432                 if (add) {
 433                         if (qdev->num_uc_addr >= qdev->dev_info.num_mac_addrs) {
 434                                 DP_ERR(edev,
 435                                        "Ucast filter table limit exceeded,"
 436                                        " Please enable promisc mode\n");
 437                                 return -ECORE_INVAL;
 438                         }
 439                 }
 440                 rc = qede_ucast_filter(eth_dev, ucast, add);
 441                 if (rc == 0)
 442                         rc = ecore_filter_ucast_cmd(edev, ucast,
 443                                                     ECORE_SPQ_MODE_CB, NULL);
 444                 /* Indicate error only for add filter operation.
 445                  * Delete filter operations are not severe.
 446                  */
 447                 if ((rc != ECORE_SUCCESS) && add) {
 448                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 449                                rc, add);
 450                 }
 451         }
 452
 453         return rc;
 454 }
 455
 456 static void
 457 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 458                   uint32_t index, __rte_unused uint32_t pool)
 459 {
 460         struct ecore_filter_ucast ucast;
 461
 462         qede_set_ucast_cmn_params(&ucast);
 463         ucast.type = ECORE_FILTER_MAC;
 464         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 465         (void)qede_mac_int_ops(eth_dev, &ucast, 1);
 466 }
 467
 468 static void
 469 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 470 {
 471         struct qede_dev *qdev = eth_dev->data->dev_private;
 472         struct ecore_dev *edev = &qdev->edev;
 473         struct ether_addr mac_addr;
 474         struct ecore_filter_ucast ucast;
 475         int rc;
 476
 477         PMD_INIT_FUNC_TRACE(edev);
 478
 479         if (index >= qdev->dev_info.num_mac_addrs) {
 480                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 481                        index, qdev->dev_info.num_mac_addrs);
 482                 return;
 483         }
 484
 485         qede_set_ucast_cmn_params(&ucast);
 486         ucast.opcode = ECORE_FILTER_REMOVE;
 487         ucast.type = ECORE_FILTER_MAC;
 488
 489         /* Use the index maintained by rte */
 490         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 491                         (struct ether_addr *)&ucast.mac);
 492
 493         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 494 }
 495
 496 static void
 497 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 498 {
 499         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 500         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 501
 502         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 503                                                mac_addr->addr_bytes)) {
 504                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 505                 ether_addr_copy(&qdev->primary_mac,
 506                                 &eth_dev->data->mac_addrs[0]);
 507                 return;
 508         }
 509
 510         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 511 }
 512
 513 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 514 {
 515         struct ecore_dev *edev = &qdev->edev;
 516         struct qed_update_vport_params params = {
 517                 .vport_id = 0,
 518                 .accept_any_vlan = action,
 519                 .update_accept_any_vlan_flg = 1,
 520         };
 521         int rc;
 522
 523         /* Proceed only if action actually needs to be performed */
 524         if (qdev->accept_any_vlan == action)
 525                 return;
 526
 527         rc = qdev->ops->vport_update(edev, &params);
 528         if (rc) {
 529                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 530                        action ? "enable" : "disable");
 531         } else {
 532                 DP_INFO(edev, "%s accept-any-vlan\n",
 533                         action ? "enabled" : "disabled");
 534                 qdev->accept_any_vlan = action;
 535         }
 536 }
 537
 538 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 539 {
 540         struct qed_update_vport_params vport_update_params;
 541         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 542         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 543         int rc;
 544
 545         memset(&vport_update_params, 0, sizeof(vport_update_params));
 546         vport_update_params.vport_id = 0;
 547         vport_update_params.update_inner_vlan_removal_flg = 1;
 548         vport_update_params.inner_vlan_removal_flg = set_stripping;
 549         rc = qdev->ops->vport_update(edev, &vport_update_params);
 550         if (rc) {
 551                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 552                 return rc;
 553         }
 554
 555         return 0;
 556 }
 557
 558 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 559 {
 560         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 561         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 562         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 563
 564         if (mask & ETH_VLAN_STRIP_MASK) {
 565                 if (rxmode->hw_vlan_strip)
 566                         (void)qede_vlan_stripping(eth_dev, 1);
 567                 else
 568                         (void)qede_vlan_stripping(eth_dev, 0);
 569         }
 570
 571         if (mask & ETH_VLAN_FILTER_MASK) {
 572                 /* VLAN filtering kicks in when a VLAN is added */
 573                 if (rxmode->hw_vlan_filter) {
 574                         qede_vlan_filter_set(eth_dev, 0, 1);
 575                 } else {
 576                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 577                                 DP_NOTICE(edev, false,
 578                                   " Please remove existing VLAN filters"
 579                                   " before disabling VLAN filtering\n");
 580                                 /* Signal app that VLAN filtering is still
 581                                  * enabled
 582                                  */
 583                                 rxmode->hw_vlan_filter = true;
 584                         } else {
 585                                 qede_vlan_filter_set(eth_dev, 0, 0);
 586                         }
 587                 }
 588         }
 589
 590         if (mask & ETH_VLAN_EXTEND_MASK)
 591                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 592                         " and classification is based on outer tag only\n");
 593
 594         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 595                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 596 }
 597
 598 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 599                                 uint16_t vlan_id, int on)
 600 {
 601         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 602         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 603         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 604         struct qede_vlan_entry *tmp = NULL;
 605         struct qede_vlan_entry *vlan;
 606         struct ecore_filter_ucast ucast;
 607         int rc;
 608
 609         if (on) {
 610                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 611                         DP_INFO(edev, "Reached max VLAN filter limit"
 612                                       " enabling accept_any_vlan\n");
 613                         qede_config_accept_any_vlan(qdev, true);
 614                         return 0;
 615                 }
 616
 617                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 618                         if (tmp->vid == vlan_id) {
 619                                 DP_INFO(edev, "VLAN %u already configured\n",
 620                                         vlan_id);
 621                                 return 0;
 622                         }
 623                 }
 624
 625                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 626                                   RTE_CACHE_LINE_SIZE);
 627
 628                 if (!vlan) {
 629                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 630                         return -ENOMEM;
 631                 }
 632
 633                 qede_set_ucast_cmn_params(&ucast);
 634                 ucast.opcode = ECORE_FILTER_ADD;
 635                 ucast.type = ECORE_FILTER_VLAN;
 636                 ucast.vlan = vlan_id;
 637                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 638                                             NULL);
 639                 if (rc != 0) {
 640                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 641                                rc);
 642                         rte_free(vlan);
 643                 } else {
 644                         vlan->vid = vlan_id;
 645                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 646                         qdev->configured_vlans++;
 647                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 648                                 vlan_id, qdev->configured_vlans);
 649                 }
 650         } else {
 651                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 652                         if (tmp->vid == vlan_id)
 653                                 break;
 654                 }
 655
 656                 if (!tmp) {
 657                         if (qdev->configured_vlans == 0) {
 658                                 DP_INFO(edev,
 659                                         "No VLAN filters configured yet\n");
 660                                 return 0;
 661                         }
 662
 663                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 664                         return -EINVAL;
 665                 }
 666
 667                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 668
 669                 qede_set_ucast_cmn_params(&ucast);
 670                 ucast.opcode = ECORE_FILTER_REMOVE;
 671                 ucast.type = ECORE_FILTER_VLAN;
 672                 ucast.vlan = vlan_id;
 673                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 674                                             NULL);
 675                 if (rc != 0) {
 676                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 677                                vlan_id, rc);
 678                 } else {
 679                         qdev->configured_vlans--;
 680                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 681                                 vlan_id, qdev->configured_vlans);
 682                 }
 683         }
 684
 685         return rc;
 686 }
 687
 688 static int qede_init_vport(struct qede_dev *qdev)
 689 {
 690         struct ecore_dev *edev = &qdev->edev;
 691         struct qed_start_vport_params start = {0};
 692         int rc;
 693
 694         start.remove_inner_vlan = 1;
 695         start.gro_enable = 0;
 696         start.mtu = qdev->mtu;
 697         start.vport_id = 0;
 698         start.drop_ttl0 = false;
 699         start.clear_stats = 1;
 700         start.handle_ptp_pkts = 0;
 701
 702         rc = qdev->ops->vport_start(edev, &start);
 703         if (rc) {
 704                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 705                 return rc;
 706         }
 707
 708         DP_INFO(edev,
 709                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 710                 start.vport_id, ETHER_MTU);
 711
 712         return 0;
 713 }
 714
 715 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 716 {
 717         struct qede_dev *qdev = eth_dev->data->dev_private;
 718         struct ecore_dev *edev = &qdev->edev;
 719         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 720         int rc, i, j;
 721
 722         PMD_INIT_FUNC_TRACE(edev);
 723
 724         /* Check requirements for 100G mode */
 725         if (edev->num_hwfns > 1) {
 726                 if (eth_dev->data->nb_rx_queues < 2 ||
 727                     eth_dev->data->nb_tx_queues < 2) {
 728                         DP_NOTICE(edev, false,
 729                                   "100G mode needs min. 2 RX/TX queues\n");
 730                         return -EINVAL;
 731                 }
 732
 733                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 734                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 735                         DP_NOTICE(edev, false,
 736                                   "100G mode needs even no. of RX/TX queues\n");
 737                         return -EINVAL;
 738                 }
 739         }
 740
 741         /* We need to have min 1 RX queue.There is no min check in
 742          * rte_eth_dev_configure(), so we are checking it here.
 743          */
 744         if (eth_dev->data->nb_rx_queues == 0) {
 745                 DP_ERR(edev, "Minimum one RX queue is required\n");
 746                 return -EINVAL;
 747         }
 748
 749         /* Sanity checks and throw warnings */
 750         if (rxmode->enable_scatter == 1)
 751                 eth_dev->data->scattered_rx = 1;
 752
 753         if (rxmode->enable_lro == 1) {
 754                 DP_INFO(edev, "LRO is not supported\n");
 755                 return -EINVAL;
 756         }
 757
 758         if (!rxmode->hw_strip_crc)
 759                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 760
 761         if (!rxmode->hw_ip_checksum)
 762                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 763                               "in hw\n");
 764
 765         /* Check for the port restart case */
 766         if (qdev->state != QEDE_DEV_INIT) {
 767                 rc = qdev->ops->vport_stop(edev, 0);
 768                 if (rc != 0)
 769                         return rc;
 770                 qede_dealloc_fp_resc(eth_dev);
 771         }
 772
 773         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 774         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 775         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 776
 777         /* Fastpath status block should be initialized before sending
 778          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 779          */
 780         rc = qede_alloc_fp_resc(qdev);
 781         if (rc != 0)
 782                 return rc;
 783
 784         /* If jumbo enabled adjust MTU */
 785         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
 786                 eth_dev->data->mtu =
 787                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 788                         ETHER_HDR_LEN - ETHER_CRC_LEN;
 789
 790         qdev->mtu = eth_dev->data->mtu;
 791
 792         /* Issue VPORT-START with default config values to allow
 793          * other port configurations early on.
 794          */
 795         rc = qede_init_vport(qdev);
 796         if (rc != 0)
 797                 return rc;
 798
 799         SLIST_INIT(&qdev->vlan_list_head);
 800
 801         /* Enable VLAN offloads by default */
 802         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
 803                                        ETH_VLAN_FILTER_MASK);
 804
 805         qdev->state = QEDE_DEV_CONFIG;
 806
 807         DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
 808                 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
 809                 qdev->num_tc);
 810
 811         return 0;
 812 }
 813
 814 /* Info about HW descriptor ring limitations */
 815 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 816         .nb_max = NUM_RX_BDS_MAX,
 817         .nb_min = 128,
 818         .nb_align = 128 /* lowest common multiple */
 819 };
 820
 821 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 822         .nb_max = NUM_TX_BDS_MAX,
 823         .nb_min = 256,
 824         .nb_align = 256
 825 };
 826
 827 static void
 828 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 829                   struct rte_eth_dev_info *dev_info)
 830 {
 831         struct qede_dev *qdev = eth_dev->data->dev_private;
 832         struct ecore_dev *edev = &qdev->edev;
 833         struct qed_link_output link;
 834         uint32_t speed_cap = 0;
 835
 836         PMD_INIT_FUNC_TRACE(edev);
 837
 838         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
 839         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 840         dev_info->rx_desc_lim = qede_rx_desc_lim;
 841         dev_info->tx_desc_lim = qede_tx_desc_lim;
 842         dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev);
 843         dev_info->max_tx_queues = dev_info->max_rx_queues;
 844         dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs;
 845         if (IS_VF(edev))
 846                 dev_info->max_vfs = 0;
 847         else
 848                 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev);
 849         dev_info->driver_name = qdev->drv_ver;
 850         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 851         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 852
 853         dev_info->default_txconf = (struct rte_eth_txconf) {
 854                 .txq_flags = QEDE_TXQ_FLAGS,
 855         };
 856
 857         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
 858                                      DEV_RX_OFFLOAD_IPV4_CKSUM |
 859                                      DEV_RX_OFFLOAD_UDP_CKSUM |
 860                                      DEV_RX_OFFLOAD_TCP_CKSUM);
 861         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 862                                      DEV_TX_OFFLOAD_IPV4_CKSUM |
 863                                      DEV_TX_OFFLOAD_UDP_CKSUM |
 864                                      DEV_TX_OFFLOAD_TCP_CKSUM);
 865
 866         memset(&link, 0, sizeof(struct qed_link_output));
 867         qdev->ops->common->get_link(edev, &link);
 868         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
 869                 speed_cap |= ETH_LINK_SPEED_1G;
 870         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
 871                 speed_cap |= ETH_LINK_SPEED_10G;
 872         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
 873                 speed_cap |= ETH_LINK_SPEED_25G;
 874         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
 875                 speed_cap |= ETH_LINK_SPEED_40G;
 876         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
 877                 speed_cap |= ETH_LINK_SPEED_50G;
 878         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
 879                 speed_cap |= ETH_LINK_SPEED_100G;
 880         dev_info->speed_capa = speed_cap;
 881 }
 882
 883 /* return 0 means link status changed, -1 means not changed */
 884 static int
 885 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
 886 {
 887         struct qede_dev *qdev = eth_dev->data->dev_private;
 888         struct ecore_dev *edev = &qdev->edev;
 889         uint16_t link_duplex;
 890         struct qed_link_output link;
 891         struct rte_eth_link *curr = &eth_dev->data->dev_link;
 892
 893         memset(&link, 0, sizeof(struct qed_link_output));
 894         qdev->ops->common->get_link(edev, &link);
 895
 896         /* Link Speed */
 897         curr->link_speed = link.speed;
 898
 899         /* Link Mode */
 900         switch (link.duplex) {
 901         case QEDE_DUPLEX_HALF:
 902                 link_duplex = ETH_LINK_HALF_DUPLEX;
 903                 break;
 904         case QEDE_DUPLEX_FULL:
 905                 link_duplex = ETH_LINK_FULL_DUPLEX;
 906                 break;
 907         case QEDE_DUPLEX_UNKNOWN:
 908         default:
 909                 link_duplex = -1;
 910         }
 911         curr->link_duplex = link_duplex;
 912
 913         /* Link Status */
 914         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
 915
 916         /* AN */
 917         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
 918                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
 919
 920         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
 921                 curr->link_speed, curr->link_duplex,
 922                 curr->link_autoneg, curr->link_status);
 923
 924         /* return 0 means link status changed, -1 means not changed */
 925         return ((curr->link_status == link.link_up) ? -1 : 0);
 926 }
 927
 928 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
 929 {
 930         struct qede_dev *qdev = eth_dev->data->dev_private;
 931         struct ecore_dev *edev = &qdev->edev;
 932
 933         PMD_INIT_FUNC_TRACE(edev);
 934
 935         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
 936
 937         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
 938                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
 939
 940         qed_configure_filter_rx_mode(eth_dev, type);
 941 }
 942
 943 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
 944 {
 945         struct qede_dev *qdev = eth_dev->data->dev_private;
 946         struct ecore_dev *edev = &qdev->edev;
 947
 948         PMD_INIT_FUNC_TRACE(edev);
 949
 950         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
 951                 qed_configure_filter_rx_mode(eth_dev,
 952                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
 953         else
 954                 qed_configure_filter_rx_mode(eth_dev,
 955                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
 956 }
 957
 958 static void qede_poll_sp_sb_cb(void *param)
 959 {
 960         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 961         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 962         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 963         int rc;
 964
 965         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 966         qede_interrupt_action(&edev->hwfns[1]);
 967
 968         rc = rte_eal_alarm_set(timer_period * US_PER_S,
 969                                qede_poll_sp_sb_cb,
 970                                (void *)eth_dev);
 971         if (rc != 0) {
 972                 DP_ERR(edev, "Unable to start periodic"
 973                              " timer rc %d\n", rc);
 974                 assert(false && "Unable to start periodic timer");
 975         }
 976 }
 977
 978 static void qede_dev_close(struct rte_eth_dev *eth_dev)
 979 {
 980         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 981         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 982         int rc;
 983
 984         PMD_INIT_FUNC_TRACE(edev);
 985
 986         /* dev_stop() shall cleanup fp resources in hw but without releasing
 987          * dma memories and sw structures so that dev_start() can be called
 988          * by the app without reconfiguration. However, in dev_close() we
 989          * can release all the resources and device can be brought up newly
 990          */
 991         if (qdev->state != QEDE_DEV_STOP)
 992                 qede_dev_stop(eth_dev);
 993         else
 994                 DP_INFO(edev, "Device is already stopped\n");
 995
 996         rc = qdev->ops->vport_stop(edev, 0);
 997         if (rc != 0)
 998                 DP_ERR(edev, "Failed to stop VPORT\n");
 999
1000         qede_dealloc_fp_resc(eth_dev);
1001
1002         qdev->ops->common->slowpath_stop(edev);
1003
1004         qdev->ops->common->remove(edev);
1005
1006         rte_intr_disable(&eth_dev->pci_dev->intr_handle);
1007
1008         rte_intr_callback_unregister(&eth_dev->pci_dev->intr_handle,
1009                                      qede_interrupt_handler, (void *)eth_dev);
1010
1011         if (edev->num_hwfns > 1)
1012                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1013
1014         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
1015 }
1016
1017 static void
1018 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1019 {
1020         struct qede_dev *qdev = eth_dev->data->dev_private;
1021         struct ecore_dev *edev = &qdev->edev;
1022         struct ecore_eth_stats stats;
1023         unsigned int i = 0, j = 0, qid;
1024         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1025         struct qede_tx_queue *txq;
1026
1027         qdev->ops->get_vport_stats(edev, &stats);
1028
1029         /* RX Stats */
1030         eth_stats->ipackets = stats.rx_ucast_pkts +
1031             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1032
1033         eth_stats->ibytes = stats.rx_ucast_bytes +
1034             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1035
1036         eth_stats->ierrors = stats.rx_crc_errors +
1037             stats.rx_align_errors +
1038             stats.rx_carrier_errors +
1039             stats.rx_oversize_packets +
1040             stats.rx_jabbers + stats.rx_undersize_packets;
1041
1042         eth_stats->rx_nombuf = stats.no_buff_discards;
1043
1044         eth_stats->imissed = stats.mftag_filter_discards +
1045             stats.mac_filter_discards +
1046             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1047
1048         /* TX stats */
1049         eth_stats->opackets = stats.tx_ucast_pkts +
1050             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1051
1052         eth_stats->obytes = stats.tx_ucast_bytes +
1053             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1054
1055         eth_stats->oerrors = stats.tx_err_drop_pkts;
1056
1057         /* Queue stats */
1058         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1059                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1060         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1061                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1062         if ((rxq_stat_cntrs != QEDE_RSS_COUNT(qdev)) ||
1063             (txq_stat_cntrs != QEDE_TSS_COUNT(qdev)))
1064                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1065                        "Not all the queue stats will be displayed. Set"
1066                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1067                        " appropriately and retry.\n");
1068
1069         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1070                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1071                         eth_stats->q_ipackets[i] =
1072                                 *(uint64_t *)(
1073                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1074                                         offsetof(struct qede_rx_queue,
1075                                         rcv_pkts));
1076                         eth_stats->q_errors[i] =
1077                                 *(uint64_t *)(
1078                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1079                                         offsetof(struct qede_rx_queue,
1080                                         rx_hw_errors)) +
1081                                 *(uint64_t *)(
1082                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1083                                         offsetof(struct qede_rx_queue,
1084                                         rx_alloc_errors));
1085                         i++;
1086                 }
1087                 if (i == rxq_stat_cntrs)
1088                         break;
1089         }
1090
1091         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1092                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1093                         txq = qdev->fp_array[(qid)].txqs[0];
1094                         eth_stats->q_opackets[j] =
1095                                 *((uint64_t *)(uintptr_t)
1096                                         (((uint64_t)(uintptr_t)(txq)) +
1097                                          offsetof(struct qede_tx_queue,
1098                                                   xmit_pkts)));
1099                         j++;
1100                 }
1101                 if (j == txq_stat_cntrs)
1102                         break;
1103         }
1104 }
1105
1106 static unsigned
1107 qede_get_xstats_count(struct qede_dev *qdev) {
1108         return RTE_DIM(qede_xstats_strings) +
1109                 (RTE_DIM(qede_rxq_xstats_strings) *
1110                  RTE_MIN(QEDE_RSS_COUNT(qdev),
1111                          RTE_ETHDEV_QUEUE_STAT_CNTRS));
1112 }
1113
1114 static int
1115 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1116                       struct rte_eth_xstat_name *xstats_names, unsigned limit)
1117 {
1118         struct qede_dev *qdev = dev->data->dev_private;
1119         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1120         unsigned int i, qid, stat_idx = 0;
1121         unsigned int rxq_stat_cntrs;
1122
1123         if (xstats_names != NULL) {
1124                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1125                         snprintf(xstats_names[stat_idx].name,
1126                                 sizeof(xstats_names[stat_idx].name),
1127                                 "%s",
1128                                 qede_xstats_strings[i].name);
1129                         stat_idx++;
1130                 }
1131
1132                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1133                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1134                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1135                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1136                                 snprintf(xstats_names[stat_idx].name,
1137                                         sizeof(xstats_names[stat_idx].name),
1138                                         "%.4s%d%s",
1139                                         qede_rxq_xstats_strings[i].name, qid,
1140                                         qede_rxq_xstats_strings[i].name + 4);
1141                                 stat_idx++;
1142                         }
1143                 }
1144         }
1145
1146         return stat_cnt;
1147 }
1148
1149 static int
1150 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1151                 unsigned int n)
1152 {
1153         struct qede_dev *qdev = dev->data->dev_private;
1154         struct ecore_dev *edev = &qdev->edev;
1155         struct ecore_eth_stats stats;
1156         const unsigned int num = qede_get_xstats_count(qdev);
1157         unsigned int i, qid, stat_idx = 0;
1158         unsigned int rxq_stat_cntrs;
1159
1160         if (n < num)
1161                 return num;
1162
1163         qdev->ops->get_vport_stats(edev, &stats);
1164
1165         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1166                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1167                                              qede_xstats_strings[i].offset);
1168                 xstats[stat_idx].id = stat_idx;
1169                 stat_idx++;
1170         }
1171
1172         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1173                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1174         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1175                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1176                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1177                                 xstats[stat_idx].value = *(uint64_t *)(
1178                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1179                                          qede_rxq_xstats_strings[i].offset);
1180                                 xstats[stat_idx].id = stat_idx;
1181                                 stat_idx++;
1182                         }
1183                 }
1184         }
1185
1186         return stat_idx;
1187 }
1188
1189 static void
1190 qede_reset_xstats(struct rte_eth_dev *dev)
1191 {
1192         struct qede_dev *qdev = dev->data->dev_private;
1193         struct ecore_dev *edev = &qdev->edev;
1194
1195         ecore_reset_vport_stats(edev);
1196         qede_reset_queue_stats(qdev, true);
1197 }
1198
1199 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1200 {
1201         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1202         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1203         struct qed_link_params link_params;
1204         int rc;
1205
1206         DP_INFO(edev, "setting link state %d\n", link_up);
1207         memset(&link_params, 0, sizeof(link_params));
1208         link_params.link_up = link_up;
1209         rc = qdev->ops->common->set_link(edev, &link_params);
1210         if (rc != ECORE_SUCCESS)
1211                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1212
1213         return rc;
1214 }
1215
1216 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1217 {
1218         return qede_dev_set_link_state(eth_dev, true);
1219 }
1220
1221 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1222 {
1223         return qede_dev_set_link_state(eth_dev, false);
1224 }
1225
1226 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1227 {
1228         struct qede_dev *qdev = eth_dev->data->dev_private;
1229         struct ecore_dev *edev = &qdev->edev;
1230
1231         ecore_reset_vport_stats(edev);
1232         qede_reset_queue_stats(qdev, false);
1233 }
1234
1235 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1236 {
1237         enum qed_filter_rx_mode_type type =
1238             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1239
1240         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1241                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1242
1243         qed_configure_filter_rx_mode(eth_dev, type);
1244 }
1245
1246 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1247 {
1248         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1249                 qed_configure_filter_rx_mode(eth_dev,
1250                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1251         else
1252                 qed_configure_filter_rx_mode(eth_dev,
1253                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1254 }
1255
1256 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1257                               struct rte_eth_fc_conf *fc_conf)
1258 {
1259         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1260         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1261         struct qed_link_output current_link;
1262         struct qed_link_params params;
1263
1264         memset(&current_link, 0, sizeof(current_link));
1265         qdev->ops->common->get_link(edev, &current_link);
1266
1267         memset(&params, 0, sizeof(params));
1268         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1269         if (fc_conf->autoneg) {
1270                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1271                         DP_ERR(edev, "Autoneg not supported\n");
1272                         return -EINVAL;
1273                 }
1274                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1275         }
1276
1277         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1278         if (fc_conf->mode == RTE_FC_FULL)
1279                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1280                                         QED_LINK_PAUSE_RX_ENABLE);
1281         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1282                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1283         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1284                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1285
1286         params.link_up = true;
1287         (void)qdev->ops->common->set_link(edev, &params);
1288
1289         return 0;
1290 }
1291
1292 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1293                               struct rte_eth_fc_conf *fc_conf)
1294 {
1295         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1296         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1297         struct qed_link_output current_link;
1298
1299         memset(&current_link, 0, sizeof(current_link));
1300         qdev->ops->common->get_link(edev, &current_link);
1301
1302         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1303                 fc_conf->autoneg = true;
1304
1305         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1306                                          QED_LINK_PAUSE_TX_ENABLE))
1307                 fc_conf->mode = RTE_FC_FULL;
1308         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1309                 fc_conf->mode = RTE_FC_RX_PAUSE;
1310         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1311                 fc_conf->mode = RTE_FC_TX_PAUSE;
1312         else
1313                 fc_conf->mode = RTE_FC_NONE;
1314
1315         return 0;
1316 }
1317
1318 static const uint32_t *
1319 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1320 {
1321         static const uint32_t ptypes[] = {
1322                 RTE_PTYPE_L3_IPV4,
1323                 RTE_PTYPE_L3_IPV6,
1324                 RTE_PTYPE_UNKNOWN
1325         };
1326
1327         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1328                 return ptypes;
1329
1330         return NULL;
1331 }
1332
1333 void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1334 {
1335         *rss_caps = 0;
1336         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1337         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1338         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1339         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1340         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1341         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1342         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1343         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1344 }
1345
1346 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1347                                 struct rte_eth_rss_conf *rss_conf)
1348 {
1349         struct qed_update_vport_params vport_update_params;
1350         struct qede_dev *qdev = eth_dev->data->dev_private;
1351         struct ecore_dev *edev = &qdev->edev;
1352         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1353         uint64_t hf = rss_conf->rss_hf;
1354         int i;
1355
1356         memset(&vport_update_params, 0, sizeof(vport_update_params));
1357
1358         if (hf != 0) {
1359                 /* Enable RSS */
1360                 qede_init_rss_caps(&qdev->rss_params.rss_caps, hf);
1361                 memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1362                        sizeof(vport_update_params.rss_params));
1363                 if (key)
1364                         memcpy(qdev->rss_params.rss_key, rss_conf->rss_key,
1365                                rss_conf->rss_key_len);
1366                 vport_update_params.update_rss_flg = 1;
1367                 qdev->rss_enabled = 1;
1368         } else {
1369                 /* Disable RSS */
1370                 qdev->rss_enabled = 0;
1371         }
1372
1373         /* If the mapping doesn't fit any supported, return */
1374         if (qdev->rss_params.rss_caps == 0 && hf != 0)
1375                 return -EINVAL;
1376
1377         DP_INFO(edev, "%s\n", (vport_update_params.update_rss_flg) ?
1378                                 "Enabling RSS" : "Disabling RSS");
1379
1380         vport_update_params.vport_id = 0;
1381
1382         return qdev->ops->vport_update(edev, &vport_update_params);
1383 }
1384
1385 int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1386                            struct rte_eth_rss_conf *rss_conf)
1387 {
1388         struct qede_dev *qdev = eth_dev->data->dev_private;
1389         uint64_t hf;
1390
1391         if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key))
1392                 return -EINVAL;
1393
1394         if (rss_conf->rss_key)
1395                 memcpy(rss_conf->rss_key, qdev->rss_params.rss_key,
1396                        sizeof(qdev->rss_params.rss_key));
1397
1398         hf = 0;
1399         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4)     ?
1400                         ETH_RSS_IPV4 : 0;
1401         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1402                         ETH_RSS_IPV6 : 0;
1403         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1404                         ETH_RSS_IPV6_EX : 0;
1405         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ?
1406                         ETH_RSS_NONFRAG_IPV4_TCP : 0;
1407         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1408                         ETH_RSS_NONFRAG_IPV6_TCP : 0;
1409         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1410                         ETH_RSS_IPV6_TCP_EX : 0;
1411
1412         rss_conf->rss_hf = hf;
1413
1414         return 0;
1415 }
1416
1417 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1418                                 struct rte_eth_rss_reta_entry64 *reta_conf,
1419                                 uint16_t reta_size)
1420 {
1421         struct qed_update_vport_params vport_update_params;
1422         struct qede_dev *qdev = eth_dev->data->dev_private;
1423         struct ecore_dev *edev = &qdev->edev;
1424         uint16_t i, idx, shift;
1425
1426         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1427                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1428                        reta_size);
1429                 return -EINVAL;
1430         }
1431
1432         memset(&vport_update_params, 0, sizeof(vport_update_params));
1433         memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1434                sizeof(vport_update_params.rss_params));
1435
1436         for (i = 0; i < reta_size; i++) {
1437                 idx = i / RTE_RETA_GROUP_SIZE;
1438                 shift = i % RTE_RETA_GROUP_SIZE;
1439                 if (reta_conf[idx].mask & (1ULL << shift)) {
1440                         uint8_t entry = reta_conf[idx].reta[shift];
1441                         qdev->rss_params.rss_ind_table[i] = entry;
1442                 }
1443         }
1444
1445         vport_update_params.update_rss_flg = 1;
1446         vport_update_params.vport_id = 0;
1447
1448         return qdev->ops->vport_update(edev, &vport_update_params);
1449 }
1450
1451 int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1452                         struct rte_eth_rss_reta_entry64 *reta_conf,
1453                         uint16_t reta_size)
1454 {
1455         struct qede_dev *qdev = eth_dev->data->dev_private;
1456         uint16_t i, idx, shift;
1457
1458         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1459                 struct ecore_dev *edev = &qdev->edev;
1460                 DP_ERR(edev, "reta_size %d is not supported\n",
1461                        reta_size);
1462         }
1463
1464         for (i = 0; i < reta_size; i++) {
1465                 idx = i / RTE_RETA_GROUP_SIZE;
1466                 shift = i % RTE_RETA_GROUP_SIZE;
1467                 if (reta_conf[idx].mask & (1ULL << shift)) {
1468                         uint8_t entry = qdev->rss_params.rss_ind_table[i];
1469                         reta_conf[idx].reta[shift] = entry;
1470                 }
1471         }
1472
1473         return 0;
1474 }
1475
1476 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1477 {
1478         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
1479         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1480         struct rte_eth_dev_info dev_info = {0};
1481         struct qede_fastpath *fp;
1482         uint32_t max_rx_pkt_len;
1483         uint32_t frame_size;
1484         uint16_t rx_buf_size;
1485         uint16_t bufsz;
1486         bool restart = false;
1487         int i;
1488
1489         PMD_INIT_FUNC_TRACE(edev);
1490         if (IS_VF(edev))
1491                 return -ENOTSUP;
1492         qede_dev_info_get(dev, &dev_info);
1493         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1494         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
1495         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
1496                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
1497                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
1498                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
1499                 return -EINVAL;
1500         }
1501         if (!dev->data->scattered_rx &&
1502             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
1503                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
1504                         dev->data->min_rx_buf_size);
1505                 return -EINVAL;
1506         }
1507         /* Temporarily replace I/O functions with dummy ones. It cannot
1508          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1509          */
1510         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
1511         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
1512         if (dev->data->dev_started) {
1513                 dev->data->dev_started = 0;
1514                 qede_dev_stop(dev);
1515                 restart = true;
1516         }
1517         rte_delay_ms(1000);
1518         qdev->mtu = mtu;
1519         /* Fix up RX buf size for all queues of the port */
1520         for_each_queue(i) {
1521                 fp = &qdev->fp_array[i];
1522                 if ((fp->type & QEDE_FASTPATH_RX) && (fp->rxq != NULL)) {
1523                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
1524                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
1525                         if (dev->data->scattered_rx)
1526                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
1527                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
1528                         else
1529                                 rx_buf_size = frame_size;
1530                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
1531                         fp->rxq->rx_buf_size = rx_buf_size;
1532                         DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
1533                 }
1534         }
1535         if (max_rx_pkt_len > ETHER_MAX_LEN)
1536                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1537         else
1538                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1539         if (!dev->data->dev_started && restart) {
1540                 qede_dev_start(dev);
1541                 dev->data->dev_started = 1;
1542         }
1543         /* update max frame size */
1544         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
1545         /* Reassign back */
1546         dev->rx_pkt_burst = qede_recv_pkts;
1547         dev->tx_pkt_burst = qede_xmit_pkts;
1548
1549         return 0;
1550 }
1551
1552 static const struct eth_dev_ops qede_eth_dev_ops = {
1553         .dev_configure = qede_dev_configure,
1554         .dev_infos_get = qede_dev_info_get,
1555         .rx_queue_setup = qede_rx_queue_setup,
1556         .rx_queue_release = qede_rx_queue_release,
1557         .tx_queue_setup = qede_tx_queue_setup,
1558         .tx_queue_release = qede_tx_queue_release,
1559         .dev_start = qede_dev_start,
1560         .dev_set_link_up = qede_dev_set_link_up,
1561         .dev_set_link_down = qede_dev_set_link_down,
1562         .link_update = qede_link_update,
1563         .promiscuous_enable = qede_promiscuous_enable,
1564         .promiscuous_disable = qede_promiscuous_disable,
1565         .allmulticast_enable = qede_allmulticast_enable,
1566         .allmulticast_disable = qede_allmulticast_disable,
1567         .dev_stop = qede_dev_stop,
1568         .dev_close = qede_dev_close,
1569         .stats_get = qede_get_stats,
1570         .stats_reset = qede_reset_stats,
1571         .xstats_get = qede_get_xstats,
1572         .xstats_reset = qede_reset_xstats,
1573         .xstats_get_names = qede_get_xstats_names,
1574         .mac_addr_add = qede_mac_addr_add,
1575         .mac_addr_remove = qede_mac_addr_remove,
1576         .mac_addr_set = qede_mac_addr_set,
1577         .vlan_offload_set = qede_vlan_offload_set,
1578         .vlan_filter_set = qede_vlan_filter_set,
1579         .flow_ctrl_set = qede_flow_ctrl_set,
1580         .flow_ctrl_get = qede_flow_ctrl_get,
1581         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1582         .rss_hash_update = qede_rss_hash_update,
1583         .rss_hash_conf_get = qede_rss_hash_conf_get,
1584         .reta_update  = qede_rss_reta_update,
1585         .reta_query  = qede_rss_reta_query,
1586         .mtu_set = qede_set_mtu,
1587 };
1588
1589 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
1590         .dev_configure = qede_dev_configure,
1591         .dev_infos_get = qede_dev_info_get,
1592         .rx_queue_setup = qede_rx_queue_setup,
1593         .rx_queue_release = qede_rx_queue_release,
1594         .tx_queue_setup = qede_tx_queue_setup,
1595         .tx_queue_release = qede_tx_queue_release,
1596         .dev_start = qede_dev_start,
1597         .dev_set_link_up = qede_dev_set_link_up,
1598         .dev_set_link_down = qede_dev_set_link_down,
1599         .link_update = qede_link_update,
1600         .promiscuous_enable = qede_promiscuous_enable,
1601         .promiscuous_disable = qede_promiscuous_disable,
1602         .allmulticast_enable = qede_allmulticast_enable,
1603         .allmulticast_disable = qede_allmulticast_disable,
1604         .dev_stop = qede_dev_stop,
1605         .dev_close = qede_dev_close,
1606         .stats_get = qede_get_stats,
1607         .stats_reset = qede_reset_stats,
1608         .xstats_get = qede_get_xstats,
1609         .xstats_reset = qede_reset_xstats,
1610         .xstats_get_names = qede_get_xstats_names,
1611         .vlan_offload_set = qede_vlan_offload_set,
1612         .vlan_filter_set = qede_vlan_filter_set,
1613         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1614         .rss_hash_update = qede_rss_hash_update,
1615         .rss_hash_conf_get = qede_rss_hash_conf_get,
1616         .reta_update  = qede_rss_reta_update,
1617         .reta_query  = qede_rss_reta_query,
1618         .mtu_set = qede_set_mtu,
1619 };
1620
1621 static void qede_update_pf_params(struct ecore_dev *edev)
1622 {
1623         struct ecore_pf_params pf_params;
1624         /* 32 rx + 32 tx */
1625         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
1626         pf_params.eth_pf_params.num_cons = 64;
1627         qed_ops->common->update_pf_params(edev, &pf_params);
1628 }
1629
1630 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
1631 {
1632         struct rte_pci_device *pci_dev;
1633         struct rte_pci_addr pci_addr;
1634         struct qede_dev *adapter;
1635         struct ecore_dev *edev;
1636         struct qed_dev_eth_info dev_info;
1637         struct qed_slowpath_params params;
1638         static bool do_once = true;
1639         uint8_t bulletin_change;
1640         uint8_t vf_mac[ETHER_ADDR_LEN];
1641         uint8_t is_mac_forced;
1642         bool is_mac_exist;
1643         /* Fix up ecore debug level */
1644         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
1645         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
1646         uint32_t max_mac_addrs;
1647         int rc;
1648
1649         /* Extract key data structures */
1650         adapter = eth_dev->data->dev_private;
1651         edev = &adapter->edev;
1652         pci_addr = eth_dev->pci_dev->addr;
1653
1654         PMD_INIT_FUNC_TRACE(edev);
1655
1656         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
1657                  pci_addr.bus, pci_addr.devid, pci_addr.function,
1658                  eth_dev->data->port_id);
1659
1660         eth_dev->rx_pkt_burst = qede_recv_pkts;
1661         eth_dev->tx_pkt_burst = qede_xmit_pkts;
1662
1663         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1664                 DP_NOTICE(edev, false,
1665                           "Skipping device init from secondary process\n");
1666                 return 0;
1667         }
1668
1669         pci_dev = eth_dev->pci_dev;
1670
1671         rte_eth_copy_pci_info(eth_dev, pci_dev);
1672
1673         /* @DPDK */
1674         edev->vendor_id = pci_dev->id.vendor_id;
1675         edev->device_id = pci_dev->id.device_id;
1676
1677         qed_ops = qed_get_eth_ops();
1678         if (!qed_ops) {
1679                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
1680                 return -EINVAL;
1681         }
1682
1683         DP_INFO(edev, "Starting qede probe\n");
1684
1685         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
1686                                     dp_module, dp_level, is_vf);
1687
1688         if (rc != 0) {
1689                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
1690                 return -ENODEV;
1691         }
1692
1693         qede_update_pf_params(edev);
1694
1695         rte_intr_callback_register(&eth_dev->pci_dev->intr_handle,
1696                                    qede_interrupt_handler, (void *)eth_dev);
1697
1698         if (rte_intr_enable(&eth_dev->pci_dev->intr_handle)) {
1699                 DP_ERR(edev, "rte_intr_enable() failed\n");
1700                 return -ENODEV;
1701         }
1702
1703         /* Start the Slowpath-process */
1704         memset(&params, 0, sizeof(struct qed_slowpath_params));
1705         params.int_mode = ECORE_INT_MODE_MSIX;
1706         params.drv_major = QEDE_PMD_VERSION_MAJOR;
1707         params.drv_minor = QEDE_PMD_VERSION_MINOR;
1708         params.drv_rev = QEDE_PMD_VERSION_REVISION;
1709         params.drv_eng = QEDE_PMD_VERSION_PATCH;
1710         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
1711                 QEDE_PMD_DRV_VER_STR_SIZE);
1712
1713         /* For CMT mode device do periodic polling for slowpath events.
1714          * This is required since uio device uses only one MSI-x
1715          * interrupt vector but we need one for each engine.
1716          */
1717         if (edev->num_hwfns > 1 && IS_PF(edev)) {
1718                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1719                                        qede_poll_sp_sb_cb,
1720                                        (void *)eth_dev);
1721                 if (rc != 0) {
1722                         DP_ERR(edev, "Unable to start periodic"
1723                                      " timer rc %d\n", rc);
1724                         return -EINVAL;
1725                 }
1726         }
1727
1728         rc = qed_ops->common->slowpath_start(edev, &params);
1729         if (rc) {
1730                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
1731                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1732                                      (void *)eth_dev);
1733                 return -ENODEV;
1734         }
1735
1736         rc = qed_ops->fill_dev_info(edev, &dev_info);
1737         if (rc) {
1738                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
1739                 qed_ops->common->slowpath_stop(edev);
1740                 qed_ops->common->remove(edev);
1741                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1742                                      (void *)eth_dev);
1743                 return -ENODEV;
1744         }
1745
1746         qede_alloc_etherdev(adapter, &dev_info);
1747
1748         adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION);
1749
1750         if (!is_vf)
1751                 adapter->dev_info.num_mac_addrs =
1752                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
1753                                             ECORE_MAC);
1754         else
1755                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
1756                                              &adapter->dev_info.num_mac_addrs);
1757
1758         /* Allocate memory for storing MAC addr */
1759         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
1760                                         (ETHER_ADDR_LEN *
1761                                         adapter->dev_info.num_mac_addrs),
1762                                         RTE_CACHE_LINE_SIZE);
1763
1764         if (eth_dev->data->mac_addrs == NULL) {
1765                 DP_ERR(edev, "Failed to allocate MAC address\n");
1766                 qed_ops->common->slowpath_stop(edev);
1767                 qed_ops->common->remove(edev);
1768                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1769                                      (void *)eth_dev);
1770                 return -ENOMEM;
1771         }
1772
1773         if (!is_vf) {
1774                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
1775                                 hw_info.hw_mac_addr,
1776                                 &eth_dev->data->mac_addrs[0]);
1777                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
1778                                 &adapter->primary_mac);
1779         } else {
1780                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
1781                                        &bulletin_change);
1782                 if (bulletin_change) {
1783                         is_mac_exist =
1784                             ecore_vf_bulletin_get_forced_mac(
1785                                                 ECORE_LEADING_HWFN(edev),
1786                                                 vf_mac,
1787                                                 &is_mac_forced);
1788                         if (is_mac_exist && is_mac_forced) {
1789                                 DP_INFO(edev, "VF macaddr received from PF\n");
1790                                 ether_addr_copy((struct ether_addr *)&vf_mac,
1791                                                 &eth_dev->data->mac_addrs[0]);
1792                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
1793                                                 &adapter->primary_mac);
1794                         } else {
1795                                 DP_NOTICE(edev, false,
1796                                           "No VF macaddr assigned\n");
1797                         }
1798                 }
1799         }
1800
1801         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
1802
1803         if (do_once) {
1804                 qede_print_adapter_info(adapter);
1805                 do_once = false;
1806         }
1807
1808         adapter->state = QEDE_DEV_INIT;
1809
1810         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
1811                   adapter->primary_mac.addr_bytes[0],
1812                   adapter->primary_mac.addr_bytes[1],
1813                   adapter->primary_mac.addr_bytes[2],
1814                   adapter->primary_mac.addr_bytes[3],
1815                   adapter->primary_mac.addr_bytes[4],
1816                   adapter->primary_mac.addr_bytes[5]);
1817
1818         return rc;
1819 }
1820
1821 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
1822 {
1823         return qede_common_dev_init(eth_dev, 1);
1824 }
1825
1826 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
1827 {
1828         return qede_common_dev_init(eth_dev, 0);
1829 }
1830
1831 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
1832 {
1833         /* only uninitialize in the primary process */
1834         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1835                 return 0;
1836
1837         /* safe to close dev here */
1838         qede_dev_close(eth_dev);
1839
1840         eth_dev->dev_ops = NULL;
1841         eth_dev->rx_pkt_burst = NULL;
1842         eth_dev->tx_pkt_burst = NULL;
1843
1844         if (eth_dev->data->mac_addrs)
1845                 rte_free(eth_dev->data->mac_addrs);
1846
1847         eth_dev->data->mac_addrs = NULL;
1848
1849         return 0;
1850 }
1851
1852 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1853 {
1854         return qede_dev_common_uninit(eth_dev);
1855 }
1856
1857 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1858 {
1859         return qede_dev_common_uninit(eth_dev);
1860 }
1861
1862 static struct rte_pci_id pci_id_qedevf_map[] = {
1863 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1864         {
1865                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF)
1866         },
1867         {
1868                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV)
1869         },
1870         {.vendor_id = 0,}
1871 };
1872
1873 static struct rte_pci_id pci_id_qede_map[] = {
1874 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1875         {
1876                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E)
1877         },
1878         {
1879                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S)
1880         },
1881         {
1882                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40)
1883         },
1884         {
1885                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25)
1886         },
1887         {
1888                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100)
1889         },
1890         {.vendor_id = 0,}
1891 };
1892
1893 static struct eth_driver rte_qedevf_pmd = {
1894         .pci_drv = {
1895                     .id_table = pci_id_qedevf_map,
1896                     .drv_flags =
1897                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1898                     .probe = rte_eth_dev_pci_probe,
1899                     .remove = rte_eth_dev_pci_remove,
1900                    },
1901         .eth_dev_init = qedevf_eth_dev_init,
1902         .eth_dev_uninit = qedevf_eth_dev_uninit,
1903         .dev_private_size = sizeof(struct qede_dev),
1904 };
1905
1906 static struct eth_driver rte_qede_pmd = {
1907         .pci_drv = {
1908                     .id_table = pci_id_qede_map,
1909                     .drv_flags =
1910                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1911                     .probe = rte_eth_dev_pci_probe,
1912                     .remove = rte_eth_dev_pci_remove,
1913                    },
1914         .eth_dev_init = qede_eth_dev_init,
1915         .eth_dev_uninit = qede_eth_dev_uninit,
1916         .dev_private_size = sizeof(struct qede_dev),
1917 };
1918
1919 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv);
1920 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
1921 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv);
1922 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);