drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12 #include <rte_kvargs.h>
  13
  14 /* Globals */
  15 static const struct qed_eth_ops *qed_ops;
  16 static int64_t timer_period = 1;
  17
  18 /* VXLAN tunnel classification mapping */
  19 const struct _qede_vxlan_tunn_types {
  20         uint16_t rte_filter_type;
  21         enum ecore_filter_ucast_type qede_type;
  22         enum ecore_tunn_clss qede_tunn_clss;
  23         const char *string;
  24 } qede_tunn_types[] = {
  25         {
  26                 ETH_TUNNEL_FILTER_OMAC,
  27                 ECORE_FILTER_MAC,
  28                 ECORE_TUNN_CLSS_MAC_VLAN,
  29                 "outer-mac"
  30         },
  31         {
  32                 ETH_TUNNEL_FILTER_TENID,
  33                 ECORE_FILTER_VNI,
  34                 ECORE_TUNN_CLSS_MAC_VNI,
  35                 "vni"
  36         },
  37         {
  38                 ETH_TUNNEL_FILTER_IMAC,
  39                 ECORE_FILTER_INNER_MAC,
  40                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  41                 "inner-mac"
  42         },
  43         {
  44                 ETH_TUNNEL_FILTER_IVLAN,
  45                 ECORE_FILTER_INNER_VLAN,
  46                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  47                 "inner-vlan"
  48         },
  49         {
  50                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  51                 ECORE_FILTER_MAC_VNI_PAIR,
  52                 ECORE_TUNN_CLSS_MAC_VNI,
  53                 "outer-mac and vni"
  54         },
  55         {
  56                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  57                 ECORE_FILTER_UNUSED,
  58                 MAX_ECORE_TUNN_CLSS,
  59                 "outer-mac and inner-mac"
  60         },
  61         {
  62                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  63                 ECORE_FILTER_UNUSED,
  64                 MAX_ECORE_TUNN_CLSS,
  65                 "outer-mac and inner-vlan"
  66         },
  67         {
  68                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  69                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  70                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  71                 "vni and inner-mac",
  72         },
  73         {
  74                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  75                 ECORE_FILTER_UNUSED,
  76                 MAX_ECORE_TUNN_CLSS,
  77                 "vni and inner-vlan",
  78         },
  79         {
  80                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  81                 ECORE_FILTER_INNER_PAIR,
  82                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  83                 "inner-mac and inner-vlan",
  84         },
  85         {
  86                 ETH_TUNNEL_FILTER_OIP,
  87                 ECORE_FILTER_UNUSED,
  88                 MAX_ECORE_TUNN_CLSS,
  89                 "outer-IP"
  90         },
  91         {
  92                 ETH_TUNNEL_FILTER_IIP,
  93                 ECORE_FILTER_UNUSED,
  94                 MAX_ECORE_TUNN_CLSS,
  95                 "inner-IP"
  96         },
  97         {
  98                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  99                 ECORE_FILTER_UNUSED,
 100                 MAX_ECORE_TUNN_CLSS,
 101                 "IMAC_IVLAN"
 102         },
 103         {
 104                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 105                 ECORE_FILTER_UNUSED,
 106                 MAX_ECORE_TUNN_CLSS,
 107                 "IMAC_IVLAN_TENID"
 108         },
 109         {
 110                 RTE_TUNNEL_FILTER_IMAC_TENID,
 111                 ECORE_FILTER_UNUSED,
 112                 MAX_ECORE_TUNN_CLSS,
 113                 "IMAC_TENID"
 114         },
 115         {
 116                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 117                 ECORE_FILTER_UNUSED,
 118                 MAX_ECORE_TUNN_CLSS,
 119                 "OMAC_TENID_IMAC"
 120         },
 121 };
 122
 123 struct rte_qede_xstats_name_off {
 124         char name[RTE_ETH_XSTATS_NAME_SIZE];
 125         uint64_t offset;
 126 };
 127
 128 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 129         {"rx_unicast_bytes",
 130                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 131         {"rx_multicast_bytes",
 132                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 133         {"rx_broadcast_bytes",
 134                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 135         {"rx_unicast_packets",
 136                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 137         {"rx_multicast_packets",
 138                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 139         {"rx_broadcast_packets",
 140                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 141
 142         {"tx_unicast_bytes",
 143                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 144         {"tx_multicast_bytes",
 145                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 146         {"tx_broadcast_bytes",
 147                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 148         {"tx_unicast_packets",
 149                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 150         {"tx_multicast_packets",
 151                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 152         {"tx_broadcast_packets",
 153                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 154
 155         {"rx_64_byte_packets",
 156                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 157         {"rx_65_to_127_byte_packets",
 158                 offsetof(struct ecore_eth_stats_common,
 159                          rx_65_to_127_byte_packets)},
 160         {"rx_128_to_255_byte_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          rx_128_to_255_byte_packets)},
 163         {"rx_256_to_511_byte_packets",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          rx_256_to_511_byte_packets)},
 166         {"rx_512_to_1023_byte_packets",
 167                 offsetof(struct ecore_eth_stats_common,
 168                          rx_512_to_1023_byte_packets)},
 169         {"rx_1024_to_1518_byte_packets",
 170                 offsetof(struct ecore_eth_stats_common,
 171                          rx_1024_to_1518_byte_packets)},
 172         {"tx_64_byte_packets",
 173                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 174         {"tx_65_to_127_byte_packets",
 175                 offsetof(struct ecore_eth_stats_common,
 176                          tx_65_to_127_byte_packets)},
 177         {"tx_128_to_255_byte_packets",
 178                 offsetof(struct ecore_eth_stats_common,
 179                          tx_128_to_255_byte_packets)},
 180         {"tx_256_to_511_byte_packets",
 181                 offsetof(struct ecore_eth_stats_common,
 182                          tx_256_to_511_byte_packets)},
 183         {"tx_512_to_1023_byte_packets",
 184                 offsetof(struct ecore_eth_stats_common,
 185                          tx_512_to_1023_byte_packets)},
 186         {"tx_1024_to_1518_byte_packets",
 187                 offsetof(struct ecore_eth_stats_common,
 188                          tx_1024_to_1518_byte_packets)},
 189
 190         {"rx_mac_crtl_frames",
 191                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 192         {"tx_mac_control_frames",
 193                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 194         {"rx_pause_frames",
 195                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 196         {"tx_pause_frames",
 197                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 198         {"rx_priority_flow_control_frames",
 199                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 200         {"tx_priority_flow_control_frames",
 201                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 202
 203         {"rx_crc_errors",
 204                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 205         {"rx_align_errors",
 206                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 207         {"rx_carrier_errors",
 208                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 209         {"rx_oversize_packet_errors",
 210                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 211         {"rx_jabber_errors",
 212                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 213         {"rx_undersize_packet_errors",
 214                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 215         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 216         {"rx_host_buffer_not_available",
 217                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 218         /* Number of packets discarded because they are bigger than MTU */
 219         {"rx_packet_too_big_discards",
 220                 offsetof(struct ecore_eth_stats_common,
 221                          packet_too_big_discard)},
 222         {"rx_ttl_zero_discards",
 223                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 224         {"rx_multi_function_tag_filter_discards",
 225                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 226         {"rx_mac_filter_discards",
 227                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 228         {"rx_hw_buffer_truncates",
 229                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 230         {"rx_hw_buffer_discards",
 231                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 232         {"tx_error_drop_packets",
 233                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 234
 235         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 236         {"rx_mac_unicast_packets",
 237                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 238         {"rx_mac_multicast_packets",
 239                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 240         {"rx_mac_broadcast_packets",
 241                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 242         {"rx_mac_frames_ok",
 243                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 244         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 245         {"tx_mac_unicast_packets",
 246                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 247         {"tx_mac_multicast_packets",
 248                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 249         {"tx_mac_broadcast_packets",
 250                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 251
 252         {"lro_coalesced_packets",
 253                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 254         {"lro_coalesced_events",
 255                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 256         {"lro_aborts_num",
 257                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 258         {"lro_not_coalesced_packets",
 259                 offsetof(struct ecore_eth_stats_common,
 260                          tpa_not_coalesced_pkts)},
 261         {"lro_coalesced_bytes",
 262                 offsetof(struct ecore_eth_stats_common,
 263                          tpa_coalesced_bytes)},
 264 };
 265
 266 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 267         {"rx_1519_to_1522_byte_packets",
 268                 offsetof(struct ecore_eth_stats, bb) +
 269                 offsetof(struct ecore_eth_stats_bb,
 270                          rx_1519_to_1522_byte_packets)},
 271         {"rx_1519_to_2047_byte_packets",
 272                 offsetof(struct ecore_eth_stats, bb) +
 273                 offsetof(struct ecore_eth_stats_bb,
 274                          rx_1519_to_2047_byte_packets)},
 275         {"rx_2048_to_4095_byte_packets",
 276                 offsetof(struct ecore_eth_stats, bb) +
 277                 offsetof(struct ecore_eth_stats_bb,
 278                          rx_2048_to_4095_byte_packets)},
 279         {"rx_4096_to_9216_byte_packets",
 280                 offsetof(struct ecore_eth_stats, bb) +
 281                 offsetof(struct ecore_eth_stats_bb,
 282                          rx_4096_to_9216_byte_packets)},
 283         {"rx_9217_to_16383_byte_packets",
 284                 offsetof(struct ecore_eth_stats, bb) +
 285                 offsetof(struct ecore_eth_stats_bb,
 286                          rx_9217_to_16383_byte_packets)},
 287
 288         {"tx_1519_to_2047_byte_packets",
 289                 offsetof(struct ecore_eth_stats, bb) +
 290                 offsetof(struct ecore_eth_stats_bb,
 291                          tx_1519_to_2047_byte_packets)},
 292         {"tx_2048_to_4095_byte_packets",
 293                 offsetof(struct ecore_eth_stats, bb) +
 294                 offsetof(struct ecore_eth_stats_bb,
 295                          tx_2048_to_4095_byte_packets)},
 296         {"tx_4096_to_9216_byte_packets",
 297                 offsetof(struct ecore_eth_stats, bb) +
 298                 offsetof(struct ecore_eth_stats_bb,
 299                          tx_4096_to_9216_byte_packets)},
 300         {"tx_9217_to_16383_byte_packets",
 301                 offsetof(struct ecore_eth_stats, bb) +
 302                 offsetof(struct ecore_eth_stats_bb,
 303                          tx_9217_to_16383_byte_packets)},
 304
 305         {"tx_lpi_entry_count",
 306                 offsetof(struct ecore_eth_stats, bb) +
 307                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 308         {"tx_total_collisions",
 309                 offsetof(struct ecore_eth_stats, bb) +
 310                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 311 };
 312
 313 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 314         {"rx_1519_to_max_byte_packets",
 315                 offsetof(struct ecore_eth_stats, ah) +
 316                 offsetof(struct ecore_eth_stats_ah,
 317                          rx_1519_to_max_byte_packets)},
 318         {"tx_1519_to_max_byte_packets",
 319                 offsetof(struct ecore_eth_stats, ah) +
 320                 offsetof(struct ecore_eth_stats_ah,
 321                          tx_1519_to_max_byte_packets)},
 322 };
 323
 324 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 325         {"rx_q_segments",
 326                 offsetof(struct qede_rx_queue, rx_segs)},
 327         {"rx_q_hw_errors",
 328                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 329         {"rx_q_allocation_errors",
 330                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 331 };
 332
 333 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 334 {
 335         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 336 }
 337
 338 static void
 339 qede_interrupt_handler(void *param)
 340 {
 341         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 342         struct qede_dev *qdev = eth_dev->data->dev_private;
 343         struct ecore_dev *edev = &qdev->edev;
 344
 345         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 346         if (rte_intr_enable(eth_dev->intr_handle))
 347                 DP_ERR(edev, "rte_intr_enable failed\n");
 348 }
 349
 350 static void
 351 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 352 {
 353         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 354         qdev->ops = qed_ops;
 355 }
 356
 357 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 358 static void qede_print_adapter_info(struct qede_dev *qdev)
 359 {
 360         struct ecore_dev *edev = &qdev->edev;
 361         struct qed_dev_info *info = &qdev->dev_info.common;
 362         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 363         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 364
 365         DP_INFO(edev, "*********************************\n");
 366         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 367         DP_INFO(edev, " Chip details : %s %c%d\n",
 368                   ECORE_IS_BB(edev) ? "BB" : "AH",
 369                   'A' + edev->chip_rev,
 370                   (int)edev->chip_metal);
 371         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 372                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 373         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 374                  ver_str, QEDE_PMD_VERSION);
 375         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 376         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 377
 378         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 379                  "%d.%d.%d.%d",
 380                 (info->mfw_rev >> 24) & 0xff,
 381                 (info->mfw_rev >> 16) & 0xff,
 382                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 383         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 384         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 385         DP_INFO(edev, "*********************************\n");
 386 }
 387 #endif
 388
 389 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 390 {
 391 #ifdef RTE_LIBRTE_QEDE_DEBUG_DRIVER
 392         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 393 #endif
 394         unsigned int i = 0, j = 0, qid;
 395         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 396         struct qede_tx_queue *txq;
 397
 398         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 399
 400         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 401                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 402         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 403                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 404
 405         for_each_rss(qid) {
 406                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 407                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 408                             sizeof(uint64_t));
 409                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 410                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 411                             sizeof(uint64_t));
 412                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 413                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 414                             sizeof(uint64_t));
 415
 416                 if (xstats)
 417                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 418                                 OSAL_MEMSET((((char *)
 419                                               (qdev->fp_array[qid].rxq)) +
 420                                              qede_rxq_xstats_strings[j].offset),
 421                                             0,
 422                                             sizeof(uint64_t));
 423
 424                 i++;
 425                 if (i == rxq_stat_cntrs)
 426                         break;
 427         }
 428
 429         i = 0;
 430
 431         for_each_tss(qid) {
 432                 txq = qdev->fp_array[qid].txq;
 433
 434                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 435                                 (((uint64_t)(uintptr_t)(txq)) +
 436                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 437                             sizeof(uint64_t));
 438
 439                 i++;
 440                 if (i == txq_stat_cntrs)
 441                         break;
 442         }
 443 }
 444
 445 static int
 446 qede_stop_vport(struct ecore_dev *edev)
 447 {
 448         struct ecore_hwfn *p_hwfn;
 449         uint8_t vport_id;
 450         int rc;
 451         int i;
 452
 453         vport_id = 0;
 454         for_each_hwfn(edev, i) {
 455                 p_hwfn = &edev->hwfns[i];
 456                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 457                                          vport_id);
 458                 if (rc != ECORE_SUCCESS) {
 459                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 460                         return rc;
 461                 }
 462         }
 463
 464         DP_INFO(edev, "vport stopped\n");
 465
 466         return 0;
 467 }
 468
 469 static int
 470 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 471 {
 472         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 473         struct ecore_sp_vport_start_params params;
 474         struct ecore_hwfn *p_hwfn;
 475         int rc;
 476         int i;
 477
 478         if (qdev->vport_started)
 479                 qede_stop_vport(edev);
 480
 481         memset(&params, 0, sizeof(params));
 482         params.vport_id = 0;
 483         params.mtu = mtu;
 484         /* @DPDK - Disable FW placement */
 485         params.zero_placement_offset = 1;
 486         for_each_hwfn(edev, i) {
 487                 p_hwfn = &edev->hwfns[i];
 488                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 489                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 490                 rc = ecore_sp_vport_start(p_hwfn, &params);
 491                 if (rc != ECORE_SUCCESS) {
 492                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 493                         return rc;
 494                 }
 495         }
 496         ecore_reset_vport_stats(edev);
 497         qdev->vport_started = true;
 498         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 499
 500         return 0;
 501 }
 502
 503 /* Activate or deactivate vport via vport-update */
 504 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 505 {
 506         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 507         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 508         struct ecore_sp_vport_update_params params;
 509         struct ecore_hwfn *p_hwfn;
 510         uint8_t i;
 511         int rc = -1;
 512
 513         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 514         params.vport_id = 0;
 515         params.update_vport_active_rx_flg = 1;
 516         params.update_vport_active_tx_flg = 1;
 517         params.vport_active_rx_flg = flg;
 518         params.vport_active_tx_flg = flg;
 519         if (!qdev->enable_tx_switching) {
 520                 if (IS_VF(edev)) {
 521                         params.update_tx_switching_flg = 1;
 522                         params.tx_switching_flg = !flg;
 523                         DP_INFO(edev, "VF tx-switching is disabled\n");
 524                 }
 525         }
 526         for_each_hwfn(edev, i) {
 527                 p_hwfn = &edev->hwfns[i];
 528                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 529                 rc = ecore_sp_vport_update(p_hwfn, &params,
 530                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 531                 if (rc != ECORE_SUCCESS) {
 532                         DP_ERR(edev, "Failed to update vport\n");
 533                         break;
 534                 }
 535         }
 536         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 537
 538         return rc;
 539 }
 540
 541 static void
 542 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 543                            uint16_t mtu, bool enable)
 544 {
 545         /* Enable LRO in split mode */
 546         sge_tpa_params->tpa_ipv4_en_flg = enable;
 547         sge_tpa_params->tpa_ipv6_en_flg = enable;
 548         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 549         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 550         /* set if tpa enable changes */
 551         sge_tpa_params->update_tpa_en_flg = 1;
 552         /* set if tpa parameters should be handled */
 553         sge_tpa_params->update_tpa_param_flg = enable;
 554
 555         sge_tpa_params->max_buffers_per_cqe = 20;
 556         /* Enable TPA in split mode. In this mode each TPA segment
 557          * starts on the new BD, so there is one BD per segment.
 558          */
 559         sge_tpa_params->tpa_pkt_split_flg = 1;
 560         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 561         sge_tpa_params->tpa_gro_consistent_flg = 0;
 562         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 563         sge_tpa_params->tpa_max_size = 0x7FFF;
 564         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 565         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 566 }
 567
 568 /* Enable/disable LRO via vport-update */
 569 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 570 {
 571         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 572         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 573         struct ecore_sp_vport_update_params params;
 574         struct ecore_sge_tpa_params tpa_params;
 575         struct ecore_hwfn *p_hwfn;
 576         int rc;
 577         int i;
 578
 579         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 580         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 581         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 582         params.vport_id = 0;
 583         params.sge_tpa_params = &tpa_params;
 584         for_each_hwfn(edev, i) {
 585                 p_hwfn = &edev->hwfns[i];
 586                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 587                 rc = ecore_sp_vport_update(p_hwfn, &params,
 588                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 589                 if (rc != ECORE_SUCCESS) {
 590                         DP_ERR(edev, "Failed to update LRO\n");
 591                         return -1;
 592                 }
 593         }
 594         qdev->enable_lro = flg;
 595         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 596
 597         return 0;
 598 }
 599
 600 /* Update MTU via vport-update without doing port restart.
 601  * The vport must be deactivated before calling this API.
 602  */
 603 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 604 {
 605         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 606         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 607         struct ecore_sp_vport_update_params params;
 608         struct ecore_hwfn *p_hwfn;
 609         int rc;
 610         int i;
 611
 612         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 613         params.vport_id = 0;
 614         params.mtu = mtu;
 615         params.vport_id = 0;
 616         for_each_hwfn(edev, i) {
 617                 p_hwfn = &edev->hwfns[i];
 618                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 619                 rc = ecore_sp_vport_update(p_hwfn, &params,
 620                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 621                 if (rc != ECORE_SUCCESS) {
 622                         DP_ERR(edev, "Failed to update MTU\n");
 623                         return -1;
 624                 }
 625         }
 626         DP_INFO(edev, "MTU updated to %u\n", mtu);
 627
 628         return 0;
 629 }
 630
 631 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 632 {
 633         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 634         ucast->is_rx_filter = true;
 635         ucast->is_tx_filter = true;
 636         /* ucast->assert_on_error = true; - For debug */
 637 }
 638
 639 static int
 640 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 641                              enum qed_filter_rx_mode_type type)
 642 {
 643         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 644         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 645         struct ecore_filter_accept_flags flags;
 646
 647         memset(&flags, 0, sizeof(flags));
 648
 649         flags.update_rx_mode_config = 1;
 650         flags.update_tx_mode_config = 1;
 651         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 652                 ECORE_ACCEPT_MCAST_MATCHED |
 653                 ECORE_ACCEPT_BCAST;
 654
 655         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 656                 ECORE_ACCEPT_MCAST_MATCHED |
 657                 ECORE_ACCEPT_BCAST;
 658
 659         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 660                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 661                 if (IS_VF(edev)) {
 662                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 663                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 664                 }
 665         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 666                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 667         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 668                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 669                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 670                         ECORE_ACCEPT_MCAST_UNMATCHED;
 671         }
 672
 673         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 674                         ECORE_SPQ_MODE_CB, NULL);
 675 }
 676
 677 static int
 678 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 679                   bool enable, bool mask)
 680 {
 681         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 682         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 683         enum _ecore_status_t rc = ECORE_INVAL;
 684         struct ecore_ptt *p_ptt;
 685         struct ecore_tunnel_info tunn;
 686         struct ecore_hwfn *p_hwfn;
 687         int i;
 688
 689         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 690         tunn.vxlan.b_update_mode = enable;
 691         tunn.vxlan.b_mode_enabled = mask;
 692         tunn.b_update_rx_cls = true;
 693         tunn.b_update_tx_cls = true;
 694         tunn.vxlan.tun_cls = clss;
 695
 696         for_each_hwfn(edev, i) {
 697                 p_hwfn = &edev->hwfns[i];
 698                 if (IS_PF(edev)) {
 699                         p_ptt = ecore_ptt_acquire(p_hwfn);
 700                         if (!p_ptt)
 701                                 return -EAGAIN;
 702                 } else {
 703                         p_ptt = NULL;
 704                 }
 705                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 706                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
 707                 if (rc != ECORE_SUCCESS) {
 708                         DP_ERR(edev, "Failed to update tunn_clss %u\n",
 709                                         tunn.vxlan.tun_cls);
 710                         if (IS_PF(edev))
 711                                 ecore_ptt_release(p_hwfn, p_ptt);
 712                         break;
 713                 }
 714         }
 715
 716         if (rc == ECORE_SUCCESS) {
 717                 qdev->vxlan.enable = enable;
 718                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 719                 DP_INFO(edev, "vxlan is %s\n", enable ? "enabled" : "disabled");
 720         }
 721
 722         return rc;
 723 }
 724
 725 static int
 726 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 727                   bool add)
 728 {
 729         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 730         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 731         struct qede_ucast_entry *tmp = NULL;
 732         struct qede_ucast_entry *u;
 733         struct ether_addr *mac_addr;
 734
 735         mac_addr  = (struct ether_addr *)ucast->mac;
 736         if (add) {
 737                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 738                         if ((memcmp(mac_addr, &tmp->mac,
 739                                     ETHER_ADDR_LEN) == 0) &&
 740                              ucast->vni == tmp->vni &&
 741                              ucast->vlan == tmp->vlan) {
 742                                 DP_INFO(edev, "Unicast MAC is already added"
 743                                         " with vlan = %u, vni = %u\n",
 744                                         ucast->vlan,  ucast->vni);
 745                                         return 0;
 746                         }
 747                 }
 748                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 749                                RTE_CACHE_LINE_SIZE);
 750                 if (!u) {
 751                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 752                         return -ENOMEM;
 753                 }
 754                 ether_addr_copy(mac_addr, &u->mac);
 755                 u->vlan = ucast->vlan;
 756                 u->vni = ucast->vni;
 757                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 758                 qdev->num_uc_addr++;
 759         } else {
 760                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 761                         if ((memcmp(mac_addr, &tmp->mac,
 762                                     ETHER_ADDR_LEN) == 0) &&
 763                             ucast->vlan == tmp->vlan      &&
 764                             ucast->vni == tmp->vni)
 765                         break;
 766                 }
 767                 if (tmp == NULL) {
 768                         DP_INFO(edev, "Unicast MAC is not found\n");
 769                         return -EINVAL;
 770                 }
 771                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 772                 qdev->num_uc_addr--;
 773         }
 774
 775         return 0;
 776 }
 777
 778 static int
 779 qede_add_mcast_filters(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
 780                        uint32_t mc_addrs_num)
 781 {
 782         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 783         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 784         struct ecore_filter_mcast mcast;
 785         struct qede_mcast_entry *m = NULL;
 786         uint8_t i;
 787         int rc;
 788
 789         for (i = 0; i < mc_addrs_num; i++) {
 790                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 791                                RTE_CACHE_LINE_SIZE);
 792                 if (!m) {
 793                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 794                         return -ENOMEM;
 795                 }
 796                 ether_addr_copy(&mc_addrs[i], &m->mac);
 797                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 798         }
 799         memset(&mcast, 0, sizeof(mcast));
 800         mcast.num_mc_addrs = mc_addrs_num;
 801         mcast.opcode = ECORE_FILTER_ADD;
 802         for (i = 0; i < mc_addrs_num; i++)
 803                 ether_addr_copy(&mc_addrs[i], (struct ether_addr *)
 804                                                         &mcast.mac[i]);
 805         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 806         if (rc != ECORE_SUCCESS) {
 807                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 808                 return -1;
 809         }
 810
 811         return 0;
 812 }
 813
 814 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 815 {
 816         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 817         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 818         struct qede_mcast_entry *tmp = NULL;
 819         struct ecore_filter_mcast mcast;
 820         int j;
 821         int rc;
 822
 823         memset(&mcast, 0, sizeof(mcast));
 824         mcast.num_mc_addrs = qdev->num_mc_addr;
 825         mcast.opcode = ECORE_FILTER_REMOVE;
 826         j = 0;
 827         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 828                 ether_addr_copy(&tmp->mac, (struct ether_addr *)&mcast.mac[j]);
 829                 j++;
 830         }
 831         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 832         if (rc != ECORE_SUCCESS) {
 833                 DP_ERR(edev, "Failed to delete multicast filter\n");
 834                 return -1;
 835         }
 836         /* Init the list */
 837         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 838                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 839                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 840         }
 841         SLIST_INIT(&qdev->mc_list_head);
 842
 843         return 0;
 844 }
 845
 846 static enum _ecore_status_t
 847 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 848                  bool add)
 849 {
 850         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 851         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 852         enum _ecore_status_t rc = ECORE_INVAL;
 853
 854         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 855                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 856                               " Please enable promisc mode\n");
 857                         return ECORE_INVAL;
 858         }
 859
 860         rc = qede_ucast_filter(eth_dev, ucast, add);
 861         if (rc == 0)
 862                 rc = ecore_filter_ucast_cmd(edev, ucast,
 863                                             ECORE_SPQ_MODE_CB, NULL);
 864         if (rc != ECORE_SUCCESS)
 865                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 866                        rc, add);
 867
 868         return rc;
 869 }
 870
 871 static int
 872 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 873                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 874 {
 875         struct ecore_filter_ucast ucast;
 876         int re;
 877
 878         qede_set_ucast_cmn_params(&ucast);
 879         ucast.type = ECORE_FILTER_MAC;
 880         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 881         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 882         return re;
 883 }
 884
 885 static void
 886 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 887 {
 888         struct qede_dev *qdev = eth_dev->data->dev_private;
 889         struct ecore_dev *edev = &qdev->edev;
 890         struct ecore_filter_ucast ucast;
 891
 892         PMD_INIT_FUNC_TRACE(edev);
 893
 894         if (index >= qdev->dev_info.num_mac_filters) {
 895                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 896                        index, qdev->dev_info.num_mac_filters);
 897                 return;
 898         }
 899
 900         qede_set_ucast_cmn_params(&ucast);
 901         ucast.opcode = ECORE_FILTER_REMOVE;
 902         ucast.type = ECORE_FILTER_MAC;
 903
 904         /* Use the index maintained by rte */
 905         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 906                         (struct ether_addr *)&ucast.mac);
 907
 908         qede_mac_int_ops(eth_dev, &ucast, false);
 909 }
 910
 911 static void
 912 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 913 {
 914         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 915         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 916
 917         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 918                                                mac_addr->addr_bytes)) {
 919                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 920                 ether_addr_copy(&qdev->primary_mac,
 921                                 &eth_dev->data->mac_addrs[0]);
 922                 return;
 923         }
 924
 925         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 926 }
 927
 928 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 929 {
 930         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 931         struct ecore_sp_vport_update_params params;
 932         struct ecore_hwfn *p_hwfn;
 933         uint8_t i;
 934         int rc;
 935
 936         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 937         params.vport_id = 0;
 938         params.update_accept_any_vlan_flg = 1;
 939         params.accept_any_vlan = flg;
 940         for_each_hwfn(edev, i) {
 941                 p_hwfn = &edev->hwfns[i];
 942                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 943                 rc = ecore_sp_vport_update(p_hwfn, &params,
 944                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 945                 if (rc != ECORE_SUCCESS) {
 946                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 947                         return;
 948                 }
 949         }
 950
 951         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 952 }
 953
 954 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 955 {
 956         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 957         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 958         struct ecore_sp_vport_update_params params;
 959         struct ecore_hwfn *p_hwfn;
 960         uint8_t i;
 961         int rc;
 962
 963         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 964         params.vport_id = 0;
 965         params.update_inner_vlan_removal_flg = 1;
 966         params.inner_vlan_removal_flg = flg;
 967         for_each_hwfn(edev, i) {
 968                 p_hwfn = &edev->hwfns[i];
 969                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 970                 rc = ecore_sp_vport_update(p_hwfn, &params,
 971                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 972                 if (rc != ECORE_SUCCESS) {
 973                         DP_ERR(edev, "Failed to update vport\n");
 974                         return -1;
 975                 }
 976         }
 977
 978         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 979         return 0;
 980 }
 981
 982 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 983                                 uint16_t vlan_id, int on)
 984 {
 985         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 986         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 987         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 988         struct qede_vlan_entry *tmp = NULL;
 989         struct qede_vlan_entry *vlan;
 990         struct ecore_filter_ucast ucast;
 991         int rc;
 992
 993         if (on) {
 994                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 995                         DP_ERR(edev, "Reached max VLAN filter limit"
 996                                       " enabling accept_any_vlan\n");
 997                         qede_config_accept_any_vlan(qdev, true);
 998                         return 0;
 999                 }
1000
1001                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1002                         if (tmp->vid == vlan_id) {
1003                                 DP_INFO(edev, "VLAN %u already configured\n",
1004                                         vlan_id);
1005                                 return 0;
1006                         }
1007                 }
1008
1009                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1010                                   RTE_CACHE_LINE_SIZE);
1011
1012                 if (!vlan) {
1013                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
1014                         return -ENOMEM;
1015                 }
1016
1017                 qede_set_ucast_cmn_params(&ucast);
1018                 ucast.opcode = ECORE_FILTER_ADD;
1019                 ucast.type = ECORE_FILTER_VLAN;
1020                 ucast.vlan = vlan_id;
1021                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1022                                             NULL);
1023                 if (rc != 0) {
1024                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1025                                rc);
1026                         rte_free(vlan);
1027                 } else {
1028                         vlan->vid = vlan_id;
1029                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1030                         qdev->configured_vlans++;
1031                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1032                                 vlan_id, qdev->configured_vlans);
1033                 }
1034         } else {
1035                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1036                         if (tmp->vid == vlan_id)
1037                                 break;
1038                 }
1039
1040                 if (!tmp) {
1041                         if (qdev->configured_vlans == 0) {
1042                                 DP_INFO(edev,
1043                                         "No VLAN filters configured yet\n");
1044                                 return 0;
1045                         }
1046
1047                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1048                         return -EINVAL;
1049                 }
1050
1051                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1052
1053                 qede_set_ucast_cmn_params(&ucast);
1054                 ucast.opcode = ECORE_FILTER_REMOVE;
1055                 ucast.type = ECORE_FILTER_VLAN;
1056                 ucast.vlan = vlan_id;
1057                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1058                                             NULL);
1059                 if (rc != 0) {
1060                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1061                                vlan_id, rc);
1062                 } else {
1063                         qdev->configured_vlans--;
1064                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1065                                 vlan_id, qdev->configured_vlans);
1066                 }
1067         }
1068
1069         return rc;
1070 }
1071
1072 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1073 {
1074         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1075         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1076         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1077
1078         if (mask & ETH_VLAN_STRIP_MASK) {
1079                 if (rxmode->hw_vlan_strip)
1080                         (void)qede_vlan_stripping(eth_dev, 1);
1081                 else
1082                         (void)qede_vlan_stripping(eth_dev, 0);
1083         }
1084
1085         if (mask & ETH_VLAN_FILTER_MASK) {
1086                 /* VLAN filtering kicks in when a VLAN is added */
1087                 if (rxmode->hw_vlan_filter) {
1088                         qede_vlan_filter_set(eth_dev, 0, 1);
1089                 } else {
1090                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1091                                 DP_ERR(edev,
1092                                   " Please remove existing VLAN filters"
1093                                   " before disabling VLAN filtering\n");
1094                                 /* Signal app that VLAN filtering is still
1095                                  * enabled
1096                                  */
1097                                 rxmode->hw_vlan_filter = true;
1098                         } else {
1099                                 qede_vlan_filter_set(eth_dev, 0, 0);
1100                         }
1101                 }
1102         }
1103
1104         if (mask & ETH_VLAN_EXTEND_MASK)
1105                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1106                         " and classification is based on outer tag only\n");
1107
1108         qdev->vlan_offload_mask = mask;
1109
1110         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1111                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1112
1113         return 0;
1114 }
1115
1116 static void qede_prandom_bytes(uint32_t *buff)
1117 {
1118         uint8_t i;
1119
1120         srand((unsigned int)time(NULL));
1121         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1122                 buff[i] = rand();
1123 }
1124
1125 int qede_config_rss(struct rte_eth_dev *eth_dev)
1126 {
1127         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1128 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
1129         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1130 #endif
1131         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1132         struct rte_eth_rss_reta_entry64 reta_conf[2];
1133         struct rte_eth_rss_conf rss_conf;
1134         uint32_t i, id, pos, q;
1135
1136         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1137         if (!rss_conf.rss_key) {
1138                 DP_INFO(edev, "Applying driver default key\n");
1139                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1140                 qede_prandom_bytes(&def_rss_key[0]);
1141                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1142         }
1143
1144         /* Configure RSS hash */
1145         if (qede_rss_hash_update(eth_dev, &rss_conf))
1146                 return -EINVAL;
1147
1148         /* Configure default RETA */
1149         memset(reta_conf, 0, sizeof(reta_conf));
1150         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1151                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1152
1153         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1154                 id = i / RTE_RETA_GROUP_SIZE;
1155                 pos = i % RTE_RETA_GROUP_SIZE;
1156                 q = i % QEDE_RSS_COUNT(qdev);
1157                 reta_conf[id].reta[pos] = q;
1158         }
1159         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1160                                  ECORE_RSS_IND_TABLE_SIZE))
1161                 return -EINVAL;
1162
1163         return 0;
1164 }
1165
1166 static void qede_fastpath_start(struct ecore_dev *edev)
1167 {
1168         struct ecore_hwfn *p_hwfn;
1169         int i;
1170
1171         for_each_hwfn(edev, i) {
1172                 p_hwfn = &edev->hwfns[i];
1173                 ecore_hw_start_fastpath(p_hwfn);
1174         }
1175 }
1176
1177 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1178 {
1179         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1180         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1181         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1182
1183         PMD_INIT_FUNC_TRACE(edev);
1184
1185         /* Configure TPA parameters */
1186         if (rxmode->enable_lro) {
1187                 if (qede_enable_tpa(eth_dev, true))
1188                         return -EINVAL;
1189                 /* Enable scatter mode for LRO */
1190                 if (!rxmode->enable_scatter)
1191                         eth_dev->data->scattered_rx = 1;
1192         }
1193
1194         /* Start queues */
1195         if (qede_start_queues(eth_dev))
1196                 goto err;
1197
1198         if (IS_PF(edev))
1199                 qede_reset_queue_stats(qdev, true);
1200
1201         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1202          * enabling RSS. Hence RSS configuration is deferred upto this point.
1203          * Also, we would like to retain similar behavior in PF case, so we
1204          * don't do PF/VF specific check here.
1205          */
1206         if (rxmode->mq_mode == ETH_MQ_RX_RSS)
1207                 if (qede_config_rss(eth_dev))
1208                         goto err;
1209
1210         /* Enable vport*/
1211         if (qede_activate_vport(eth_dev, true))
1212                 goto err;
1213
1214         /* Update link status */
1215         qede_link_update(eth_dev, 0);
1216
1217         /* Start/resume traffic */
1218         qede_fastpath_start(edev);
1219
1220         DP_INFO(edev, "Device started\n");
1221
1222         return 0;
1223 err:
1224         DP_ERR(edev, "Device start fails\n");
1225         return -1; /* common error code is < 0 */
1226 }
1227
1228 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1229 {
1230         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1231         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1232
1233         PMD_INIT_FUNC_TRACE(edev);
1234
1235         /* Disable vport */
1236         if (qede_activate_vport(eth_dev, false))
1237                 return;
1238
1239         if (qdev->enable_lro)
1240                 qede_enable_tpa(eth_dev, false);
1241
1242         /* Stop queues */
1243         qede_stop_queues(eth_dev);
1244
1245         /* Disable traffic */
1246         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1247
1248         if (IS_PF(edev))
1249                 qede_mac_addr_remove(eth_dev, 0);
1250
1251         DP_INFO(edev, "Device is stopped\n");
1252 }
1253
1254 #define QEDE_TX_SWITCHING               "vf_txswitch"
1255
1256 const char *valid_args[] = {
1257         QEDE_TX_SWITCHING,
1258         NULL,
1259 };
1260
1261 static int qede_args_check(const char *key, const char *val, void *opaque)
1262 {
1263         unsigned long tmp;
1264         int ret = 0;
1265         struct rte_eth_dev *eth_dev = opaque;
1266         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1267 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
1268         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1269 #endif
1270
1271         errno = 0;
1272         tmp = strtoul(val, NULL, 0);
1273         if (errno) {
1274                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1275                 return errno;
1276         }
1277
1278         if (strcmp(QEDE_TX_SWITCHING, key) == 0)
1279                 qdev->enable_tx_switching = !!tmp;
1280
1281         return ret;
1282 }
1283
1284 static int qede_args(struct rte_eth_dev *eth_dev)
1285 {
1286         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1287         struct rte_kvargs *kvlist;
1288         struct rte_devargs *devargs;
1289         int ret;
1290         int i;
1291
1292         devargs = pci_dev->device.devargs;
1293         if (!devargs)
1294                 return 0; /* return success */
1295
1296         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1297         if (kvlist == NULL)
1298                 return -EINVAL;
1299
1300          /* Process parameters. */
1301         for (i = 0; (valid_args[i] != NULL); ++i) {
1302                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1303                         ret = rte_kvargs_process(kvlist, valid_args[i],
1304                                                  qede_args_check, eth_dev);
1305                         if (ret != ECORE_SUCCESS) {
1306                                 rte_kvargs_free(kvlist);
1307                                 return ret;
1308                         }
1309                 }
1310         }
1311         rte_kvargs_free(kvlist);
1312
1313         return 0;
1314 }
1315
1316 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1317 {
1318         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1319         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1320         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1321         int ret;
1322
1323         PMD_INIT_FUNC_TRACE(edev);
1324
1325         /* Check requirements for 100G mode */
1326         if (ECORE_IS_CMT(edev)) {
1327                 if (eth_dev->data->nb_rx_queues < 2 ||
1328                                 eth_dev->data->nb_tx_queues < 2) {
1329                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1330                         return -EINVAL;
1331                 }
1332
1333                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1334                                 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1335                         DP_ERR(edev,
1336                                         "100G mode needs even no. of RX/TX queues\n");
1337                         return -EINVAL;
1338                 }
1339         }
1340
1341         /* We need to have min 1 RX queue.There is no min check in
1342          * rte_eth_dev_configure(), so we are checking it here.
1343          */
1344         if (eth_dev->data->nb_rx_queues == 0) {
1345                 DP_ERR(edev, "Minimum one RX queue is required\n");
1346                 return -EINVAL;
1347         }
1348
1349         /* Enable Tx switching by default */
1350         qdev->enable_tx_switching = 1;
1351
1352         /* Parse devargs and fix up rxmode */
1353         if (qede_args(eth_dev))
1354                 return -ENOTSUP;
1355
1356         /* Sanity checks and throw warnings */
1357         if (rxmode->enable_scatter)
1358                 eth_dev->data->scattered_rx = 1;
1359
1360         if (!rxmode->hw_strip_crc)
1361                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1362
1363         if (!rxmode->hw_ip_checksum)
1364                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1365                                 "in hw\n");
1366         if (rxmode->header_split)
1367                 DP_INFO(edev, "Header split enable is not supported\n");
1368         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1369                                 ETH_MQ_RX_RSS)) {
1370                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1371                 return -ENOTSUP;
1372         }
1373         /* Flow director mode check */
1374         if (qede_check_fdir_support(eth_dev))
1375                 return -ENOTSUP;
1376
1377         qede_dealloc_fp_resc(eth_dev);
1378         qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1379         qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1380         if (qede_alloc_fp_resc(qdev))
1381                 return -ENOMEM;
1382
1383         /* If jumbo enabled adjust MTU */
1384         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
1385                 eth_dev->data->mtu =
1386                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1387                                 ETHER_HDR_LEN - ETHER_CRC_LEN;
1388
1389         if (qede_start_vport(qdev, eth_dev->data->mtu))
1390                 return -1;
1391         qdev->mtu = eth_dev->data->mtu;
1392
1393         /* Enable VLAN offloads by default */
1394         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1395                         ETH_VLAN_FILTER_MASK |
1396                         ETH_VLAN_EXTEND_MASK);
1397         if (ret)
1398                 return ret;
1399
1400         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1401                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1402
1403         return 0;
1404 }
1405
1406 /* Info about HW descriptor ring limitations */
1407 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1408         .nb_max = 0x8000, /* 32K */
1409         .nb_min = 128,
1410         .nb_align = 128 /* lowest common multiple */
1411 };
1412
1413 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1414         .nb_max = 0x8000, /* 32K */
1415         .nb_min = 256,
1416         .nb_align = 256,
1417         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1418         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1419 };
1420
1421 static void
1422 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1423                   struct rte_eth_dev_info *dev_info)
1424 {
1425         struct qede_dev *qdev = eth_dev->data->dev_private;
1426         struct ecore_dev *edev = &qdev->edev;
1427         struct qed_link_output link;
1428         uint32_t speed_cap = 0;
1429
1430         PMD_INIT_FUNC_TRACE(edev);
1431
1432         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1433         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1434         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1435         dev_info->rx_desc_lim = qede_rx_desc_lim;
1436         dev_info->tx_desc_lim = qede_tx_desc_lim;
1437
1438         if (IS_PF(edev))
1439                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1440                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1441         else
1442                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1443                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1444         dev_info->max_tx_queues = dev_info->max_rx_queues;
1445
1446         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1447         dev_info->max_vfs = 0;
1448         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1449         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1450         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1451
1452         dev_info->default_txconf = (struct rte_eth_txconf) {
1453                 .txq_flags = QEDE_TXQ_FLAGS,
1454         };
1455
1456         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
1457                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
1458                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1459                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1460                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1461                                      DEV_RX_OFFLOAD_TCP_LRO);
1462
1463         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1464                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1465                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1466                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1467                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1468                                      DEV_TX_OFFLOAD_TCP_TSO |
1469                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1470
1471         memset(&link, 0, sizeof(struct qed_link_output));
1472         qdev->ops->common->get_link(edev, &link);
1473         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1474                 speed_cap |= ETH_LINK_SPEED_1G;
1475         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1476                 speed_cap |= ETH_LINK_SPEED_10G;
1477         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1478                 speed_cap |= ETH_LINK_SPEED_25G;
1479         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1480                 speed_cap |= ETH_LINK_SPEED_40G;
1481         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1482                 speed_cap |= ETH_LINK_SPEED_50G;
1483         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1484                 speed_cap |= ETH_LINK_SPEED_100G;
1485         dev_info->speed_capa = speed_cap;
1486 }
1487
1488 /* return 0 means link status changed, -1 means not changed */
1489 int
1490 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1491 {
1492         struct qede_dev *qdev = eth_dev->data->dev_private;
1493         struct ecore_dev *edev = &qdev->edev;
1494         uint16_t link_duplex;
1495         struct qed_link_output link;
1496         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1497
1498         memset(&link, 0, sizeof(struct qed_link_output));
1499         qdev->ops->common->get_link(edev, &link);
1500
1501         /* Link Speed */
1502         curr->link_speed = link.speed;
1503
1504         /* Link Mode */
1505         switch (link.duplex) {
1506         case QEDE_DUPLEX_HALF:
1507                 link_duplex = ETH_LINK_HALF_DUPLEX;
1508                 break;
1509         case QEDE_DUPLEX_FULL:
1510                 link_duplex = ETH_LINK_FULL_DUPLEX;
1511                 break;
1512         case QEDE_DUPLEX_UNKNOWN:
1513         default:
1514                 link_duplex = -1;
1515         }
1516         curr->link_duplex = link_duplex;
1517
1518         /* Link Status */
1519         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1520
1521         /* AN */
1522         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1523                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1524
1525         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1526                 curr->link_speed, curr->link_duplex,
1527                 curr->link_autoneg, curr->link_status);
1528
1529         /* return 0 means link status changed, -1 means not changed */
1530         return ((curr->link_status == link.link_up) ? -1 : 0);
1531 }
1532
1533 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1534 {
1535 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1536         struct qede_dev *qdev = eth_dev->data->dev_private;
1537         struct ecore_dev *edev = &qdev->edev;
1538
1539         PMD_INIT_FUNC_TRACE(edev);
1540 #endif
1541
1542         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1543
1544         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1545                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1546
1547         qed_configure_filter_rx_mode(eth_dev, type);
1548 }
1549
1550 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1551 {
1552 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1553         struct qede_dev *qdev = eth_dev->data->dev_private;
1554         struct ecore_dev *edev = &qdev->edev;
1555
1556         PMD_INIT_FUNC_TRACE(edev);
1557 #endif
1558
1559         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1560                 qed_configure_filter_rx_mode(eth_dev,
1561                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1562         else
1563                 qed_configure_filter_rx_mode(eth_dev,
1564                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1565 }
1566
1567 static void qede_poll_sp_sb_cb(void *param)
1568 {
1569         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1570         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1571         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1572         int rc;
1573
1574         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1575         qede_interrupt_action(&edev->hwfns[1]);
1576
1577         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1578                                qede_poll_sp_sb_cb,
1579                                (void *)eth_dev);
1580         if (rc != 0) {
1581                 DP_ERR(edev, "Unable to start periodic"
1582                              " timer rc %d\n", rc);
1583                 assert(false && "Unable to start periodic timer");
1584         }
1585 }
1586
1587 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1588 {
1589         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1590         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1591         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1592
1593         PMD_INIT_FUNC_TRACE(edev);
1594
1595         /* dev_stop() shall cleanup fp resources in hw but without releasing
1596          * dma memories and sw structures so that dev_start() can be called
1597          * by the app without reconfiguration. However, in dev_close() we
1598          * can release all the resources and device can be brought up newly
1599          */
1600         if (eth_dev->data->dev_started)
1601                 qede_dev_stop(eth_dev);
1602
1603         qede_stop_vport(edev);
1604         qdev->vport_started = false;
1605         qede_fdir_dealloc_resc(eth_dev);
1606         qede_dealloc_fp_resc(eth_dev);
1607
1608         eth_dev->data->nb_rx_queues = 0;
1609         eth_dev->data->nb_tx_queues = 0;
1610
1611         /* Bring the link down */
1612         qede_dev_set_link_state(eth_dev, false);
1613         qdev->ops->common->slowpath_stop(edev);
1614         qdev->ops->common->remove(edev);
1615         rte_intr_disable(&pci_dev->intr_handle);
1616         rte_intr_callback_unregister(&pci_dev->intr_handle,
1617                                      qede_interrupt_handler, (void *)eth_dev);
1618         if (ECORE_IS_CMT(edev))
1619                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1620 }
1621
1622 static int
1623 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1624 {
1625         struct qede_dev *qdev = eth_dev->data->dev_private;
1626         struct ecore_dev *edev = &qdev->edev;
1627         struct ecore_eth_stats stats;
1628         unsigned int i = 0, j = 0, qid;
1629         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1630         struct qede_tx_queue *txq;
1631
1632         ecore_get_vport_stats(edev, &stats);
1633
1634         /* RX Stats */
1635         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1636             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1637
1638         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1639             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1640
1641         eth_stats->ierrors = stats.common.rx_crc_errors +
1642             stats.common.rx_align_errors +
1643             stats.common.rx_carrier_errors +
1644             stats.common.rx_oversize_packets +
1645             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1646
1647         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1648
1649         eth_stats->imissed = stats.common.mftag_filter_discards +
1650             stats.common.mac_filter_discards +
1651             stats.common.no_buff_discards +
1652             stats.common.brb_truncates + stats.common.brb_discards;
1653
1654         /* TX stats */
1655         eth_stats->opackets = stats.common.tx_ucast_pkts +
1656             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1657
1658         eth_stats->obytes = stats.common.tx_ucast_bytes +
1659             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1660
1661         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1662
1663         /* Queue stats */
1664         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1665                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1666         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1667                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1668         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1669             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1670                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1671                        "Not all the queue stats will be displayed. Set"
1672                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1673                        " appropriately and retry.\n");
1674
1675         for_each_rss(qid) {
1676                 eth_stats->q_ipackets[i] =
1677                         *(uint64_t *)(
1678                                 ((char *)(qdev->fp_array[qid].rxq)) +
1679                                 offsetof(struct qede_rx_queue,
1680                                 rcv_pkts));
1681                 eth_stats->q_errors[i] =
1682                         *(uint64_t *)(
1683                                 ((char *)(qdev->fp_array[qid].rxq)) +
1684                                 offsetof(struct qede_rx_queue,
1685                                 rx_hw_errors)) +
1686                         *(uint64_t *)(
1687                                 ((char *)(qdev->fp_array[qid].rxq)) +
1688                                 offsetof(struct qede_rx_queue,
1689                                 rx_alloc_errors));
1690                 i++;
1691                 if (i == rxq_stat_cntrs)
1692                         break;
1693         }
1694
1695         for_each_tss(qid) {
1696                 txq = qdev->fp_array[qid].txq;
1697                 eth_stats->q_opackets[j] =
1698                         *((uint64_t *)(uintptr_t)
1699                                 (((uint64_t)(uintptr_t)(txq)) +
1700                                  offsetof(struct qede_tx_queue,
1701                                           xmit_pkts)));
1702                 j++;
1703                 if (j == txq_stat_cntrs)
1704                         break;
1705         }
1706
1707         return 0;
1708 }
1709
1710 static unsigned
1711 qede_get_xstats_count(struct qede_dev *qdev) {
1712         if (ECORE_IS_BB(&qdev->edev))
1713                 return RTE_DIM(qede_xstats_strings) +
1714                        RTE_DIM(qede_bb_xstats_strings) +
1715                        (RTE_DIM(qede_rxq_xstats_strings) *
1716                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1717                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1718         else
1719                 return RTE_DIM(qede_xstats_strings) +
1720                        RTE_DIM(qede_ah_xstats_strings) +
1721                        (RTE_DIM(qede_rxq_xstats_strings) *
1722                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1723                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1724 }
1725
1726 static int
1727 qede_get_xstats_names(struct rte_eth_dev *dev,
1728                       struct rte_eth_xstat_name *xstats_names,
1729                       __rte_unused unsigned int limit)
1730 {
1731         struct qede_dev *qdev = dev->data->dev_private;
1732         struct ecore_dev *edev = &qdev->edev;
1733         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1734         unsigned int i, qid, stat_idx = 0;
1735         unsigned int rxq_stat_cntrs;
1736
1737         if (xstats_names != NULL) {
1738                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1739                         snprintf(xstats_names[stat_idx].name,
1740                                 sizeof(xstats_names[stat_idx].name),
1741                                 "%s",
1742                                 qede_xstats_strings[i].name);
1743                         stat_idx++;
1744                 }
1745
1746                 if (ECORE_IS_BB(edev)) {
1747                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1748                                 snprintf(xstats_names[stat_idx].name,
1749                                         sizeof(xstats_names[stat_idx].name),
1750                                         "%s",
1751                                         qede_bb_xstats_strings[i].name);
1752                                 stat_idx++;
1753                         }
1754                 } else {
1755                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1756                                 snprintf(xstats_names[stat_idx].name,
1757                                         sizeof(xstats_names[stat_idx].name),
1758                                         "%s",
1759                                         qede_ah_xstats_strings[i].name);
1760                                 stat_idx++;
1761                         }
1762                 }
1763
1764                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1765                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1766                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1767                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1768                                 snprintf(xstats_names[stat_idx].name,
1769                                         sizeof(xstats_names[stat_idx].name),
1770                                         "%.4s%d%s",
1771                                         qede_rxq_xstats_strings[i].name, qid,
1772                                         qede_rxq_xstats_strings[i].name + 4);
1773                                 stat_idx++;
1774                         }
1775                 }
1776         }
1777
1778         return stat_cnt;
1779 }
1780
1781 static int
1782 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1783                 unsigned int n)
1784 {
1785         struct qede_dev *qdev = dev->data->dev_private;
1786         struct ecore_dev *edev = &qdev->edev;
1787         struct ecore_eth_stats stats;
1788         const unsigned int num = qede_get_xstats_count(qdev);
1789         unsigned int i, qid, stat_idx = 0;
1790         unsigned int rxq_stat_cntrs;
1791
1792         if (n < num)
1793                 return num;
1794
1795         ecore_get_vport_stats(edev, &stats);
1796
1797         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1798                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1799                                              qede_xstats_strings[i].offset);
1800                 xstats[stat_idx].id = stat_idx;
1801                 stat_idx++;
1802         }
1803
1804         if (ECORE_IS_BB(edev)) {
1805                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1806                         xstats[stat_idx].value =
1807                                         *(uint64_t *)(((char *)&stats) +
1808                                         qede_bb_xstats_strings[i].offset);
1809                         xstats[stat_idx].id = stat_idx;
1810                         stat_idx++;
1811                 }
1812         } else {
1813                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1814                         xstats[stat_idx].value =
1815                                         *(uint64_t *)(((char *)&stats) +
1816                                         qede_ah_xstats_strings[i].offset);
1817                         xstats[stat_idx].id = stat_idx;
1818                         stat_idx++;
1819                 }
1820         }
1821
1822         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1823                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1824         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1825                 for_each_rss(qid) {
1826                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1827                                 xstats[stat_idx].value = *(uint64_t *)(
1828                                         ((char *)(qdev->fp_array[qid].rxq)) +
1829                                          qede_rxq_xstats_strings[i].offset);
1830                                 xstats[stat_idx].id = stat_idx;
1831                                 stat_idx++;
1832                         }
1833                 }
1834         }
1835
1836         return stat_idx;
1837 }
1838
1839 static void
1840 qede_reset_xstats(struct rte_eth_dev *dev)
1841 {
1842         struct qede_dev *qdev = dev->data->dev_private;
1843         struct ecore_dev *edev = &qdev->edev;
1844
1845         ecore_reset_vport_stats(edev);
1846         qede_reset_queue_stats(qdev, true);
1847 }
1848
1849 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1850 {
1851         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1852         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1853         struct qed_link_params link_params;
1854         int rc;
1855
1856         DP_INFO(edev, "setting link state %d\n", link_up);
1857         memset(&link_params, 0, sizeof(link_params));
1858         link_params.link_up = link_up;
1859         rc = qdev->ops->common->set_link(edev, &link_params);
1860         if (rc != ECORE_SUCCESS)
1861                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1862
1863         return rc;
1864 }
1865
1866 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1867 {
1868         return qede_dev_set_link_state(eth_dev, true);
1869 }
1870
1871 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1872 {
1873         return qede_dev_set_link_state(eth_dev, false);
1874 }
1875
1876 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1877 {
1878         struct qede_dev *qdev = eth_dev->data->dev_private;
1879         struct ecore_dev *edev = &qdev->edev;
1880
1881         ecore_reset_vport_stats(edev);
1882         qede_reset_queue_stats(qdev, false);
1883 }
1884
1885 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1886 {
1887         enum qed_filter_rx_mode_type type =
1888             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1889
1890         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1891                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1892
1893         qed_configure_filter_rx_mode(eth_dev, type);
1894 }
1895
1896 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1897 {
1898         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1899                 qed_configure_filter_rx_mode(eth_dev,
1900                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1901         else
1902                 qed_configure_filter_rx_mode(eth_dev,
1903                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1904 }
1905
1906 static int
1907 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
1908                       uint32_t mc_addrs_num)
1909 {
1910         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1911         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1912         uint8_t i;
1913
1914         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1915                 DP_ERR(edev, "Reached max multicast filters limit,"
1916                              "Please enable multicast promisc mode\n");
1917                 return -ENOSPC;
1918         }
1919
1920         for (i = 0; i < mc_addrs_num; i++) {
1921                 if (!is_multicast_ether_addr(&mc_addrs[i])) {
1922                         DP_ERR(edev, "Not a valid multicast MAC\n");
1923                         return -EINVAL;
1924                 }
1925         }
1926
1927         /* Flush all existing entries */
1928         if (qede_del_mcast_filters(eth_dev))
1929                 return -1;
1930
1931         /* Set new mcast list */
1932         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1933 }
1934
1935 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1936                               struct rte_eth_fc_conf *fc_conf)
1937 {
1938         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1939         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1940         struct qed_link_output current_link;
1941         struct qed_link_params params;
1942
1943         memset(&current_link, 0, sizeof(current_link));
1944         qdev->ops->common->get_link(edev, &current_link);
1945
1946         memset(&params, 0, sizeof(params));
1947         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1948         if (fc_conf->autoneg) {
1949                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1950                         DP_ERR(edev, "Autoneg not supported\n");
1951                         return -EINVAL;
1952                 }
1953                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1954         }
1955
1956         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1957         if (fc_conf->mode == RTE_FC_FULL)
1958                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1959                                         QED_LINK_PAUSE_RX_ENABLE);
1960         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1961                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1962         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1963                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1964
1965         params.link_up = true;
1966         (void)qdev->ops->common->set_link(edev, &params);
1967
1968         return 0;
1969 }
1970
1971 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1972                               struct rte_eth_fc_conf *fc_conf)
1973 {
1974         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1975         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1976         struct qed_link_output current_link;
1977
1978         memset(&current_link, 0, sizeof(current_link));
1979         qdev->ops->common->get_link(edev, &current_link);
1980
1981         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1982                 fc_conf->autoneg = true;
1983
1984         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1985                                          QED_LINK_PAUSE_TX_ENABLE))
1986                 fc_conf->mode = RTE_FC_FULL;
1987         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1988                 fc_conf->mode = RTE_FC_RX_PAUSE;
1989         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1990                 fc_conf->mode = RTE_FC_TX_PAUSE;
1991         else
1992                 fc_conf->mode = RTE_FC_NONE;
1993
1994         return 0;
1995 }
1996
1997 static const uint32_t *
1998 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1999 {
2000         static const uint32_t ptypes[] = {
2001                 RTE_PTYPE_L2_ETHER,
2002                 RTE_PTYPE_L2_ETHER_VLAN,
2003                 RTE_PTYPE_L3_IPV4,
2004                 RTE_PTYPE_L3_IPV6,
2005                 RTE_PTYPE_L4_TCP,
2006                 RTE_PTYPE_L4_UDP,
2007                 RTE_PTYPE_TUNNEL_VXLAN,
2008                 RTE_PTYPE_L4_FRAG,
2009                 /* Inner */
2010                 RTE_PTYPE_INNER_L2_ETHER,
2011                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2012                 RTE_PTYPE_INNER_L3_IPV4,
2013                 RTE_PTYPE_INNER_L3_IPV6,
2014                 RTE_PTYPE_INNER_L4_TCP,
2015                 RTE_PTYPE_INNER_L4_UDP,
2016                 RTE_PTYPE_INNER_L4_FRAG,
2017                 RTE_PTYPE_UNKNOWN
2018         };
2019
2020         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2021                 return ptypes;
2022
2023         return NULL;
2024 }
2025
2026 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2027 {
2028         *rss_caps = 0;
2029         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2030         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2031         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2032         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2033         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2034         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2035         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2036         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2037 }
2038
2039 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2040                          struct rte_eth_rss_conf *rss_conf)
2041 {
2042         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2043         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2044         struct ecore_sp_vport_update_params vport_update_params;
2045         struct ecore_rss_params rss_params;
2046         struct ecore_hwfn *p_hwfn;
2047         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2048         uint64_t hf = rss_conf->rss_hf;
2049         uint8_t len = rss_conf->rss_key_len;
2050         uint8_t idx;
2051         uint8_t i;
2052         int rc;
2053
2054         memset(&vport_update_params, 0, sizeof(vport_update_params));
2055         memset(&rss_params, 0, sizeof(rss_params));
2056
2057         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2058                 (unsigned long)hf, len, key);
2059
2060         if (hf != 0) {
2061                 /* Enabling RSS */
2062                 DP_INFO(edev, "Enabling rss\n");
2063
2064                 /* RSS caps */
2065                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2066                 rss_params.update_rss_capabilities = 1;
2067
2068                 /* RSS hash key */
2069                 if (key) {
2070                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2071                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2072                                 return -EINVAL;
2073                         }
2074                         DP_INFO(edev, "Applying user supplied hash key\n");
2075                         rss_params.update_rss_key = 1;
2076                         memcpy(&rss_params.rss_key, key, len);
2077                 }
2078                 rss_params.rss_enable = 1;
2079         }
2080
2081         rss_params.update_rss_config = 1;
2082         /* tbl_size has to be set with capabilities */
2083         rss_params.rss_table_size_log = 7;
2084         vport_update_params.vport_id = 0;
2085         /* pass the L2 handles instead of qids */
2086         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2087                 idx = i % QEDE_RSS_COUNT(qdev);
2088                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2089         }
2090         vport_update_params.rss_params = &rss_params;
2091
2092         for_each_hwfn(edev, i) {
2093                 p_hwfn = &edev->hwfns[i];
2094                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2095                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2096                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2097                 if (rc) {
2098                         DP_ERR(edev, "vport-update for RSS failed\n");
2099                         return rc;
2100                 }
2101         }
2102         qdev->rss_enable = rss_params.rss_enable;
2103
2104         /* Update local structure for hash query */
2105         qdev->rss_conf.rss_hf = hf;
2106         qdev->rss_conf.rss_key_len = len;
2107         if (qdev->rss_enable) {
2108                 if  (qdev->rss_conf.rss_key == NULL) {
2109                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2110                         if (qdev->rss_conf.rss_key == NULL) {
2111                                 DP_ERR(edev, "No memory to store RSS key\n");
2112                                 return -ENOMEM;
2113                         }
2114                 }
2115                 if (key && len) {
2116                         DP_INFO(edev, "Storing RSS key\n");
2117                         memcpy(qdev->rss_conf.rss_key, key, len);
2118                 }
2119         } else if (!qdev->rss_enable && len == 0) {
2120                 if (qdev->rss_conf.rss_key) {
2121                         free(qdev->rss_conf.rss_key);
2122                         qdev->rss_conf.rss_key = NULL;
2123                         DP_INFO(edev, "Free RSS key\n");
2124                 }
2125         }
2126
2127         return 0;
2128 }
2129
2130 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2131                            struct rte_eth_rss_conf *rss_conf)
2132 {
2133         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2134
2135         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2136         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2137
2138         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2139                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2140                        rss_conf->rss_key_len);
2141         return 0;
2142 }
2143
2144 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2145                                     struct ecore_rss_params *rss)
2146 {
2147         int i, fn;
2148         bool rss_mode = 1; /* enable */
2149         struct ecore_queue_cid *cid;
2150         struct ecore_rss_params *t_rss;
2151
2152         /* In regular scenario, we'd simply need to take input handlers.
2153          * But in CMT, we'd have to split the handlers according to the
2154          * engine they were configured on. We'd then have to understand
2155          * whether RSS is really required, since 2-queues on CMT doesn't
2156          * require RSS.
2157          */
2158
2159         /* CMT should be round-robin */
2160         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2161                 cid = rss->rss_ind_table[i];
2162
2163                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2164                         t_rss = &rss[0];
2165                 else
2166                         t_rss = &rss[1];
2167
2168                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2169         }
2170
2171         t_rss = &rss[1];
2172         t_rss->update_rss_ind_table = 1;
2173         t_rss->rss_table_size_log = 7;
2174         t_rss->update_rss_config = 1;
2175
2176         /* Make sure RSS is actually required */
2177         for_each_hwfn(edev, fn) {
2178                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2179                      i++) {
2180                         if (rss[fn].rss_ind_table[i] !=
2181                             rss[fn].rss_ind_table[0])
2182                                 break;
2183                 }
2184
2185                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2186                         DP_INFO(edev,
2187                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2188                         rss_mode = 0;
2189                         goto out;
2190                 }
2191         }
2192
2193 out:
2194         t_rss->rss_enable = rss_mode;
2195
2196         return rss_mode;
2197 }
2198
2199 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2200                          struct rte_eth_rss_reta_entry64 *reta_conf,
2201                          uint16_t reta_size)
2202 {
2203         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2204         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2205         struct ecore_sp_vport_update_params vport_update_params;
2206         struct ecore_rss_params *params;
2207         struct ecore_hwfn *p_hwfn;
2208         uint16_t i, idx, shift;
2209         uint8_t entry;
2210         int rc = 0;
2211
2212         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2213                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2214                        reta_size);
2215                 return -EINVAL;
2216         }
2217
2218         memset(&vport_update_params, 0, sizeof(vport_update_params));
2219         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2220                              RTE_CACHE_LINE_SIZE);
2221         if (params == NULL) {
2222                 DP_ERR(edev, "failed to allocate memory\n");
2223                 return -ENOMEM;
2224         }
2225
2226         for (i = 0; i < reta_size; i++) {
2227                 idx = i / RTE_RETA_GROUP_SIZE;
2228                 shift = i % RTE_RETA_GROUP_SIZE;
2229                 if (reta_conf[idx].mask & (1ULL << shift)) {
2230                         entry = reta_conf[idx].reta[shift];
2231                         /* Pass rxq handles to ecore */
2232                         params->rss_ind_table[i] =
2233                                         qdev->fp_array[entry].rxq->handle;
2234                         /* Update the local copy for RETA query command */
2235                         qdev->rss_ind_table[i] = entry;
2236                 }
2237         }
2238
2239         params->update_rss_ind_table = 1;
2240         params->rss_table_size_log = 7;
2241         params->update_rss_config = 1;
2242
2243         /* Fix up RETA for CMT mode device */
2244         if (ECORE_IS_CMT(edev))
2245                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2246                                                             params);
2247         vport_update_params.vport_id = 0;
2248         /* Use the current value of rss_enable */
2249         params->rss_enable = qdev->rss_enable;
2250         vport_update_params.rss_params = params;
2251
2252         for_each_hwfn(edev, i) {
2253                 p_hwfn = &edev->hwfns[i];
2254                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2255                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2256                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2257                 if (rc) {
2258                         DP_ERR(edev, "vport-update for RSS failed\n");
2259                         goto out;
2260                 }
2261         }
2262
2263 out:
2264         rte_free(params);
2265         return rc;
2266 }
2267
2268 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2269                                struct rte_eth_rss_reta_entry64 *reta_conf,
2270                                uint16_t reta_size)
2271 {
2272         struct qede_dev *qdev = eth_dev->data->dev_private;
2273         struct ecore_dev *edev = &qdev->edev;
2274         uint16_t i, idx, shift;
2275         uint8_t entry;
2276
2277         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2278                 DP_ERR(edev, "reta_size %d is not supported\n",
2279                        reta_size);
2280                 return -EINVAL;
2281         }
2282
2283         for (i = 0; i < reta_size; i++) {
2284                 idx = i / RTE_RETA_GROUP_SIZE;
2285                 shift = i % RTE_RETA_GROUP_SIZE;
2286                 if (reta_conf[idx].mask & (1ULL << shift)) {
2287                         entry = qdev->rss_ind_table[i];
2288                         reta_conf[idx].reta[shift] = entry;
2289                 }
2290         }
2291
2292         return 0;
2293 }
2294
2295
2296
2297 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2298 {
2299         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2300         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2301         struct rte_eth_dev_info dev_info = {0};
2302         struct qede_fastpath *fp;
2303         uint32_t max_rx_pkt_len;
2304         uint32_t frame_size;
2305         uint16_t rx_buf_size;
2306         uint16_t bufsz;
2307         bool restart = false;
2308         int i;
2309
2310         PMD_INIT_FUNC_TRACE(edev);
2311         qede_dev_info_get(dev, &dev_info);
2312         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2313         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2314         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2315                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2316                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2317                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2318                 return -EINVAL;
2319         }
2320         if (!dev->data->scattered_rx &&
2321             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2322                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2323                         dev->data->min_rx_buf_size);
2324                 return -EINVAL;
2325         }
2326         /* Temporarily replace I/O functions with dummy ones. It cannot
2327          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2328          */
2329         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2330         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2331         if (dev->data->dev_started) {
2332                 dev->data->dev_started = 0;
2333                 qede_dev_stop(dev);
2334                 restart = true;
2335         } else {
2336                 if (IS_PF(edev))
2337                         qede_mac_addr_remove(dev, 0);
2338         }
2339         rte_delay_ms(1000);
2340         qede_start_vport(qdev, mtu); /* Recreate vport */
2341         qdev->mtu = mtu;
2342
2343         /* Fix up RX buf size for all queues of the port */
2344         for_each_rss(i) {
2345                 fp = &qdev->fp_array[i];
2346                 if (fp->rxq != NULL) {
2347                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2348                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2349                         if (dev->data->scattered_rx)
2350                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
2351                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2352                         else
2353                                 rx_buf_size = frame_size;
2354                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2355                         fp->rxq->rx_buf_size = rx_buf_size;
2356                         DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2357                 }
2358         }
2359         if (max_rx_pkt_len > ETHER_MAX_LEN)
2360                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2361         else
2362                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2363
2364         /* Restore config lost due to vport stop */
2365         if (IS_PF(edev))
2366                 qede_mac_addr_set(dev, &qdev->primary_mac);
2367
2368         if (dev->data->promiscuous)
2369                 qede_promiscuous_enable(dev);
2370         else
2371                 qede_promiscuous_disable(dev);
2372
2373         if (dev->data->all_multicast)
2374                 qede_allmulticast_enable(dev);
2375         else
2376                 qede_allmulticast_disable(dev);
2377
2378         qede_vlan_offload_set(dev, qdev->vlan_offload_mask);
2379
2380         if (!dev->data->dev_started && restart) {
2381                 qede_dev_start(dev);
2382                 dev->data->dev_started = 1;
2383         }
2384
2385         /* update max frame size */
2386         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2387         /* Reassign back */
2388         dev->rx_pkt_burst = qede_recv_pkts;
2389         dev->tx_pkt_burst = qede_xmit_pkts;
2390
2391         return 0;
2392 }
2393
2394 static int
2395 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2396                        struct rte_eth_udp_tunnel *tunnel_udp,
2397                        bool add)
2398 {
2399         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2400         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2401         struct ecore_tunnel_info tunn; /* @DPDK */
2402         struct ecore_hwfn *p_hwfn;
2403         struct ecore_ptt *p_ptt;
2404         uint16_t udp_port;
2405         int rc, i;
2406
2407         PMD_INIT_FUNC_TRACE(edev);
2408
2409         memset(&tunn, 0, sizeof(tunn));
2410         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2411                 /* Enable VxLAN tunnel if needed before UDP port update using
2412                  * default MAC/VLAN classification.
2413                  */
2414                 if (add) {
2415                         if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2416                                 DP_INFO(edev,
2417                                         "UDP port %u was already configured\n",
2418                                         tunnel_udp->udp_port);
2419                                 return ECORE_SUCCESS;
2420                         }
2421                         /* Enable VXLAN if it was not enabled while adding
2422                          * VXLAN filter.
2423                          */
2424                         if (!qdev->vxlan.enable) {
2425                                 rc = qede_vxlan_enable(eth_dev,
2426                                         ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2427                                 if (rc != ECORE_SUCCESS) {
2428                                         DP_ERR(edev, "Failed to enable VXLAN "
2429                                                 "prior to updating UDP port\n");
2430                                         return rc;
2431                                 }
2432                         }
2433                         udp_port = tunnel_udp->udp_port;
2434                 } else {
2435                         if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2436                                 DP_ERR(edev, "UDP port %u doesn't exist\n",
2437                                         tunnel_udp->udp_port);
2438                                 return ECORE_INVAL;
2439                         }
2440                         udp_port = 0;
2441                 }
2442
2443                 tunn.vxlan_port.b_update_port = true;
2444                 tunn.vxlan_port.port = udp_port;
2445                 for_each_hwfn(edev, i) {
2446                         p_hwfn = &edev->hwfns[i];
2447                         if (IS_PF(edev)) {
2448                                 p_ptt = ecore_ptt_acquire(p_hwfn);
2449                                 if (!p_ptt)
2450                                         return -EAGAIN;
2451                         } else {
2452                                 p_ptt = NULL;
2453                         }
2454                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, &tunn,
2455                                                 ECORE_SPQ_MODE_CB, NULL);
2456                         if (rc != ECORE_SUCCESS) {
2457                                 DP_ERR(edev, "Unable to config UDP port %u\n",
2458                                        tunn.vxlan_port.port);
2459                                 if (IS_PF(edev))
2460                                         ecore_ptt_release(p_hwfn, p_ptt);
2461                                 return rc;
2462                         }
2463                 }
2464
2465                 qdev->vxlan.udp_port = udp_port;
2466                 /* If the request is to delete UDP port and if the number of
2467                  * VXLAN filters have reached 0 then VxLAN offload can be be
2468                  * disabled.
2469                  */
2470                 if (!add && qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2471                         return qede_vxlan_enable(eth_dev,
2472                                         ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2473         }
2474
2475         return 0;
2476 }
2477
2478 static int
2479 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2480                       struct rte_eth_udp_tunnel *tunnel_udp)
2481 {
2482         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2483 }
2484
2485 static int
2486 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2487                       struct rte_eth_udp_tunnel *tunnel_udp)
2488 {
2489         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2490 }
2491
2492 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2493                                        uint32_t *clss, char *str)
2494 {
2495         uint16_t j;
2496         *clss = MAX_ECORE_TUNN_CLSS;
2497
2498         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2499                 if (filter == qede_tunn_types[j].rte_filter_type) {
2500                         *type = qede_tunn_types[j].qede_type;
2501                         *clss = qede_tunn_types[j].qede_tunn_clss;
2502                         strcpy(str, qede_tunn_types[j].string);
2503                         return;
2504                 }
2505         }
2506 }
2507
2508 static int
2509 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2510                               const struct rte_eth_tunnel_filter_conf *conf,
2511                               uint32_t type)
2512 {
2513         /* Init commmon ucast params first */
2514         qede_set_ucast_cmn_params(ucast);
2515
2516         /* Copy out the required fields based on classification type */
2517         ucast->type = type;
2518
2519         switch (type) {
2520         case ECORE_FILTER_VNI:
2521                 ucast->vni = conf->tenant_id;
2522         break;
2523         case ECORE_FILTER_INNER_VLAN:
2524                 ucast->vlan = conf->inner_vlan;
2525         break;
2526         case ECORE_FILTER_MAC:
2527                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2528                        ETHER_ADDR_LEN);
2529         break;
2530         case ECORE_FILTER_INNER_MAC:
2531                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2532                        ETHER_ADDR_LEN);
2533         break;
2534         case ECORE_FILTER_MAC_VNI_PAIR:
2535                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2536                         ETHER_ADDR_LEN);
2537                 ucast->vni = conf->tenant_id;
2538         break;
2539         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2540                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2541                         ETHER_ADDR_LEN);
2542                 ucast->vni = conf->tenant_id;
2543         break;
2544         case ECORE_FILTER_INNER_PAIR:
2545                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2546                         ETHER_ADDR_LEN);
2547                 ucast->vlan = conf->inner_vlan;
2548         break;
2549         default:
2550                 return -EINVAL;
2551         }
2552
2553         return ECORE_SUCCESS;
2554 }
2555
2556 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2557                                   enum rte_filter_op filter_op,
2558                                   const struct rte_eth_tunnel_filter_conf *conf)
2559 {
2560         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2561         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2562         enum ecore_filter_ucast_type type;
2563         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2564         struct ecore_filter_ucast ucast = {0};
2565         char str[80];
2566         uint16_t filter_type = 0;
2567         int rc;
2568
2569         PMD_INIT_FUNC_TRACE(edev);
2570
2571         switch (filter_op) {
2572         case RTE_ETH_FILTER_ADD:
2573                 if (IS_VF(edev))
2574                         return qede_vxlan_enable(eth_dev,
2575                                         ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2576
2577                 filter_type = conf->filter_type;
2578                 /* Determine if the given filter classification is supported */
2579                 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2580                 if (clss == MAX_ECORE_TUNN_CLSS) {
2581                         DP_ERR(edev, "Unsupported filter type\n");
2582                         return -EINVAL;
2583                 }
2584                 /* Init tunnel ucast params */
2585                 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2586                 if (rc != ECORE_SUCCESS) {
2587                         DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2588                         conf->filter_type);
2589                         return rc;
2590                 }
2591                 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2592                         str, filter_op, ucast.type);
2593
2594                 ucast.opcode = ECORE_FILTER_ADD;
2595
2596                 /* Skip MAC/VLAN if filter is based on VNI */
2597                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2598                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2599                         if (rc == 0) {
2600                                 /* Enable accept anyvlan */
2601                                 qede_config_accept_any_vlan(qdev, true);
2602                         }
2603                 } else {
2604                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
2605                         if (rc == 0)
2606                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2607                                                     ECORE_SPQ_MODE_CB, NULL);
2608                 }
2609
2610                 if (rc != ECORE_SUCCESS)
2611                         return rc;
2612
2613                 qdev->vxlan.num_filters++;
2614                 qdev->vxlan.filter_type = filter_type;
2615                 if (!qdev->vxlan.enable)
2616                         return qede_vxlan_enable(eth_dev, clss, true, true);
2617
2618         break;
2619         case RTE_ETH_FILTER_DELETE:
2620                 if (IS_VF(edev))
2621                         return qede_vxlan_enable(eth_dev,
2622                                 ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2623
2624                 filter_type = conf->filter_type;
2625                 /* Determine if the given filter classification is supported */
2626                 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2627                 if (clss == MAX_ECORE_TUNN_CLSS) {
2628                         DP_ERR(edev, "Unsupported filter type\n");
2629                         return -EINVAL;
2630                 }
2631                 /* Init tunnel ucast params */
2632                 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2633                 if (rc != ECORE_SUCCESS) {
2634                         DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2635                         conf->filter_type);
2636                         return rc;
2637                 }
2638                 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2639                         str, filter_op, ucast.type);
2640
2641                 ucast.opcode = ECORE_FILTER_REMOVE;
2642
2643                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2644                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2645                 } else {
2646                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
2647                         if (rc == 0)
2648                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2649                                                     ECORE_SPQ_MODE_CB, NULL);
2650                 }
2651                 if (rc != ECORE_SUCCESS)
2652                         return rc;
2653
2654                 qdev->vxlan.num_filters--;
2655
2656                 /* Disable VXLAN if VXLAN filters become 0 */
2657                 if (qdev->vxlan.num_filters == 0)
2658                         return qede_vxlan_enable(eth_dev, clss, false, true);
2659         break;
2660         default:
2661                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2662                 return -EINVAL;
2663         }
2664
2665         return 0;
2666 }
2667
2668 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2669                          enum rte_filter_type filter_type,
2670                          enum rte_filter_op filter_op,
2671                          void *arg)
2672 {
2673         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2674         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2675         struct rte_eth_tunnel_filter_conf *filter_conf =
2676                         (struct rte_eth_tunnel_filter_conf *)arg;
2677
2678         switch (filter_type) {
2679         case RTE_ETH_FILTER_TUNNEL:
2680                 switch (filter_conf->tunnel_type) {
2681                 case RTE_TUNNEL_TYPE_VXLAN:
2682                         DP_INFO(edev,
2683                                 "Packet steering to the specified Rx queue"
2684                                 " is not supported with VXLAN tunneling");
2685                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
2686                                                       filter_conf));
2687                 /* Place holders for future tunneling support */
2688                 case RTE_TUNNEL_TYPE_GENEVE:
2689                 case RTE_TUNNEL_TYPE_TEREDO:
2690                 case RTE_TUNNEL_TYPE_NVGRE:
2691                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2692                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2693                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2694                                 filter_conf->tunnel_type);
2695                         return -EINVAL;
2696                 case RTE_TUNNEL_TYPE_NONE:
2697                 default:
2698                         return 0;
2699                 }
2700                 break;
2701         case RTE_ETH_FILTER_FDIR:
2702                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2703         case RTE_ETH_FILTER_NTUPLE:
2704                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2705         case RTE_ETH_FILTER_MACVLAN:
2706         case RTE_ETH_FILTER_ETHERTYPE:
2707         case RTE_ETH_FILTER_FLEXIBLE:
2708         case RTE_ETH_FILTER_SYN:
2709         case RTE_ETH_FILTER_HASH:
2710         case RTE_ETH_FILTER_L2_TUNNEL:
2711         case RTE_ETH_FILTER_MAX:
2712         default:
2713                 DP_ERR(edev, "Unsupported filter type %d\n",
2714                         filter_type);
2715                 return -EINVAL;
2716         }
2717
2718         return 0;
2719 }
2720
2721 static const struct eth_dev_ops qede_eth_dev_ops = {
2722         .dev_configure = qede_dev_configure,
2723         .dev_infos_get = qede_dev_info_get,
2724         .rx_queue_setup = qede_rx_queue_setup,
2725         .rx_queue_release = qede_rx_queue_release,
2726         .tx_queue_setup = qede_tx_queue_setup,
2727         .tx_queue_release = qede_tx_queue_release,
2728         .dev_start = qede_dev_start,
2729         .dev_set_link_up = qede_dev_set_link_up,
2730         .dev_set_link_down = qede_dev_set_link_down,
2731         .link_update = qede_link_update,
2732         .promiscuous_enable = qede_promiscuous_enable,
2733         .promiscuous_disable = qede_promiscuous_disable,
2734         .allmulticast_enable = qede_allmulticast_enable,
2735         .allmulticast_disable = qede_allmulticast_disable,
2736         .set_mc_addr_list = qede_set_mc_addr_list,
2737         .dev_stop = qede_dev_stop,
2738         .dev_close = qede_dev_close,
2739         .stats_get = qede_get_stats,
2740         .stats_reset = qede_reset_stats,
2741         .xstats_get = qede_get_xstats,
2742         .xstats_reset = qede_reset_xstats,
2743         .xstats_get_names = qede_get_xstats_names,
2744         .mac_addr_add = qede_mac_addr_add,
2745         .mac_addr_remove = qede_mac_addr_remove,
2746         .mac_addr_set = qede_mac_addr_set,
2747         .vlan_offload_set = qede_vlan_offload_set,
2748         .vlan_filter_set = qede_vlan_filter_set,
2749         .flow_ctrl_set = qede_flow_ctrl_set,
2750         .flow_ctrl_get = qede_flow_ctrl_get,
2751         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2752         .rss_hash_update = qede_rss_hash_update,
2753         .rss_hash_conf_get = qede_rss_hash_conf_get,
2754         .reta_update  = qede_rss_reta_update,
2755         .reta_query  = qede_rss_reta_query,
2756         .mtu_set = qede_set_mtu,
2757         .filter_ctrl = qede_dev_filter_ctrl,
2758         .udp_tunnel_port_add = qede_udp_dst_port_add,
2759         .udp_tunnel_port_del = qede_udp_dst_port_del,
2760 };
2761
2762 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2763         .dev_configure = qede_dev_configure,
2764         .dev_infos_get = qede_dev_info_get,
2765         .rx_queue_setup = qede_rx_queue_setup,
2766         .rx_queue_release = qede_rx_queue_release,
2767         .tx_queue_setup = qede_tx_queue_setup,
2768         .tx_queue_release = qede_tx_queue_release,
2769         .dev_start = qede_dev_start,
2770         .dev_set_link_up = qede_dev_set_link_up,
2771         .dev_set_link_down = qede_dev_set_link_down,
2772         .link_update = qede_link_update,
2773         .promiscuous_enable = qede_promiscuous_enable,
2774         .promiscuous_disable = qede_promiscuous_disable,
2775         .allmulticast_enable = qede_allmulticast_enable,
2776         .allmulticast_disable = qede_allmulticast_disable,
2777         .set_mc_addr_list = qede_set_mc_addr_list,
2778         .dev_stop = qede_dev_stop,
2779         .dev_close = qede_dev_close,
2780         .stats_get = qede_get_stats,
2781         .stats_reset = qede_reset_stats,
2782         .xstats_get = qede_get_xstats,
2783         .xstats_reset = qede_reset_xstats,
2784         .xstats_get_names = qede_get_xstats_names,
2785         .vlan_offload_set = qede_vlan_offload_set,
2786         .vlan_filter_set = qede_vlan_filter_set,
2787         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2788         .rss_hash_update = qede_rss_hash_update,
2789         .rss_hash_conf_get = qede_rss_hash_conf_get,
2790         .reta_update  = qede_rss_reta_update,
2791         .reta_query  = qede_rss_reta_query,
2792         .mtu_set = qede_set_mtu,
2793         .udp_tunnel_port_add = qede_udp_dst_port_add,
2794         .udp_tunnel_port_del = qede_udp_dst_port_del,
2795 };
2796
2797 static void qede_update_pf_params(struct ecore_dev *edev)
2798 {
2799         struct ecore_pf_params pf_params;
2800
2801         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2802         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2803         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2804         qed_ops->common->update_pf_params(edev, &pf_params);
2805 }
2806
2807 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2808 {
2809         struct rte_pci_device *pci_dev;
2810         struct rte_pci_addr pci_addr;
2811         struct qede_dev *adapter;
2812         struct ecore_dev *edev;
2813         struct qed_dev_eth_info dev_info;
2814         struct qed_slowpath_params params;
2815         static bool do_once = true;
2816         uint8_t bulletin_change;
2817         uint8_t vf_mac[ETHER_ADDR_LEN];
2818         uint8_t is_mac_forced;
2819         bool is_mac_exist;
2820         /* Fix up ecore debug level */
2821         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2822         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2823         int rc;
2824
2825         /* Extract key data structures */
2826         adapter = eth_dev->data->dev_private;
2827         adapter->ethdev = eth_dev;
2828         edev = &adapter->edev;
2829         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2830         pci_addr = pci_dev->addr;
2831
2832         PMD_INIT_FUNC_TRACE(edev);
2833
2834         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2835                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2836                  eth_dev->data->port_id);
2837
2838         eth_dev->rx_pkt_burst = qede_recv_pkts;
2839         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2840         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2841
2842         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2843                 DP_ERR(edev, "Skipping device init from secondary process\n");
2844                 return 0;
2845         }
2846
2847         rte_eth_copy_pci_info(eth_dev, pci_dev);
2848
2849         /* @DPDK */
2850         edev->vendor_id = pci_dev->id.vendor_id;
2851         edev->device_id = pci_dev->id.device_id;
2852
2853         qed_ops = qed_get_eth_ops();
2854         if (!qed_ops) {
2855                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2856                 return -EINVAL;
2857         }
2858
2859         DP_INFO(edev, "Starting qede probe\n");
2860         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2861                                     dp_level, is_vf);
2862         if (rc != 0) {
2863                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2864                 return -ENODEV;
2865         }
2866         qede_update_pf_params(edev);
2867         rte_intr_callback_register(&pci_dev->intr_handle,
2868                                    qede_interrupt_handler, (void *)eth_dev);
2869         if (rte_intr_enable(&pci_dev->intr_handle)) {
2870                 DP_ERR(edev, "rte_intr_enable() failed\n");
2871                 return -ENODEV;
2872         }
2873
2874         /* Start the Slowpath-process */
2875         memset(&params, 0, sizeof(struct qed_slowpath_params));
2876         params.int_mode = ECORE_INT_MODE_MSIX;
2877         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2878         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2879         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2880         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2881         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2882                 QEDE_PMD_DRV_VER_STR_SIZE);
2883
2884         /* For CMT mode device do periodic polling for slowpath events.
2885          * This is required since uio device uses only one MSI-x
2886          * interrupt vector but we need one for each engine.
2887          */
2888         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2889                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2890                                        qede_poll_sp_sb_cb,
2891                                        (void *)eth_dev);
2892                 if (rc != 0) {
2893                         DP_ERR(edev, "Unable to start periodic"
2894                                      " timer rc %d\n", rc);
2895                         return -EINVAL;
2896                 }
2897         }
2898
2899         rc = qed_ops->common->slowpath_start(edev, &params);
2900         if (rc) {
2901                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2902                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2903                                      (void *)eth_dev);
2904                 return -ENODEV;
2905         }
2906
2907         rc = qed_ops->fill_dev_info(edev, &dev_info);
2908         if (rc) {
2909                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2910                 qed_ops->common->slowpath_stop(edev);
2911                 qed_ops->common->remove(edev);
2912                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2913                                      (void *)eth_dev);
2914                 return -ENODEV;
2915         }
2916
2917         qede_alloc_etherdev(adapter, &dev_info);
2918
2919         adapter->ops->common->set_name(edev, edev->name);
2920
2921         if (!is_vf)
2922                 adapter->dev_info.num_mac_filters =
2923                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2924                                             ECORE_MAC);
2925         else
2926                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2927                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2928
2929         /* Allocate memory for storing MAC addr */
2930         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2931                                         (ETHER_ADDR_LEN *
2932                                         adapter->dev_info.num_mac_filters),
2933                                         RTE_CACHE_LINE_SIZE);
2934
2935         if (eth_dev->data->mac_addrs == NULL) {
2936                 DP_ERR(edev, "Failed to allocate MAC address\n");
2937                 qed_ops->common->slowpath_stop(edev);
2938                 qed_ops->common->remove(edev);
2939                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2940                                      (void *)eth_dev);
2941                 return -ENOMEM;
2942         }
2943
2944         if (!is_vf) {
2945                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2946                                 hw_info.hw_mac_addr,
2947                                 &eth_dev->data->mac_addrs[0]);
2948                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2949                                 &adapter->primary_mac);
2950         } else {
2951                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2952                                        &bulletin_change);
2953                 if (bulletin_change) {
2954                         is_mac_exist =
2955                             ecore_vf_bulletin_get_forced_mac(
2956                                                 ECORE_LEADING_HWFN(edev),
2957                                                 vf_mac,
2958                                                 &is_mac_forced);
2959                         if (is_mac_exist && is_mac_forced) {
2960                                 DP_INFO(edev, "VF macaddr received from PF\n");
2961                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2962                                                 &eth_dev->data->mac_addrs[0]);
2963                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2964                                                 &adapter->primary_mac);
2965                         } else {
2966                                 DP_ERR(edev, "No VF macaddr assigned\n");
2967                         }
2968                 }
2969         }
2970
2971         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2972
2973         if (do_once) {
2974 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2975                 qede_print_adapter_info(adapter);
2976 #endif
2977                 do_once = false;
2978         }
2979
2980         /* Bring-up the link */
2981         qede_dev_set_link_state(eth_dev, true);
2982
2983         adapter->num_tx_queues = 0;
2984         adapter->num_rx_queues = 0;
2985         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2986         SLIST_INIT(&adapter->vlan_list_head);
2987         SLIST_INIT(&adapter->uc_list_head);
2988         SLIST_INIT(&adapter->mc_list_head);
2989         adapter->mtu = ETHER_MTU;
2990         adapter->vport_started = false;
2991
2992         /* VF tunnel offloads is enabled by default in PF driver */
2993         adapter->vxlan.enable = true;
2994         adapter->vxlan.num_filters = 0;
2995         adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2996                                      ETH_TUNNEL_FILTER_IVLAN;
2997         adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2998
2999         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3000                 adapter->primary_mac.addr_bytes[0],
3001                 adapter->primary_mac.addr_bytes[1],
3002                 adapter->primary_mac.addr_bytes[2],
3003                 adapter->primary_mac.addr_bytes[3],
3004                 adapter->primary_mac.addr_bytes[4],
3005                 adapter->primary_mac.addr_bytes[5]);
3006
3007         DP_INFO(edev, "Device initialized\n");
3008
3009         return 0;
3010 }
3011
3012 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3013 {
3014         return qede_common_dev_init(eth_dev, 1);
3015 }
3016
3017 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3018 {
3019         return qede_common_dev_init(eth_dev, 0);
3020 }
3021
3022 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3023 {
3024 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3025         struct qede_dev *qdev = eth_dev->data->dev_private;
3026         struct ecore_dev *edev = &qdev->edev;
3027
3028         PMD_INIT_FUNC_TRACE(edev);
3029 #endif
3030
3031         /* only uninitialize in the primary process */
3032         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3033                 return 0;
3034
3035         /* safe to close dev here */
3036         qede_dev_close(eth_dev);
3037
3038         eth_dev->dev_ops = NULL;
3039         eth_dev->rx_pkt_burst = NULL;
3040         eth_dev->tx_pkt_burst = NULL;
3041
3042         if (eth_dev->data->mac_addrs)
3043                 rte_free(eth_dev->data->mac_addrs);
3044
3045         eth_dev->data->mac_addrs = NULL;
3046
3047         return 0;
3048 }
3049
3050 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3051 {
3052         return qede_dev_common_uninit(eth_dev);
3053 }
3054
3055 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3056 {
3057         return qede_dev_common_uninit(eth_dev);
3058 }
3059
3060 static const struct rte_pci_id pci_id_qedevf_map[] = {
3061 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3062         {
3063                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3064         },
3065         {
3066                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3067         },
3068         {
3069                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3070         },
3071         {.vendor_id = 0,}
3072 };
3073
3074 static const struct rte_pci_id pci_id_qede_map[] = {
3075 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3076         {
3077                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3078         },
3079         {
3080                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3081         },
3082         {
3083                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3084         },
3085         {
3086                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3087         },
3088         {
3089                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3090         },
3091         {
3092                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3093         },
3094         {
3095                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3096         },
3097         {
3098                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3099         },
3100         {
3101                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3102         },
3103         {
3104                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3105         },
3106         {.vendor_id = 0,}
3107 };
3108
3109 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3110         struct rte_pci_device *pci_dev)
3111 {
3112         return rte_eth_dev_pci_generic_probe(pci_dev,
3113                 sizeof(struct qede_dev), qedevf_eth_dev_init);
3114 }
3115
3116 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3117 {
3118         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3119 }
3120
3121 static struct rte_pci_driver rte_qedevf_pmd = {
3122         .id_table = pci_id_qedevf_map,
3123         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3124         .probe = qedevf_eth_dev_pci_probe,
3125         .remove = qedevf_eth_dev_pci_remove,
3126 };
3127
3128 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3129         struct rte_pci_device *pci_dev)
3130 {
3131         return rte_eth_dev_pci_generic_probe(pci_dev,
3132                 sizeof(struct qede_dev), qede_eth_dev_init);
3133 }
3134
3135 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3136 {
3137         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3138 }
3139
3140 static struct rte_pci_driver rte_qede_pmd = {
3141         .id_table = pci_id_qede_map,
3142         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3143         .probe = qede_eth_dev_pci_probe,
3144         .remove = qede_eth_dev_pci_remove,
3145 };
3146
3147 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3148 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3149 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3150 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3151 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3152 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");