2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
9 #include "qede_ethdev.h"
10 #include <rte_alarm.h>
11 #include <rte_version.h>
14 static const struct qed_eth_ops *qed_ops;
15 static const char *drivername = "qede pmd";
16 static int64_t timer_period = 1;
18 struct rte_qede_xstats_name_off {
19 char name[RTE_ETH_XSTATS_NAME_SIZE];
23 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
24 {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
25 {"rx_multicast_bytes",
26 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
27 {"rx_broadcast_bytes",
28 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
29 {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
30 {"rx_multicast_packets",
31 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
32 {"rx_broadcast_packets",
33 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
35 {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
36 {"tx_multicast_bytes",
37 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
38 {"tx_broadcast_bytes",
39 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
40 {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
41 {"tx_multicast_packets",
42 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
43 {"tx_broadcast_packets",
44 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
46 {"rx_64_byte_packets",
47 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
48 {"rx_65_to_127_byte_packets",
49 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
50 {"rx_128_to_255_byte_packets",
51 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
52 {"rx_256_to_511_byte_packets",
53 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
54 {"rx_512_to_1023_byte_packets",
55 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
56 {"rx_1024_to_1518_byte_packets",
57 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
58 {"rx_1519_to_1522_byte_packets",
59 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
60 {"rx_1519_to_2047_byte_packets",
61 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
62 {"rx_2048_to_4095_byte_packets",
63 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
64 {"rx_4096_to_9216_byte_packets",
65 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
66 {"rx_9217_to_16383_byte_packets",
67 offsetof(struct ecore_eth_stats,
68 rx_9217_to_16383_byte_packets)},
69 {"tx_64_byte_packets",
70 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
71 {"tx_65_to_127_byte_packets",
72 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
73 {"tx_128_to_255_byte_packets",
74 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
75 {"tx_256_to_511_byte_packets",
76 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
77 {"tx_512_to_1023_byte_packets",
78 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
79 {"tx_1024_to_1518_byte_packets",
80 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
81 {"trx_1519_to_1522_byte_packets",
82 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
83 {"tx_2048_to_4095_byte_packets",
84 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
85 {"tx_4096_to_9216_byte_packets",
86 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
87 {"tx_9217_to_16383_byte_packets",
88 offsetof(struct ecore_eth_stats,
89 tx_9217_to_16383_byte_packets)},
91 {"rx_mac_crtl_frames",
92 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
93 {"tx_mac_control_frames",
94 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
95 {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
96 {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
97 {"rx_priority_flow_control_frames",
98 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
99 {"tx_priority_flow_control_frames",
100 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
102 {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
103 {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
104 {"rx_carrier_errors",
105 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
106 {"rx_oversize_packet_errors",
107 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
108 {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
109 {"rx_undersize_packet_errors",
110 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
111 {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
112 {"rx_host_buffer_not_available",
113 offsetof(struct ecore_eth_stats, no_buff_discards)},
114 /* Number of packets discarded because they are bigger than MTU */
115 {"rx_packet_too_big_discards",
116 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
117 {"rx_ttl_zero_discards",
118 offsetof(struct ecore_eth_stats, ttl0_discard)},
119 {"rx_multi_function_tag_filter_discards",
120 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
121 {"rx_mac_filter_discards",
122 offsetof(struct ecore_eth_stats, mac_filter_discards)},
123 {"rx_hw_buffer_truncates",
124 offsetof(struct ecore_eth_stats, brb_truncates)},
125 {"rx_hw_buffer_discards",
126 offsetof(struct ecore_eth_stats, brb_discards)},
127 {"tx_lpi_entry_count",
128 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
129 {"tx_total_collisions",
130 offsetof(struct ecore_eth_stats, tx_total_collisions)},
131 {"tx_error_drop_packets",
132 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
134 {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
135 {"rx_mac_unicast_packets",
136 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
137 {"rx_mac_multicast_packets",
138 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
139 {"rx_mac_broadcast_packets",
140 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
142 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
143 {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
144 {"tx_mac_unicast_packets",
145 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
146 {"tx_mac_multicast_packets",
147 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
148 {"tx_mac_broadcast_packets",
149 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
151 {"lro_coalesced_packets",
152 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
153 {"lro_coalesced_events",
154 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
156 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
157 {"lro_not_coalesced_packets",
158 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
159 {"lro_coalesced_bytes",
160 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
163 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
165 offsetof(struct qede_rx_queue, rx_segs)},
167 offsetof(struct qede_rx_queue, rx_hw_errors)},
168 {"rx_q_allocation_errors",
169 offsetof(struct qede_rx_queue, rx_alloc_errors)}
172 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
174 ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
178 qede_interrupt_handler(__rte_unused struct rte_intr_handle *handle, void *param)
180 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
181 struct qede_dev *qdev = eth_dev->data->dev_private;
182 struct ecore_dev *edev = &qdev->edev;
184 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
185 if (rte_intr_enable(ð_dev->pci_dev->intr_handle))
186 DP_ERR(edev, "rte_intr_enable failed\n");
190 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
192 rte_memcpy(&qdev->dev_info, info, sizeof(*info));
193 qdev->num_tc = qdev->dev_info.num_tc;
197 static void qede_print_adapter_info(struct qede_dev *qdev)
199 struct ecore_dev *edev = &qdev->edev;
200 struct qed_dev_info *info = &qdev->dev_info.common;
201 static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
202 static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
204 DP_INFO(edev, "*********************************\n");
205 DP_INFO(edev, " DPDK version:%s\n", rte_version());
206 DP_INFO(edev, " Chip details : %s %c%d\n",
207 ECORE_IS_BB(edev) ? "BB" : "AH",
208 'A' + edev->chip_rev,
209 (int)edev->chip_metal);
210 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
211 info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
212 snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
213 ver_str, QEDE_PMD_VERSION);
214 DP_INFO(edev, " Driver version : %s\n", drv_ver);
215 DP_INFO(edev, " Firmware version : %s\n", ver_str);
217 snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
219 (info->mfw_rev >> 24) & 0xff,
220 (info->mfw_rev >> 16) & 0xff,
221 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
222 DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
223 DP_INFO(edev, " Firmware file : %s\n", fw_file);
224 DP_INFO(edev, "*********************************\n");
227 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
229 memset(ucast, 0, sizeof(struct ecore_filter_ucast));
230 ucast->is_rx_filter = true;
231 ucast->is_tx_filter = true;
232 /* ucast->assert_on_error = true; - For debug */
236 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
239 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
240 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
241 struct qede_ucast_entry *tmp = NULL;
242 struct qede_ucast_entry *u;
243 struct ether_addr *mac_addr;
245 mac_addr = (struct ether_addr *)ucast->mac;
247 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
248 if ((memcmp(mac_addr, &tmp->mac,
249 ETHER_ADDR_LEN) == 0) &&
250 ucast->vlan == tmp->vlan) {
251 DP_ERR(edev, "Unicast MAC is already added"
252 " with vlan = %u, vni = %u\n",
253 ucast->vlan, ucast->vni);
257 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
258 RTE_CACHE_LINE_SIZE);
260 DP_ERR(edev, "Did not allocate memory for ucast\n");
263 ether_addr_copy(mac_addr, &u->mac);
264 u->vlan = ucast->vlan;
265 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
268 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
269 if ((memcmp(mac_addr, &tmp->mac,
270 ETHER_ADDR_LEN) == 0) &&
271 ucast->vlan == tmp->vlan)
275 DP_INFO(edev, "Unicast MAC is not found\n");
278 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
286 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
289 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
290 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
291 struct ether_addr *mac_addr;
292 struct qede_mcast_entry *tmp = NULL;
293 struct qede_mcast_entry *m;
295 mac_addr = (struct ether_addr *)mcast->mac;
297 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
298 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
300 "Multicast MAC is already added\n");
304 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
305 RTE_CACHE_LINE_SIZE);
308 "Did not allocate memory for mcast\n");
311 ether_addr_copy(mac_addr, &m->mac);
312 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
315 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
316 if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
320 DP_INFO(edev, "Multicast mac is not found\n");
323 SLIST_REMOVE(&qdev->mc_list_head, tmp,
324 qede_mcast_entry, list);
331 static enum _ecore_status_t
332 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
335 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
336 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
337 enum _ecore_status_t rc;
338 struct ecore_filter_mcast mcast;
339 struct qede_mcast_entry *tmp;
343 if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
345 if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
347 "Mcast filter table limit exceeded, "
348 "Please enable mcast promisc mode\n");
352 rc = qede_mcast_filter(eth_dev, ucast, add);
354 DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
355 memset(&mcast, 0, sizeof(mcast));
356 mcast.num_mc_addrs = qdev->num_mc_addr;
357 mcast.opcode = ECORE_FILTER_ADD;
358 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
359 ether_addr_copy(&tmp->mac,
360 (struct ether_addr *)&mcast.mac[j]);
363 rc = ecore_filter_mcast_cmd(edev, &mcast,
364 ECORE_SPQ_MODE_CB, NULL);
366 if (rc != ECORE_SUCCESS) {
367 DP_ERR(edev, "Failed to add multicast filter"
368 " rc = %d, op = %d\n", rc, add);
370 } else { /* Unicast */
372 if (qdev->num_uc_addr >= qdev->dev_info.num_mac_addrs) {
374 "Ucast filter table limit exceeded,"
375 " Please enable promisc mode\n");
379 rc = qede_ucast_filter(eth_dev, ucast, add);
381 rc = ecore_filter_ucast_cmd(edev, ucast,
382 ECORE_SPQ_MODE_CB, NULL);
383 if (rc != ECORE_SUCCESS) {
384 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
393 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
394 uint32_t index, __rte_unused uint32_t pool)
396 struct ecore_filter_ucast ucast;
398 qede_set_ucast_cmn_params(&ucast);
399 ucast.type = ECORE_FILTER_MAC;
400 ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
401 (void)qede_mac_int_ops(eth_dev, &ucast, 1);
405 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
407 struct qede_dev *qdev = eth_dev->data->dev_private;
408 struct ecore_dev *edev = &qdev->edev;
409 struct ether_addr mac_addr;
410 struct ecore_filter_ucast ucast;
413 PMD_INIT_FUNC_TRACE(edev);
415 if (index >= qdev->dev_info.num_mac_addrs) {
416 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
417 index, qdev->dev_info.num_mac_addrs);
421 qede_set_ucast_cmn_params(&ucast);
422 ucast.opcode = ECORE_FILTER_REMOVE;
423 ucast.type = ECORE_FILTER_MAC;
425 /* Use the index maintained by rte */
426 ether_addr_copy(ð_dev->data->mac_addrs[index],
427 (struct ether_addr *)&ucast.mac);
429 ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
433 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
435 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
436 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
438 if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
439 mac_addr->addr_bytes)) {
440 DP_ERR(edev, "Setting MAC address is not allowed\n");
441 ether_addr_copy(&qdev->primary_mac,
442 ð_dev->data->mac_addrs[0]);
446 qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
449 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
451 struct ecore_dev *edev = &qdev->edev;
452 struct qed_update_vport_params params = {
454 .accept_any_vlan = action,
455 .update_accept_any_vlan_flg = 1,
459 /* Proceed only if action actually needs to be performed */
460 if (qdev->accept_any_vlan == action)
463 rc = qdev->ops->vport_update(edev, ¶ms);
465 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
466 action ? "enable" : "disable");
468 DP_INFO(edev, "%s accept-any-vlan\n",
469 action ? "enabled" : "disabled");
470 qdev->accept_any_vlan = action;
474 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
476 struct qed_update_vport_params vport_update_params;
477 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
478 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
481 memset(&vport_update_params, 0, sizeof(vport_update_params));
482 vport_update_params.vport_id = 0;
483 vport_update_params.update_inner_vlan_removal_flg = 1;
484 vport_update_params.inner_vlan_removal_flg = set_stripping;
485 rc = qdev->ops->vport_update(edev, &vport_update_params);
487 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
494 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
496 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
497 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
498 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
500 if (mask & ETH_VLAN_STRIP_MASK) {
501 if (rxmode->hw_vlan_strip)
502 (void)qede_vlan_stripping(eth_dev, 1);
504 (void)qede_vlan_stripping(eth_dev, 0);
507 if (mask & ETH_VLAN_FILTER_MASK) {
508 /* VLAN filtering kicks in when a VLAN is added */
509 if (rxmode->hw_vlan_filter) {
510 qede_vlan_filter_set(eth_dev, 0, 1);
512 if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
513 DP_NOTICE(edev, false,
514 " Please remove existing VLAN filters"
515 " before disabling VLAN filtering\n");
516 /* Signal app that VLAN filtering is still
519 rxmode->hw_vlan_filter = true;
521 qede_vlan_filter_set(eth_dev, 0, 0);
526 if (mask & ETH_VLAN_EXTEND_MASK)
527 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
528 " and classification is based on outer tag only\n");
530 DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
531 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
534 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
535 uint16_t vlan_id, int on)
537 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
538 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
539 struct qed_dev_eth_info *dev_info = &qdev->dev_info;
540 struct qede_vlan_entry *tmp = NULL;
541 struct qede_vlan_entry *vlan;
542 struct ecore_filter_ucast ucast;
546 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
547 DP_INFO(edev, "Reached max VLAN filter limit"
548 " enabling accept_any_vlan\n");
549 qede_config_accept_any_vlan(qdev, true);
553 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
554 if (tmp->vid == vlan_id) {
555 DP_ERR(edev, "VLAN %u already configured\n",
561 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
562 RTE_CACHE_LINE_SIZE);
565 DP_ERR(edev, "Did not allocate memory for VLAN\n");
569 qede_set_ucast_cmn_params(&ucast);
570 ucast.opcode = ECORE_FILTER_ADD;
571 ucast.type = ECORE_FILTER_VLAN;
572 ucast.vlan = vlan_id;
573 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
576 DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
581 SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
582 qdev->configured_vlans++;
583 DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
584 vlan_id, qdev->configured_vlans);
587 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
588 if (tmp->vid == vlan_id)
593 if (qdev->configured_vlans == 0) {
595 "No VLAN filters configured yet\n");
599 DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
603 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
605 qede_set_ucast_cmn_params(&ucast);
606 ucast.opcode = ECORE_FILTER_REMOVE;
607 ucast.type = ECORE_FILTER_VLAN;
608 ucast.vlan = vlan_id;
609 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
612 DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
615 qdev->configured_vlans--;
616 DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
617 vlan_id, qdev->configured_vlans);
624 static int qede_init_vport(struct qede_dev *qdev)
626 struct ecore_dev *edev = &qdev->edev;
627 struct qed_start_vport_params start = {0};
630 start.remove_inner_vlan = 1;
631 start.gro_enable = 0;
632 start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
634 start.drop_ttl0 = false;
635 start.clear_stats = 1;
636 start.handle_ptp_pkts = 0;
638 rc = qdev->ops->vport_start(edev, &start);
640 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
645 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
646 start.vport_id, ETHER_MTU);
651 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
653 struct qede_dev *qdev = eth_dev->data->dev_private;
654 struct ecore_dev *edev = &qdev->edev;
655 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode;
658 PMD_INIT_FUNC_TRACE(edev);
660 /* Check requirements for 100G mode */
661 if (edev->num_hwfns > 1) {
662 if (eth_dev->data->nb_rx_queues < 2 ||
663 eth_dev->data->nb_tx_queues < 2) {
664 DP_NOTICE(edev, false,
665 "100G mode needs min. 2 RX/TX queues\n");
669 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
670 (eth_dev->data->nb_tx_queues % 2 != 0)) {
671 DP_NOTICE(edev, false,
672 "100G mode needs even no. of RX/TX queues\n");
677 /* Sanity checks and throw warnings */
678 if (rxmode->enable_scatter == 1)
679 eth_dev->data->scattered_rx = 1;
681 if (rxmode->enable_lro == 1) {
682 DP_INFO(edev, "LRO is not supported\n");
686 if (!rxmode->hw_strip_crc)
687 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
689 if (!rxmode->hw_ip_checksum)
690 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
693 /* Check for the port restart case */
694 if (qdev->state != QEDE_DEV_INIT) {
695 rc = qdev->ops->vport_stop(edev, 0);
698 qede_dealloc_fp_resc(eth_dev);
701 qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
702 qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
703 qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
705 /* Fastpath status block should be initialized before sending
706 * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
708 rc = qede_alloc_fp_resc(qdev);
712 /* Issue VPORT-START with default config values to allow
713 * other port configurations early on.
715 rc = qede_init_vport(qdev);
719 SLIST_INIT(&qdev->vlan_list_head);
721 /* Enable VLAN offloads by default */
722 qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK |
723 ETH_VLAN_FILTER_MASK |
724 ETH_VLAN_EXTEND_MASK);
726 qdev->state = QEDE_DEV_CONFIG;
728 DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
729 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
735 /* Info about HW descriptor ring limitations */
736 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
737 .nb_max = NUM_RX_BDS_MAX,
739 .nb_align = 128 /* lowest common multiple */
742 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
743 .nb_max = NUM_TX_BDS_MAX,
749 qede_dev_info_get(struct rte_eth_dev *eth_dev,
750 struct rte_eth_dev_info *dev_info)
752 struct qede_dev *qdev = eth_dev->data->dev_private;
753 struct ecore_dev *edev = &qdev->edev;
754 struct qed_link_output link;
755 uint32_t speed_cap = 0;
757 PMD_INIT_FUNC_TRACE(edev);
759 dev_info->min_rx_bufsize = (uint32_t)(ETHER_MIN_MTU +
761 dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
762 dev_info->rx_desc_lim = qede_rx_desc_lim;
763 dev_info->tx_desc_lim = qede_tx_desc_lim;
764 dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev);
765 dev_info->max_tx_queues = dev_info->max_rx_queues;
766 dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs;
768 dev_info->max_vfs = 0;
770 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev);
771 dev_info->driver_name = qdev->drv_ver;
772 dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
773 dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
775 dev_info->default_txconf = (struct rte_eth_txconf) {
776 .txq_flags = QEDE_TXQ_FLAGS,
779 dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
780 DEV_RX_OFFLOAD_IPV4_CKSUM |
781 DEV_RX_OFFLOAD_UDP_CKSUM |
782 DEV_RX_OFFLOAD_TCP_CKSUM);
783 dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
784 DEV_TX_OFFLOAD_IPV4_CKSUM |
785 DEV_TX_OFFLOAD_UDP_CKSUM |
786 DEV_TX_OFFLOAD_TCP_CKSUM);
788 memset(&link, 0, sizeof(struct qed_link_output));
789 qdev->ops->common->get_link(edev, &link);
790 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
791 speed_cap |= ETH_LINK_SPEED_1G;
792 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
793 speed_cap |= ETH_LINK_SPEED_10G;
794 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
795 speed_cap |= ETH_LINK_SPEED_25G;
796 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
797 speed_cap |= ETH_LINK_SPEED_40G;
798 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
799 speed_cap |= ETH_LINK_SPEED_50G;
800 if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
801 speed_cap |= ETH_LINK_SPEED_100G;
802 dev_info->speed_capa = speed_cap;
805 /* return 0 means link status changed, -1 means not changed */
807 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
809 struct qede_dev *qdev = eth_dev->data->dev_private;
810 struct ecore_dev *edev = &qdev->edev;
811 uint16_t link_duplex;
812 struct qed_link_output link;
813 struct rte_eth_link *curr = ð_dev->data->dev_link;
815 memset(&link, 0, sizeof(struct qed_link_output));
816 qdev->ops->common->get_link(edev, &link);
819 curr->link_speed = link.speed;
822 switch (link.duplex) {
823 case QEDE_DUPLEX_HALF:
824 link_duplex = ETH_LINK_HALF_DUPLEX;
826 case QEDE_DUPLEX_FULL:
827 link_duplex = ETH_LINK_FULL_DUPLEX;
829 case QEDE_DUPLEX_UNKNOWN:
833 curr->link_duplex = link_duplex;
836 curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
839 curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
840 ETH_LINK_AUTONEG : ETH_LINK_FIXED;
842 DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
843 curr->link_speed, curr->link_duplex,
844 curr->link_autoneg, curr->link_status);
846 /* return 0 means link status changed, -1 means not changed */
847 return ((curr->link_status == link.link_up) ? -1 : 0);
850 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
852 struct qede_dev *qdev = eth_dev->data->dev_private;
853 struct ecore_dev *edev = &qdev->edev;
855 PMD_INIT_FUNC_TRACE(edev);
857 enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
859 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
860 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
862 qed_configure_filter_rx_mode(eth_dev, type);
865 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
867 struct qede_dev *qdev = eth_dev->data->dev_private;
868 struct ecore_dev *edev = &qdev->edev;
870 PMD_INIT_FUNC_TRACE(edev);
872 if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
873 qed_configure_filter_rx_mode(eth_dev,
874 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
876 qed_configure_filter_rx_mode(eth_dev,
877 QED_FILTER_RX_MODE_TYPE_REGULAR);
880 static void qede_poll_sp_sb_cb(void *param)
882 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
883 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
884 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
887 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
888 qede_interrupt_action(&edev->hwfns[1]);
890 rc = rte_eal_alarm_set(timer_period * US_PER_S,
894 DP_ERR(edev, "Unable to start periodic"
895 " timer rc %d\n", rc);
896 assert(false && "Unable to start periodic timer");
900 static void qede_dev_close(struct rte_eth_dev *eth_dev)
902 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
903 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
906 PMD_INIT_FUNC_TRACE(edev);
908 /* dev_stop() shall cleanup fp resources in hw but without releasing
909 * dma memories and sw structures so that dev_start() can be called
910 * by the app without reconfiguration. However, in dev_close() we
911 * can release all the resources and device can be brought up newly
913 if (qdev->state != QEDE_DEV_STOP)
914 qede_dev_stop(eth_dev);
916 DP_INFO(edev, "Device is already stopped\n");
918 rc = qdev->ops->vport_stop(edev, 0);
920 DP_ERR(edev, "Failed to stop VPORT\n");
922 qede_dealloc_fp_resc(eth_dev);
924 qdev->ops->common->slowpath_stop(edev);
926 qdev->ops->common->remove(edev);
928 rte_intr_disable(ð_dev->pci_dev->intr_handle);
930 rte_intr_callback_unregister(ð_dev->pci_dev->intr_handle,
931 qede_interrupt_handler, (void *)eth_dev);
933 if (edev->num_hwfns > 1)
934 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
936 qdev->state = QEDE_DEV_INIT; /* Go back to init state */
940 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
942 struct qede_dev *qdev = eth_dev->data->dev_private;
943 struct ecore_dev *edev = &qdev->edev;
944 struct ecore_eth_stats stats;
945 unsigned int i = 0, j = 0, qid;
946 unsigned int rxq_stat_cntrs, txq_stat_cntrs;
947 struct qede_tx_queue *txq;
949 qdev->ops->get_vport_stats(edev, &stats);
952 eth_stats->ipackets = stats.rx_ucast_pkts +
953 stats.rx_mcast_pkts + stats.rx_bcast_pkts;
955 eth_stats->ibytes = stats.rx_ucast_bytes +
956 stats.rx_mcast_bytes + stats.rx_bcast_bytes;
958 eth_stats->ierrors = stats.rx_crc_errors +
959 stats.rx_align_errors +
960 stats.rx_carrier_errors +
961 stats.rx_oversize_packets +
962 stats.rx_jabbers + stats.rx_undersize_packets;
964 eth_stats->rx_nombuf = stats.no_buff_discards;
966 eth_stats->imissed = stats.mftag_filter_discards +
967 stats.mac_filter_discards +
968 stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
971 eth_stats->opackets = stats.tx_ucast_pkts +
972 stats.tx_mcast_pkts + stats.tx_bcast_pkts;
974 eth_stats->obytes = stats.tx_ucast_bytes +
975 stats.tx_mcast_bytes + stats.tx_bcast_bytes;
977 eth_stats->oerrors = stats.tx_err_drop_pkts;
980 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
981 RTE_ETHDEV_QUEUE_STAT_CNTRS);
982 txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
983 RTE_ETHDEV_QUEUE_STAT_CNTRS);
984 if ((rxq_stat_cntrs != QEDE_RSS_COUNT(qdev)) ||
985 (txq_stat_cntrs != QEDE_TSS_COUNT(qdev)))
986 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
987 "Not all the queue stats will be displayed. Set"
988 " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
989 " appropriately and retry.\n");
991 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
992 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
993 eth_stats->q_ipackets[i] =
995 ((char *)(qdev->fp_array[(qid)].rxq)) +
996 offsetof(struct qede_rx_queue,
998 eth_stats->q_errors[i] =
1000 ((char *)(qdev->fp_array[(qid)].rxq)) +
1001 offsetof(struct qede_rx_queue,
1004 ((char *)(qdev->fp_array[(qid)].rxq)) +
1005 offsetof(struct qede_rx_queue,
1009 if (i == rxq_stat_cntrs)
1013 for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1014 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1015 txq = qdev->fp_array[(qid)].txqs[0];
1016 eth_stats->q_opackets[j] =
1017 *((uint64_t *)(uintptr_t)
1018 (((uint64_t)(uintptr_t)(txq)) +
1019 offsetof(struct qede_tx_queue,
1023 if (j == txq_stat_cntrs)
1029 qede_get_xstats_count(struct qede_dev *qdev) {
1030 return RTE_DIM(qede_xstats_strings) +
1031 (RTE_DIM(qede_rxq_xstats_strings) *
1032 RTE_MIN(QEDE_RSS_COUNT(qdev),
1033 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1037 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1038 struct rte_eth_xstat_name *xstats_names, unsigned limit)
1040 struct qede_dev *qdev = dev->data->dev_private;
1041 const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1042 unsigned int i, qid, stat_idx = 0;
1043 unsigned int rxq_stat_cntrs;
1045 if (xstats_names != NULL) {
1046 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1047 snprintf(xstats_names[stat_idx].name,
1048 sizeof(xstats_names[stat_idx].name),
1050 qede_xstats_strings[i].name);
1054 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1055 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1056 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1057 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1058 snprintf(xstats_names[stat_idx].name,
1059 sizeof(xstats_names[stat_idx].name),
1061 qede_rxq_xstats_strings[i].name, qid,
1062 qede_rxq_xstats_strings[i].name + 4);
1072 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1075 struct qede_dev *qdev = dev->data->dev_private;
1076 struct ecore_dev *edev = &qdev->edev;
1077 struct ecore_eth_stats stats;
1078 const unsigned int num = qede_get_xstats_count(qdev);
1079 unsigned int i, qid, stat_idx = 0;
1080 unsigned int rxq_stat_cntrs;
1085 qdev->ops->get_vport_stats(edev, &stats);
1087 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1088 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1089 qede_xstats_strings[i].offset);
1090 xstats[stat_idx].id = stat_idx;
1094 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1095 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1096 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1097 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1098 for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1099 xstats[stat_idx].value = *(uint64_t *)(
1100 ((char *)(qdev->fp_array[(qid)].rxq)) +
1101 qede_rxq_xstats_strings[i].offset);
1102 xstats[stat_idx].id = stat_idx;
1112 qede_reset_xstats(struct rte_eth_dev *dev)
1114 struct qede_dev *qdev = dev->data->dev_private;
1115 struct ecore_dev *edev = &qdev->edev;
1117 ecore_reset_vport_stats(edev);
1120 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1122 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1123 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1124 struct qed_link_params link_params;
1127 DP_INFO(edev, "setting link state %d\n", link_up);
1128 memset(&link_params, 0, sizeof(link_params));
1129 link_params.link_up = link_up;
1130 rc = qdev->ops->common->set_link(edev, &link_params);
1131 if (rc != ECORE_SUCCESS)
1132 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1137 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1139 return qede_dev_set_link_state(eth_dev, true);
1142 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1144 return qede_dev_set_link_state(eth_dev, false);
1147 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1149 struct qede_dev *qdev = eth_dev->data->dev_private;
1150 struct ecore_dev *edev = &qdev->edev;
1152 ecore_reset_vport_stats(edev);
1155 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1157 enum qed_filter_rx_mode_type type =
1158 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1160 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1161 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1163 qed_configure_filter_rx_mode(eth_dev, type);
1166 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1168 if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1169 qed_configure_filter_rx_mode(eth_dev,
1170 QED_FILTER_RX_MODE_TYPE_PROMISC);
1172 qed_configure_filter_rx_mode(eth_dev,
1173 QED_FILTER_RX_MODE_TYPE_REGULAR);
1176 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1177 struct rte_eth_fc_conf *fc_conf)
1179 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1180 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1181 struct qed_link_output current_link;
1182 struct qed_link_params params;
1184 memset(¤t_link, 0, sizeof(current_link));
1185 qdev->ops->common->get_link(edev, ¤t_link);
1187 memset(¶ms, 0, sizeof(params));
1188 params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1189 if (fc_conf->autoneg) {
1190 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1191 DP_ERR(edev, "Autoneg not supported\n");
1194 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1197 /* Pause is assumed to be supported (SUPPORTED_Pause) */
1198 if (fc_conf->mode == RTE_FC_FULL)
1199 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1200 QED_LINK_PAUSE_RX_ENABLE);
1201 if (fc_conf->mode == RTE_FC_TX_PAUSE)
1202 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1203 if (fc_conf->mode == RTE_FC_RX_PAUSE)
1204 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1206 params.link_up = true;
1207 (void)qdev->ops->common->set_link(edev, ¶ms);
1212 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1213 struct rte_eth_fc_conf *fc_conf)
1215 struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1216 struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1217 struct qed_link_output current_link;
1219 memset(¤t_link, 0, sizeof(current_link));
1220 qdev->ops->common->get_link(edev, ¤t_link);
1222 if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1223 fc_conf->autoneg = true;
1225 if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1226 QED_LINK_PAUSE_TX_ENABLE))
1227 fc_conf->mode = RTE_FC_FULL;
1228 else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1229 fc_conf->mode = RTE_FC_RX_PAUSE;
1230 else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1231 fc_conf->mode = RTE_FC_TX_PAUSE;
1233 fc_conf->mode = RTE_FC_NONE;
1238 static const uint32_t *
1239 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1241 static const uint32_t ptypes[] = {
1247 if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1253 void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1256 *rss_caps |= (hf & ETH_RSS_IPV4) ? ECORE_RSS_IPV4 : 0;
1257 *rss_caps |= (hf & ETH_RSS_IPV6) ? ECORE_RSS_IPV6 : 0;
1258 *rss_caps |= (hf & ETH_RSS_IPV6_EX) ? ECORE_RSS_IPV6 : 0;
1259 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? ECORE_RSS_IPV4_TCP : 0;
1260 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? ECORE_RSS_IPV6_TCP : 0;
1261 *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX) ? ECORE_RSS_IPV6_TCP : 0;
1262 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? ECORE_RSS_IPV4_UDP : 0;
1263 *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? ECORE_RSS_IPV6_UDP : 0;
1266 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1267 struct rte_eth_rss_conf *rss_conf)
1269 struct qed_update_vport_params vport_update_params;
1270 struct qede_dev *qdev = eth_dev->data->dev_private;
1271 struct ecore_dev *edev = &qdev->edev;
1272 uint32_t *key = (uint32_t *)rss_conf->rss_key;
1273 uint64_t hf = rss_conf->rss_hf;
1276 memset(&vport_update_params, 0, sizeof(vport_update_params));
1280 qede_init_rss_caps(&qdev->rss_params.rss_caps, hf);
1281 memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1282 sizeof(vport_update_params.rss_params));
1284 memcpy(qdev->rss_params.rss_key, rss_conf->rss_key,
1285 rss_conf->rss_key_len);
1286 vport_update_params.update_rss_flg = 1;
1287 qdev->rss_enabled = 1;
1290 qdev->rss_enabled = 0;
1293 /* If the mapping doesn't fit any supported, return */
1294 if (qdev->rss_params.rss_caps == 0 && hf != 0)
1297 DP_INFO(edev, "%s\n", (vport_update_params.update_rss_flg) ?
1298 "Enabling RSS" : "Disabling RSS");
1300 vport_update_params.vport_id = 0;
1302 return qdev->ops->vport_update(edev, &vport_update_params);
1305 int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1306 struct rte_eth_rss_conf *rss_conf)
1308 struct qede_dev *qdev = eth_dev->data->dev_private;
1311 if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key))
1314 if (rss_conf->rss_key)
1315 memcpy(rss_conf->rss_key, qdev->rss_params.rss_key,
1316 sizeof(qdev->rss_params.rss_key));
1319 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4) ?
1321 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6) ?
1323 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6) ?
1324 ETH_RSS_IPV6_EX : 0;
1325 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ?
1326 ETH_RSS_NONFRAG_IPV4_TCP : 0;
1327 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1328 ETH_RSS_NONFRAG_IPV6_TCP : 0;
1329 hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1330 ETH_RSS_IPV6_TCP_EX : 0;
1332 rss_conf->rss_hf = hf;
1337 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1338 struct rte_eth_rss_reta_entry64 *reta_conf,
1341 struct qed_update_vport_params vport_update_params;
1342 struct qede_dev *qdev = eth_dev->data->dev_private;
1343 struct ecore_dev *edev = &qdev->edev;
1344 uint16_t i, idx, shift;
1346 if (reta_size > ETH_RSS_RETA_SIZE_128) {
1347 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1352 memset(&vport_update_params, 0, sizeof(vport_update_params));
1353 memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1354 sizeof(vport_update_params.rss_params));
1356 for (i = 0; i < reta_size; i++) {
1357 idx = i / RTE_RETA_GROUP_SIZE;
1358 shift = i % RTE_RETA_GROUP_SIZE;
1359 if (reta_conf[idx].mask & (1ULL << shift)) {
1360 uint8_t entry = reta_conf[idx].reta[shift];
1361 qdev->rss_params.rss_ind_table[i] = entry;
1365 vport_update_params.update_rss_flg = 1;
1366 vport_update_params.vport_id = 0;
1368 return qdev->ops->vport_update(edev, &vport_update_params);
1371 int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1372 struct rte_eth_rss_reta_entry64 *reta_conf,
1375 struct qede_dev *qdev = eth_dev->data->dev_private;
1376 uint16_t i, idx, shift;
1378 if (reta_size > ETH_RSS_RETA_SIZE_128) {
1379 struct ecore_dev *edev = &qdev->edev;
1380 DP_ERR(edev, "reta_size %d is not supported\n",
1384 for (i = 0; i < reta_size; i++) {
1385 idx = i / RTE_RETA_GROUP_SIZE;
1386 shift = i % RTE_RETA_GROUP_SIZE;
1387 if (reta_conf[idx].mask & (1ULL << shift)) {
1388 uint8_t entry = qdev->rss_params.rss_ind_table[i];
1389 reta_conf[idx].reta[shift] = entry;
1396 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1398 uint32_t frame_size;
1399 struct qede_dev *qdev = dev->data->dev_private;
1400 struct rte_eth_dev_info dev_info = {0};
1402 qede_dev_info_get(dev, &dev_info);
1405 frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4;
1407 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1410 if (!dev->data->scattered_rx &&
1411 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1414 if (frame_size > ETHER_MAX_LEN)
1415 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1417 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1419 /* update max frame size */
1420 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1423 qede_dev_start(dev);
1428 static const struct eth_dev_ops qede_eth_dev_ops = {
1429 .dev_configure = qede_dev_configure,
1430 .dev_infos_get = qede_dev_info_get,
1431 .rx_queue_setup = qede_rx_queue_setup,
1432 .rx_queue_release = qede_rx_queue_release,
1433 .tx_queue_setup = qede_tx_queue_setup,
1434 .tx_queue_release = qede_tx_queue_release,
1435 .dev_start = qede_dev_start,
1436 .dev_set_link_up = qede_dev_set_link_up,
1437 .dev_set_link_down = qede_dev_set_link_down,
1438 .link_update = qede_link_update,
1439 .promiscuous_enable = qede_promiscuous_enable,
1440 .promiscuous_disable = qede_promiscuous_disable,
1441 .allmulticast_enable = qede_allmulticast_enable,
1442 .allmulticast_disable = qede_allmulticast_disable,
1443 .dev_stop = qede_dev_stop,
1444 .dev_close = qede_dev_close,
1445 .stats_get = qede_get_stats,
1446 .stats_reset = qede_reset_stats,
1447 .xstats_get = qede_get_xstats,
1448 .xstats_reset = qede_reset_xstats,
1449 .xstats_get_names = qede_get_xstats_names,
1450 .mac_addr_add = qede_mac_addr_add,
1451 .mac_addr_remove = qede_mac_addr_remove,
1452 .mac_addr_set = qede_mac_addr_set,
1453 .vlan_offload_set = qede_vlan_offload_set,
1454 .vlan_filter_set = qede_vlan_filter_set,
1455 .flow_ctrl_set = qede_flow_ctrl_set,
1456 .flow_ctrl_get = qede_flow_ctrl_get,
1457 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1458 .rss_hash_update = qede_rss_hash_update,
1459 .rss_hash_conf_get = qede_rss_hash_conf_get,
1460 .reta_update = qede_rss_reta_update,
1461 .reta_query = qede_rss_reta_query,
1462 .mtu_set = qede_set_mtu,
1465 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
1466 .dev_configure = qede_dev_configure,
1467 .dev_infos_get = qede_dev_info_get,
1468 .rx_queue_setup = qede_rx_queue_setup,
1469 .rx_queue_release = qede_rx_queue_release,
1470 .tx_queue_setup = qede_tx_queue_setup,
1471 .tx_queue_release = qede_tx_queue_release,
1472 .dev_start = qede_dev_start,
1473 .dev_set_link_up = qede_dev_set_link_up,
1474 .dev_set_link_down = qede_dev_set_link_down,
1475 .link_update = qede_link_update,
1476 .promiscuous_enable = qede_promiscuous_enable,
1477 .promiscuous_disable = qede_promiscuous_disable,
1478 .allmulticast_enable = qede_allmulticast_enable,
1479 .allmulticast_disable = qede_allmulticast_disable,
1480 .dev_stop = qede_dev_stop,
1481 .dev_close = qede_dev_close,
1482 .stats_get = qede_get_stats,
1483 .stats_reset = qede_reset_stats,
1484 .xstats_get = qede_get_xstats,
1485 .xstats_reset = qede_reset_xstats,
1486 .xstats_get_names = qede_get_xstats_names,
1487 .vlan_offload_set = qede_vlan_offload_set,
1488 .vlan_filter_set = qede_vlan_filter_set,
1489 .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1490 .rss_hash_update = qede_rss_hash_update,
1491 .rss_hash_conf_get = qede_rss_hash_conf_get,
1492 .reta_update = qede_rss_reta_update,
1493 .reta_query = qede_rss_reta_query,
1494 .mtu_set = qede_set_mtu,
1497 static void qede_update_pf_params(struct ecore_dev *edev)
1499 struct ecore_pf_params pf_params;
1501 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
1502 pf_params.eth_pf_params.num_cons = 64;
1503 qed_ops->common->update_pf_params(edev, &pf_params);
1506 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
1508 struct rte_pci_device *pci_dev;
1509 struct rte_pci_addr pci_addr;
1510 struct qede_dev *adapter;
1511 struct ecore_dev *edev;
1512 struct qed_dev_eth_info dev_info;
1513 struct qed_slowpath_params params;
1514 static bool do_once = true;
1515 uint8_t bulletin_change;
1516 uint8_t vf_mac[ETHER_ADDR_LEN];
1517 uint8_t is_mac_forced;
1519 /* Fix up ecore debug level */
1520 uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
1521 uint8_t dp_level = ECORE_LEVEL_VERBOSE;
1522 uint32_t max_mac_addrs;
1525 /* Extract key data structures */
1526 adapter = eth_dev->data->dev_private;
1527 edev = &adapter->edev;
1528 pci_addr = eth_dev->pci_dev->addr;
1530 PMD_INIT_FUNC_TRACE(edev);
1532 snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
1533 pci_addr.bus, pci_addr.devid, pci_addr.function,
1534 eth_dev->data->port_id);
1536 eth_dev->rx_pkt_burst = qede_recv_pkts;
1537 eth_dev->tx_pkt_burst = qede_xmit_pkts;
1539 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1540 DP_NOTICE(edev, false,
1541 "Skipping device init from secondary process\n");
1545 pci_dev = eth_dev->pci_dev;
1547 rte_eth_copy_pci_info(eth_dev, pci_dev);
1550 edev->vendor_id = pci_dev->id.vendor_id;
1551 edev->device_id = pci_dev->id.device_id;
1553 qed_ops = qed_get_eth_ops();
1555 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
1559 DP_INFO(edev, "Starting qede probe\n");
1561 rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
1562 dp_module, dp_level, is_vf);
1565 DP_ERR(edev, "qede probe failed rc %d\n", rc);
1569 qede_update_pf_params(edev);
1571 rte_intr_callback_register(ð_dev->pci_dev->intr_handle,
1572 qede_interrupt_handler, (void *)eth_dev);
1574 if (rte_intr_enable(ð_dev->pci_dev->intr_handle)) {
1575 DP_ERR(edev, "rte_intr_enable() failed\n");
1579 /* Start the Slowpath-process */
1580 memset(¶ms, 0, sizeof(struct qed_slowpath_params));
1581 params.int_mode = ECORE_INT_MODE_MSIX;
1582 params.drv_major = QEDE_PMD_VERSION_MAJOR;
1583 params.drv_minor = QEDE_PMD_VERSION_MINOR;
1584 params.drv_rev = QEDE_PMD_VERSION_REVISION;
1585 params.drv_eng = QEDE_PMD_VERSION_PATCH;
1586 strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
1587 QEDE_PMD_DRV_VER_STR_SIZE);
1589 /* For CMT mode device do periodic polling for slowpath events.
1590 * This is required since uio device uses only one MSI-x
1591 * interrupt vector but we need one for each engine.
1593 if (edev->num_hwfns > 1 && IS_PF(edev)) {
1594 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1598 DP_ERR(edev, "Unable to start periodic"
1599 " timer rc %d\n", rc);
1604 rc = qed_ops->common->slowpath_start(edev, ¶ms);
1606 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
1607 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1612 rc = qed_ops->fill_dev_info(edev, &dev_info);
1614 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
1615 qed_ops->common->slowpath_stop(edev);
1616 qed_ops->common->remove(edev);
1617 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1622 qede_alloc_etherdev(adapter, &dev_info);
1624 adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION);
1627 adapter->dev_info.num_mac_addrs =
1628 (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
1631 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
1632 &adapter->dev_info.num_mac_addrs);
1634 /* Allocate memory for storing MAC addr */
1635 eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
1637 adapter->dev_info.num_mac_addrs),
1638 RTE_CACHE_LINE_SIZE);
1640 if (eth_dev->data->mac_addrs == NULL) {
1641 DP_ERR(edev, "Failed to allocate MAC address\n");
1642 qed_ops->common->slowpath_stop(edev);
1643 qed_ops->common->remove(edev);
1644 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1650 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
1651 hw_info.hw_mac_addr,
1652 ð_dev->data->mac_addrs[0]);
1653 ether_addr_copy(ð_dev->data->mac_addrs[0],
1654 &adapter->primary_mac);
1656 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
1658 if (bulletin_change) {
1660 ecore_vf_bulletin_get_forced_mac(
1661 ECORE_LEADING_HWFN(edev),
1664 if (is_mac_exist && is_mac_forced) {
1665 DP_INFO(edev, "VF macaddr received from PF\n");
1666 ether_addr_copy((struct ether_addr *)&vf_mac,
1667 ð_dev->data->mac_addrs[0]);
1668 ether_addr_copy(ð_dev->data->mac_addrs[0],
1669 &adapter->primary_mac);
1671 DP_NOTICE(edev, false,
1672 "No VF macaddr assigned\n");
1677 eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
1680 qede_print_adapter_info(adapter);
1684 adapter->state = QEDE_DEV_INIT;
1686 DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
1687 adapter->primary_mac.addr_bytes[0],
1688 adapter->primary_mac.addr_bytes[1],
1689 adapter->primary_mac.addr_bytes[2],
1690 adapter->primary_mac.addr_bytes[3],
1691 adapter->primary_mac.addr_bytes[4],
1692 adapter->primary_mac.addr_bytes[5]);
1697 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
1699 return qede_common_dev_init(eth_dev, 1);
1702 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
1704 return qede_common_dev_init(eth_dev, 0);
1707 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
1709 /* only uninitialize in the primary process */
1710 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1713 /* safe to close dev here */
1714 qede_dev_close(eth_dev);
1716 eth_dev->dev_ops = NULL;
1717 eth_dev->rx_pkt_burst = NULL;
1718 eth_dev->tx_pkt_burst = NULL;
1720 if (eth_dev->data->mac_addrs)
1721 rte_free(eth_dev->data->mac_addrs);
1723 eth_dev->data->mac_addrs = NULL;
1728 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1730 return qede_dev_common_uninit(eth_dev);
1733 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1735 return qede_dev_common_uninit(eth_dev);
1738 static struct rte_pci_id pci_id_qedevf_map[] = {
1739 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1741 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF)
1744 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV)
1749 static struct rte_pci_id pci_id_qede_map[] = {
1750 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1752 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E)
1755 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S)
1758 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40)
1761 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25)
1764 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100)
1769 static struct eth_driver rte_qedevf_pmd = {
1771 .id_table = pci_id_qedevf_map,
1773 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1774 .probe = rte_eth_dev_pci_probe,
1775 .remove = rte_eth_dev_pci_remove,
1777 .eth_dev_init = qedevf_eth_dev_init,
1778 .eth_dev_uninit = qedevf_eth_dev_uninit,
1779 .dev_private_size = sizeof(struct qede_dev),
1782 static struct eth_driver rte_qede_pmd = {
1784 .id_table = pci_id_qede_map,
1786 RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1787 .probe = rte_eth_dev_pci_probe,
1788 .remove = rte_eth_dev_pci_remove,
1790 .eth_dev_init = qede_eth_dev_init,
1791 .eth_dev_uninit = qede_eth_dev_uninit,
1792 .dev_private_size = sizeof(struct qede_dev),
1795 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv);
1796 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
1797 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv);
1798 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);