drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
 129         {"rx_multicast_bytes",
 130                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
 131         {"rx_broadcast_bytes",
 132                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
 133         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
 134         {"rx_multicast_packets",
 135                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
 136         {"rx_broadcast_packets",
 137                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
 138
 139         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
 140         {"tx_multicast_bytes",
 141                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
 142         {"tx_broadcast_bytes",
 143                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
 144         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
 145         {"tx_multicast_packets",
 146                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
 147         {"tx_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
 149
 150         {"rx_64_byte_packets",
 151                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
 152         {"rx_65_to_127_byte_packets",
 153                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
 154         {"rx_128_to_255_byte_packets",
 155                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
 156         {"rx_256_to_511_byte_packets",
 157                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
 158         {"rx_512_to_1023_byte_packets",
 159                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
 160         {"rx_1024_to_1518_byte_packets",
 161                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
 162         {"rx_1519_to_1522_byte_packets",
 163                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
 164         {"rx_1519_to_2047_byte_packets",
 165                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
 166         {"rx_2048_to_4095_byte_packets",
 167                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
 168         {"rx_4096_to_9216_byte_packets",
 169                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
 170         {"rx_9217_to_16383_byte_packets",
 171                 offsetof(struct ecore_eth_stats,
 172                          rx_9217_to_16383_byte_packets)},
 173         {"tx_64_byte_packets",
 174                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
 175         {"tx_65_to_127_byte_packets",
 176                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
 177         {"tx_128_to_255_byte_packets",
 178                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
 181         {"tx_512_to_1023_byte_packets",
 182                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
 183         {"tx_1024_to_1518_byte_packets",
 184                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
 185         {"trx_1519_to_1522_byte_packets",
 186                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
 187         {"tx_2048_to_4095_byte_packets",
 188                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
 189         {"tx_4096_to_9216_byte_packets",
 190                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
 191         {"tx_9217_to_16383_byte_packets",
 192                 offsetof(struct ecore_eth_stats,
 193                          tx_9217_to_16383_byte_packets)},
 194
 195         {"rx_mac_crtl_frames",
 196                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
 197         {"tx_mac_control_frames",
 198                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
 199         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
 200         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 205
 206         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 207         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 208         {"rx_carrier_errors",
 209                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 210         {"rx_oversize_packet_errors",
 211                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 212         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 213         {"rx_undersize_packet_errors",
 214                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 215         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 216         {"rx_host_buffer_not_available",
 217                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 218         /* Number of packets discarded because they are bigger than MTU */
 219         {"rx_packet_too_big_discards",
 220                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats, brb_discards)},
 231         {"tx_lpi_entry_count",
 232                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 233         {"tx_total_collisions",
 234                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 263         {"lro_coalesced_bytes",
 264                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 265 };
 266
 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 268         {"rx_q_segments",
 269                 offsetof(struct qede_rx_queue, rx_segs)},
 270         {"rx_q_hw_errors",
 271                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 272         {"rx_q_allocation_errors",
 273                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 274 };
 275
 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 277 {
 278         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 279 }
 280
 281 static void
 282 qede_interrupt_handler(void *param)
 283 {
 284         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 285         struct qede_dev *qdev = eth_dev->data->dev_private;
 286         struct ecore_dev *edev = &qdev->edev;
 287
 288         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 289         if (rte_intr_enable(eth_dev->intr_handle))
 290                 DP_ERR(edev, "rte_intr_enable failed\n");
 291 }
 292
 293 static void
 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 295 {
 296         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 297         qdev->num_tc = qdev->dev_info.num_tc;
 298         qdev->ops = qed_ops;
 299 }
 300
 301 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 302 static void qede_print_adapter_info(struct qede_dev *qdev)
 303 {
 304         struct ecore_dev *edev = &qdev->edev;
 305         struct qed_dev_info *info = &qdev->dev_info.common;
 306         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 307         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 308
 309         DP_INFO(edev, "*********************************\n");
 310         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 311         DP_INFO(edev, " Chip details : %s %c%d\n",
 312                   ECORE_IS_BB(edev) ? "BB" : "AH",
 313                   'A' + edev->chip_rev,
 314                   (int)edev->chip_metal);
 315         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 316                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 317         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 318                  ver_str, QEDE_PMD_VERSION);
 319         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 320         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 321
 322         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 323                  "%d.%d.%d.%d",
 324                 (info->mfw_rev >> 24) & 0xff,
 325                 (info->mfw_rev >> 16) & 0xff,
 326                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 327         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 328         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 329         DP_INFO(edev, "*********************************\n");
 330 }
 331 #endif
 332
 333 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 334 {
 335         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 336         ucast->is_rx_filter = true;
 337         ucast->is_tx_filter = true;
 338         /* ucast->assert_on_error = true; - For debug */
 339 }
 340
 341 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn,
 342                                     uint8_t clss, bool mode, bool mask)
 343 {
 344         memset(p_tunn, 0, sizeof(struct ecore_tunnel_info));
 345         p_tunn->vxlan.b_update_mode = mode;
 346         p_tunn->vxlan.b_mode_enabled = mask;
 347         p_tunn->b_update_rx_cls = true;
 348         p_tunn->b_update_tx_cls = true;
 349         p_tunn->vxlan.tun_cls = clss;
 350 }
 351
 352 static int
 353 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 354                   bool add)
 355 {
 356         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 357         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 358         struct qede_ucast_entry *tmp = NULL;
 359         struct qede_ucast_entry *u;
 360         struct ether_addr *mac_addr;
 361
 362         mac_addr  = (struct ether_addr *)ucast->mac;
 363         if (add) {
 364                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 365                         if ((memcmp(mac_addr, &tmp->mac,
 366                                     ETHER_ADDR_LEN) == 0) &&
 367                              ucast->vlan == tmp->vlan) {
 368                                 DP_ERR(edev, "Unicast MAC is already added"
 369                                        " with vlan = %u, vni = %u\n",
 370                                        ucast->vlan,  ucast->vni);
 371                                         return -EEXIST;
 372                         }
 373                 }
 374                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 375                                RTE_CACHE_LINE_SIZE);
 376                 if (!u) {
 377                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 378                         return -ENOMEM;
 379                 }
 380                 ether_addr_copy(mac_addr, &u->mac);
 381                 u->vlan = ucast->vlan;
 382                 u->vni = ucast->vni;
 383                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 384                 qdev->num_uc_addr++;
 385         } else {
 386                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 387                         if ((memcmp(mac_addr, &tmp->mac,
 388                                     ETHER_ADDR_LEN) == 0) &&
 389                             ucast->vlan == tmp->vlan      &&
 390                             ucast->vni == tmp->vni)
 391                         break;
 392                 }
 393                 if (tmp == NULL) {
 394                         DP_INFO(edev, "Unicast MAC is not found\n");
 395                         return -EINVAL;
 396                 }
 397                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 398                 qdev->num_uc_addr--;
 399         }
 400
 401         return 0;
 402 }
 403
 404 static int
 405 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 406                   bool add)
 407 {
 408         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 409         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 410         struct ether_addr *mac_addr;
 411         struct qede_mcast_entry *tmp = NULL;
 412         struct qede_mcast_entry *m;
 413
 414         mac_addr  = (struct ether_addr *)mcast->mac;
 415         if (add) {
 416                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 417                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 418                                 DP_ERR(edev,
 419                                         "Multicast MAC is already added\n");
 420                                 return -EEXIST;
 421                         }
 422                 }
 423                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 424                         RTE_CACHE_LINE_SIZE);
 425                 if (!m) {
 426                         DP_ERR(edev,
 427                                 "Did not allocate memory for mcast\n");
 428                         return -ENOMEM;
 429                 }
 430                 ether_addr_copy(mac_addr, &m->mac);
 431                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 432                 qdev->num_mc_addr++;
 433         } else {
 434                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 435                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 436                                 break;
 437                 }
 438                 if (tmp == NULL) {
 439                         DP_INFO(edev, "Multicast mac is not found\n");
 440                         return -EINVAL;
 441                 }
 442                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 443                              qede_mcast_entry, list);
 444                 qdev->num_mc_addr--;
 445         }
 446
 447         return 0;
 448 }
 449
 450 static enum _ecore_status_t
 451 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 452                  bool add)
 453 {
 454         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 455         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 456         enum _ecore_status_t rc;
 457         struct ecore_filter_mcast mcast;
 458         struct qede_mcast_entry *tmp;
 459         uint16_t j = 0;
 460
 461         /* Multicast */
 462         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 463                 if (add) {
 464                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 465                                 DP_ERR(edev,
 466                                        "Mcast filter table limit exceeded, "
 467                                        "Please enable mcast promisc mode\n");
 468                                 return -ECORE_INVAL;
 469                         }
 470                 }
 471                 rc = qede_mcast_filter(eth_dev, ucast, add);
 472                 if (rc == 0) {
 473                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 474                         memset(&mcast, 0, sizeof(mcast));
 475                         mcast.num_mc_addrs = qdev->num_mc_addr;
 476                         mcast.opcode = ECORE_FILTER_ADD;
 477                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 478                                 ether_addr_copy(&tmp->mac,
 479                                         (struct ether_addr *)&mcast.mac[j]);
 480                                 j++;
 481                         }
 482                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 483                                                     ECORE_SPQ_MODE_CB, NULL);
 484                 }
 485                 if (rc != ECORE_SUCCESS) {
 486                         DP_ERR(edev, "Failed to add multicast filter"
 487                                " rc = %d, op = %d\n", rc, add);
 488                 }
 489         } else { /* Unicast */
 490                 if (add) {
 491                         if (qdev->num_uc_addr >=
 492                             qdev->dev_info.num_mac_filters) {
 493                                 DP_ERR(edev,
 494                                        "Ucast filter table limit exceeded,"
 495                                        " Please enable promisc mode\n");
 496                                 return -ECORE_INVAL;
 497                         }
 498                 }
 499                 rc = qede_ucast_filter(eth_dev, ucast, add);
 500                 if (rc == 0)
 501                         rc = ecore_filter_ucast_cmd(edev, ucast,
 502                                                     ECORE_SPQ_MODE_CB, NULL);
 503                 if (rc != ECORE_SUCCESS) {
 504                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 505                                rc, add);
 506                 }
 507         }
 508
 509         return rc;
 510 }
 511
 512 static int
 513 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 514                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 515 {
 516         struct ecore_filter_ucast ucast;
 517         int re;
 518
 519         qede_set_ucast_cmn_params(&ucast);
 520         ucast.type = ECORE_FILTER_MAC;
 521         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 522         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 523         return re;
 524 }
 525
 526 static void
 527 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 528 {
 529         struct qede_dev *qdev = eth_dev->data->dev_private;
 530         struct ecore_dev *edev = &qdev->edev;
 531         struct ecore_filter_ucast ucast;
 532
 533         PMD_INIT_FUNC_TRACE(edev);
 534
 535         if (index >= qdev->dev_info.num_mac_filters) {
 536                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 537                        index, qdev->dev_info.num_mac_filters);
 538                 return;
 539         }
 540
 541         qede_set_ucast_cmn_params(&ucast);
 542         ucast.opcode = ECORE_FILTER_REMOVE;
 543         ucast.type = ECORE_FILTER_MAC;
 544
 545         /* Use the index maintained by rte */
 546         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 547                         (struct ether_addr *)&ucast.mac);
 548
 549         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 550 }
 551
 552 static void
 553 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 554 {
 555         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 556         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 557
 558         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 559                                                mac_addr->addr_bytes)) {
 560                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 561                 ether_addr_copy(&qdev->primary_mac,
 562                                 &eth_dev->data->mac_addrs[0]);
 563                 return;
 564         }
 565
 566         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 567 }
 568
 569 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 570 {
 571         struct ecore_dev *edev = &qdev->edev;
 572         struct qed_update_vport_params params = {
 573                 .vport_id = 0,
 574                 .accept_any_vlan = action,
 575                 .update_accept_any_vlan_flg = 1,
 576         };
 577         int rc;
 578
 579         /* Proceed only if action actually needs to be performed */
 580         if (qdev->accept_any_vlan == action)
 581                 return;
 582
 583         rc = qdev->ops->vport_update(edev, &params);
 584         if (rc) {
 585                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 586                        action ? "enable" : "disable");
 587         } else {
 588                 DP_INFO(edev, "%s accept-any-vlan\n",
 589                         action ? "enabled" : "disabled");
 590                 qdev->accept_any_vlan = action;
 591         }
 592 }
 593
 594 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 595 {
 596         struct qed_update_vport_params vport_update_params;
 597         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 598         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 599         int rc;
 600
 601         memset(&vport_update_params, 0, sizeof(vport_update_params));
 602         vport_update_params.vport_id = 0;
 603         vport_update_params.update_inner_vlan_removal_flg = 1;
 604         vport_update_params.inner_vlan_removal_flg = set_stripping;
 605         rc = qdev->ops->vport_update(edev, &vport_update_params);
 606         if (rc) {
 607                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 608                 return rc;
 609         }
 610         qdev->vlan_strip_flg = set_stripping;
 611
 612         return 0;
 613 }
 614
 615 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 616                                 uint16_t vlan_id, int on)
 617 {
 618         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 619         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 620         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 621         struct qede_vlan_entry *tmp = NULL;
 622         struct qede_vlan_entry *vlan;
 623         struct ecore_filter_ucast ucast;
 624         int rc;
 625
 626         if (on) {
 627                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 628                         DP_ERR(edev, "Reached max VLAN filter limit"
 629                                       " enabling accept_any_vlan\n");
 630                         qede_config_accept_any_vlan(qdev, true);
 631                         return 0;
 632                 }
 633
 634                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 635                         if (tmp->vid == vlan_id) {
 636                                 DP_ERR(edev, "VLAN %u already configured\n",
 637                                        vlan_id);
 638                                 return -EEXIST;
 639                         }
 640                 }
 641
 642                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 643                                   RTE_CACHE_LINE_SIZE);
 644
 645                 if (!vlan) {
 646                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 647                         return -ENOMEM;
 648                 }
 649
 650                 qede_set_ucast_cmn_params(&ucast);
 651                 ucast.opcode = ECORE_FILTER_ADD;
 652                 ucast.type = ECORE_FILTER_VLAN;
 653                 ucast.vlan = vlan_id;
 654                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 655                                             NULL);
 656                 if (rc != 0) {
 657                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 658                                rc);
 659                         rte_free(vlan);
 660                 } else {
 661                         vlan->vid = vlan_id;
 662                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 663                         qdev->configured_vlans++;
 664                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 665                                 vlan_id, qdev->configured_vlans);
 666                 }
 667         } else {
 668                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 669                         if (tmp->vid == vlan_id)
 670                                 break;
 671                 }
 672
 673                 if (!tmp) {
 674                         if (qdev->configured_vlans == 0) {
 675                                 DP_INFO(edev,
 676                                         "No VLAN filters configured yet\n");
 677                                 return 0;
 678                         }
 679
 680                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 681                         return -EINVAL;
 682                 }
 683
 684                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 685
 686                 qede_set_ucast_cmn_params(&ucast);
 687                 ucast.opcode = ECORE_FILTER_REMOVE;
 688                 ucast.type = ECORE_FILTER_VLAN;
 689                 ucast.vlan = vlan_id;
 690                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 691                                             NULL);
 692                 if (rc != 0) {
 693                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 694                                vlan_id, rc);
 695                 } else {
 696                         qdev->configured_vlans--;
 697                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 698                                 vlan_id, qdev->configured_vlans);
 699                 }
 700         }
 701
 702         return rc;
 703 }
 704
 705 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 706 {
 707         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 708         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 709         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 710
 711         if (mask & ETH_VLAN_STRIP_MASK) {
 712                 if (rxmode->hw_vlan_strip)
 713                         (void)qede_vlan_stripping(eth_dev, 1);
 714                 else
 715                         (void)qede_vlan_stripping(eth_dev, 0);
 716         }
 717
 718         if (mask & ETH_VLAN_FILTER_MASK) {
 719                 /* VLAN filtering kicks in when a VLAN is added */
 720                 if (rxmode->hw_vlan_filter) {
 721                         qede_vlan_filter_set(eth_dev, 0, 1);
 722                 } else {
 723                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 724                                 DP_ERR(edev,
 725                                   " Please remove existing VLAN filters"
 726                                   " before disabling VLAN filtering\n");
 727                                 /* Signal app that VLAN filtering is still
 728                                  * enabled
 729                                  */
 730                                 rxmode->hw_vlan_filter = true;
 731                         } else {
 732                                 qede_vlan_filter_set(eth_dev, 0, 0);
 733                         }
 734                 }
 735         }
 736
 737         if (mask & ETH_VLAN_EXTEND_MASK)
 738                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 739                         " and classification is based on outer tag only\n");
 740
 741         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 742                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 743 }
 744
 745 static int qede_init_vport(struct qede_dev *qdev)
 746 {
 747         struct ecore_dev *edev = &qdev->edev;
 748         struct qed_start_vport_params start = {0};
 749         int rc;
 750
 751         start.remove_inner_vlan = 1;
 752         start.enable_lro = qdev->enable_lro;
 753         start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
 754         start.vport_id = 0;
 755         start.drop_ttl0 = false;
 756         start.clear_stats = 1;
 757         start.handle_ptp_pkts = 0;
 758
 759         rc = qdev->ops->vport_start(edev, &start);
 760         if (rc) {
 761                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 762                 return rc;
 763         }
 764
 765         DP_INFO(edev,
 766                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 767                 start.vport_id, ETHER_MTU);
 768
 769         return 0;
 770 }
 771
 772 static void qede_prandom_bytes(uint32_t *buff)
 773 {
 774         uint8_t i;
 775
 776         srand((unsigned int)time(NULL));
 777         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 778                 buff[i] = rand();
 779 }
 780
 781 int qede_config_rss(struct rte_eth_dev *eth_dev)
 782 {
 783         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 784 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 785         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 786 #endif
 787         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 788         struct rte_eth_rss_reta_entry64 reta_conf[2];
 789         struct rte_eth_rss_conf rss_conf;
 790         uint32_t i, id, pos, q;
 791
 792         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 793         if (!rss_conf.rss_key) {
 794                 DP_INFO(edev, "Applying driver default key\n");
 795                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 796                 qede_prandom_bytes(&def_rss_key[0]);
 797                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 798         }
 799
 800         /* Configure RSS hash */
 801         if (qede_rss_hash_update(eth_dev, &rss_conf))
 802                 return -EINVAL;
 803
 804         /* Configure default RETA */
 805         memset(reta_conf, 0, sizeof(reta_conf));
 806         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 807                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
 808
 809         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 810                 id = i / RTE_RETA_GROUP_SIZE;
 811                 pos = i % RTE_RETA_GROUP_SIZE;
 812                 q = i % QEDE_RSS_COUNT(qdev);
 813                 reta_conf[id].reta[pos] = q;
 814         }
 815         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
 816                                  ECORE_RSS_IND_TABLE_SIZE))
 817                 return -EINVAL;
 818
 819         return 0;
 820 }
 821
 822 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 823 {
 824         struct qede_dev *qdev = eth_dev->data->dev_private;
 825         struct ecore_dev *edev = &qdev->edev;
 826         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 827         int rc;
 828
 829         PMD_INIT_FUNC_TRACE(edev);
 830
 831         /* Check requirements for 100G mode */
 832         if (edev->num_hwfns > 1) {
 833                 if (eth_dev->data->nb_rx_queues < 2 ||
 834                     eth_dev->data->nb_tx_queues < 2) {
 835                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
 836                         return -EINVAL;
 837                 }
 838
 839                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 840                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 841                         DP_ERR(edev,
 842                                   "100G mode needs even no. of RX/TX queues\n");
 843                         return -EINVAL;
 844                 }
 845         }
 846
 847         /* Sanity checks and throw warnings */
 848         if (rxmode->enable_scatter == 1)
 849                 eth_dev->data->scattered_rx = 1;
 850
 851         if (!rxmode->hw_strip_crc)
 852                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 853
 854         if (!rxmode->hw_ip_checksum)
 855                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 856                               "in hw\n");
 857
 858         if (rxmode->enable_lro) {
 859                 qdev->enable_lro = true;
 860                 /* Enable scatter mode for LRO */
 861                 if (!rxmode->enable_scatter)
 862                         eth_dev->data->scattered_rx = 1;
 863         }
 864
 865         /* Check for the port restart case */
 866         if (qdev->state != QEDE_DEV_INIT) {
 867                 rc = qdev->ops->vport_stop(edev, 0);
 868                 if (rc != 0)
 869                         return rc;
 870                 qede_dealloc_fp_resc(eth_dev);
 871         }
 872
 873         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 874         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 875         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 876
 877         /* Fastpath status block should be initialized before sending
 878          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 879          */
 880         rc = qede_alloc_fp_resc(qdev);
 881         if (rc != 0)
 882                 return rc;
 883
 884         /* Issue VPORT-START with default config values to allow
 885          * other port configurations early on.
 886          */
 887         rc = qede_init_vport(qdev);
 888         if (rc != 0)
 889                 return rc;
 890
 891         if (!(rxmode->mq_mode == ETH_MQ_RX_RSS ||
 892             rxmode->mq_mode == ETH_MQ_RX_NONE)) {
 893                 DP_ERR(edev, "Unsupported RSS mode\n");
 894                 qdev->ops->vport_stop(edev, 0);
 895                 qede_dealloc_fp_resc(eth_dev);
 896                 return -EINVAL;
 897         }
 898
 899         /* Flow director mode check */
 900         rc = qede_check_fdir_support(eth_dev);
 901         if (rc) {
 902                 qdev->ops->vport_stop(edev, 0);
 903                 qede_dealloc_fp_resc(eth_dev);
 904                 return -EINVAL;
 905         }
 906         SLIST_INIT(&qdev->fdir_info.fdir_list_head);
 907
 908         SLIST_INIT(&qdev->vlan_list_head);
 909
 910         /* Enable VLAN offloads by default */
 911         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
 912                                        ETH_VLAN_FILTER_MASK |
 913                                        ETH_VLAN_EXTEND_MASK);
 914
 915         qdev->state = QEDE_DEV_CONFIG;
 916
 917         DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
 918                 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
 919                 qdev->num_tc);
 920
 921         return 0;
 922 }
 923
 924 /* Info about HW descriptor ring limitations */
 925 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 926         .nb_max = NUM_RX_BDS_MAX,
 927         .nb_min = 128,
 928         .nb_align = 128 /* lowest common multiple */
 929 };
 930
 931 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 932         .nb_max = NUM_TX_BDS_MAX,
 933         .nb_min = 256,
 934         .nb_align = 256,
 935         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
 936         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
 937 };
 938
 939 static void
 940 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 941                   struct rte_eth_dev_info *dev_info)
 942 {
 943         struct qede_dev *qdev = eth_dev->data->dev_private;
 944         struct ecore_dev *edev = &qdev->edev;
 945         struct qed_link_output link;
 946         uint32_t speed_cap = 0;
 947
 948         PMD_INIT_FUNC_TRACE(edev);
 949
 950         dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 951         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
 952         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 953         dev_info->rx_desc_lim = qede_rx_desc_lim;
 954         dev_info->tx_desc_lim = qede_tx_desc_lim;
 955
 956         if (IS_PF(edev))
 957                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
 958                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
 959         else
 960                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
 961                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
 962         dev_info->max_tx_queues = dev_info->max_rx_queues;
 963
 964         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
 965         dev_info->max_vfs = 0;
 966         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 967         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 968         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 969
 970         dev_info->default_txconf = (struct rte_eth_txconf) {
 971                 .txq_flags = QEDE_TXQ_FLAGS,
 972         };
 973
 974         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
 975                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
 976                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
 977                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
 978                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 979                                      DEV_RX_OFFLOAD_TCP_LRO);
 980
 981         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 982                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
 983                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
 984                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
 985                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 986                                      DEV_TX_OFFLOAD_TCP_TSO |
 987                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
 988
 989         memset(&link, 0, sizeof(struct qed_link_output));
 990         qdev->ops->common->get_link(edev, &link);
 991         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
 992                 speed_cap |= ETH_LINK_SPEED_1G;
 993         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
 994                 speed_cap |= ETH_LINK_SPEED_10G;
 995         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
 996                 speed_cap |= ETH_LINK_SPEED_25G;
 997         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
 998                 speed_cap |= ETH_LINK_SPEED_40G;
 999         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1000                 speed_cap |= ETH_LINK_SPEED_50G;
1001         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1002                 speed_cap |= ETH_LINK_SPEED_100G;
1003         dev_info->speed_capa = speed_cap;
1004 }
1005
1006 /* return 0 means link status changed, -1 means not changed */
1007 static int
1008 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1009 {
1010         struct qede_dev *qdev = eth_dev->data->dev_private;
1011         struct ecore_dev *edev = &qdev->edev;
1012         uint16_t link_duplex;
1013         struct qed_link_output link;
1014         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1015
1016         memset(&link, 0, sizeof(struct qed_link_output));
1017         qdev->ops->common->get_link(edev, &link);
1018
1019         /* Link Speed */
1020         curr->link_speed = link.speed;
1021
1022         /* Link Mode */
1023         switch (link.duplex) {
1024         case QEDE_DUPLEX_HALF:
1025                 link_duplex = ETH_LINK_HALF_DUPLEX;
1026                 break;
1027         case QEDE_DUPLEX_FULL:
1028                 link_duplex = ETH_LINK_FULL_DUPLEX;
1029                 break;
1030         case QEDE_DUPLEX_UNKNOWN:
1031         default:
1032                 link_duplex = -1;
1033         }
1034         curr->link_duplex = link_duplex;
1035
1036         /* Link Status */
1037         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1038
1039         /* AN */
1040         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1041                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1042
1043         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1044                 curr->link_speed, curr->link_duplex,
1045                 curr->link_autoneg, curr->link_status);
1046
1047         /* return 0 means link status changed, -1 means not changed */
1048         return ((curr->link_status == link.link_up) ? -1 : 0);
1049 }
1050
1051 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1052 {
1053 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1054         struct qede_dev *qdev = eth_dev->data->dev_private;
1055         struct ecore_dev *edev = &qdev->edev;
1056
1057         PMD_INIT_FUNC_TRACE(edev);
1058 #endif
1059
1060         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1061
1062         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1063                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1064
1065         qed_configure_filter_rx_mode(eth_dev, type);
1066 }
1067
1068 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1069 {
1070 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1071         struct qede_dev *qdev = eth_dev->data->dev_private;
1072         struct ecore_dev *edev = &qdev->edev;
1073
1074         PMD_INIT_FUNC_TRACE(edev);
1075 #endif
1076
1077         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1078                 qed_configure_filter_rx_mode(eth_dev,
1079                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1080         else
1081                 qed_configure_filter_rx_mode(eth_dev,
1082                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1083 }
1084
1085 static void qede_poll_sp_sb_cb(void *param)
1086 {
1087         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1088         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1089         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1090         int rc;
1091
1092         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1093         qede_interrupt_action(&edev->hwfns[1]);
1094
1095         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1096                                qede_poll_sp_sb_cb,
1097                                (void *)eth_dev);
1098         if (rc != 0) {
1099                 DP_ERR(edev, "Unable to start periodic"
1100                              " timer rc %d\n", rc);
1101                 assert(false && "Unable to start periodic timer");
1102         }
1103 }
1104
1105 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1106 {
1107         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1108         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1109         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1110         int rc;
1111
1112         PMD_INIT_FUNC_TRACE(edev);
1113
1114         qede_fdir_dealloc_resc(eth_dev);
1115
1116         /* dev_stop() shall cleanup fp resources in hw but without releasing
1117          * dma memories and sw structures so that dev_start() can be called
1118          * by the app without reconfiguration. However, in dev_close() we
1119          * can release all the resources and device can be brought up newly
1120          */
1121         if (qdev->state != QEDE_DEV_STOP)
1122                 qede_dev_stop(eth_dev);
1123         else
1124                 DP_INFO(edev, "Device is already stopped\n");
1125
1126         rc = qdev->ops->vport_stop(edev, 0);
1127         if (rc != 0)
1128                 DP_ERR(edev, "Failed to stop VPORT\n");
1129
1130         qede_dealloc_fp_resc(eth_dev);
1131
1132         qdev->ops->common->slowpath_stop(edev);
1133
1134         qdev->ops->common->remove(edev);
1135
1136         rte_intr_disable(&pci_dev->intr_handle);
1137
1138         rte_intr_callback_unregister(&pci_dev->intr_handle,
1139                                      qede_interrupt_handler, (void *)eth_dev);
1140
1141         if (edev->num_hwfns > 1)
1142                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1143
1144         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
1145 }
1146
1147 static void
1148 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1149 {
1150         struct qede_dev *qdev = eth_dev->data->dev_private;
1151         struct ecore_dev *edev = &qdev->edev;
1152         struct ecore_eth_stats stats;
1153         unsigned int i = 0, j = 0, qid;
1154         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1155         struct qede_tx_queue *txq;
1156
1157         qdev->ops->get_vport_stats(edev, &stats);
1158
1159         /* RX Stats */
1160         eth_stats->ipackets = stats.rx_ucast_pkts +
1161             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1162
1163         eth_stats->ibytes = stats.rx_ucast_bytes +
1164             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1165
1166         eth_stats->ierrors = stats.rx_crc_errors +
1167             stats.rx_align_errors +
1168             stats.rx_carrier_errors +
1169             stats.rx_oversize_packets +
1170             stats.rx_jabbers + stats.rx_undersize_packets;
1171
1172         eth_stats->rx_nombuf = stats.no_buff_discards;
1173
1174         eth_stats->imissed = stats.mftag_filter_discards +
1175             stats.mac_filter_discards +
1176             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1177
1178         /* TX stats */
1179         eth_stats->opackets = stats.tx_ucast_pkts +
1180             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1181
1182         eth_stats->obytes = stats.tx_ucast_bytes +
1183             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1184
1185         eth_stats->oerrors = stats.tx_err_drop_pkts;
1186
1187         /* Queue stats */
1188         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1189                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1190         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1191                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1192         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1193             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1194                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1195                        "Not all the queue stats will be displayed. Set"
1196                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1197                        " appropriately and retry.\n");
1198
1199         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1200                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1201                         eth_stats->q_ipackets[i] =
1202                                 *(uint64_t *)(
1203                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1204                                         offsetof(struct qede_rx_queue,
1205                                         rcv_pkts));
1206                         eth_stats->q_errors[i] =
1207                                 *(uint64_t *)(
1208                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1209                                         offsetof(struct qede_rx_queue,
1210                                         rx_hw_errors)) +
1211                                 *(uint64_t *)(
1212                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1213                                         offsetof(struct qede_rx_queue,
1214                                         rx_alloc_errors));
1215                         i++;
1216                 }
1217                 if (i == rxq_stat_cntrs)
1218                         break;
1219         }
1220
1221         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1222                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1223                         txq = qdev->fp_array[(qid)].txqs[0];
1224                         eth_stats->q_opackets[j] =
1225                                 *((uint64_t *)(uintptr_t)
1226                                         (((uint64_t)(uintptr_t)(txq)) +
1227                                          offsetof(struct qede_tx_queue,
1228                                                   xmit_pkts)));
1229                         j++;
1230                 }
1231                 if (j == txq_stat_cntrs)
1232                         break;
1233         }
1234 }
1235
1236 static unsigned
1237 qede_get_xstats_count(struct qede_dev *qdev) {
1238         return RTE_DIM(qede_xstats_strings) +
1239                 (RTE_DIM(qede_rxq_xstats_strings) *
1240                  RTE_MIN(QEDE_RSS_COUNT(qdev),
1241                          RTE_ETHDEV_QUEUE_STAT_CNTRS));
1242 }
1243
1244 static int
1245 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1246                       struct rte_eth_xstat_name *xstats_names,
1247                       __rte_unused unsigned int limit)
1248 {
1249         struct qede_dev *qdev = dev->data->dev_private;
1250         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1251         unsigned int i, qid, stat_idx = 0;
1252         unsigned int rxq_stat_cntrs;
1253
1254         if (xstats_names != NULL) {
1255                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1256                         snprintf(xstats_names[stat_idx].name,
1257                                 sizeof(xstats_names[stat_idx].name),
1258                                 "%s",
1259                                 qede_xstats_strings[i].name);
1260                         stat_idx++;
1261                 }
1262
1263                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1264                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1265                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1266                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1267                                 snprintf(xstats_names[stat_idx].name,
1268                                         sizeof(xstats_names[stat_idx].name),
1269                                         "%.4s%d%s",
1270                                         qede_rxq_xstats_strings[i].name, qid,
1271                                         qede_rxq_xstats_strings[i].name + 4);
1272                                 stat_idx++;
1273                         }
1274                 }
1275         }
1276
1277         return stat_cnt;
1278 }
1279
1280 static int
1281 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1282                 unsigned int n)
1283 {
1284         struct qede_dev *qdev = dev->data->dev_private;
1285         struct ecore_dev *edev = &qdev->edev;
1286         struct ecore_eth_stats stats;
1287         const unsigned int num = qede_get_xstats_count(qdev);
1288         unsigned int i, qid, stat_idx = 0;
1289         unsigned int rxq_stat_cntrs;
1290
1291         if (n < num)
1292                 return num;
1293
1294         qdev->ops->get_vport_stats(edev, &stats);
1295
1296         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1297                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1298                                              qede_xstats_strings[i].offset);
1299                 xstats[stat_idx].id = stat_idx;
1300                 stat_idx++;
1301         }
1302
1303         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1304                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1305         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1306                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1307                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1308                                 xstats[stat_idx].value = *(uint64_t *)(
1309                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1310                                          qede_rxq_xstats_strings[i].offset);
1311                                 xstats[stat_idx].id = stat_idx;
1312                                 stat_idx++;
1313                         }
1314                 }
1315         }
1316
1317         return stat_idx;
1318 }
1319
1320 static void
1321 qede_reset_xstats(struct rte_eth_dev *dev)
1322 {
1323         struct qede_dev *qdev = dev->data->dev_private;
1324         struct ecore_dev *edev = &qdev->edev;
1325
1326         ecore_reset_vport_stats(edev);
1327 }
1328
1329 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1330 {
1331         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1332         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1333         struct qed_link_params link_params;
1334         int rc;
1335
1336         DP_INFO(edev, "setting link state %d\n", link_up);
1337         memset(&link_params, 0, sizeof(link_params));
1338         link_params.link_up = link_up;
1339         rc = qdev->ops->common->set_link(edev, &link_params);
1340         if (rc != ECORE_SUCCESS)
1341                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1342
1343         return rc;
1344 }
1345
1346 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1347 {
1348         return qede_dev_set_link_state(eth_dev, true);
1349 }
1350
1351 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1352 {
1353         return qede_dev_set_link_state(eth_dev, false);
1354 }
1355
1356 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1357 {
1358         struct qede_dev *qdev = eth_dev->data->dev_private;
1359         struct ecore_dev *edev = &qdev->edev;
1360
1361         ecore_reset_vport_stats(edev);
1362 }
1363
1364 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1365 {
1366         enum qed_filter_rx_mode_type type =
1367             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1368
1369         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1370                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1371
1372         qed_configure_filter_rx_mode(eth_dev, type);
1373 }
1374
1375 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1376 {
1377         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1378                 qed_configure_filter_rx_mode(eth_dev,
1379                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1380         else
1381                 qed_configure_filter_rx_mode(eth_dev,
1382                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1383 }
1384
1385 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1386                               struct rte_eth_fc_conf *fc_conf)
1387 {
1388         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1389         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1390         struct qed_link_output current_link;
1391         struct qed_link_params params;
1392
1393         memset(&current_link, 0, sizeof(current_link));
1394         qdev->ops->common->get_link(edev, &current_link);
1395
1396         memset(&params, 0, sizeof(params));
1397         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1398         if (fc_conf->autoneg) {
1399                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1400                         DP_ERR(edev, "Autoneg not supported\n");
1401                         return -EINVAL;
1402                 }
1403                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1404         }
1405
1406         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1407         if (fc_conf->mode == RTE_FC_FULL)
1408                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1409                                         QED_LINK_PAUSE_RX_ENABLE);
1410         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1411                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1412         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1413                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1414
1415         params.link_up = true;
1416         (void)qdev->ops->common->set_link(edev, &params);
1417
1418         return 0;
1419 }
1420
1421 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1422                               struct rte_eth_fc_conf *fc_conf)
1423 {
1424         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1425         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1426         struct qed_link_output current_link;
1427
1428         memset(&current_link, 0, sizeof(current_link));
1429         qdev->ops->common->get_link(edev, &current_link);
1430
1431         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1432                 fc_conf->autoneg = true;
1433
1434         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1435                                          QED_LINK_PAUSE_TX_ENABLE))
1436                 fc_conf->mode = RTE_FC_FULL;
1437         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1438                 fc_conf->mode = RTE_FC_RX_PAUSE;
1439         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1440                 fc_conf->mode = RTE_FC_TX_PAUSE;
1441         else
1442                 fc_conf->mode = RTE_FC_NONE;
1443
1444         return 0;
1445 }
1446
1447 static const uint32_t *
1448 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1449 {
1450         static const uint32_t ptypes[] = {
1451                 RTE_PTYPE_L3_IPV4,
1452                 RTE_PTYPE_L3_IPV6,
1453                 RTE_PTYPE_UNKNOWN
1454         };
1455
1456         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1457                 return ptypes;
1458
1459         return NULL;
1460 }
1461
1462 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1463 {
1464         *rss_caps = 0;
1465         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1466         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1467         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1468         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1469         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1470         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1471         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1472         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1473 }
1474
1475 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1476                          struct rte_eth_rss_conf *rss_conf)
1477 {
1478         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1479         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1480         struct ecore_sp_vport_update_params vport_update_params;
1481         struct ecore_rss_params rss_params;
1482         struct ecore_hwfn *p_hwfn;
1483         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1484         uint64_t hf = rss_conf->rss_hf;
1485         uint8_t len = rss_conf->rss_key_len;
1486         uint8_t idx;
1487         uint8_t i;
1488         int rc;
1489
1490         memset(&vport_update_params, 0, sizeof(vport_update_params));
1491         memset(&rss_params, 0, sizeof(rss_params));
1492
1493         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1494                 (unsigned long)hf, len, key);
1495
1496         if (hf != 0) {
1497                 /* Enabling RSS */
1498                 DP_INFO(edev, "Enabling rss\n");
1499
1500                 /* RSS caps */
1501                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1502                 rss_params.update_rss_capabilities = 1;
1503
1504                 /* RSS hash key */
1505                 if (key) {
1506                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1507                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1508                                 return -EINVAL;
1509                         }
1510                         DP_INFO(edev, "Applying user supplied hash key\n");
1511                         rss_params.update_rss_key = 1;
1512                         memcpy(&rss_params.rss_key, key, len);
1513                 }
1514                 rss_params.rss_enable = 1;
1515         }
1516
1517         rss_params.update_rss_config = 1;
1518         /* tbl_size has to be set with capabilities */
1519         rss_params.rss_table_size_log = 7;
1520         vport_update_params.vport_id = 0;
1521         /* pass the L2 handles instead of qids */
1522         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1523                 idx = qdev->rss_ind_table[i];
1524                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1525         }
1526         vport_update_params.rss_params = &rss_params;
1527
1528         for_each_hwfn(edev, i) {
1529                 p_hwfn = &edev->hwfns[i];
1530                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1531                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1532                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1533                 if (rc) {
1534                         DP_ERR(edev, "vport-update for RSS failed\n");
1535                         return rc;
1536                 }
1537         }
1538         qdev->rss_enable = rss_params.rss_enable;
1539
1540         /* Update local structure for hash query */
1541         qdev->rss_conf.rss_hf = hf;
1542         qdev->rss_conf.rss_key_len = len;
1543         if (qdev->rss_enable) {
1544                 if  (qdev->rss_conf.rss_key == NULL) {
1545                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1546                         if (qdev->rss_conf.rss_key == NULL) {
1547                                 DP_ERR(edev, "No memory to store RSS key\n");
1548                                 return -ENOMEM;
1549                         }
1550                 }
1551                 if (key && len) {
1552                         DP_INFO(edev, "Storing RSS key\n");
1553                         memcpy(qdev->rss_conf.rss_key, key, len);
1554                 }
1555         } else if (!qdev->rss_enable && len == 0) {
1556                 if (qdev->rss_conf.rss_key) {
1557                         free(qdev->rss_conf.rss_key);
1558                         qdev->rss_conf.rss_key = NULL;
1559                         DP_INFO(edev, "Free RSS key\n");
1560                 }
1561         }
1562
1563         return 0;
1564 }
1565
1566 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1567                            struct rte_eth_rss_conf *rss_conf)
1568 {
1569         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1570
1571         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1572         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1573
1574         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1575                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1576                        rss_conf->rss_key_len);
1577         return 0;
1578 }
1579
1580 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
1581                                     struct ecore_rss_params *rss)
1582 {
1583         int i, fn;
1584         bool rss_mode = 1; /* enable */
1585         struct ecore_queue_cid *cid;
1586         struct ecore_rss_params *t_rss;
1587
1588         /* In regular scenario, we'd simply need to take input handlers.
1589          * But in CMT, we'd have to split the handlers according to the
1590          * engine they were configured on. We'd then have to understand
1591          * whether RSS is really required, since 2-queues on CMT doesn't
1592          * require RSS.
1593          */
1594
1595         /* CMT should be round-robin */
1596         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1597                 cid = rss->rss_ind_table[i];
1598
1599                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
1600                         t_rss = &rss[0];
1601                 else
1602                         t_rss = &rss[1];
1603
1604                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
1605         }
1606
1607         t_rss = &rss[1];
1608         t_rss->update_rss_ind_table = 1;
1609         t_rss->rss_table_size_log = 7;
1610         t_rss->update_rss_config = 1;
1611
1612         /* Make sure RSS is actually required */
1613         for_each_hwfn(edev, fn) {
1614                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
1615                      i++) {
1616                         if (rss[fn].rss_ind_table[i] !=
1617                             rss[fn].rss_ind_table[0])
1618                                 break;
1619                 }
1620
1621                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
1622                         DP_INFO(edev,
1623                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
1624                         rss_mode = 0;
1625                         goto out;
1626                 }
1627         }
1628
1629 out:
1630         t_rss->rss_enable = rss_mode;
1631
1632         return rss_mode;
1633 }
1634
1635 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1636                          struct rte_eth_rss_reta_entry64 *reta_conf,
1637                          uint16_t reta_size)
1638 {
1639         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1640         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1641         struct ecore_sp_vport_update_params vport_update_params;
1642         struct ecore_rss_params *params;
1643         struct ecore_hwfn *p_hwfn;
1644         uint16_t i, idx, shift;
1645         uint8_t entry;
1646         int rc = 0;
1647
1648         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1649                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1650                        reta_size);
1651                 return -EINVAL;
1652         }
1653
1654         memset(&vport_update_params, 0, sizeof(vport_update_params));
1655         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
1656                              RTE_CACHE_LINE_SIZE);
1657
1658         for (i = 0; i < reta_size; i++) {
1659                 idx = i / RTE_RETA_GROUP_SIZE;
1660                 shift = i % RTE_RETA_GROUP_SIZE;
1661                 if (reta_conf[idx].mask & (1ULL << shift)) {
1662                         entry = reta_conf[idx].reta[shift];
1663                         /* Pass rxq handles to ecore */
1664                         params->rss_ind_table[i] =
1665                                         qdev->fp_array[entry].rxq->handle;
1666                         /* Update the local copy for RETA query command */
1667                         qdev->rss_ind_table[i] = entry;
1668                 }
1669         }
1670
1671         params->update_rss_ind_table = 1;
1672         params->rss_table_size_log = 7;
1673         params->update_rss_config = 1;
1674
1675         /* Fix up RETA for CMT mode device */
1676         if (edev->num_hwfns > 1)
1677                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
1678                                                             params);
1679         vport_update_params.vport_id = 0;
1680         /* Use the current value of rss_enable */
1681         params->rss_enable = qdev->rss_enable;
1682         vport_update_params.rss_params = params;
1683
1684         for_each_hwfn(edev, i) {
1685                 p_hwfn = &edev->hwfns[i];
1686                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1687                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1688                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1689                 if (rc) {
1690                         DP_ERR(edev, "vport-update for RSS failed\n");
1691                         goto out;
1692                 }
1693         }
1694
1695 out:
1696         rte_free(params);
1697         return rc;
1698 }
1699
1700 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1701                                struct rte_eth_rss_reta_entry64 *reta_conf,
1702                                uint16_t reta_size)
1703 {
1704         struct qede_dev *qdev = eth_dev->data->dev_private;
1705         struct ecore_dev *edev = &qdev->edev;
1706         uint16_t i, idx, shift;
1707         uint8_t entry;
1708
1709         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1710                 DP_ERR(edev, "reta_size %d is not supported\n",
1711                        reta_size);
1712                 return -EINVAL;
1713         }
1714
1715         for (i = 0; i < reta_size; i++) {
1716                 idx = i / RTE_RETA_GROUP_SIZE;
1717                 shift = i % RTE_RETA_GROUP_SIZE;
1718                 if (reta_conf[idx].mask & (1ULL << shift)) {
1719                         entry = qdev->rss_ind_table[i];
1720                         reta_conf[idx].reta[shift] = entry;
1721                 }
1722         }
1723
1724         return 0;
1725 }
1726
1727 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1728 {
1729         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
1730         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1731         struct rte_eth_dev_info dev_info = {0};
1732         struct qede_fastpath *fp;
1733         uint32_t frame_size;
1734         uint16_t rx_buf_size;
1735         uint16_t bufsz;
1736         int i;
1737
1738         PMD_INIT_FUNC_TRACE(edev);
1739         qede_dev_info_get(dev, &dev_info);
1740         frame_size = mtu + QEDE_ETH_OVERHEAD;
1741         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
1742                 DP_ERR(edev, "MTU %u out of range\n", mtu);
1743                 return -EINVAL;
1744         }
1745         if (!dev->data->scattered_rx &&
1746             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
1747                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
1748                         dev->data->min_rx_buf_size);
1749                 return -EINVAL;
1750         }
1751         /* Temporarily replace I/O functions with dummy ones. It cannot
1752          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1753          */
1754         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
1755         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
1756         qede_dev_stop(dev);
1757         rte_delay_ms(1000);
1758         qdev->mtu = mtu;
1759         /* Fix up RX buf size for all queues of the port */
1760         for_each_queue(i) {
1761                 fp = &qdev->fp_array[i];
1762                 if (fp->type & QEDE_FASTPATH_RX) {
1763                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
1764                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
1765                         if (dev->data->scattered_rx)
1766                                 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
1767                         else
1768                                 rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
1769                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
1770                         fp->rxq->rx_buf_size = rx_buf_size;
1771                         DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
1772                 }
1773         }
1774         qede_dev_start(dev);
1775         if (frame_size > ETHER_MAX_LEN)
1776                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1777         else
1778                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1779         /* update max frame size */
1780         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1781         /* Reassign back */
1782         dev->rx_pkt_burst = qede_recv_pkts;
1783         dev->tx_pkt_burst = qede_xmit_pkts;
1784
1785         return 0;
1786 }
1787
1788 static int
1789 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
1790                        struct rte_eth_udp_tunnel *tunnel_udp,
1791                        bool add)
1792 {
1793         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1794         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1795         struct ecore_tunnel_info tunn; /* @DPDK */
1796         struct ecore_hwfn *p_hwfn;
1797         int rc, i;
1798
1799         PMD_INIT_FUNC_TRACE(edev);
1800
1801         memset(&tunn, 0, sizeof(tunn));
1802         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
1803                 tunn.vxlan_port.b_update_port = true;
1804                 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port :
1805                                                   QEDE_VXLAN_DEF_PORT;
1806                 for_each_hwfn(edev, i) {
1807                         p_hwfn = &edev->hwfns[i];
1808                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
1809                                                 ECORE_SPQ_MODE_CB, NULL);
1810                         if (rc != ECORE_SUCCESS) {
1811                                 DP_ERR(edev, "Unable to config UDP port %u\n",
1812                                        tunn.vxlan_port.port);
1813                                 return rc;
1814                         }
1815                 }
1816         }
1817
1818         return 0;
1819 }
1820
1821 static int
1822 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
1823                       struct rte_eth_udp_tunnel *tunnel_udp)
1824 {
1825         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
1826 }
1827
1828 static int
1829 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
1830                       struct rte_eth_udp_tunnel *tunnel_udp)
1831 {
1832         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
1833 }
1834
1835 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
1836                                        uint32_t *clss, char *str)
1837 {
1838         uint16_t j;
1839         *clss = MAX_ECORE_TUNN_CLSS;
1840
1841         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
1842                 if (filter == qede_tunn_types[j].rte_filter_type) {
1843                         *type = qede_tunn_types[j].qede_type;
1844                         *clss = qede_tunn_types[j].qede_tunn_clss;
1845                         strcpy(str, qede_tunn_types[j].string);
1846                         return;
1847                 }
1848         }
1849 }
1850
1851 static int
1852 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
1853                               const struct rte_eth_tunnel_filter_conf *conf,
1854                               uint32_t type)
1855 {
1856         /* Init commmon ucast params first */
1857         qede_set_ucast_cmn_params(ucast);
1858
1859         /* Copy out the required fields based on classification type */
1860         ucast->type = type;
1861
1862         switch (type) {
1863         case ECORE_FILTER_VNI:
1864                 ucast->vni = conf->tenant_id;
1865         break;
1866         case ECORE_FILTER_INNER_VLAN:
1867                 ucast->vlan = conf->inner_vlan;
1868         break;
1869         case ECORE_FILTER_MAC:
1870                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1871                        ETHER_ADDR_LEN);
1872         break;
1873         case ECORE_FILTER_INNER_MAC:
1874                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1875                        ETHER_ADDR_LEN);
1876         break;
1877         case ECORE_FILTER_MAC_VNI_PAIR:
1878                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1879                         ETHER_ADDR_LEN);
1880                 ucast->vni = conf->tenant_id;
1881         break;
1882         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1883                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1884                         ETHER_ADDR_LEN);
1885                 ucast->vni = conf->tenant_id;
1886         break;
1887         case ECORE_FILTER_INNER_PAIR:
1888                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1889                         ETHER_ADDR_LEN);
1890                 ucast->vlan = conf->inner_vlan;
1891         break;
1892         default:
1893                 return -EINVAL;
1894         }
1895
1896         return ECORE_SUCCESS;
1897 }
1898
1899 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
1900                                   enum rte_filter_op filter_op,
1901                                   const struct rte_eth_tunnel_filter_conf *conf)
1902 {
1903         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1904         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1905         struct ecore_tunnel_info tunn;
1906         struct ecore_hwfn *p_hwfn;
1907         enum ecore_filter_ucast_type type;
1908         enum ecore_tunn_clss clss;
1909         struct ecore_filter_ucast ucast;
1910         char str[80];
1911         uint16_t filter_type;
1912         int rc, i;
1913
1914         filter_type = conf->filter_type | qdev->vxlan_filter_type;
1915         /* First determine if the given filter classification is supported */
1916         qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
1917         if (clss == MAX_ECORE_TUNN_CLSS) {
1918                 DP_ERR(edev, "Wrong filter type\n");
1919                 return -EINVAL;
1920         }
1921         /* Init tunnel ucast params */
1922         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
1923         if (rc != ECORE_SUCCESS) {
1924                 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
1925                                 conf->filter_type);
1926                 return rc;
1927         }
1928         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
1929                 str, filter_op, ucast.type);
1930         switch (filter_op) {
1931         case RTE_ETH_FILTER_ADD:
1932                 ucast.opcode = ECORE_FILTER_ADD;
1933
1934                 /* Skip MAC/VLAN if filter is based on VNI */
1935                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1936                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
1937                         if (rc == 0) {
1938                                 /* Enable accept anyvlan */
1939                                 qede_config_accept_any_vlan(qdev, true);
1940                         }
1941                 } else {
1942                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
1943                         if (rc == 0)
1944                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1945                                                     ECORE_SPQ_MODE_CB, NULL);
1946                 }
1947
1948                 if (rc != ECORE_SUCCESS)
1949                         return rc;
1950
1951                 qdev->vxlan_filter_type = filter_type;
1952
1953                 DP_INFO(edev, "Enabling VXLAN tunneling\n");
1954                 qede_set_cmn_tunn_param(&tunn, clss, true, true);
1955                 for_each_hwfn(edev, i) {
1956                         p_hwfn = &edev->hwfns[i];
1957                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1958                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
1959                         if (rc != ECORE_SUCCESS) {
1960                                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
1961                                        tunn.vxlan.tun_cls);
1962                         }
1963                 }
1964                 qdev->num_tunn_filters++; /* Filter added successfully */
1965         break;
1966         case RTE_ETH_FILTER_DELETE:
1967                 ucast.opcode = ECORE_FILTER_REMOVE;
1968
1969                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1970                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
1971                 } else {
1972                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
1973                         if (rc == 0)
1974                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1975                                                     ECORE_SPQ_MODE_CB, NULL);
1976                 }
1977                 if (rc != ECORE_SUCCESS)
1978                         return rc;
1979
1980                 qdev->vxlan_filter_type = filter_type;
1981                 qdev->num_tunn_filters--;
1982
1983                 /* Disable VXLAN if VXLAN filters become 0 */
1984                 if (qdev->num_tunn_filters == 0) {
1985                         DP_INFO(edev, "Disabling VXLAN tunneling\n");
1986
1987                         /* Use 0 as tunnel mode */
1988                         qede_set_cmn_tunn_param(&tunn, clss, false, true);
1989                         for_each_hwfn(edev, i) {
1990                                 p_hwfn = &edev->hwfns[i];
1991                                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
1992                                         ECORE_SPQ_MODE_CB, NULL);
1993                                 if (rc != ECORE_SUCCESS) {
1994                                         DP_ERR(edev,
1995                                                 "Failed to update tunn_clss %u\n",
1996                                                 tunn.vxlan.tun_cls);
1997                                         break;
1998                                 }
1999                         }
2000                 }
2001         break;
2002         default:
2003                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2004                 return -EINVAL;
2005         }
2006         DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
2007
2008         return 0;
2009 }
2010
2011 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2012                          enum rte_filter_type filter_type,
2013                          enum rte_filter_op filter_op,
2014                          void *arg)
2015 {
2016         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2017         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2018         struct rte_eth_tunnel_filter_conf *filter_conf =
2019                         (struct rte_eth_tunnel_filter_conf *)arg;
2020
2021         switch (filter_type) {
2022         case RTE_ETH_FILTER_TUNNEL:
2023                 switch (filter_conf->tunnel_type) {
2024                 case RTE_TUNNEL_TYPE_VXLAN:
2025                         DP_INFO(edev,
2026                                 "Packet steering to the specified Rx queue"
2027                                 " is not supported with VXLAN tunneling");
2028                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
2029                                                       filter_conf));
2030                 /* Place holders for future tunneling support */
2031                 case RTE_TUNNEL_TYPE_GENEVE:
2032                 case RTE_TUNNEL_TYPE_TEREDO:
2033                 case RTE_TUNNEL_TYPE_NVGRE:
2034                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2035                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2036                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2037                                 filter_conf->tunnel_type);
2038                         return -EINVAL;
2039                 case RTE_TUNNEL_TYPE_NONE:
2040                 default:
2041                         return 0;
2042                 }
2043                 break;
2044         case RTE_ETH_FILTER_FDIR:
2045                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2046         case RTE_ETH_FILTER_NTUPLE:
2047                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2048         case RTE_ETH_FILTER_MACVLAN:
2049         case RTE_ETH_FILTER_ETHERTYPE:
2050         case RTE_ETH_FILTER_FLEXIBLE:
2051         case RTE_ETH_FILTER_SYN:
2052         case RTE_ETH_FILTER_HASH:
2053         case RTE_ETH_FILTER_L2_TUNNEL:
2054         case RTE_ETH_FILTER_MAX:
2055         default:
2056                 DP_ERR(edev, "Unsupported filter type %d\n",
2057                         filter_type);
2058                 return -EINVAL;
2059         }
2060
2061         return 0;
2062 }
2063
2064 static const struct eth_dev_ops qede_eth_dev_ops = {
2065         .dev_configure = qede_dev_configure,
2066         .dev_infos_get = qede_dev_info_get,
2067         .rx_queue_setup = qede_rx_queue_setup,
2068         .rx_queue_release = qede_rx_queue_release,
2069         .tx_queue_setup = qede_tx_queue_setup,
2070         .tx_queue_release = qede_tx_queue_release,
2071         .dev_start = qede_dev_start,
2072         .dev_set_link_up = qede_dev_set_link_up,
2073         .dev_set_link_down = qede_dev_set_link_down,
2074         .link_update = qede_link_update,
2075         .promiscuous_enable = qede_promiscuous_enable,
2076         .promiscuous_disable = qede_promiscuous_disable,
2077         .allmulticast_enable = qede_allmulticast_enable,
2078         .allmulticast_disable = qede_allmulticast_disable,
2079         .dev_stop = qede_dev_stop,
2080         .dev_close = qede_dev_close,
2081         .stats_get = qede_get_stats,
2082         .stats_reset = qede_reset_stats,
2083         .xstats_get = qede_get_xstats,
2084         .xstats_reset = qede_reset_xstats,
2085         .xstats_get_names = qede_get_xstats_names,
2086         .mac_addr_add = qede_mac_addr_add,
2087         .mac_addr_remove = qede_mac_addr_remove,
2088         .mac_addr_set = qede_mac_addr_set,
2089         .vlan_offload_set = qede_vlan_offload_set,
2090         .vlan_filter_set = qede_vlan_filter_set,
2091         .flow_ctrl_set = qede_flow_ctrl_set,
2092         .flow_ctrl_get = qede_flow_ctrl_get,
2093         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2094         .rss_hash_update = qede_rss_hash_update,
2095         .rss_hash_conf_get = qede_rss_hash_conf_get,
2096         .reta_update  = qede_rss_reta_update,
2097         .reta_query  = qede_rss_reta_query,
2098         .mtu_set = qede_set_mtu,
2099         .filter_ctrl = qede_dev_filter_ctrl,
2100         .udp_tunnel_port_add = qede_udp_dst_port_add,
2101         .udp_tunnel_port_del = qede_udp_dst_port_del,
2102 };
2103
2104 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2105         .dev_configure = qede_dev_configure,
2106         .dev_infos_get = qede_dev_info_get,
2107         .rx_queue_setup = qede_rx_queue_setup,
2108         .rx_queue_release = qede_rx_queue_release,
2109         .tx_queue_setup = qede_tx_queue_setup,
2110         .tx_queue_release = qede_tx_queue_release,
2111         .dev_start = qede_dev_start,
2112         .dev_set_link_up = qede_dev_set_link_up,
2113         .dev_set_link_down = qede_dev_set_link_down,
2114         .link_update = qede_link_update,
2115         .promiscuous_enable = qede_promiscuous_enable,
2116         .promiscuous_disable = qede_promiscuous_disable,
2117         .allmulticast_enable = qede_allmulticast_enable,
2118         .allmulticast_disable = qede_allmulticast_disable,
2119         .dev_stop = qede_dev_stop,
2120         .dev_close = qede_dev_close,
2121         .stats_get = qede_get_stats,
2122         .stats_reset = qede_reset_stats,
2123         .xstats_get = qede_get_xstats,
2124         .xstats_reset = qede_reset_xstats,
2125         .xstats_get_names = qede_get_xstats_names,
2126         .vlan_offload_set = qede_vlan_offload_set,
2127         .vlan_filter_set = qede_vlan_filter_set,
2128         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2129         .rss_hash_update = qede_rss_hash_update,
2130         .rss_hash_conf_get = qede_rss_hash_conf_get,
2131         .reta_update  = qede_rss_reta_update,
2132         .reta_query  = qede_rss_reta_query,
2133         .mtu_set = qede_set_mtu,
2134 };
2135
2136 static void qede_update_pf_params(struct ecore_dev *edev)
2137 {
2138         struct ecore_pf_params pf_params;
2139
2140         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2141         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2142         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2143         qed_ops->common->update_pf_params(edev, &pf_params);
2144 }
2145
2146 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2147 {
2148         struct rte_pci_device *pci_dev;
2149         struct rte_pci_addr pci_addr;
2150         struct qede_dev *adapter;
2151         struct ecore_dev *edev;
2152         struct qed_dev_eth_info dev_info;
2153         struct qed_slowpath_params params;
2154         static bool do_once = true;
2155         uint8_t bulletin_change;
2156         uint8_t vf_mac[ETHER_ADDR_LEN];
2157         uint8_t is_mac_forced;
2158         bool is_mac_exist;
2159         /* Fix up ecore debug level */
2160         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2161         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2162         int rc;
2163
2164         /* Extract key data structures */
2165         adapter = eth_dev->data->dev_private;
2166         edev = &adapter->edev;
2167         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2168         pci_addr = pci_dev->addr;
2169
2170         PMD_INIT_FUNC_TRACE(edev);
2171
2172         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2173                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2174                  eth_dev->data->port_id);
2175
2176         eth_dev->rx_pkt_burst = qede_recv_pkts;
2177         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2178         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2179
2180         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2181                 DP_NOTICE(edev, false,
2182                           "Skipping device init from secondary process\n");
2183                 return 0;
2184         }
2185
2186         rte_eth_copy_pci_info(eth_dev, pci_dev);
2187
2188         /* @DPDK */
2189         edev->vendor_id = pci_dev->id.vendor_id;
2190         edev->device_id = pci_dev->id.device_id;
2191
2192         qed_ops = qed_get_eth_ops();
2193         if (!qed_ops) {
2194                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2195                 return -EINVAL;
2196         }
2197
2198         DP_INFO(edev, "Starting qede probe\n");
2199
2200         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
2201                                     dp_module, dp_level, is_vf);
2202
2203         if (rc != 0) {
2204                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2205                 return -ENODEV;
2206         }
2207
2208         qede_update_pf_params(edev);
2209
2210         rte_intr_callback_register(&pci_dev->intr_handle,
2211                                    qede_interrupt_handler, (void *)eth_dev);
2212
2213         if (rte_intr_enable(&pci_dev->intr_handle)) {
2214                 DP_ERR(edev, "rte_intr_enable() failed\n");
2215                 return -ENODEV;
2216         }
2217
2218         /* Start the Slowpath-process */
2219         memset(&params, 0, sizeof(struct qed_slowpath_params));
2220         params.int_mode = ECORE_INT_MODE_MSIX;
2221         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2222         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2223         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2224         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2225         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2226                 QEDE_PMD_DRV_VER_STR_SIZE);
2227
2228         /* For CMT mode device do periodic polling for slowpath events.
2229          * This is required since uio device uses only one MSI-x
2230          * interrupt vector but we need one for each engine.
2231          */
2232         if (edev->num_hwfns > 1 && IS_PF(edev)) {
2233                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2234                                        qede_poll_sp_sb_cb,
2235                                        (void *)eth_dev);
2236                 if (rc != 0) {
2237                         DP_ERR(edev, "Unable to start periodic"
2238                                      " timer rc %d\n", rc);
2239                         return -EINVAL;
2240                 }
2241         }
2242
2243         rc = qed_ops->common->slowpath_start(edev, &params);
2244         if (rc) {
2245                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2246                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2247                                      (void *)eth_dev);
2248                 return -ENODEV;
2249         }
2250
2251         rc = qed_ops->fill_dev_info(edev, &dev_info);
2252         if (rc) {
2253                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2254                 qed_ops->common->slowpath_stop(edev);
2255                 qed_ops->common->remove(edev);
2256                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2257                                      (void *)eth_dev);
2258                 return -ENODEV;
2259         }
2260
2261         qede_alloc_etherdev(adapter, &dev_info);
2262
2263         adapter->ops->common->set_name(edev, edev->name);
2264
2265         if (!is_vf)
2266                 adapter->dev_info.num_mac_filters =
2267                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2268                                             ECORE_MAC);
2269         else
2270                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2271                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2272
2273         /* Allocate memory for storing MAC addr */
2274         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2275                                         (ETHER_ADDR_LEN *
2276                                         adapter->dev_info.num_mac_filters),
2277                                         RTE_CACHE_LINE_SIZE);
2278
2279         if (eth_dev->data->mac_addrs == NULL) {
2280                 DP_ERR(edev, "Failed to allocate MAC address\n");
2281                 qed_ops->common->slowpath_stop(edev);
2282                 qed_ops->common->remove(edev);
2283                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2284                                      (void *)eth_dev);
2285                 return -ENOMEM;
2286         }
2287
2288         if (!is_vf) {
2289                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2290                                 hw_info.hw_mac_addr,
2291                                 &eth_dev->data->mac_addrs[0]);
2292                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2293                                 &adapter->primary_mac);
2294         } else {
2295                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2296                                        &bulletin_change);
2297                 if (bulletin_change) {
2298                         is_mac_exist =
2299                             ecore_vf_bulletin_get_forced_mac(
2300                                                 ECORE_LEADING_HWFN(edev),
2301                                                 vf_mac,
2302                                                 &is_mac_forced);
2303                         if (is_mac_exist && is_mac_forced) {
2304                                 DP_INFO(edev, "VF macaddr received from PF\n");
2305                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2306                                                 &eth_dev->data->mac_addrs[0]);
2307                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2308                                                 &adapter->primary_mac);
2309                         } else {
2310                                 DP_NOTICE(edev, false,
2311                                           "No VF macaddr assigned\n");
2312                         }
2313                 }
2314         }
2315
2316         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2317
2318         if (do_once) {
2319 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2320                 qede_print_adapter_info(adapter);
2321 #endif
2322                 do_once = false;
2323         }
2324
2325         adapter->state = QEDE_DEV_INIT;
2326
2327         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2328                   adapter->primary_mac.addr_bytes[0],
2329                   adapter->primary_mac.addr_bytes[1],
2330                   adapter->primary_mac.addr_bytes[2],
2331                   adapter->primary_mac.addr_bytes[3],
2332                   adapter->primary_mac.addr_bytes[4],
2333                   adapter->primary_mac.addr_bytes[5]);
2334
2335         return rc;
2336 }
2337
2338 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2339 {
2340         return qede_common_dev_init(eth_dev, 1);
2341 }
2342
2343 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2344 {
2345         return qede_common_dev_init(eth_dev, 0);
2346 }
2347
2348 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2349 {
2350         /* only uninitialize in the primary process */
2351         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2352                 return 0;
2353
2354         /* safe to close dev here */
2355         qede_dev_close(eth_dev);
2356
2357         eth_dev->dev_ops = NULL;
2358         eth_dev->rx_pkt_burst = NULL;
2359         eth_dev->tx_pkt_burst = NULL;
2360
2361         if (eth_dev->data->mac_addrs)
2362                 rte_free(eth_dev->data->mac_addrs);
2363
2364         eth_dev->data->mac_addrs = NULL;
2365
2366         return 0;
2367 }
2368
2369 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2370 {
2371         return qede_dev_common_uninit(eth_dev);
2372 }
2373
2374 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2375 {
2376         return qede_dev_common_uninit(eth_dev);
2377 }
2378
2379 static const struct rte_pci_id pci_id_qedevf_map[] = {
2380 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2381         {
2382                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2383         },
2384         {
2385                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2386         },
2387         {
2388                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2389         },
2390         {.vendor_id = 0,}
2391 };
2392
2393 static const struct rte_pci_id pci_id_qede_map[] = {
2394 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2395         {
2396                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2397         },
2398         {
2399                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2400         },
2401         {
2402                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2403         },
2404         {
2405                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2406         },
2407         {
2408                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2409         },
2410         {
2411                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2412         },
2413         {
2414                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2415         },
2416         {
2417                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2418         },
2419         {
2420                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2421         },
2422         {
2423                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2424         },
2425         {.vendor_id = 0,}
2426 };
2427
2428 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2429         struct rte_pci_device *pci_dev)
2430 {
2431         return rte_eth_dev_pci_generic_probe(pci_dev,
2432                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2433 }
2434
2435 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2436 {
2437         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2438 }
2439
2440 static struct rte_pci_driver rte_qedevf_pmd = {
2441         .id_table = pci_id_qedevf_map,
2442         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2443         .probe = qedevf_eth_dev_pci_probe,
2444         .remove = qedevf_eth_dev_pci_remove,
2445 };
2446
2447 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2448         struct rte_pci_device *pci_dev)
2449 {
2450         return rte_eth_dev_pci_generic_probe(pci_dev,
2451                 sizeof(struct qede_dev), qede_eth_dev_init);
2452 }
2453
2454 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2455 {
2456         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2457 }
2458
2459 static struct rte_pci_driver rte_qede_pmd = {
2460         .id_table = pci_id_qede_map,
2461         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2462         .probe = qede_eth_dev_pci_probe,
2463         .remove = qede_eth_dev_pci_remove,
2464 };
2465
2466 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2467 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2468 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2469 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2470 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2471 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");