drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_alarm.h>
   9 #include <rte_version.h>
  10 #include <rte_kvargs.h>
  11
  12 /* Globals */
  13 int qede_logtype_init;
  14 int qede_logtype_driver;
  15
  16 static const struct qed_eth_ops *qed_ops;
  17 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  18
  19 /* VXLAN tunnel classification mapping */
  20 const struct _qede_udp_tunn_types {
  21         uint16_t rte_filter_type;
  22         enum ecore_filter_ucast_type qede_type;
  23         enum ecore_tunn_clss qede_tunn_clss;
  24         const char *string;
  25 } qede_tunn_types[] = {
  26         {
  27                 ETH_TUNNEL_FILTER_OMAC,
  28                 ECORE_FILTER_MAC,
  29                 ECORE_TUNN_CLSS_MAC_VLAN,
  30                 "outer-mac"
  31         },
  32         {
  33                 ETH_TUNNEL_FILTER_TENID,
  34                 ECORE_FILTER_VNI,
  35                 ECORE_TUNN_CLSS_MAC_VNI,
  36                 "vni"
  37         },
  38         {
  39                 ETH_TUNNEL_FILTER_IMAC,
  40                 ECORE_FILTER_INNER_MAC,
  41                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  42                 "inner-mac"
  43         },
  44         {
  45                 ETH_TUNNEL_FILTER_IVLAN,
  46                 ECORE_FILTER_INNER_VLAN,
  47                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  48                 "inner-vlan"
  49         },
  50         {
  51                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  52                 ECORE_FILTER_MAC_VNI_PAIR,
  53                 ECORE_TUNN_CLSS_MAC_VNI,
  54                 "outer-mac and vni"
  55         },
  56         {
  57                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  58                 ECORE_FILTER_UNUSED,
  59                 MAX_ECORE_TUNN_CLSS,
  60                 "outer-mac and inner-mac"
  61         },
  62         {
  63                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  64                 ECORE_FILTER_UNUSED,
  65                 MAX_ECORE_TUNN_CLSS,
  66                 "outer-mac and inner-vlan"
  67         },
  68         {
  69                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  70                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  71                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  72                 "vni and inner-mac",
  73         },
  74         {
  75                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  76                 ECORE_FILTER_UNUSED,
  77                 MAX_ECORE_TUNN_CLSS,
  78                 "vni and inner-vlan",
  79         },
  80         {
  81                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  82                 ECORE_FILTER_INNER_PAIR,
  83                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  84                 "inner-mac and inner-vlan",
  85         },
  86         {
  87                 ETH_TUNNEL_FILTER_OIP,
  88                 ECORE_FILTER_UNUSED,
  89                 MAX_ECORE_TUNN_CLSS,
  90                 "outer-IP"
  91         },
  92         {
  93                 ETH_TUNNEL_FILTER_IIP,
  94                 ECORE_FILTER_UNUSED,
  95                 MAX_ECORE_TUNN_CLSS,
  96                 "inner-IP"
  97         },
  98         {
  99                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
 100                 ECORE_FILTER_UNUSED,
 101                 MAX_ECORE_TUNN_CLSS,
 102                 "IMAC_IVLAN"
 103         },
 104         {
 105                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 106                 ECORE_FILTER_UNUSED,
 107                 MAX_ECORE_TUNN_CLSS,
 108                 "IMAC_IVLAN_TENID"
 109         },
 110         {
 111                 RTE_TUNNEL_FILTER_IMAC_TENID,
 112                 ECORE_FILTER_UNUSED,
 113                 MAX_ECORE_TUNN_CLSS,
 114                 "IMAC_TENID"
 115         },
 116         {
 117                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 118                 ECORE_FILTER_UNUSED,
 119                 MAX_ECORE_TUNN_CLSS,
 120                 "OMAC_TENID_IMAC"
 121         },
 122 };
 123
 124 struct rte_qede_xstats_name_off {
 125         char name[RTE_ETH_XSTATS_NAME_SIZE];
 126         uint64_t offset;
 127 };
 128
 129 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 130         {"rx_unicast_bytes",
 131                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 132         {"rx_multicast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 134         {"rx_broadcast_bytes",
 135                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 136         {"rx_unicast_packets",
 137                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 138         {"rx_multicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 140         {"rx_broadcast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 142
 143         {"tx_unicast_bytes",
 144                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 145         {"tx_multicast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 147         {"tx_broadcast_bytes",
 148                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 149         {"tx_unicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 151         {"tx_multicast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 153         {"tx_broadcast_packets",
 154                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 155
 156         {"rx_64_byte_packets",
 157                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 158         {"rx_65_to_127_byte_packets",
 159                 offsetof(struct ecore_eth_stats_common,
 160                          rx_65_to_127_byte_packets)},
 161         {"rx_128_to_255_byte_packets",
 162                 offsetof(struct ecore_eth_stats_common,
 163                          rx_128_to_255_byte_packets)},
 164         {"rx_256_to_511_byte_packets",
 165                 offsetof(struct ecore_eth_stats_common,
 166                          rx_256_to_511_byte_packets)},
 167         {"rx_512_to_1023_byte_packets",
 168                 offsetof(struct ecore_eth_stats_common,
 169                          rx_512_to_1023_byte_packets)},
 170         {"rx_1024_to_1518_byte_packets",
 171                 offsetof(struct ecore_eth_stats_common,
 172                          rx_1024_to_1518_byte_packets)},
 173         {"tx_64_byte_packets",
 174                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 175         {"tx_65_to_127_byte_packets",
 176                 offsetof(struct ecore_eth_stats_common,
 177                          tx_65_to_127_byte_packets)},
 178         {"tx_128_to_255_byte_packets",
 179                 offsetof(struct ecore_eth_stats_common,
 180                          tx_128_to_255_byte_packets)},
 181         {"tx_256_to_511_byte_packets",
 182                 offsetof(struct ecore_eth_stats_common,
 183                          tx_256_to_511_byte_packets)},
 184         {"tx_512_to_1023_byte_packets",
 185                 offsetof(struct ecore_eth_stats_common,
 186                          tx_512_to_1023_byte_packets)},
 187         {"tx_1024_to_1518_byte_packets",
 188                 offsetof(struct ecore_eth_stats_common,
 189                          tx_1024_to_1518_byte_packets)},
 190
 191         {"rx_mac_crtl_frames",
 192                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 193         {"tx_mac_control_frames",
 194                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 195         {"rx_pause_frames",
 196                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 197         {"tx_pause_frames",
 198                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 199         {"rx_priority_flow_control_frames",
 200                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 201         {"tx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 203
 204         {"rx_crc_errors",
 205                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 206         {"rx_align_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 208         {"rx_carrier_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 210         {"rx_oversize_packet_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 212         {"rx_jabber_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 214         {"rx_undersize_packet_errors",
 215                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 216         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 217         {"rx_host_buffer_not_available",
 218                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 219         /* Number of packets discarded because they are bigger than MTU */
 220         {"rx_packet_too_big_discards",
 221                 offsetof(struct ecore_eth_stats_common,
 222                          packet_too_big_discard)},
 223         {"rx_ttl_zero_discards",
 224                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 225         {"rx_multi_function_tag_filter_discards",
 226                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 227         {"rx_mac_filter_discards",
 228                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 229         {"rx_hw_buffer_truncates",
 230                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 231         {"rx_hw_buffer_discards",
 232                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 233         {"tx_error_drop_packets",
 234                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 235
 236         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 237         {"rx_mac_unicast_packets",
 238                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 239         {"rx_mac_multicast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 241         {"rx_mac_broadcast_packets",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 243         {"rx_mac_frames_ok",
 244                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 245         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 246         {"tx_mac_unicast_packets",
 247                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 248         {"tx_mac_multicast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 250         {"tx_mac_broadcast_packets",
 251                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 252
 253         {"lro_coalesced_packets",
 254                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 255         {"lro_coalesced_events",
 256                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 257         {"lro_aborts_num",
 258                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 259         {"lro_not_coalesced_packets",
 260                 offsetof(struct ecore_eth_stats_common,
 261                          tpa_not_coalesced_pkts)},
 262         {"lro_coalesced_bytes",
 263                 offsetof(struct ecore_eth_stats_common,
 264                          tpa_coalesced_bytes)},
 265 };
 266
 267 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 268         {"rx_1519_to_1522_byte_packets",
 269                 offsetof(struct ecore_eth_stats, bb) +
 270                 offsetof(struct ecore_eth_stats_bb,
 271                          rx_1519_to_1522_byte_packets)},
 272         {"rx_1519_to_2047_byte_packets",
 273                 offsetof(struct ecore_eth_stats, bb) +
 274                 offsetof(struct ecore_eth_stats_bb,
 275                          rx_1519_to_2047_byte_packets)},
 276         {"rx_2048_to_4095_byte_packets",
 277                 offsetof(struct ecore_eth_stats, bb) +
 278                 offsetof(struct ecore_eth_stats_bb,
 279                          rx_2048_to_4095_byte_packets)},
 280         {"rx_4096_to_9216_byte_packets",
 281                 offsetof(struct ecore_eth_stats, bb) +
 282                 offsetof(struct ecore_eth_stats_bb,
 283                          rx_4096_to_9216_byte_packets)},
 284         {"rx_9217_to_16383_byte_packets",
 285                 offsetof(struct ecore_eth_stats, bb) +
 286                 offsetof(struct ecore_eth_stats_bb,
 287                          rx_9217_to_16383_byte_packets)},
 288
 289         {"tx_1519_to_2047_byte_packets",
 290                 offsetof(struct ecore_eth_stats, bb) +
 291                 offsetof(struct ecore_eth_stats_bb,
 292                          tx_1519_to_2047_byte_packets)},
 293         {"tx_2048_to_4095_byte_packets",
 294                 offsetof(struct ecore_eth_stats, bb) +
 295                 offsetof(struct ecore_eth_stats_bb,
 296                          tx_2048_to_4095_byte_packets)},
 297         {"tx_4096_to_9216_byte_packets",
 298                 offsetof(struct ecore_eth_stats, bb) +
 299                 offsetof(struct ecore_eth_stats_bb,
 300                          tx_4096_to_9216_byte_packets)},
 301         {"tx_9217_to_16383_byte_packets",
 302                 offsetof(struct ecore_eth_stats, bb) +
 303                 offsetof(struct ecore_eth_stats_bb,
 304                          tx_9217_to_16383_byte_packets)},
 305
 306         {"tx_lpi_entry_count",
 307                 offsetof(struct ecore_eth_stats, bb) +
 308                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 309         {"tx_total_collisions",
 310                 offsetof(struct ecore_eth_stats, bb) +
 311                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 312 };
 313
 314 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 315         {"rx_1519_to_max_byte_packets",
 316                 offsetof(struct ecore_eth_stats, ah) +
 317                 offsetof(struct ecore_eth_stats_ah,
 318                          rx_1519_to_max_byte_packets)},
 319         {"tx_1519_to_max_byte_packets",
 320                 offsetof(struct ecore_eth_stats, ah) +
 321                 offsetof(struct ecore_eth_stats_ah,
 322                          tx_1519_to_max_byte_packets)},
 323 };
 324
 325 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 326         {"rx_q_segments",
 327                 offsetof(struct qede_rx_queue, rx_segs)},
 328         {"rx_q_hw_errors",
 329                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 330         {"rx_q_allocation_errors",
 331                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 332 };
 333
 334 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 335 {
 336         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 337 }
 338
 339 static void
 340 qede_interrupt_handler_intx(void *param)
 341 {
 342         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 343         struct qede_dev *qdev = eth_dev->data->dev_private;
 344         struct ecore_dev *edev = &qdev->edev;
 345         u64 status;
 346
 347         /* Check if our device actually raised an interrupt */
 348         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 349         if (status & 0x1) {
 350                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 351
 352                 if (rte_intr_enable(eth_dev->intr_handle))
 353                         DP_ERR(edev, "rte_intr_enable failed\n");
 354         }
 355 }
 356
 357 static void
 358 qede_interrupt_handler(void *param)
 359 {
 360         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 361         struct qede_dev *qdev = eth_dev->data->dev_private;
 362         struct ecore_dev *edev = &qdev->edev;
 363
 364         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 365         if (rte_intr_enable(eth_dev->intr_handle))
 366                 DP_ERR(edev, "rte_intr_enable failed\n");
 367 }
 368
 369 static void
 370 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 371 {
 372         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 373         qdev->ops = qed_ops;
 374 }
 375
 376 static void qede_print_adapter_info(struct qede_dev *qdev)
 377 {
 378         struct ecore_dev *edev = &qdev->edev;
 379         struct qed_dev_info *info = &qdev->dev_info.common;
 380         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 381         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 382
 383         DP_INFO(edev, "*********************************\n");
 384         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 385         DP_INFO(edev, " Chip details : %s %c%d\n",
 386                   ECORE_IS_BB(edev) ? "BB" : "AH",
 387                   'A' + edev->chip_rev,
 388                   (int)edev->chip_metal);
 389         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 390                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 391         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 392                  ver_str, QEDE_PMD_VERSION);
 393         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 394         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 395
 396         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 397                  "%d.%d.%d.%d",
 398                 (info->mfw_rev >> 24) & 0xff,
 399                 (info->mfw_rev >> 16) & 0xff,
 400                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 401         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 402         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 403         DP_INFO(edev, "*********************************\n");
 404 }
 405
 406 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 407 {
 408         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 409         unsigned int i = 0, j = 0, qid;
 410         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 411         struct qede_tx_queue *txq;
 412
 413         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 414
 415         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 416                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 417         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 418                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 419
 420         for_each_rss(qid) {
 421                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 422                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 423                             sizeof(uint64_t));
 424                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 425                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 426                             sizeof(uint64_t));
 427                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 428                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 429                             sizeof(uint64_t));
 430
 431                 if (xstats)
 432                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 433                                 OSAL_MEMSET((((char *)
 434                                               (qdev->fp_array[qid].rxq)) +
 435                                              qede_rxq_xstats_strings[j].offset),
 436                                             0,
 437                                             sizeof(uint64_t));
 438
 439                 i++;
 440                 if (i == rxq_stat_cntrs)
 441                         break;
 442         }
 443
 444         i = 0;
 445
 446         for_each_tss(qid) {
 447                 txq = qdev->fp_array[qid].txq;
 448
 449                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 450                                 (((uint64_t)(uintptr_t)(txq)) +
 451                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 452                             sizeof(uint64_t));
 453
 454                 i++;
 455                 if (i == txq_stat_cntrs)
 456                         break;
 457         }
 458 }
 459
 460 static int
 461 qede_stop_vport(struct ecore_dev *edev)
 462 {
 463         struct ecore_hwfn *p_hwfn;
 464         uint8_t vport_id;
 465         int rc;
 466         int i;
 467
 468         vport_id = 0;
 469         for_each_hwfn(edev, i) {
 470                 p_hwfn = &edev->hwfns[i];
 471                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 472                                          vport_id);
 473                 if (rc != ECORE_SUCCESS) {
 474                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 475                         return rc;
 476                 }
 477         }
 478
 479         DP_INFO(edev, "vport stopped\n");
 480
 481         return 0;
 482 }
 483
 484 static int
 485 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 486 {
 487         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 488         struct ecore_sp_vport_start_params params;
 489         struct ecore_hwfn *p_hwfn;
 490         int rc;
 491         int i;
 492
 493         if (qdev->vport_started)
 494                 qede_stop_vport(edev);
 495
 496         memset(&params, 0, sizeof(params));
 497         params.vport_id = 0;
 498         params.mtu = mtu;
 499         /* @DPDK - Disable FW placement */
 500         params.zero_placement_offset = 1;
 501         for_each_hwfn(edev, i) {
 502                 p_hwfn = &edev->hwfns[i];
 503                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 504                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 505                 rc = ecore_sp_vport_start(p_hwfn, &params);
 506                 if (rc != ECORE_SUCCESS) {
 507                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 508                         return rc;
 509                 }
 510         }
 511         ecore_reset_vport_stats(edev);
 512         qdev->vport_started = true;
 513         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 514
 515         return 0;
 516 }
 517
 518 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 519 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 520
 521 /* Activate or deactivate vport via vport-update */
 522 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 523 {
 524         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 525         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 526         struct ecore_sp_vport_update_params params;
 527         struct ecore_hwfn *p_hwfn;
 528         uint8_t i;
 529         int rc = -1;
 530
 531         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 532         params.vport_id = 0;
 533         params.update_vport_active_rx_flg = 1;
 534         params.update_vport_active_tx_flg = 1;
 535         params.vport_active_rx_flg = flg;
 536         params.vport_active_tx_flg = flg;
 537         if (~qdev->enable_tx_switching & flg) {
 538                 params.update_tx_switching_flg = 1;
 539                 params.tx_switching_flg = !flg;
 540         }
 541         for_each_hwfn(edev, i) {
 542                 p_hwfn = &edev->hwfns[i];
 543                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 544                 rc = ecore_sp_vport_update(p_hwfn, &params,
 545                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 546                 if (rc != ECORE_SUCCESS) {
 547                         DP_ERR(edev, "Failed to update vport\n");
 548                         break;
 549                 }
 550         }
 551         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 552
 553         return rc;
 554 }
 555
 556 static void
 557 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 558                            uint16_t mtu, bool enable)
 559 {
 560         /* Enable LRO in split mode */
 561         sge_tpa_params->tpa_ipv4_en_flg = enable;
 562         sge_tpa_params->tpa_ipv6_en_flg = enable;
 563         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 564         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 565         /* set if tpa enable changes */
 566         sge_tpa_params->update_tpa_en_flg = 1;
 567         /* set if tpa parameters should be handled */
 568         sge_tpa_params->update_tpa_param_flg = enable;
 569
 570         sge_tpa_params->max_buffers_per_cqe = 20;
 571         /* Enable TPA in split mode. In this mode each TPA segment
 572          * starts on the new BD, so there is one BD per segment.
 573          */
 574         sge_tpa_params->tpa_pkt_split_flg = 1;
 575         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 576         sge_tpa_params->tpa_gro_consistent_flg = 0;
 577         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 578         sge_tpa_params->tpa_max_size = 0x7FFF;
 579         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 580         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 581 }
 582
 583 /* Enable/disable LRO via vport-update */
 584 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 585 {
 586         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 587         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 588         struct ecore_sp_vport_update_params params;
 589         struct ecore_sge_tpa_params tpa_params;
 590         struct ecore_hwfn *p_hwfn;
 591         int rc;
 592         int i;
 593
 594         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 595         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 596         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 597         params.vport_id = 0;
 598         params.sge_tpa_params = &tpa_params;
 599         for_each_hwfn(edev, i) {
 600                 p_hwfn = &edev->hwfns[i];
 601                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 602                 rc = ecore_sp_vport_update(p_hwfn, &params,
 603                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 604                 if (rc != ECORE_SUCCESS) {
 605                         DP_ERR(edev, "Failed to update LRO\n");
 606                         return -1;
 607                 }
 608         }
 609         qdev->enable_lro = flg;
 610         eth_dev->data->lro = flg;
 611
 612         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 613
 614         return 0;
 615 }
 616
 617 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 618 {
 619         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 620         ucast->is_rx_filter = true;
 621         ucast->is_tx_filter = true;
 622         /* ucast->assert_on_error = true; - For debug */
 623 }
 624
 625 static int
 626 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 627                              enum qed_filter_rx_mode_type type)
 628 {
 629         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 630         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 631         struct ecore_filter_accept_flags flags;
 632
 633         memset(&flags, 0, sizeof(flags));
 634
 635         flags.update_rx_mode_config = 1;
 636         flags.update_tx_mode_config = 1;
 637         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 638                 ECORE_ACCEPT_MCAST_MATCHED |
 639                 ECORE_ACCEPT_BCAST;
 640
 641         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 642                 ECORE_ACCEPT_MCAST_MATCHED |
 643                 ECORE_ACCEPT_BCAST;
 644
 645         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 646                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 647                 if (IS_VF(edev)) {
 648                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 649                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 650                 }
 651         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 652                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 653         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 654                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 655                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 656                         ECORE_ACCEPT_MCAST_UNMATCHED;
 657         }
 658
 659         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 660                         ECORE_SPQ_MODE_CB, NULL);
 661 }
 662
 663 static int
 664 qede_tunnel_update(struct qede_dev *qdev,
 665                    struct ecore_tunnel_info *tunn_info)
 666 {
 667         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 668         enum _ecore_status_t rc = ECORE_INVAL;
 669         struct ecore_hwfn *p_hwfn;
 670         struct ecore_ptt *p_ptt;
 671         int i;
 672
 673         for_each_hwfn(edev, i) {
 674                 p_hwfn = &edev->hwfns[i];
 675                 if (IS_PF(edev)) {
 676                         p_ptt = ecore_ptt_acquire(p_hwfn);
 677                         if (!p_ptt) {
 678                                 DP_ERR(p_hwfn, "Can't acquire PTT\n");
 679                                 return -EAGAIN;
 680                         }
 681                 } else {
 682                         p_ptt = NULL;
 683                 }
 684
 685                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 686                                 tunn_info, ECORE_SPQ_MODE_CB, NULL);
 687                 if (IS_PF(edev))
 688                         ecore_ptt_release(p_hwfn, p_ptt);
 689
 690                 if (rc != ECORE_SUCCESS)
 691                         break;
 692         }
 693
 694         return rc;
 695 }
 696
 697 static int
 698 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 699                   bool enable)
 700 {
 701         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 702         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 703         enum _ecore_status_t rc = ECORE_INVAL;
 704         struct ecore_tunnel_info tunn;
 705
 706         if (qdev->vxlan.enable == enable)
 707                 return ECORE_SUCCESS;
 708
 709         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 710         tunn.vxlan.b_update_mode = true;
 711         tunn.vxlan.b_mode_enabled = enable;
 712         tunn.b_update_rx_cls = true;
 713         tunn.b_update_tx_cls = true;
 714         tunn.vxlan.tun_cls = clss;
 715
 716         tunn.vxlan_port.b_update_port = true;
 717         tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
 718
 719         rc = qede_tunnel_update(qdev, &tunn);
 720         if (rc == ECORE_SUCCESS) {
 721                 qdev->vxlan.enable = enable;
 722                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 723                 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
 724                         enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
 725         } else {
 726                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 727                        tunn.vxlan.tun_cls);
 728         }
 729
 730         return rc;
 731 }
 732
 733 static int
 734 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 735                   bool enable)
 736 {
 737         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 738         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 739         enum _ecore_status_t rc = ECORE_INVAL;
 740         struct ecore_tunnel_info tunn;
 741
 742         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 743         tunn.l2_geneve.b_update_mode = true;
 744         tunn.l2_geneve.b_mode_enabled = enable;
 745         tunn.ip_geneve.b_update_mode = true;
 746         tunn.ip_geneve.b_mode_enabled = enable;
 747         tunn.l2_geneve.tun_cls = clss;
 748         tunn.ip_geneve.tun_cls = clss;
 749         tunn.b_update_rx_cls = true;
 750         tunn.b_update_tx_cls = true;
 751
 752         tunn.geneve_port.b_update_port = true;
 753         tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
 754
 755         rc = qede_tunnel_update(qdev, &tunn);
 756         if (rc == ECORE_SUCCESS) {
 757                 qdev->geneve.enable = enable;
 758                 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
 759                 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
 760                         enable ? "enabled" : "disabled", qdev->geneve.udp_port);
 761         } else {
 762                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 763                        clss);
 764         }
 765
 766         return rc;
 767 }
 768
 769 static int
 770 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 771                   bool enable)
 772 {
 773         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 774         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 775         enum _ecore_status_t rc = ECORE_INVAL;
 776         struct ecore_tunnel_info tunn;
 777
 778         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 779         tunn.ip_gre.b_update_mode = true;
 780         tunn.ip_gre.b_mode_enabled = enable;
 781         tunn.ip_gre.tun_cls = clss;
 782         tunn.ip_gre.tun_cls = clss;
 783         tunn.b_update_rx_cls = true;
 784         tunn.b_update_tx_cls = true;
 785
 786         rc = qede_tunnel_update(qdev, &tunn);
 787         if (rc == ECORE_SUCCESS) {
 788                 qdev->ipgre.enable = enable;
 789                 DP_INFO(edev, "IPGRE is %s\n",
 790                         enable ? "enabled" : "disabled");
 791         } else {
 792                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 793                        clss);
 794         }
 795
 796         return rc;
 797 }
 798
 799 static int
 800 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 801                  enum rte_eth_tunnel_type tunn_type, bool enable)
 802 {
 803         int rc = -EINVAL;
 804
 805         switch (tunn_type) {
 806         case RTE_TUNNEL_TYPE_VXLAN:
 807                 rc = qede_vxlan_enable(eth_dev, clss, enable);
 808                 break;
 809         case RTE_TUNNEL_TYPE_GENEVE:
 810                 rc = qede_geneve_enable(eth_dev, clss, enable);
 811                 break;
 812         case RTE_TUNNEL_TYPE_IP_IN_GRE:
 813                 rc = qede_ipgre_enable(eth_dev, clss, enable);
 814                 break;
 815         default:
 816                 rc = -EINVAL;
 817                 break;
 818         }
 819
 820         return rc;
 821 }
 822
 823 static int
 824 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 825                   bool add)
 826 {
 827         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 828         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 829         struct qede_ucast_entry *tmp = NULL;
 830         struct qede_ucast_entry *u;
 831         struct ether_addr *mac_addr;
 832
 833         mac_addr  = (struct ether_addr *)ucast->mac;
 834         if (add) {
 835                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 836                         if ((memcmp(mac_addr, &tmp->mac,
 837                                     ETHER_ADDR_LEN) == 0) &&
 838                              ucast->vni == tmp->vni &&
 839                              ucast->vlan == tmp->vlan) {
 840                                 DP_INFO(edev, "Unicast MAC is already added"
 841                                         " with vlan = %u, vni = %u\n",
 842                                         ucast->vlan,  ucast->vni);
 843                                         return 0;
 844                         }
 845                 }
 846                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 847                                RTE_CACHE_LINE_SIZE);
 848                 if (!u) {
 849                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 850                         return -ENOMEM;
 851                 }
 852                 ether_addr_copy(mac_addr, &u->mac);
 853                 u->vlan = ucast->vlan;
 854                 u->vni = ucast->vni;
 855                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 856                 qdev->num_uc_addr++;
 857         } else {
 858                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 859                         if ((memcmp(mac_addr, &tmp->mac,
 860                                     ETHER_ADDR_LEN) == 0) &&
 861                             ucast->vlan == tmp->vlan      &&
 862                             ucast->vni == tmp->vni)
 863                         break;
 864                 }
 865                 if (tmp == NULL) {
 866                         DP_INFO(edev, "Unicast MAC is not found\n");
 867                         return -EINVAL;
 868                 }
 869                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 870                 qdev->num_uc_addr--;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int
 877 qede_add_mcast_filters(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
 878                        uint32_t mc_addrs_num)
 879 {
 880         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 881         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 882         struct ecore_filter_mcast mcast;
 883         struct qede_mcast_entry *m = NULL;
 884         uint8_t i;
 885         int rc;
 886
 887         for (i = 0; i < mc_addrs_num; i++) {
 888                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 889                                RTE_CACHE_LINE_SIZE);
 890                 if (!m) {
 891                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 892                         return -ENOMEM;
 893                 }
 894                 ether_addr_copy(&mc_addrs[i], &m->mac);
 895                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 896         }
 897         memset(&mcast, 0, sizeof(mcast));
 898         mcast.num_mc_addrs = mc_addrs_num;
 899         mcast.opcode = ECORE_FILTER_ADD;
 900         for (i = 0; i < mc_addrs_num; i++)
 901                 ether_addr_copy(&mc_addrs[i], (struct ether_addr *)
 902                                                         &mcast.mac[i]);
 903         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 904         if (rc != ECORE_SUCCESS) {
 905                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 906                 return -1;
 907         }
 908
 909         return 0;
 910 }
 911
 912 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 913 {
 914         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 915         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 916         struct qede_mcast_entry *tmp = NULL;
 917         struct ecore_filter_mcast mcast;
 918         int j;
 919         int rc;
 920
 921         memset(&mcast, 0, sizeof(mcast));
 922         mcast.num_mc_addrs = qdev->num_mc_addr;
 923         mcast.opcode = ECORE_FILTER_REMOVE;
 924         j = 0;
 925         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 926                 ether_addr_copy(&tmp->mac, (struct ether_addr *)&mcast.mac[j]);
 927                 j++;
 928         }
 929         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 930         if (rc != ECORE_SUCCESS) {
 931                 DP_ERR(edev, "Failed to delete multicast filter\n");
 932                 return -1;
 933         }
 934         /* Init the list */
 935         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 936                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 937                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 938         }
 939         SLIST_INIT(&qdev->mc_list_head);
 940
 941         return 0;
 942 }
 943
 944 static enum _ecore_status_t
 945 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 946                  bool add)
 947 {
 948         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 949         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 950         enum _ecore_status_t rc = ECORE_INVAL;
 951
 952         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 953                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 954                               " Please enable promisc mode\n");
 955                         return ECORE_INVAL;
 956         }
 957
 958         rc = qede_ucast_filter(eth_dev, ucast, add);
 959         if (rc == 0)
 960                 rc = ecore_filter_ucast_cmd(edev, ucast,
 961                                             ECORE_SPQ_MODE_CB, NULL);
 962         /* Indicate error only for add filter operation.
 963          * Delete filter operations are not severe.
 964          */
 965         if ((rc != ECORE_SUCCESS) && add)
 966                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 967                        rc, add);
 968
 969         return rc;
 970 }
 971
 972 static int
 973 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 974                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 975 {
 976         struct ecore_filter_ucast ucast;
 977         int re;
 978
 979         if (!is_valid_assigned_ether_addr(mac_addr))
 980                 return -EINVAL;
 981
 982         qede_set_ucast_cmn_params(&ucast);
 983         ucast.opcode = ECORE_FILTER_ADD;
 984         ucast.type = ECORE_FILTER_MAC;
 985         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 986         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 987         return re;
 988 }
 989
 990 static void
 991 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 992 {
 993         struct qede_dev *qdev = eth_dev->data->dev_private;
 994         struct ecore_dev *edev = &qdev->edev;
 995         struct ecore_filter_ucast ucast;
 996
 997         PMD_INIT_FUNC_TRACE(edev);
 998
 999         if (index >= qdev->dev_info.num_mac_filters) {
1000                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
1001                        index, qdev->dev_info.num_mac_filters);
1002                 return;
1003         }
1004
1005         if (!is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
1006                 return;
1007
1008         qede_set_ucast_cmn_params(&ucast);
1009         ucast.opcode = ECORE_FILTER_REMOVE;
1010         ucast.type = ECORE_FILTER_MAC;
1011
1012         /* Use the index maintained by rte */
1013         ether_addr_copy(&eth_dev->data->mac_addrs[index],
1014                         (struct ether_addr *)&ucast.mac);
1015
1016         qede_mac_int_ops(eth_dev, &ucast, false);
1017 }
1018
1019 static int
1020 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1021 {
1022         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1023         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1024
1025         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1026                                                mac_addr->addr_bytes)) {
1027                 DP_ERR(edev, "Setting MAC address is not allowed\n");
1028                 return -EPERM;
1029         }
1030
1031         qede_mac_addr_remove(eth_dev, 0);
1032
1033         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1034 }
1035
1036 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1037 {
1038         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1039         struct ecore_sp_vport_update_params params;
1040         struct ecore_hwfn *p_hwfn;
1041         uint8_t i;
1042         int rc;
1043
1044         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1045         params.vport_id = 0;
1046         params.update_accept_any_vlan_flg = 1;
1047         params.accept_any_vlan = flg;
1048         for_each_hwfn(edev, i) {
1049                 p_hwfn = &edev->hwfns[i];
1050                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1051                 rc = ecore_sp_vport_update(p_hwfn, &params,
1052                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1053                 if (rc != ECORE_SUCCESS) {
1054                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1055                         return;
1056                 }
1057         }
1058
1059         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1060 }
1061
1062 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1063 {
1064         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1065         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1066         struct ecore_sp_vport_update_params params;
1067         struct ecore_hwfn *p_hwfn;
1068         uint8_t i;
1069         int rc;
1070
1071         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1072         params.vport_id = 0;
1073         params.update_inner_vlan_removal_flg = 1;
1074         params.inner_vlan_removal_flg = flg;
1075         for_each_hwfn(edev, i) {
1076                 p_hwfn = &edev->hwfns[i];
1077                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1078                 rc = ecore_sp_vport_update(p_hwfn, &params,
1079                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1080                 if (rc != ECORE_SUCCESS) {
1081                         DP_ERR(edev, "Failed to update vport\n");
1082                         return -1;
1083                 }
1084         }
1085
1086         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1087         return 0;
1088 }
1089
1090 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1091                                 uint16_t vlan_id, int on)
1092 {
1093         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1094         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1095         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1096         struct qede_vlan_entry *tmp = NULL;
1097         struct qede_vlan_entry *vlan;
1098         struct ecore_filter_ucast ucast;
1099         int rc;
1100
1101         if (on) {
1102                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1103                         DP_ERR(edev, "Reached max VLAN filter limit"
1104                                       " enabling accept_any_vlan\n");
1105                         qede_config_accept_any_vlan(qdev, true);
1106                         return 0;
1107                 }
1108
1109                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1110                         if (tmp->vid == vlan_id) {
1111                                 DP_INFO(edev, "VLAN %u already configured\n",
1112                                         vlan_id);
1113                                 return 0;
1114                         }
1115                 }
1116
1117                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1118                                   RTE_CACHE_LINE_SIZE);
1119
1120                 if (!vlan) {
1121                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
1122                         return -ENOMEM;
1123                 }
1124
1125                 qede_set_ucast_cmn_params(&ucast);
1126                 ucast.opcode = ECORE_FILTER_ADD;
1127                 ucast.type = ECORE_FILTER_VLAN;
1128                 ucast.vlan = vlan_id;
1129                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1130                                             NULL);
1131                 if (rc != 0) {
1132                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1133                                rc);
1134                         rte_free(vlan);
1135                 } else {
1136                         vlan->vid = vlan_id;
1137                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1138                         qdev->configured_vlans++;
1139                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1140                                 vlan_id, qdev->configured_vlans);
1141                 }
1142         } else {
1143                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1144                         if (tmp->vid == vlan_id)
1145                                 break;
1146                 }
1147
1148                 if (!tmp) {
1149                         if (qdev->configured_vlans == 0) {
1150                                 DP_INFO(edev,
1151                                         "No VLAN filters configured yet\n");
1152                                 return 0;
1153                         }
1154
1155                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1156                         return -EINVAL;
1157                 }
1158
1159                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1160
1161                 qede_set_ucast_cmn_params(&ucast);
1162                 ucast.opcode = ECORE_FILTER_REMOVE;
1163                 ucast.type = ECORE_FILTER_VLAN;
1164                 ucast.vlan = vlan_id;
1165                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1166                                             NULL);
1167                 if (rc != 0) {
1168                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1169                                vlan_id, rc);
1170                 } else {
1171                         qdev->configured_vlans--;
1172                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1173                                 vlan_id, qdev->configured_vlans);
1174                 }
1175         }
1176
1177         return rc;
1178 }
1179
1180 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1181 {
1182         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1183         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1184         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1185
1186         if (mask & ETH_VLAN_STRIP_MASK) {
1187                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1188                         (void)qede_vlan_stripping(eth_dev, 1);
1189                 else
1190                         (void)qede_vlan_stripping(eth_dev, 0);
1191         }
1192
1193         if (mask & ETH_VLAN_FILTER_MASK) {
1194                 /* VLAN filtering kicks in when a VLAN is added */
1195                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1196                         qede_vlan_filter_set(eth_dev, 0, 1);
1197                 } else {
1198                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1199                                 DP_ERR(edev,
1200                                   " Please remove existing VLAN filters"
1201                                   " before disabling VLAN filtering\n");
1202                                 /* Signal app that VLAN filtering is still
1203                                  * enabled
1204                                  */
1205                                 eth_dev->data->dev_conf.rxmode.offloads |=
1206                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1207                         } else {
1208                                 qede_vlan_filter_set(eth_dev, 0, 0);
1209                         }
1210                 }
1211         }
1212
1213         if (mask & ETH_VLAN_EXTEND_MASK)
1214                 DP_ERR(edev, "Extend VLAN not supported\n");
1215
1216         qdev->vlan_offload_mask = mask;
1217
1218         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1219
1220         return 0;
1221 }
1222
1223 static void qede_prandom_bytes(uint32_t *buff)
1224 {
1225         uint8_t i;
1226
1227         srand((unsigned int)time(NULL));
1228         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1229                 buff[i] = rand();
1230 }
1231
1232 int qede_config_rss(struct rte_eth_dev *eth_dev)
1233 {
1234         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1235         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1236         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1237         struct rte_eth_rss_reta_entry64 reta_conf[2];
1238         struct rte_eth_rss_conf rss_conf;
1239         uint32_t i, id, pos, q;
1240
1241         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1242         if (!rss_conf.rss_key) {
1243                 DP_INFO(edev, "Applying driver default key\n");
1244                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1245                 qede_prandom_bytes(&def_rss_key[0]);
1246                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1247         }
1248
1249         /* Configure RSS hash */
1250         if (qede_rss_hash_update(eth_dev, &rss_conf))
1251                 return -EINVAL;
1252
1253         /* Configure default RETA */
1254         memset(reta_conf, 0, sizeof(reta_conf));
1255         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1256                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1257
1258         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1259                 id = i / RTE_RETA_GROUP_SIZE;
1260                 pos = i % RTE_RETA_GROUP_SIZE;
1261                 q = i % QEDE_RSS_COUNT(qdev);
1262                 reta_conf[id].reta[pos] = q;
1263         }
1264         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1265                                  ECORE_RSS_IND_TABLE_SIZE))
1266                 return -EINVAL;
1267
1268         return 0;
1269 }
1270
1271 static void qede_fastpath_start(struct ecore_dev *edev)
1272 {
1273         struct ecore_hwfn *p_hwfn;
1274         int i;
1275
1276         for_each_hwfn(edev, i) {
1277                 p_hwfn = &edev->hwfns[i];
1278                 ecore_hw_start_fastpath(p_hwfn);
1279         }
1280 }
1281
1282 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1283 {
1284         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1285         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1286         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1287
1288         PMD_INIT_FUNC_TRACE(edev);
1289
1290         /* Update MTU only if it has changed */
1291         if (eth_dev->data->mtu != qdev->mtu) {
1292                 if (qede_update_mtu(eth_dev, qdev->mtu))
1293                         goto err;
1294         }
1295
1296         /* Configure TPA parameters */
1297         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1298                 if (qede_enable_tpa(eth_dev, true))
1299                         return -EINVAL;
1300                 /* Enable scatter mode for LRO */
1301                 if (!eth_dev->data->scattered_rx)
1302                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1303         }
1304
1305         /* Start queues */
1306         if (qede_start_queues(eth_dev))
1307                 goto err;
1308
1309         if (IS_PF(edev))
1310                 qede_reset_queue_stats(qdev, true);
1311
1312         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1313          * enabling RSS. Hence RSS configuration is deferred upto this point.
1314          * Also, we would like to retain similar behavior in PF case, so we
1315          * don't do PF/VF specific check here.
1316          */
1317         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1318                 if (qede_config_rss(eth_dev))
1319                         goto err;
1320
1321         /* Enable vport*/
1322         if (qede_activate_vport(eth_dev, true))
1323                 goto err;
1324
1325         /* Update link status */
1326         qede_link_update(eth_dev, 0);
1327
1328         /* Start/resume traffic */
1329         qede_fastpath_start(edev);
1330
1331         DP_INFO(edev, "Device started\n");
1332
1333         return 0;
1334 err:
1335         DP_ERR(edev, "Device start fails\n");
1336         return -1; /* common error code is < 0 */
1337 }
1338
1339 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1340 {
1341         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1342         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1343
1344         PMD_INIT_FUNC_TRACE(edev);
1345
1346         /* Disable vport */
1347         if (qede_activate_vport(eth_dev, false))
1348                 return;
1349
1350         if (qdev->enable_lro)
1351                 qede_enable_tpa(eth_dev, false);
1352
1353         /* Stop queues */
1354         qede_stop_queues(eth_dev);
1355
1356         /* Disable traffic */
1357         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1358
1359         DP_INFO(edev, "Device is stopped\n");
1360 }
1361
1362 const char *valid_args[] = {
1363         QEDE_NPAR_TX_SWITCHING,
1364         QEDE_VF_TX_SWITCHING,
1365         NULL,
1366 };
1367
1368 static int qede_args_check(const char *key, const char *val, void *opaque)
1369 {
1370         unsigned long tmp;
1371         int ret = 0;
1372         struct rte_eth_dev *eth_dev = opaque;
1373         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1374         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1375
1376         errno = 0;
1377         tmp = strtoul(val, NULL, 0);
1378         if (errno) {
1379                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1380                 return errno;
1381         }
1382
1383         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1384             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1385                 qdev->enable_tx_switching = !!tmp;
1386                 DP_INFO(edev, "Disabling %s tx-switching\n",
1387                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1388                         "VF" : "NPAR");
1389         }
1390
1391         return ret;
1392 }
1393
1394 static int qede_args(struct rte_eth_dev *eth_dev)
1395 {
1396         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1397         struct rte_kvargs *kvlist;
1398         struct rte_devargs *devargs;
1399         int ret;
1400         int i;
1401
1402         devargs = pci_dev->device.devargs;
1403         if (!devargs)
1404                 return 0; /* return success */
1405
1406         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1407         if (kvlist == NULL)
1408                 return -EINVAL;
1409
1410          /* Process parameters. */
1411         for (i = 0; (valid_args[i] != NULL); ++i) {
1412                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1413                         ret = rte_kvargs_process(kvlist, valid_args[i],
1414                                                  qede_args_check, eth_dev);
1415                         if (ret != ECORE_SUCCESS) {
1416                                 rte_kvargs_free(kvlist);
1417                                 return ret;
1418                         }
1419                 }
1420         }
1421         rte_kvargs_free(kvlist);
1422
1423         return 0;
1424 }
1425
1426 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1427 {
1428         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1429         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1430         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1431         int ret;
1432
1433         PMD_INIT_FUNC_TRACE(edev);
1434
1435         /* Check requirements for 100G mode */
1436         if (ECORE_IS_CMT(edev)) {
1437                 if (eth_dev->data->nb_rx_queues < 2 ||
1438                     eth_dev->data->nb_tx_queues < 2) {
1439                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1440                         return -EINVAL;
1441                 }
1442
1443                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1444                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
1445                         DP_ERR(edev,
1446                                "100G mode needs even no. of RX/TX queues\n");
1447                         return -EINVAL;
1448                 }
1449         }
1450
1451         /* We need to have min 1 RX queue.There is no min check in
1452          * rte_eth_dev_configure(), so we are checking it here.
1453          */
1454         if (eth_dev->data->nb_rx_queues == 0) {
1455                 DP_ERR(edev, "Minimum one RX queue is required\n");
1456                 return -EINVAL;
1457         }
1458
1459         /* Enable Tx switching by default */
1460         qdev->enable_tx_switching = 1;
1461
1462         /* Parse devargs and fix up rxmode */
1463         if (qede_args(eth_dev))
1464                 DP_NOTICE(edev, false,
1465                           "Invalid devargs supplied, requested change will not take effect\n");
1466
1467         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1468               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1469                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1470                 return -ENOTSUP;
1471         }
1472         /* Flow director mode check */
1473         if (qede_check_fdir_support(eth_dev))
1474                 return -ENOTSUP;
1475
1476         qede_dealloc_fp_resc(eth_dev);
1477         qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1478         qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1479         if (qede_alloc_fp_resc(qdev))
1480                 return -ENOMEM;
1481
1482         /* If jumbo enabled adjust MTU */
1483         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1484                 eth_dev->data->mtu =
1485                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1486                         ETHER_HDR_LEN - ETHER_CRC_LEN;
1487
1488         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1489                 eth_dev->data->scattered_rx = 1;
1490
1491         if (qede_start_vport(qdev, eth_dev->data->mtu))
1492                 return -1;
1493
1494         qdev->mtu = eth_dev->data->mtu;
1495
1496         /* Enable VLAN offloads by default */
1497         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1498                                              ETH_VLAN_FILTER_MASK);
1499         if (ret)
1500                 return ret;
1501
1502         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1503                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1504
1505         return 0;
1506 }
1507
1508 /* Info about HW descriptor ring limitations */
1509 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1510         .nb_max = 0x8000, /* 32K */
1511         .nb_min = 128,
1512         .nb_align = 128 /* lowest common multiple */
1513 };
1514
1515 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1516         .nb_max = 0x8000, /* 32K */
1517         .nb_min = 256,
1518         .nb_align = 256,
1519         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1520         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1521 };
1522
1523 static void
1524 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1525                   struct rte_eth_dev_info *dev_info)
1526 {
1527         struct qede_dev *qdev = eth_dev->data->dev_private;
1528         struct ecore_dev *edev = &qdev->edev;
1529         struct qed_link_output link;
1530         uint32_t speed_cap = 0;
1531
1532         PMD_INIT_FUNC_TRACE(edev);
1533
1534         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1535         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1536         dev_info->rx_desc_lim = qede_rx_desc_lim;
1537         dev_info->tx_desc_lim = qede_tx_desc_lim;
1538
1539         if (IS_PF(edev))
1540                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1541                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1542         else
1543                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1544                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1545         dev_info->max_tx_queues = dev_info->max_rx_queues;
1546
1547         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1548         dev_info->max_vfs = 0;
1549         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1550         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1551         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1552         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1553                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1554                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1555                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1556                                      DEV_RX_OFFLOAD_TCP_LRO     |
1557                                      DEV_RX_OFFLOAD_CRC_STRIP   |
1558                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1559                                      DEV_RX_OFFLOAD_SCATTER     |
1560                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1561                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1562                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1563         dev_info->rx_queue_offload_capa = 0;
1564
1565         /* TX offloads are on a per-packet basis, so it is applicable
1566          * to both at port and queue levels.
1567          */
1568         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1569                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1570                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1571                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1572                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1573                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1574                                      DEV_TX_OFFLOAD_TCP_TSO     |
1575                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1576                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1577         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1578
1579         dev_info->default_txconf = (struct rte_eth_txconf) {
1580                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1581         };
1582
1583         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1584                 /* Packets are always dropped if no descriptors are available */
1585                 .rx_drop_en = 1,
1586                 .offloads = 0,
1587         };
1588
1589         memset(&link, 0, sizeof(struct qed_link_output));
1590         qdev->ops->common->get_link(edev, &link);
1591         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1592                 speed_cap |= ETH_LINK_SPEED_1G;
1593         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1594                 speed_cap |= ETH_LINK_SPEED_10G;
1595         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1596                 speed_cap |= ETH_LINK_SPEED_25G;
1597         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1598                 speed_cap |= ETH_LINK_SPEED_40G;
1599         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1600                 speed_cap |= ETH_LINK_SPEED_50G;
1601         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1602                 speed_cap |= ETH_LINK_SPEED_100G;
1603         dev_info->speed_capa = speed_cap;
1604 }
1605
1606 /* return 0 means link status changed, -1 means not changed */
1607 int
1608 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1609 {
1610         struct qede_dev *qdev = eth_dev->data->dev_private;
1611         struct ecore_dev *edev = &qdev->edev;
1612         struct qed_link_output q_link;
1613         struct rte_eth_link link;
1614         uint16_t link_duplex;
1615
1616         memset(&q_link, 0, sizeof(q_link));
1617         memset(&link, 0, sizeof(link));
1618
1619         qdev->ops->common->get_link(edev, &q_link);
1620
1621         /* Link Speed */
1622         link.link_speed = q_link.speed;
1623
1624         /* Link Mode */
1625         switch (q_link.duplex) {
1626         case QEDE_DUPLEX_HALF:
1627                 link_duplex = ETH_LINK_HALF_DUPLEX;
1628                 break;
1629         case QEDE_DUPLEX_FULL:
1630                 link_duplex = ETH_LINK_FULL_DUPLEX;
1631                 break;
1632         case QEDE_DUPLEX_UNKNOWN:
1633         default:
1634                 link_duplex = -1;
1635         }
1636         link.link_duplex = link_duplex;
1637
1638         /* Link Status */
1639         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1640
1641         /* AN */
1642         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1643                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1644
1645         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1646                 link.link_speed, link.link_duplex,
1647                 link.link_autoneg, link.link_status);
1648
1649         return rte_eth_linkstatus_set(eth_dev, &link);
1650 }
1651
1652 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1653 {
1654 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1655         struct qede_dev *qdev = eth_dev->data->dev_private;
1656         struct ecore_dev *edev = &qdev->edev;
1657
1658         PMD_INIT_FUNC_TRACE(edev);
1659 #endif
1660
1661         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1662
1663         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1664                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1665
1666         qed_configure_filter_rx_mode(eth_dev, type);
1667 }
1668
1669 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1670 {
1671 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1672         struct qede_dev *qdev = eth_dev->data->dev_private;
1673         struct ecore_dev *edev = &qdev->edev;
1674
1675         PMD_INIT_FUNC_TRACE(edev);
1676 #endif
1677
1678         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1679                 qed_configure_filter_rx_mode(eth_dev,
1680                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1681         else
1682                 qed_configure_filter_rx_mode(eth_dev,
1683                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1684 }
1685
1686 static void qede_poll_sp_sb_cb(void *param)
1687 {
1688         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1689         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1690         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1691         int rc;
1692
1693         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1694         qede_interrupt_action(&edev->hwfns[1]);
1695
1696         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1697                                qede_poll_sp_sb_cb,
1698                                (void *)eth_dev);
1699         if (rc != 0) {
1700                 DP_ERR(edev, "Unable to start periodic"
1701                              " timer rc %d\n", rc);
1702                 assert(false && "Unable to start periodic timer");
1703         }
1704 }
1705
1706 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1707 {
1708         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1709         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1710         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1711
1712         PMD_INIT_FUNC_TRACE(edev);
1713
1714         /* dev_stop() shall cleanup fp resources in hw but without releasing
1715          * dma memories and sw structures so that dev_start() can be called
1716          * by the app without reconfiguration. However, in dev_close() we
1717          * can release all the resources and device can be brought up newly
1718          */
1719         if (eth_dev->data->dev_started)
1720                 qede_dev_stop(eth_dev);
1721
1722         qede_stop_vport(edev);
1723         qdev->vport_started = false;
1724         qede_fdir_dealloc_resc(eth_dev);
1725         qede_dealloc_fp_resc(eth_dev);
1726
1727         eth_dev->data->nb_rx_queues = 0;
1728         eth_dev->data->nb_tx_queues = 0;
1729
1730         /* Bring the link down */
1731         qede_dev_set_link_state(eth_dev, false);
1732         qdev->ops->common->slowpath_stop(edev);
1733         qdev->ops->common->remove(edev);
1734         rte_intr_disable(&pci_dev->intr_handle);
1735
1736         switch (pci_dev->intr_handle.type) {
1737         case RTE_INTR_HANDLE_UIO_INTX:
1738         case RTE_INTR_HANDLE_VFIO_LEGACY:
1739                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1740                                              qede_interrupt_handler_intx,
1741                                              (void *)eth_dev);
1742                 break;
1743         default:
1744                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1745                                            qede_interrupt_handler,
1746                                            (void *)eth_dev);
1747         }
1748
1749         if (ECORE_IS_CMT(edev))
1750                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1751 }
1752
1753 static int
1754 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1755 {
1756         struct qede_dev *qdev = eth_dev->data->dev_private;
1757         struct ecore_dev *edev = &qdev->edev;
1758         struct ecore_eth_stats stats;
1759         unsigned int i = 0, j = 0, qid;
1760         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1761         struct qede_tx_queue *txq;
1762
1763         ecore_get_vport_stats(edev, &stats);
1764
1765         /* RX Stats */
1766         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1767             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1768
1769         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1770             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1771
1772         eth_stats->ierrors = stats.common.rx_crc_errors +
1773             stats.common.rx_align_errors +
1774             stats.common.rx_carrier_errors +
1775             stats.common.rx_oversize_packets +
1776             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1777
1778         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1779
1780         eth_stats->imissed = stats.common.mftag_filter_discards +
1781             stats.common.mac_filter_discards +
1782             stats.common.no_buff_discards +
1783             stats.common.brb_truncates + stats.common.brb_discards;
1784
1785         /* TX stats */
1786         eth_stats->opackets = stats.common.tx_ucast_pkts +
1787             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1788
1789         eth_stats->obytes = stats.common.tx_ucast_bytes +
1790             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1791
1792         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1793
1794         /* Queue stats */
1795         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1796                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1797         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1798                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1799         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1800             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1801                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1802                        "Not all the queue stats will be displayed. Set"
1803                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1804                        " appropriately and retry.\n");
1805
1806         for_each_rss(qid) {
1807                 eth_stats->q_ipackets[i] =
1808                         *(uint64_t *)(
1809                                 ((char *)(qdev->fp_array[qid].rxq)) +
1810                                 offsetof(struct qede_rx_queue,
1811                                 rcv_pkts));
1812                 eth_stats->q_errors[i] =
1813                         *(uint64_t *)(
1814                                 ((char *)(qdev->fp_array[qid].rxq)) +
1815                                 offsetof(struct qede_rx_queue,
1816                                 rx_hw_errors)) +
1817                         *(uint64_t *)(
1818                                 ((char *)(qdev->fp_array[qid].rxq)) +
1819                                 offsetof(struct qede_rx_queue,
1820                                 rx_alloc_errors));
1821                 i++;
1822                 if (i == rxq_stat_cntrs)
1823                         break;
1824         }
1825
1826         for_each_tss(qid) {
1827                 txq = qdev->fp_array[qid].txq;
1828                 eth_stats->q_opackets[j] =
1829                         *((uint64_t *)(uintptr_t)
1830                                 (((uint64_t)(uintptr_t)(txq)) +
1831                                  offsetof(struct qede_tx_queue,
1832                                           xmit_pkts)));
1833                 j++;
1834                 if (j == txq_stat_cntrs)
1835                         break;
1836         }
1837
1838         return 0;
1839 }
1840
1841 static unsigned
1842 qede_get_xstats_count(struct qede_dev *qdev) {
1843         if (ECORE_IS_BB(&qdev->edev))
1844                 return RTE_DIM(qede_xstats_strings) +
1845                        RTE_DIM(qede_bb_xstats_strings) +
1846                        (RTE_DIM(qede_rxq_xstats_strings) *
1847                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1848                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1849         else
1850                 return RTE_DIM(qede_xstats_strings) +
1851                        RTE_DIM(qede_ah_xstats_strings) +
1852                        (RTE_DIM(qede_rxq_xstats_strings) *
1853                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1854                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1855 }
1856
1857 static int
1858 qede_get_xstats_names(struct rte_eth_dev *dev,
1859                       struct rte_eth_xstat_name *xstats_names,
1860                       __rte_unused unsigned int limit)
1861 {
1862         struct qede_dev *qdev = dev->data->dev_private;
1863         struct ecore_dev *edev = &qdev->edev;
1864         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1865         unsigned int i, qid, stat_idx = 0;
1866         unsigned int rxq_stat_cntrs;
1867
1868         if (xstats_names != NULL) {
1869                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1870                         snprintf(xstats_names[stat_idx].name,
1871                                 sizeof(xstats_names[stat_idx].name),
1872                                 "%s",
1873                                 qede_xstats_strings[i].name);
1874                         stat_idx++;
1875                 }
1876
1877                 if (ECORE_IS_BB(edev)) {
1878                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1879                                 snprintf(xstats_names[stat_idx].name,
1880                                         sizeof(xstats_names[stat_idx].name),
1881                                         "%s",
1882                                         qede_bb_xstats_strings[i].name);
1883                                 stat_idx++;
1884                         }
1885                 } else {
1886                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1887                                 snprintf(xstats_names[stat_idx].name,
1888                                         sizeof(xstats_names[stat_idx].name),
1889                                         "%s",
1890                                         qede_ah_xstats_strings[i].name);
1891                                 stat_idx++;
1892                         }
1893                 }
1894
1895                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1896                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1897                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1898                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1899                                 snprintf(xstats_names[stat_idx].name,
1900                                         sizeof(xstats_names[stat_idx].name),
1901                                         "%.4s%d%s",
1902                                         qede_rxq_xstats_strings[i].name, qid,
1903                                         qede_rxq_xstats_strings[i].name + 4);
1904                                 stat_idx++;
1905                         }
1906                 }
1907         }
1908
1909         return stat_cnt;
1910 }
1911
1912 static int
1913 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1914                 unsigned int n)
1915 {
1916         struct qede_dev *qdev = dev->data->dev_private;
1917         struct ecore_dev *edev = &qdev->edev;
1918         struct ecore_eth_stats stats;
1919         const unsigned int num = qede_get_xstats_count(qdev);
1920         unsigned int i, qid, stat_idx = 0;
1921         unsigned int rxq_stat_cntrs;
1922
1923         if (n < num)
1924                 return num;
1925
1926         ecore_get_vport_stats(edev, &stats);
1927
1928         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1929                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1930                                              qede_xstats_strings[i].offset);
1931                 xstats[stat_idx].id = stat_idx;
1932                 stat_idx++;
1933         }
1934
1935         if (ECORE_IS_BB(edev)) {
1936                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1937                         xstats[stat_idx].value =
1938                                         *(uint64_t *)(((char *)&stats) +
1939                                         qede_bb_xstats_strings[i].offset);
1940                         xstats[stat_idx].id = stat_idx;
1941                         stat_idx++;
1942                 }
1943         } else {
1944                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1945                         xstats[stat_idx].value =
1946                                         *(uint64_t *)(((char *)&stats) +
1947                                         qede_ah_xstats_strings[i].offset);
1948                         xstats[stat_idx].id = stat_idx;
1949                         stat_idx++;
1950                 }
1951         }
1952
1953         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1954                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1955         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1956                 for_each_rss(qid) {
1957                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1958                                 xstats[stat_idx].value = *(uint64_t *)(
1959                                         ((char *)(qdev->fp_array[qid].rxq)) +
1960                                          qede_rxq_xstats_strings[i].offset);
1961                                 xstats[stat_idx].id = stat_idx;
1962                                 stat_idx++;
1963                         }
1964                 }
1965         }
1966
1967         return stat_idx;
1968 }
1969
1970 static void
1971 qede_reset_xstats(struct rte_eth_dev *dev)
1972 {
1973         struct qede_dev *qdev = dev->data->dev_private;
1974         struct ecore_dev *edev = &qdev->edev;
1975
1976         ecore_reset_vport_stats(edev);
1977         qede_reset_queue_stats(qdev, true);
1978 }
1979
1980 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1981 {
1982         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1983         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1984         struct qed_link_params link_params;
1985         int rc;
1986
1987         DP_INFO(edev, "setting link state %d\n", link_up);
1988         memset(&link_params, 0, sizeof(link_params));
1989         link_params.link_up = link_up;
1990         rc = qdev->ops->common->set_link(edev, &link_params);
1991         if (rc != ECORE_SUCCESS)
1992                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1993
1994         return rc;
1995 }
1996
1997 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1998 {
1999         return qede_dev_set_link_state(eth_dev, true);
2000 }
2001
2002 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
2003 {
2004         return qede_dev_set_link_state(eth_dev, false);
2005 }
2006
2007 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
2008 {
2009         struct qede_dev *qdev = eth_dev->data->dev_private;
2010         struct ecore_dev *edev = &qdev->edev;
2011
2012         ecore_reset_vport_stats(edev);
2013         qede_reset_queue_stats(qdev, false);
2014 }
2015
2016 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
2017 {
2018         enum qed_filter_rx_mode_type type =
2019             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
2020
2021         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2022                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
2023
2024         qed_configure_filter_rx_mode(eth_dev, type);
2025 }
2026
2027 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
2028 {
2029         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2030                 qed_configure_filter_rx_mode(eth_dev,
2031                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
2032         else
2033                 qed_configure_filter_rx_mode(eth_dev,
2034                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
2035 }
2036
2037 static int
2038 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
2039                       uint32_t mc_addrs_num)
2040 {
2041         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2042         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2043         uint8_t i;
2044
2045         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
2046                 DP_ERR(edev, "Reached max multicast filters limit,"
2047                              "Please enable multicast promisc mode\n");
2048                 return -ENOSPC;
2049         }
2050
2051         for (i = 0; i < mc_addrs_num; i++) {
2052                 if (!is_multicast_ether_addr(&mc_addrs[i])) {
2053                         DP_ERR(edev, "Not a valid multicast MAC\n");
2054                         return -EINVAL;
2055                 }
2056         }
2057
2058         /* Flush all existing entries */
2059         if (qede_del_mcast_filters(eth_dev))
2060                 return -1;
2061
2062         /* Set new mcast list */
2063         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
2064 }
2065
2066 /* Update MTU via vport-update without doing port restart.
2067  * The vport must be deactivated before calling this API.
2068  */
2069 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
2070 {
2071         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2072         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2073         struct ecore_hwfn *p_hwfn;
2074         int rc;
2075         int i;
2076
2077         if (IS_PF(edev)) {
2078                 struct ecore_sp_vport_update_params params;
2079
2080                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
2081                 params.vport_id = 0;
2082                 params.mtu = mtu;
2083                 params.vport_id = 0;
2084                 for_each_hwfn(edev, i) {
2085                         p_hwfn = &edev->hwfns[i];
2086                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2087                         rc = ecore_sp_vport_update(p_hwfn, &params,
2088                                         ECORE_SPQ_MODE_EBLOCK, NULL);
2089                         if (rc != ECORE_SUCCESS)
2090                                 goto err;
2091                 }
2092         } else {
2093                 for_each_hwfn(edev, i) {
2094                         p_hwfn = &edev->hwfns[i];
2095                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
2096                         if (rc == ECORE_INVAL) {
2097                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
2098                                 /* Recreate vport */
2099                                 rc = qede_start_vport(qdev, mtu);
2100                                 if (rc != ECORE_SUCCESS)
2101                                         goto err;
2102
2103                                 /* Restore config lost due to vport stop */
2104                                 if (eth_dev->data->promiscuous)
2105                                         qede_promiscuous_enable(eth_dev);
2106                                 else
2107                                         qede_promiscuous_disable(eth_dev);
2108
2109                                 if (eth_dev->data->all_multicast)
2110                                         qede_allmulticast_enable(eth_dev);
2111                                 else
2112                                         qede_allmulticast_disable(eth_dev);
2113
2114                                 qede_vlan_offload_set(eth_dev,
2115                                                       qdev->vlan_offload_mask);
2116                         } else if (rc != ECORE_SUCCESS) {
2117                                 goto err;
2118                         }
2119                 }
2120         }
2121         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
2122
2123         return 0;
2124
2125 err:
2126         DP_ERR(edev, "Failed to update MTU\n");
2127         return -1;
2128 }
2129
2130 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2131                               struct rte_eth_fc_conf *fc_conf)
2132 {
2133         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2134         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2135         struct qed_link_output current_link;
2136         struct qed_link_params params;
2137
2138         memset(&current_link, 0, sizeof(current_link));
2139         qdev->ops->common->get_link(edev, &current_link);
2140
2141         memset(&params, 0, sizeof(params));
2142         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2143         if (fc_conf->autoneg) {
2144                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2145                         DP_ERR(edev, "Autoneg not supported\n");
2146                         return -EINVAL;
2147                 }
2148                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2149         }
2150
2151         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2152         if (fc_conf->mode == RTE_FC_FULL)
2153                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2154                                         QED_LINK_PAUSE_RX_ENABLE);
2155         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2156                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2157         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2158                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2159
2160         params.link_up = true;
2161         (void)qdev->ops->common->set_link(edev, &params);
2162
2163         return 0;
2164 }
2165
2166 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2167                               struct rte_eth_fc_conf *fc_conf)
2168 {
2169         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2170         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2171         struct qed_link_output current_link;
2172
2173         memset(&current_link, 0, sizeof(current_link));
2174         qdev->ops->common->get_link(edev, &current_link);
2175
2176         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2177                 fc_conf->autoneg = true;
2178
2179         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2180                                          QED_LINK_PAUSE_TX_ENABLE))
2181                 fc_conf->mode = RTE_FC_FULL;
2182         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2183                 fc_conf->mode = RTE_FC_RX_PAUSE;
2184         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2185                 fc_conf->mode = RTE_FC_TX_PAUSE;
2186         else
2187                 fc_conf->mode = RTE_FC_NONE;
2188
2189         return 0;
2190 }
2191
2192 static const uint32_t *
2193 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2194 {
2195         static const uint32_t ptypes[] = {
2196                 RTE_PTYPE_L2_ETHER,
2197                 RTE_PTYPE_L2_ETHER_VLAN,
2198                 RTE_PTYPE_L3_IPV4,
2199                 RTE_PTYPE_L3_IPV6,
2200                 RTE_PTYPE_L4_TCP,
2201                 RTE_PTYPE_L4_UDP,
2202                 RTE_PTYPE_TUNNEL_VXLAN,
2203                 RTE_PTYPE_L4_FRAG,
2204                 RTE_PTYPE_TUNNEL_GENEVE,
2205                 RTE_PTYPE_TUNNEL_GRE,
2206                 /* Inner */
2207                 RTE_PTYPE_INNER_L2_ETHER,
2208                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2209                 RTE_PTYPE_INNER_L3_IPV4,
2210                 RTE_PTYPE_INNER_L3_IPV6,
2211                 RTE_PTYPE_INNER_L4_TCP,
2212                 RTE_PTYPE_INNER_L4_UDP,
2213                 RTE_PTYPE_INNER_L4_FRAG,
2214                 RTE_PTYPE_UNKNOWN
2215         };
2216
2217         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2218                 return ptypes;
2219
2220         return NULL;
2221 }
2222
2223 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2224 {
2225         *rss_caps = 0;
2226         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2227         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2228         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2229         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2230         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2231         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2232         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2233         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2234 }
2235
2236 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2237                          struct rte_eth_rss_conf *rss_conf)
2238 {
2239         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2240         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2241         struct ecore_sp_vport_update_params vport_update_params;
2242         struct ecore_rss_params rss_params;
2243         struct ecore_hwfn *p_hwfn;
2244         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2245         uint64_t hf = rss_conf->rss_hf;
2246         uint8_t len = rss_conf->rss_key_len;
2247         uint8_t idx;
2248         uint8_t i;
2249         int rc;
2250
2251         memset(&vport_update_params, 0, sizeof(vport_update_params));
2252         memset(&rss_params, 0, sizeof(rss_params));
2253
2254         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2255                 (unsigned long)hf, len, key);
2256
2257         if (hf != 0) {
2258                 /* Enabling RSS */
2259                 DP_INFO(edev, "Enabling rss\n");
2260
2261                 /* RSS caps */
2262                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2263                 rss_params.update_rss_capabilities = 1;
2264
2265                 /* RSS hash key */
2266                 if (key) {
2267                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2268                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2269                                 return -EINVAL;
2270                         }
2271                         DP_INFO(edev, "Applying user supplied hash key\n");
2272                         rss_params.update_rss_key = 1;
2273                         memcpy(&rss_params.rss_key, key, len);
2274                 }
2275                 rss_params.rss_enable = 1;
2276         }
2277
2278         rss_params.update_rss_config = 1;
2279         /* tbl_size has to be set with capabilities */
2280         rss_params.rss_table_size_log = 7;
2281         vport_update_params.vport_id = 0;
2282         /* pass the L2 handles instead of qids */
2283         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2284                 idx = i % QEDE_RSS_COUNT(qdev);
2285                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2286         }
2287         vport_update_params.rss_params = &rss_params;
2288
2289         for_each_hwfn(edev, i) {
2290                 p_hwfn = &edev->hwfns[i];
2291                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2292                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2293                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2294                 if (rc) {
2295                         DP_ERR(edev, "vport-update for RSS failed\n");
2296                         return rc;
2297                 }
2298         }
2299         qdev->rss_enable = rss_params.rss_enable;
2300
2301         /* Update local structure for hash query */
2302         qdev->rss_conf.rss_hf = hf;
2303         qdev->rss_conf.rss_key_len = len;
2304         if (qdev->rss_enable) {
2305                 if  (qdev->rss_conf.rss_key == NULL) {
2306                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2307                         if (qdev->rss_conf.rss_key == NULL) {
2308                                 DP_ERR(edev, "No memory to store RSS key\n");
2309                                 return -ENOMEM;
2310                         }
2311                 }
2312                 if (key && len) {
2313                         DP_INFO(edev, "Storing RSS key\n");
2314                         memcpy(qdev->rss_conf.rss_key, key, len);
2315                 }
2316         } else if (!qdev->rss_enable && len == 0) {
2317                 if (qdev->rss_conf.rss_key) {
2318                         free(qdev->rss_conf.rss_key);
2319                         qdev->rss_conf.rss_key = NULL;
2320                         DP_INFO(edev, "Free RSS key\n");
2321                 }
2322         }
2323
2324         return 0;
2325 }
2326
2327 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2328                            struct rte_eth_rss_conf *rss_conf)
2329 {
2330         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2331
2332         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2333         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2334
2335         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2336                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2337                        rss_conf->rss_key_len);
2338         return 0;
2339 }
2340
2341 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2342                                     struct ecore_rss_params *rss)
2343 {
2344         int i, fn;
2345         bool rss_mode = 1; /* enable */
2346         struct ecore_queue_cid *cid;
2347         struct ecore_rss_params *t_rss;
2348
2349         /* In regular scenario, we'd simply need to take input handlers.
2350          * But in CMT, we'd have to split the handlers according to the
2351          * engine they were configured on. We'd then have to understand
2352          * whether RSS is really required, since 2-queues on CMT doesn't
2353          * require RSS.
2354          */
2355
2356         /* CMT should be round-robin */
2357         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2358                 cid = rss->rss_ind_table[i];
2359
2360                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2361                         t_rss = &rss[0];
2362                 else
2363                         t_rss = &rss[1];
2364
2365                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2366         }
2367
2368         t_rss = &rss[1];
2369         t_rss->update_rss_ind_table = 1;
2370         t_rss->rss_table_size_log = 7;
2371         t_rss->update_rss_config = 1;
2372
2373         /* Make sure RSS is actually required */
2374         for_each_hwfn(edev, fn) {
2375                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2376                      i++) {
2377                         if (rss[fn].rss_ind_table[i] !=
2378                             rss[fn].rss_ind_table[0])
2379                                 break;
2380                 }
2381
2382                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2383                         DP_INFO(edev,
2384                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2385                         rss_mode = 0;
2386                         goto out;
2387                 }
2388         }
2389
2390 out:
2391         t_rss->rss_enable = rss_mode;
2392
2393         return rss_mode;
2394 }
2395
2396 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2397                          struct rte_eth_rss_reta_entry64 *reta_conf,
2398                          uint16_t reta_size)
2399 {
2400         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2401         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2402         struct ecore_sp_vport_update_params vport_update_params;
2403         struct ecore_rss_params *params;
2404         struct ecore_hwfn *p_hwfn;
2405         uint16_t i, idx, shift;
2406         uint8_t entry;
2407         int rc = 0;
2408
2409         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2410                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2411                        reta_size);
2412                 return -EINVAL;
2413         }
2414
2415         memset(&vport_update_params, 0, sizeof(vport_update_params));
2416         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2417                              RTE_CACHE_LINE_SIZE);
2418         if (params == NULL) {
2419                 DP_ERR(edev, "failed to allocate memory\n");
2420                 return -ENOMEM;
2421         }
2422
2423         for (i = 0; i < reta_size; i++) {
2424                 idx = i / RTE_RETA_GROUP_SIZE;
2425                 shift = i % RTE_RETA_GROUP_SIZE;
2426                 if (reta_conf[idx].mask & (1ULL << shift)) {
2427                         entry = reta_conf[idx].reta[shift];
2428                         /* Pass rxq handles to ecore */
2429                         params->rss_ind_table[i] =
2430                                         qdev->fp_array[entry].rxq->handle;
2431                         /* Update the local copy for RETA query command */
2432                         qdev->rss_ind_table[i] = entry;
2433                 }
2434         }
2435
2436         params->update_rss_ind_table = 1;
2437         params->rss_table_size_log = 7;
2438         params->update_rss_config = 1;
2439
2440         /* Fix up RETA for CMT mode device */
2441         if (ECORE_IS_CMT(edev))
2442                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2443                                                             params);
2444         vport_update_params.vport_id = 0;
2445         /* Use the current value of rss_enable */
2446         params->rss_enable = qdev->rss_enable;
2447         vport_update_params.rss_params = params;
2448
2449         for_each_hwfn(edev, i) {
2450                 p_hwfn = &edev->hwfns[i];
2451                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2452                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2453                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2454                 if (rc) {
2455                         DP_ERR(edev, "vport-update for RSS failed\n");
2456                         goto out;
2457                 }
2458         }
2459
2460 out:
2461         rte_free(params);
2462         return rc;
2463 }
2464
2465 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2466                                struct rte_eth_rss_reta_entry64 *reta_conf,
2467                                uint16_t reta_size)
2468 {
2469         struct qede_dev *qdev = eth_dev->data->dev_private;
2470         struct ecore_dev *edev = &qdev->edev;
2471         uint16_t i, idx, shift;
2472         uint8_t entry;
2473
2474         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2475                 DP_ERR(edev, "reta_size %d is not supported\n",
2476                        reta_size);
2477                 return -EINVAL;
2478         }
2479
2480         for (i = 0; i < reta_size; i++) {
2481                 idx = i / RTE_RETA_GROUP_SIZE;
2482                 shift = i % RTE_RETA_GROUP_SIZE;
2483                 if (reta_conf[idx].mask & (1ULL << shift)) {
2484                         entry = qdev->rss_ind_table[i];
2485                         reta_conf[idx].reta[shift] = entry;
2486                 }
2487         }
2488
2489         return 0;
2490 }
2491
2492
2493
2494 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2495 {
2496         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2497         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2498         struct rte_eth_dev_info dev_info = {0};
2499         struct qede_fastpath *fp;
2500         uint32_t max_rx_pkt_len;
2501         uint32_t frame_size;
2502         uint16_t rx_buf_size;
2503         uint16_t bufsz;
2504         bool restart = false;
2505         int i;
2506
2507         PMD_INIT_FUNC_TRACE(edev);
2508         qede_dev_info_get(dev, &dev_info);
2509         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2510         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2511         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2512                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2513                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2514                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2515                 return -EINVAL;
2516         }
2517         if (!dev->data->scattered_rx &&
2518             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2519                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2520                         dev->data->min_rx_buf_size);
2521                 return -EINVAL;
2522         }
2523         /* Temporarily replace I/O functions with dummy ones. It cannot
2524          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2525          */
2526         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2527         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2528         if (dev->data->dev_started) {
2529                 dev->data->dev_started = 0;
2530                 qede_dev_stop(dev);
2531                 restart = true;
2532         }
2533         rte_delay_ms(1000);
2534         qdev->mtu = mtu;
2535
2536         /* Fix up RX buf size for all queues of the port */
2537         for_each_rss(i) {
2538                 fp = &qdev->fp_array[i];
2539                 if (fp->rxq != NULL) {
2540                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2541                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2542                         if (dev->data->scattered_rx)
2543                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
2544                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2545                         else
2546                                 rx_buf_size = frame_size;
2547                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2548                         fp->rxq->rx_buf_size = rx_buf_size;
2549                         DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2550                 }
2551         }
2552         if (max_rx_pkt_len > ETHER_MAX_LEN)
2553                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2554         else
2555                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2556
2557         if (!dev->data->dev_started && restart) {
2558                 qede_dev_start(dev);
2559                 dev->data->dev_started = 1;
2560         }
2561
2562         /* update max frame size */
2563         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2564         /* Reassign back */
2565         dev->rx_pkt_burst = qede_recv_pkts;
2566         dev->tx_pkt_burst = qede_xmit_pkts;
2567
2568         return 0;
2569 }
2570
2571 static int
2572 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2573                       struct rte_eth_udp_tunnel *tunnel_udp)
2574 {
2575         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2576         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2577         struct ecore_tunnel_info tunn; /* @DPDK */
2578         uint16_t udp_port;
2579         int rc;
2580
2581         PMD_INIT_FUNC_TRACE(edev);
2582
2583         memset(&tunn, 0, sizeof(tunn));
2584
2585         switch (tunnel_udp->prot_type) {
2586         case RTE_TUNNEL_TYPE_VXLAN:
2587                 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2588                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2589                                 tunnel_udp->udp_port);
2590                         return ECORE_INVAL;
2591                 }
2592                 udp_port = 0;
2593
2594                 tunn.vxlan_port.b_update_port = true;
2595                 tunn.vxlan_port.port = udp_port;
2596
2597                 rc = qede_tunnel_update(qdev, &tunn);
2598                 if (rc != ECORE_SUCCESS) {
2599                         DP_ERR(edev, "Unable to config UDP port %u\n",
2600                                tunn.vxlan_port.port);
2601                         return rc;
2602                 }
2603
2604                 qdev->vxlan.udp_port = udp_port;
2605                 /* If the request is to delete UDP port and if the number of
2606                  * VXLAN filters have reached 0 then VxLAN offload can be be
2607                  * disabled.
2608                  */
2609                 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2610                         return qede_vxlan_enable(eth_dev,
2611                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2612
2613                 break;
2614         case RTE_TUNNEL_TYPE_GENEVE:
2615                 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2616                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2617                                 tunnel_udp->udp_port);
2618                         return ECORE_INVAL;
2619                 }
2620
2621                 udp_port = 0;
2622
2623                 tunn.geneve_port.b_update_port = true;
2624                 tunn.geneve_port.port = udp_port;
2625
2626                 rc = qede_tunnel_update(qdev, &tunn);
2627                 if (rc != ECORE_SUCCESS) {
2628                         DP_ERR(edev, "Unable to config UDP port %u\n",
2629                                tunn.vxlan_port.port);
2630                         return rc;
2631                 }
2632
2633                 qdev->vxlan.udp_port = udp_port;
2634                 /* If the request is to delete UDP port and if the number of
2635                  * GENEVE filters have reached 0 then GENEVE offload can be be
2636                  * disabled.
2637                  */
2638                 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2639                         return qede_geneve_enable(eth_dev,
2640                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2641
2642                 break;
2643
2644         default:
2645                 return ECORE_INVAL;
2646         }
2647
2648         return 0;
2649
2650 }
2651 static int
2652 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2653                       struct rte_eth_udp_tunnel *tunnel_udp)
2654 {
2655         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2656         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2657         struct ecore_tunnel_info tunn; /* @DPDK */
2658         uint16_t udp_port;
2659         int rc;
2660
2661         PMD_INIT_FUNC_TRACE(edev);
2662
2663         memset(&tunn, 0, sizeof(tunn));
2664
2665         switch (tunnel_udp->prot_type) {
2666         case RTE_TUNNEL_TYPE_VXLAN:
2667                 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2668                         DP_INFO(edev,
2669                                 "UDP port %u for VXLAN was already configured\n",
2670                                 tunnel_udp->udp_port);
2671                         return ECORE_SUCCESS;
2672                 }
2673
2674                 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2675                  * it was not enabled while adding VXLAN filter before UDP port
2676                  * update.
2677                  */
2678                 if (!qdev->vxlan.enable) {
2679                         rc = qede_vxlan_enable(eth_dev,
2680                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2681                         if (rc != ECORE_SUCCESS) {
2682                                 DP_ERR(edev, "Failed to enable VXLAN "
2683                                         "prior to updating UDP port\n");
2684                                 return rc;
2685                         }
2686                 }
2687                 udp_port = tunnel_udp->udp_port;
2688
2689                 tunn.vxlan_port.b_update_port = true;
2690                 tunn.vxlan_port.port = udp_port;
2691
2692                 rc = qede_tunnel_update(qdev, &tunn);
2693                 if (rc != ECORE_SUCCESS) {
2694                         DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2695                                udp_port);
2696                         return rc;
2697                 }
2698
2699                 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2700
2701                 qdev->vxlan.udp_port = udp_port;
2702                 break;
2703         case RTE_TUNNEL_TYPE_GENEVE:
2704                 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2705                         DP_INFO(edev,
2706                                 "UDP port %u for GENEVE was already configured\n",
2707                                 tunnel_udp->udp_port);
2708                         return ECORE_SUCCESS;
2709                 }
2710
2711                 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2712                  * it was not enabled while adding GENEVE filter before UDP port
2713                  * update.
2714                  */
2715                 if (!qdev->geneve.enable) {
2716                         rc = qede_geneve_enable(eth_dev,
2717                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2718                         if (rc != ECORE_SUCCESS) {
2719                                 DP_ERR(edev, "Failed to enable GENEVE "
2720                                         "prior to updating UDP port\n");
2721                                 return rc;
2722                         }
2723                 }
2724                 udp_port = tunnel_udp->udp_port;
2725
2726                 tunn.geneve_port.b_update_port = true;
2727                 tunn.geneve_port.port = udp_port;
2728
2729                 rc = qede_tunnel_update(qdev, &tunn);
2730                 if (rc != ECORE_SUCCESS) {
2731                         DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2732                                udp_port);
2733                         return rc;
2734                 }
2735
2736                 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2737
2738                 qdev->geneve.udp_port = udp_port;
2739                 break;
2740         default:
2741                 return ECORE_INVAL;
2742         }
2743
2744         return 0;
2745 }
2746
2747 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2748                                        uint32_t *clss, char *str)
2749 {
2750         uint16_t j;
2751         *clss = MAX_ECORE_TUNN_CLSS;
2752
2753         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2754                 if (filter == qede_tunn_types[j].rte_filter_type) {
2755                         *type = qede_tunn_types[j].qede_type;
2756                         *clss = qede_tunn_types[j].qede_tunn_clss;
2757                         strcpy(str, qede_tunn_types[j].string);
2758                         return;
2759                 }
2760         }
2761 }
2762
2763 static int
2764 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2765                               const struct rte_eth_tunnel_filter_conf *conf,
2766                               uint32_t type)
2767 {
2768         /* Init commmon ucast params first */
2769         qede_set_ucast_cmn_params(ucast);
2770
2771         /* Copy out the required fields based on classification type */
2772         ucast->type = type;
2773
2774         switch (type) {
2775         case ECORE_FILTER_VNI:
2776                 ucast->vni = conf->tenant_id;
2777         break;
2778         case ECORE_FILTER_INNER_VLAN:
2779                 ucast->vlan = conf->inner_vlan;
2780         break;
2781         case ECORE_FILTER_MAC:
2782                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2783                        ETHER_ADDR_LEN);
2784         break;
2785         case ECORE_FILTER_INNER_MAC:
2786                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2787                        ETHER_ADDR_LEN);
2788         break;
2789         case ECORE_FILTER_MAC_VNI_PAIR:
2790                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2791                         ETHER_ADDR_LEN);
2792                 ucast->vni = conf->tenant_id;
2793         break;
2794         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2795                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2796                         ETHER_ADDR_LEN);
2797                 ucast->vni = conf->tenant_id;
2798         break;
2799         case ECORE_FILTER_INNER_PAIR:
2800                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2801                         ETHER_ADDR_LEN);
2802                 ucast->vlan = conf->inner_vlan;
2803         break;
2804         default:
2805                 return -EINVAL;
2806         }
2807
2808         return ECORE_SUCCESS;
2809 }
2810
2811 static int
2812 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2813                          const struct rte_eth_tunnel_filter_conf *conf,
2814                          __attribute__((unused)) enum rte_filter_op filter_op,
2815                          enum ecore_tunn_clss *clss,
2816                          bool add)
2817 {
2818         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2819         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2820         struct ecore_filter_ucast ucast = {0};
2821         enum ecore_filter_ucast_type type;
2822         uint16_t filter_type = 0;
2823         char str[80];
2824         int rc;
2825
2826         filter_type = conf->filter_type;
2827         /* Determine if the given filter classification is supported */
2828         qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2829         if (*clss == MAX_ECORE_TUNN_CLSS) {
2830                 DP_ERR(edev, "Unsupported filter type\n");
2831                 return -EINVAL;
2832         }
2833         /* Init tunnel ucast params */
2834         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2835         if (rc != ECORE_SUCCESS) {
2836                 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2837                 conf->filter_type);
2838                 return rc;
2839         }
2840         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2841                 str, filter_op, ucast.type);
2842
2843         ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2844
2845         /* Skip MAC/VLAN if filter is based on VNI */
2846         if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2847                 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2848                 if ((rc == 0) && add) {
2849                         /* Enable accept anyvlan */
2850                         qede_config_accept_any_vlan(qdev, true);
2851                 }
2852         } else {
2853                 rc = qede_ucast_filter(eth_dev, &ucast, add);
2854                 if (rc == 0)
2855                         rc = ecore_filter_ucast_cmd(edev, &ucast,
2856                                             ECORE_SPQ_MODE_CB, NULL);
2857         }
2858
2859         return rc;
2860 }
2861
2862 static int
2863 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2864                         enum rte_filter_op filter_op,
2865                         const struct rte_eth_tunnel_filter_conf *conf)
2866 {
2867         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2868         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2869         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2870         bool add;
2871         int rc;
2872
2873         PMD_INIT_FUNC_TRACE(edev);
2874
2875         switch (filter_op) {
2876         case RTE_ETH_FILTER_ADD:
2877                 add = true;
2878                 break;
2879         case RTE_ETH_FILTER_DELETE:
2880                 add = false;
2881                 break;
2882         default:
2883                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2884                 return -EINVAL;
2885         }
2886
2887         if (IS_VF(edev))
2888                 return qede_tunn_enable(eth_dev,
2889                                         ECORE_TUNN_CLSS_MAC_VLAN,
2890                                         conf->tunnel_type, add);
2891
2892         rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2893         if (rc != ECORE_SUCCESS)
2894                 return rc;
2895
2896         if (add) {
2897                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2898                         qdev->vxlan.num_filters++;
2899                         qdev->vxlan.filter_type = conf->filter_type;
2900                 } else { /* GENEVE */
2901                         qdev->geneve.num_filters++;
2902                         qdev->geneve.filter_type = conf->filter_type;
2903                 }
2904
2905                 if (!qdev->vxlan.enable || !qdev->geneve.enable ||
2906                     !qdev->ipgre.enable)
2907                         return qede_tunn_enable(eth_dev, clss,
2908                                                 conf->tunnel_type,
2909                                                 true);
2910         } else {
2911                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2912                         qdev->vxlan.num_filters--;
2913                 else /*GENEVE*/
2914                         qdev->geneve.num_filters--;
2915
2916                 /* Disable VXLAN if VXLAN filters become 0 */
2917                 if ((qdev->vxlan.num_filters == 0) ||
2918                     (qdev->geneve.num_filters == 0))
2919                         return qede_tunn_enable(eth_dev, clss,
2920                                                 conf->tunnel_type,
2921                                                 false);
2922         }
2923
2924         return 0;
2925 }
2926
2927 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2928                          enum rte_filter_type filter_type,
2929                          enum rte_filter_op filter_op,
2930                          void *arg)
2931 {
2932         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2933         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2934         struct rte_eth_tunnel_filter_conf *filter_conf =
2935                         (struct rte_eth_tunnel_filter_conf *)arg;
2936
2937         switch (filter_type) {
2938         case RTE_ETH_FILTER_TUNNEL:
2939                 switch (filter_conf->tunnel_type) {
2940                 case RTE_TUNNEL_TYPE_VXLAN:
2941                 case RTE_TUNNEL_TYPE_GENEVE:
2942                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2943                         DP_INFO(edev,
2944                                 "Packet steering to the specified Rx queue"
2945                                 " is not supported with UDP tunneling");
2946                         return(qede_tunn_filter_config(eth_dev, filter_op,
2947                                                       filter_conf));
2948                 case RTE_TUNNEL_TYPE_TEREDO:
2949                 case RTE_TUNNEL_TYPE_NVGRE:
2950                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2951                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2952                                 filter_conf->tunnel_type);
2953                         return -EINVAL;
2954                 case RTE_TUNNEL_TYPE_NONE:
2955                 default:
2956                         return 0;
2957                 }
2958                 break;
2959         case RTE_ETH_FILTER_FDIR:
2960                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2961         case RTE_ETH_FILTER_NTUPLE:
2962                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2963         case RTE_ETH_FILTER_MACVLAN:
2964         case RTE_ETH_FILTER_ETHERTYPE:
2965         case RTE_ETH_FILTER_FLEXIBLE:
2966         case RTE_ETH_FILTER_SYN:
2967         case RTE_ETH_FILTER_HASH:
2968         case RTE_ETH_FILTER_L2_TUNNEL:
2969         case RTE_ETH_FILTER_MAX:
2970         default:
2971                 DP_ERR(edev, "Unsupported filter type %d\n",
2972                         filter_type);
2973                 return -EINVAL;
2974         }
2975
2976         return 0;
2977 }
2978
2979 static const struct eth_dev_ops qede_eth_dev_ops = {
2980         .dev_configure = qede_dev_configure,
2981         .dev_infos_get = qede_dev_info_get,
2982         .rx_queue_setup = qede_rx_queue_setup,
2983         .rx_queue_release = qede_rx_queue_release,
2984         .tx_queue_setup = qede_tx_queue_setup,
2985         .tx_queue_release = qede_tx_queue_release,
2986         .dev_start = qede_dev_start,
2987         .dev_set_link_up = qede_dev_set_link_up,
2988         .dev_set_link_down = qede_dev_set_link_down,
2989         .link_update = qede_link_update,
2990         .promiscuous_enable = qede_promiscuous_enable,
2991         .promiscuous_disable = qede_promiscuous_disable,
2992         .allmulticast_enable = qede_allmulticast_enable,
2993         .allmulticast_disable = qede_allmulticast_disable,
2994         .set_mc_addr_list = qede_set_mc_addr_list,
2995         .dev_stop = qede_dev_stop,
2996         .dev_close = qede_dev_close,
2997         .stats_get = qede_get_stats,
2998         .stats_reset = qede_reset_stats,
2999         .xstats_get = qede_get_xstats,
3000         .xstats_reset = qede_reset_xstats,
3001         .xstats_get_names = qede_get_xstats_names,
3002         .mac_addr_add = qede_mac_addr_add,
3003         .mac_addr_remove = qede_mac_addr_remove,
3004         .mac_addr_set = qede_mac_addr_set,
3005         .vlan_offload_set = qede_vlan_offload_set,
3006         .vlan_filter_set = qede_vlan_filter_set,
3007         .flow_ctrl_set = qede_flow_ctrl_set,
3008         .flow_ctrl_get = qede_flow_ctrl_get,
3009         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
3010         .rss_hash_update = qede_rss_hash_update,
3011         .rss_hash_conf_get = qede_rss_hash_conf_get,
3012         .reta_update  = qede_rss_reta_update,
3013         .reta_query  = qede_rss_reta_query,
3014         .mtu_set = qede_set_mtu,
3015         .filter_ctrl = qede_dev_filter_ctrl,
3016         .udp_tunnel_port_add = qede_udp_dst_port_add,
3017         .udp_tunnel_port_del = qede_udp_dst_port_del,
3018 };
3019
3020 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
3021         .dev_configure = qede_dev_configure,
3022         .dev_infos_get = qede_dev_info_get,
3023         .rx_queue_setup = qede_rx_queue_setup,
3024         .rx_queue_release = qede_rx_queue_release,
3025         .tx_queue_setup = qede_tx_queue_setup,
3026         .tx_queue_release = qede_tx_queue_release,
3027         .dev_start = qede_dev_start,
3028         .dev_set_link_up = qede_dev_set_link_up,
3029         .dev_set_link_down = qede_dev_set_link_down,
3030         .link_update = qede_link_update,
3031         .promiscuous_enable = qede_promiscuous_enable,
3032         .promiscuous_disable = qede_promiscuous_disable,
3033         .allmulticast_enable = qede_allmulticast_enable,
3034         .allmulticast_disable = qede_allmulticast_disable,
3035         .set_mc_addr_list = qede_set_mc_addr_list,
3036         .dev_stop = qede_dev_stop,
3037         .dev_close = qede_dev_close,
3038         .stats_get = qede_get_stats,
3039         .stats_reset = qede_reset_stats,
3040         .xstats_get = qede_get_xstats,
3041         .xstats_reset = qede_reset_xstats,
3042         .xstats_get_names = qede_get_xstats_names,
3043         .vlan_offload_set = qede_vlan_offload_set,
3044         .vlan_filter_set = qede_vlan_filter_set,
3045         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
3046         .rss_hash_update = qede_rss_hash_update,
3047         .rss_hash_conf_get = qede_rss_hash_conf_get,
3048         .reta_update  = qede_rss_reta_update,
3049         .reta_query  = qede_rss_reta_query,
3050         .mtu_set = qede_set_mtu,
3051         .udp_tunnel_port_add = qede_udp_dst_port_add,
3052         .udp_tunnel_port_del = qede_udp_dst_port_del,
3053         .mac_addr_add = qede_mac_addr_add,
3054         .mac_addr_remove = qede_mac_addr_remove,
3055         .mac_addr_set = qede_mac_addr_set,
3056 };
3057
3058 static void qede_update_pf_params(struct ecore_dev *edev)
3059 {
3060         struct ecore_pf_params pf_params;
3061
3062         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
3063         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
3064         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
3065         qed_ops->common->update_pf_params(edev, &pf_params);
3066 }
3067
3068 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
3069 {
3070         struct rte_pci_device *pci_dev;
3071         struct rte_pci_addr pci_addr;
3072         struct qede_dev *adapter;
3073         struct ecore_dev *edev;
3074         struct qed_dev_eth_info dev_info;
3075         struct qed_slowpath_params params;
3076         static bool do_once = true;
3077         uint8_t bulletin_change;
3078         uint8_t vf_mac[ETHER_ADDR_LEN];
3079         uint8_t is_mac_forced;
3080         bool is_mac_exist;
3081         /* Fix up ecore debug level */
3082         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
3083         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
3084         uint32_t int_mode;
3085         int rc;
3086
3087         /* Extract key data structures */
3088         adapter = eth_dev->data->dev_private;
3089         adapter->ethdev = eth_dev;
3090         edev = &adapter->edev;
3091         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3092         pci_addr = pci_dev->addr;
3093
3094         PMD_INIT_FUNC_TRACE(edev);
3095
3096         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
3097                  pci_addr.bus, pci_addr.devid, pci_addr.function,
3098                  eth_dev->data->port_id);
3099
3100         eth_dev->rx_pkt_burst = qede_recv_pkts;
3101         eth_dev->tx_pkt_burst = qede_xmit_pkts;
3102         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
3103
3104         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3105                 DP_ERR(edev, "Skipping device init from secondary process\n");
3106                 return 0;
3107         }
3108
3109         rte_eth_copy_pci_info(eth_dev, pci_dev);
3110
3111         /* @DPDK */
3112         edev->vendor_id = pci_dev->id.vendor_id;
3113         edev->device_id = pci_dev->id.device_id;
3114
3115         qed_ops = qed_get_eth_ops();
3116         if (!qed_ops) {
3117                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3118                 return -EINVAL;
3119         }
3120
3121         DP_INFO(edev, "Starting qede probe\n");
3122         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3123                                     dp_level, is_vf);
3124         if (rc != 0) {
3125                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3126                 return -ENODEV;
3127         }
3128         qede_update_pf_params(edev);
3129
3130         switch (pci_dev->intr_handle.type) {
3131         case RTE_INTR_HANDLE_UIO_INTX:
3132         case RTE_INTR_HANDLE_VFIO_LEGACY:
3133                 int_mode = ECORE_INT_MODE_INTA;
3134                 rte_intr_callback_register(&pci_dev->intr_handle,
3135                                            qede_interrupt_handler_intx,
3136                                            (void *)eth_dev);
3137                 break;
3138         default:
3139                 int_mode = ECORE_INT_MODE_MSIX;
3140                 rte_intr_callback_register(&pci_dev->intr_handle,
3141                                            qede_interrupt_handler,
3142                                            (void *)eth_dev);
3143         }
3144
3145         if (rte_intr_enable(&pci_dev->intr_handle)) {
3146                 DP_ERR(edev, "rte_intr_enable() failed\n");
3147                 return -ENODEV;
3148         }
3149
3150         /* Start the Slowpath-process */
3151         memset(&params, 0, sizeof(struct qed_slowpath_params));
3152
3153         params.int_mode = int_mode;
3154         params.drv_major = QEDE_PMD_VERSION_MAJOR;
3155         params.drv_minor = QEDE_PMD_VERSION_MINOR;
3156         params.drv_rev = QEDE_PMD_VERSION_REVISION;
3157         params.drv_eng = QEDE_PMD_VERSION_PATCH;
3158         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3159                 QEDE_PMD_DRV_VER_STR_SIZE);
3160
3161         /* For CMT mode device do periodic polling for slowpath events.
3162          * This is required since uio device uses only one MSI-x
3163          * interrupt vector but we need one for each engine.
3164          */
3165         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3166                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
3167                                        qede_poll_sp_sb_cb,
3168                                        (void *)eth_dev);
3169                 if (rc != 0) {
3170                         DP_ERR(edev, "Unable to start periodic"
3171                                      " timer rc %d\n", rc);
3172                         return -EINVAL;
3173                 }
3174         }
3175
3176         rc = qed_ops->common->slowpath_start(edev, &params);
3177         if (rc) {
3178                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3179                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3180                                      (void *)eth_dev);
3181                 return -ENODEV;
3182         }
3183
3184         rc = qed_ops->fill_dev_info(edev, &dev_info);
3185         if (rc) {
3186                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3187                 qed_ops->common->slowpath_stop(edev);
3188                 qed_ops->common->remove(edev);
3189                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3190                                      (void *)eth_dev);
3191                 return -ENODEV;
3192         }
3193
3194         qede_alloc_etherdev(adapter, &dev_info);
3195
3196         adapter->ops->common->set_name(edev, edev->name);
3197
3198         if (!is_vf)
3199                 adapter->dev_info.num_mac_filters =
3200                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3201                                             ECORE_MAC);
3202         else
3203                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3204                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
3205
3206         /* Allocate memory for storing MAC addr */
3207         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3208                                         (ETHER_ADDR_LEN *
3209                                         adapter->dev_info.num_mac_filters),
3210                                         RTE_CACHE_LINE_SIZE);
3211
3212         if (eth_dev->data->mac_addrs == NULL) {
3213                 DP_ERR(edev, "Failed to allocate MAC address\n");
3214                 qed_ops->common->slowpath_stop(edev);
3215                 qed_ops->common->remove(edev);
3216                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3217                                      (void *)eth_dev);
3218                 return -ENOMEM;
3219         }
3220
3221         if (!is_vf) {
3222                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3223                                 hw_info.hw_mac_addr,
3224                                 &eth_dev->data->mac_addrs[0]);
3225                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3226                                 &adapter->primary_mac);
3227         } else {
3228                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3229                                        &bulletin_change);
3230                 if (bulletin_change) {
3231                         is_mac_exist =
3232                             ecore_vf_bulletin_get_forced_mac(
3233                                                 ECORE_LEADING_HWFN(edev),
3234                                                 vf_mac,
3235                                                 &is_mac_forced);
3236                         if (is_mac_exist) {
3237                                 DP_INFO(edev, "VF macaddr received from PF\n");
3238                                 ether_addr_copy((struct ether_addr *)&vf_mac,
3239                                                 &eth_dev->data->mac_addrs[0]);
3240                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3241                                                 &adapter->primary_mac);
3242                         } else {
3243                                 DP_ERR(edev, "No VF macaddr assigned\n");
3244                         }
3245                 }
3246         }
3247
3248         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3249
3250         if (do_once) {
3251                 qede_print_adapter_info(adapter);
3252                 do_once = false;
3253         }
3254
3255         /* Bring-up the link */
3256         qede_dev_set_link_state(eth_dev, true);
3257
3258         adapter->num_tx_queues = 0;
3259         adapter->num_rx_queues = 0;
3260         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3261         SLIST_INIT(&adapter->vlan_list_head);
3262         SLIST_INIT(&adapter->uc_list_head);
3263         SLIST_INIT(&adapter->mc_list_head);
3264         adapter->mtu = ETHER_MTU;
3265         adapter->vport_started = false;
3266
3267         /* VF tunnel offloads is enabled by default in PF driver */
3268         adapter->vxlan.num_filters = 0;
3269         adapter->geneve.num_filters = 0;
3270         adapter->ipgre.num_filters = 0;
3271         if (is_vf) {
3272                 adapter->vxlan.enable = true;
3273                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3274                                              ETH_TUNNEL_FILTER_IVLAN;
3275                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3276                 adapter->geneve.enable = true;
3277                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3278                                               ETH_TUNNEL_FILTER_IVLAN;
3279                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3280                 adapter->ipgre.enable = true;
3281                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
3282                                              ETH_TUNNEL_FILTER_IVLAN;
3283         } else {
3284                 adapter->vxlan.enable = false;
3285                 adapter->geneve.enable = false;
3286                 adapter->ipgre.enable = false;
3287         }
3288
3289         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3290                 adapter->primary_mac.addr_bytes[0],
3291                 adapter->primary_mac.addr_bytes[1],
3292                 adapter->primary_mac.addr_bytes[2],
3293                 adapter->primary_mac.addr_bytes[3],
3294                 adapter->primary_mac.addr_bytes[4],
3295                 adapter->primary_mac.addr_bytes[5]);
3296
3297         DP_INFO(edev, "Device initialized\n");
3298
3299         return 0;
3300 }
3301
3302 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3303 {
3304         return qede_common_dev_init(eth_dev, 1);
3305 }
3306
3307 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3308 {
3309         return qede_common_dev_init(eth_dev, 0);
3310 }
3311
3312 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3313 {
3314 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3315         struct qede_dev *qdev = eth_dev->data->dev_private;
3316         struct ecore_dev *edev = &qdev->edev;
3317
3318         PMD_INIT_FUNC_TRACE(edev);
3319 #endif
3320
3321         /* only uninitialize in the primary process */
3322         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3323                 return 0;
3324
3325         /* safe to close dev here */
3326         qede_dev_close(eth_dev);
3327
3328         eth_dev->dev_ops = NULL;
3329         eth_dev->rx_pkt_burst = NULL;
3330         eth_dev->tx_pkt_burst = NULL;
3331
3332         if (eth_dev->data->mac_addrs)
3333                 rte_free(eth_dev->data->mac_addrs);
3334
3335         eth_dev->data->mac_addrs = NULL;
3336
3337         return 0;
3338 }
3339
3340 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3341 {
3342         return qede_dev_common_uninit(eth_dev);
3343 }
3344
3345 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3346 {
3347         return qede_dev_common_uninit(eth_dev);
3348 }
3349
3350 static const struct rte_pci_id pci_id_qedevf_map[] = {
3351 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3352         {
3353                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3354         },
3355         {
3356                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3357         },
3358         {
3359                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3360         },
3361         {.vendor_id = 0,}
3362 };
3363
3364 static const struct rte_pci_id pci_id_qede_map[] = {
3365 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3366         {
3367                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3368         },
3369         {
3370                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3371         },
3372         {
3373                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3374         },
3375         {
3376                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3377         },
3378         {
3379                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3380         },
3381         {
3382                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3383         },
3384         {
3385                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3386         },
3387         {
3388                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3389         },
3390         {
3391                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3392         },
3393         {
3394                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3395         },
3396         {.vendor_id = 0,}
3397 };
3398
3399 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3400         struct rte_pci_device *pci_dev)
3401 {
3402         return rte_eth_dev_pci_generic_probe(pci_dev,
3403                 sizeof(struct qede_dev), qedevf_eth_dev_init);
3404 }
3405
3406 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3407 {
3408         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3409 }
3410
3411 static struct rte_pci_driver rte_qedevf_pmd = {
3412         .id_table = pci_id_qedevf_map,
3413         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3414         .probe = qedevf_eth_dev_pci_probe,
3415         .remove = qedevf_eth_dev_pci_remove,
3416 };
3417
3418 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3419         struct rte_pci_device *pci_dev)
3420 {
3421         return rte_eth_dev_pci_generic_probe(pci_dev,
3422                 sizeof(struct qede_dev), qede_eth_dev_init);
3423 }
3424
3425 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3426 {
3427         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3428 }
3429
3430 static struct rte_pci_driver rte_qede_pmd = {
3431         .id_table = pci_id_qede_map,
3432         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3433         .probe = qede_eth_dev_pci_probe,
3434         .remove = qede_eth_dev_pci_remove,
3435 };
3436
3437 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3438 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3439 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3440 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3441 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3442 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3443
3444 RTE_INIT(qede_init_log)
3445 {
3446         qede_logtype_init = rte_log_register("pmd.net.qede.init");
3447         if (qede_logtype_init >= 0)
3448                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3449         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3450         if (qede_logtype_driver >= 0)
3451                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
3452 }