drivers/net/qede/qede_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include <rte_net.h>
   8 #include "qede_rxtx.h"
   9
  10 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  11 {
  12         struct rte_mbuf *new_mb = NULL;
  13         struct eth_rx_bd *rx_bd;
  14         dma_addr_t mapping;
  15         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  16
  17         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  18         if (unlikely(!new_mb)) {
  19                 PMD_RX_LOG(ERR, rxq,
  20                            "Failed to allocate rx buffer "
  21                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  22                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  23                            rte_mempool_avail_count(rxq->mb_pool),
  24                            rte_mempool_in_use_count(rxq->mb_pool));
  25                 return -ENOMEM;
  26         }
  27         rxq->sw_rx_ring[idx].mbuf = new_mb;
  28         rxq->sw_rx_ring[idx].page_offset = 0;
  29         mapping = rte_mbuf_data_iova_default(new_mb);
  30         /* Advance PROD and get BD pointer */
  31         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  32         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  33         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  34         rxq->sw_rx_prod++;
  35         return 0;
  36 }
  37
  38 int
  39 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  40                     uint16_t nb_desc, unsigned int socket_id,
  41                     __rte_unused const struct rte_eth_rxconf *rx_conf,
  42                     struct rte_mempool *mp)
  43 {
  44         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
  45         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
  46         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  47         struct qede_rx_queue *rxq;
  48         uint16_t max_rx_pkt_len;
  49         uint16_t bufsz;
  50         size_t size;
  51         int rc;
  52
  53         PMD_INIT_FUNC_TRACE(edev);
  54
  55         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
  56         if (!rte_is_power_of_2(nb_desc)) {
  57                 DP_ERR(edev, "Ring size %u is not power of 2\n",
  58                           nb_desc);
  59                 return -EINVAL;
  60         }
  61
  62         /* Free memory prior to re-allocation if needed... */
  63         if (dev->data->rx_queues[queue_idx] != NULL) {
  64                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
  65                 dev->data->rx_queues[queue_idx] = NULL;
  66         }
  67
  68         /* First allocate the rx queue data structure */
  69         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
  70                                  RTE_CACHE_LINE_SIZE, socket_id);
  71
  72         if (!rxq) {
  73                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
  74                           socket_id);
  75                 return -ENOMEM;
  76         }
  77
  78         rxq->qdev = qdev;
  79         rxq->mb_pool = mp;
  80         rxq->nb_rx_desc = nb_desc;
  81         rxq->queue_id = queue_idx;
  82         rxq->port_id = dev->data->port_id;
  83
  84         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
  85
  86         /* Fix up RX buffer size */
  87         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
  88         if ((rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) ||
  89             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
  90                 if (!dev->data->scattered_rx) {
  91                         DP_INFO(edev, "Forcing scatter-gather mode\n");
  92                         dev->data->scattered_rx = 1;
  93                 }
  94         }
  95
  96         if (dev->data->scattered_rx)
  97                 rxq->rx_buf_size = bufsz + ETHER_HDR_LEN +
  98                                    ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
  99         else
 100                 rxq->rx_buf_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
 101         /* Align to cache-line size if needed */
 102         rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
 103
 104         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 105                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 106
 107         /* Allocate the parallel driver ring for Rx buffers */
 108         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 109         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 110                                              RTE_CACHE_LINE_SIZE, socket_id);
 111         if (!rxq->sw_rx_ring) {
 112                 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
 113                        " socket %u\n", socket_id);
 114                 rte_free(rxq);
 115                 return -ENOMEM;
 116         }
 117
 118         /* Allocate FW Rx ring  */
 119         rc = qdev->ops->common->chain_alloc(edev,
 120                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 121                                             ECORE_CHAIN_MODE_NEXT_PTR,
 122                                             ECORE_CHAIN_CNT_TYPE_U16,
 123                                             rxq->nb_rx_desc,
 124                                             sizeof(struct eth_rx_bd),
 125                                             &rxq->rx_bd_ring,
 126                                             NULL);
 127
 128         if (rc != ECORE_SUCCESS) {
 129                 DP_ERR(edev, "Memory allocation fails for RX BD ring"
 130                        " on socket %u\n", socket_id);
 131                 rte_free(rxq->sw_rx_ring);
 132                 rte_free(rxq);
 133                 return -ENOMEM;
 134         }
 135
 136         /* Allocate FW completion ring */
 137         rc = qdev->ops->common->chain_alloc(edev,
 138                                             ECORE_CHAIN_USE_TO_CONSUME,
 139                                             ECORE_CHAIN_MODE_PBL,
 140                                             ECORE_CHAIN_CNT_TYPE_U16,
 141                                             rxq->nb_rx_desc,
 142                                             sizeof(union eth_rx_cqe),
 143                                             &rxq->rx_comp_ring,
 144                                             NULL);
 145
 146         if (rc != ECORE_SUCCESS) {
 147                 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
 148                        " on socket %u\n", socket_id);
 149                 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 150                 rte_free(rxq->sw_rx_ring);
 151                 rte_free(rxq);
 152                 return -ENOMEM;
 153         }
 154
 155         dev->data->rx_queues[queue_idx] = rxq;
 156         qdev->fp_array[queue_idx].rxq = rxq;
 157
 158         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 159                   queue_idx, nb_desc, rxq->rx_buf_size, socket_id);
 160
 161         return 0;
 162 }
 163
 164 static void
 165 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
 166                     struct qede_rx_queue *rxq)
 167 {
 168         DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
 169         ecore_chain_reset(&rxq->rx_bd_ring);
 170         ecore_chain_reset(&rxq->rx_comp_ring);
 171         rxq->sw_rx_prod = 0;
 172         rxq->sw_rx_cons = 0;
 173         *rxq->hw_cons_ptr = 0;
 174 }
 175
 176 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
 177 {
 178         uint16_t i;
 179
 180         if (rxq->sw_rx_ring) {
 181                 for (i = 0; i < rxq->nb_rx_desc; i++) {
 182                         if (rxq->sw_rx_ring[i].mbuf) {
 183                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
 184                                 rxq->sw_rx_ring[i].mbuf = NULL;
 185                         }
 186                 }
 187         }
 188 }
 189
 190 void qede_rx_queue_release(void *rx_queue)
 191 {
 192         struct qede_rx_queue *rxq = rx_queue;
 193         struct qede_dev *qdev = rxq->qdev;
 194         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 195
 196         PMD_INIT_FUNC_TRACE(edev);
 197
 198         if (rxq) {
 199                 qede_rx_queue_release_mbufs(rxq);
 200                 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 201                 qdev->ops->common->chain_free(edev, &rxq->rx_comp_ring);
 202                 rte_free(rxq->sw_rx_ring);
 203                 rte_free(rxq);
 204         }
 205 }
 206
 207 /* Stops a given RX queue in the HW */
 208 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 209 {
 210         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 211         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 212         struct ecore_hwfn *p_hwfn;
 213         struct qede_rx_queue *rxq;
 214         int hwfn_index;
 215         int rc;
 216
 217         if (rx_queue_id < eth_dev->data->nb_rx_queues) {
 218                 rxq = eth_dev->data->rx_queues[rx_queue_id];
 219                 hwfn_index = rx_queue_id % edev->num_hwfns;
 220                 p_hwfn = &edev->hwfns[hwfn_index];
 221                 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
 222                                 true, false);
 223                 if (rc != ECORE_SUCCESS) {
 224                         DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
 225                         return -1;
 226                 }
 227                 qede_rx_queue_release_mbufs(rxq);
 228                 qede_rx_queue_reset(qdev, rxq);
 229                 eth_dev->data->rx_queue_state[rx_queue_id] =
 230                         RTE_ETH_QUEUE_STATE_STOPPED;
 231                 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
 232         } else {
 233                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 234                 rc = -EINVAL;
 235         }
 236
 237         return rc;
 238 }
 239
 240 int
 241 qede_tx_queue_setup(struct rte_eth_dev *dev,
 242                     uint16_t queue_idx,
 243                     uint16_t nb_desc,
 244                     unsigned int socket_id,
 245                     const struct rte_eth_txconf *tx_conf)
 246 {
 247         struct qede_dev *qdev = dev->data->dev_private;
 248         struct ecore_dev *edev = &qdev->edev;
 249         struct qede_tx_queue *txq;
 250         int rc;
 251
 252         PMD_INIT_FUNC_TRACE(edev);
 253
 254         if (!rte_is_power_of_2(nb_desc)) {
 255                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 256                        nb_desc);
 257                 return -EINVAL;
 258         }
 259
 260         /* Free memory prior to re-allocation if needed... */
 261         if (dev->data->tx_queues[queue_idx] != NULL) {
 262                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 263                 dev->data->tx_queues[queue_idx] = NULL;
 264         }
 265
 266         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 267                                  RTE_CACHE_LINE_SIZE, socket_id);
 268
 269         if (txq == NULL) {
 270                 DP_ERR(edev,
 271                        "Unable to allocate memory for txq on socket %u",
 272                        socket_id);
 273                 return -ENOMEM;
 274         }
 275
 276         txq->nb_tx_desc = nb_desc;
 277         txq->qdev = qdev;
 278         txq->port_id = dev->data->port_id;
 279
 280         rc = qdev->ops->common->chain_alloc(edev,
 281                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 282                                             ECORE_CHAIN_MODE_PBL,
 283                                             ECORE_CHAIN_CNT_TYPE_U16,
 284                                             txq->nb_tx_desc,
 285                                             sizeof(union eth_tx_bd_types),
 286                                             &txq->tx_pbl,
 287                                             NULL);
 288         if (rc != ECORE_SUCCESS) {
 289                 DP_ERR(edev,
 290                        "Unable to allocate memory for txbd ring on socket %u",
 291                        socket_id);
 292                 qede_tx_queue_release(txq);
 293                 return -ENOMEM;
 294         }
 295
 296         /* Allocate software ring */
 297         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 298                                              (sizeof(struct qede_tx_entry) *
 299                                               txq->nb_tx_desc),
 300                                              RTE_CACHE_LINE_SIZE, socket_id);
 301
 302         if (!txq->sw_tx_ring) {
 303                 DP_ERR(edev,
 304                        "Unable to allocate memory for txbd ring on socket %u",
 305                        socket_id);
 306                 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 307                 qede_tx_queue_release(txq);
 308                 return -ENOMEM;
 309         }
 310
 311         txq->queue_id = queue_idx;
 312
 313         txq->nb_tx_avail = txq->nb_tx_desc;
 314
 315         txq->tx_free_thresh =
 316             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 317             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 318
 319         dev->data->tx_queues[queue_idx] = txq;
 320         qdev->fp_array[queue_idx].txq = txq;
 321
 322         DP_INFO(edev,
 323                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 324                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 325
 326         return 0;
 327 }
 328
 329 static void
 330 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
 331                     struct qede_tx_queue *txq)
 332 {
 333         DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
 334         ecore_chain_reset(&txq->tx_pbl);
 335         txq->sw_tx_cons = 0;
 336         txq->sw_tx_prod = 0;
 337         *txq->hw_cons_ptr = 0;
 338 }
 339
 340 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
 341 {
 342         uint16_t i;
 343
 344         if (txq->sw_tx_ring) {
 345                 for (i = 0; i < txq->nb_tx_desc; i++) {
 346                         if (txq->sw_tx_ring[i].mbuf) {
 347                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
 348                                 txq->sw_tx_ring[i].mbuf = NULL;
 349                         }
 350                 }
 351         }
 352 }
 353
 354 void qede_tx_queue_release(void *tx_queue)
 355 {
 356         struct qede_tx_queue *txq = tx_queue;
 357         struct qede_dev *qdev = txq->qdev;
 358         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 359
 360         PMD_INIT_FUNC_TRACE(edev);
 361
 362         if (txq) {
 363                 qede_tx_queue_release_mbufs(txq);
 364                 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 365                 rte_free(txq->sw_tx_ring);
 366                 rte_free(txq);
 367         }
 368 }
 369
 370 /* This function allocates fast-path status block memory */
 371 static int
 372 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 373                   uint16_t sb_id)
 374 {
 375         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 376         struct status_block_e4 *sb_virt;
 377         dma_addr_t sb_phys;
 378         int rc;
 379
 380         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
 381                                           sizeof(struct status_block_e4));
 382         if (!sb_virt) {
 383                 DP_ERR(edev, "Status block allocation failed\n");
 384                 return -ENOMEM;
 385         }
 386         rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
 387                                         sb_phys, sb_id);
 388         if (rc) {
 389                 DP_ERR(edev, "Status block initialization failed\n");
 390                 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
 391                                        sizeof(struct status_block_e4));
 392                 return rc;
 393         }
 394
 395         return 0;
 396 }
 397
 398 int qede_alloc_fp_resc(struct qede_dev *qdev)
 399 {
 400         struct ecore_dev *edev = &qdev->edev;
 401         struct qede_fastpath *fp;
 402         uint32_t num_sbs;
 403         uint16_t sb_idx;
 404
 405         if (IS_VF(edev))
 406                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 407         else
 408                 num_sbs = ecore_cxt_get_proto_cid_count
 409                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 410
 411         if (num_sbs == 0) {
 412                 DP_ERR(edev, "No status blocks available\n");
 413                 return -EINVAL;
 414         }
 415
 416         qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
 417                                 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
 418
 419         if (!qdev->fp_array) {
 420                 DP_ERR(edev, "fp array allocation failed\n");
 421                 return -ENOMEM;
 422         }
 423
 424         memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
 425                         sizeof(*qdev->fp_array));
 426
 427         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 428                 fp = &qdev->fp_array[sb_idx];
 429                 if (!fp)
 430                         continue;
 431                 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
 432                                 RTE_CACHE_LINE_SIZE);
 433                 if (!fp->sb_info) {
 434                         DP_ERR(edev, "FP sb_info allocation fails\n");
 435                         return -1;
 436                 }
 437                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 438                         DP_ERR(edev, "FP status block allocation fails\n");
 439                         return -1;
 440                 }
 441                 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
 442                                 fp->sb_info->igu_sb_id);
 443         }
 444
 445         return 0;
 446 }
 447
 448 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 449 {
 450         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 451         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 452         struct qede_fastpath *fp;
 453         uint16_t sb_idx;
 454         uint8_t i;
 455
 456         PMD_INIT_FUNC_TRACE(edev);
 457
 458         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 459                 fp = &qdev->fp_array[sb_idx];
 460                 if (!fp)
 461                         continue;
 462                 DP_INFO(edev, "Free sb_info index 0x%x\n",
 463                                 fp->sb_info->igu_sb_id);
 464                 if (fp->sb_info) {
 465                         OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
 466                                 fp->sb_info->sb_phys,
 467                                 sizeof(struct status_block_e4));
 468                         rte_free(fp->sb_info);
 469                         fp->sb_info = NULL;
 470                 }
 471         }
 472
 473         /* Free packet buffers and ring memories */
 474         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 475                 if (eth_dev->data->rx_queues[i]) {
 476                         qede_rx_queue_release(eth_dev->data->rx_queues[i]);
 477                         eth_dev->data->rx_queues[i] = NULL;
 478                 }
 479         }
 480
 481         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
 482                 if (eth_dev->data->tx_queues[i]) {
 483                         qede_tx_queue_release(eth_dev->data->tx_queues[i]);
 484                         eth_dev->data->tx_queues[i] = NULL;
 485                 }
 486         }
 487
 488         if (qdev->fp_array)
 489                 rte_free(qdev->fp_array);
 490         qdev->fp_array = NULL;
 491 }
 492
 493 static inline void
 494 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
 495                     struct qede_rx_queue *rxq)
 496 {
 497         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 498         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 499         struct eth_rx_prod_data rx_prods = { 0 };
 500
 501         /* Update producers */
 502         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 503         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 504
 505         /* Make sure that the BD and SGE data is updated before updating the
 506          * producers since FW might read the BD/SGE right after the producer
 507          * is updated.
 508          */
 509         rte_wmb();
 510
 511         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 512                         (uint32_t *)&rx_prods);
 513
 514         /* mmiowb is needed to synchronize doorbell writes from more than one
 515          * processor. It guarantees that the write arrives to the device before
 516          * the napi lock is released and another qede_poll is called (possibly
 517          * on another CPU). Without this barrier, the next doorbell can bypass
 518          * this doorbell. This is applicable to IA64/Altix systems.
 519          */
 520         rte_wmb();
 521
 522         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 523 }
 524
 525 /* Starts a given RX queue in HW */
 526 static int
 527 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 528 {
 529         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 530         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 531         struct ecore_queue_start_common_params params;
 532         struct ecore_rxq_start_ret_params ret_params;
 533         struct qede_rx_queue *rxq;
 534         struct qede_fastpath *fp;
 535         struct ecore_hwfn *p_hwfn;
 536         dma_addr_t p_phys_table;
 537         uint16_t page_cnt;
 538         uint16_t j;
 539         int hwfn_index;
 540         int rc;
 541
 542         if (rx_queue_id < eth_dev->data->nb_rx_queues) {
 543                 fp = &qdev->fp_array[rx_queue_id];
 544                 rxq = eth_dev->data->rx_queues[rx_queue_id];
 545                 /* Allocate buffers for the Rx ring */
 546                 for (j = 0; j < rxq->nb_rx_desc; j++) {
 547                         rc = qede_alloc_rx_buffer(rxq);
 548                         if (rc) {
 549                                 DP_ERR(edev, "RX buffer allocation failed"
 550                                                 " for rxq = %u\n", rx_queue_id);
 551                                 return -ENOMEM;
 552                         }
 553                 }
 554                 /* disable interrupts */
 555                 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 556                 /* Prepare ramrod */
 557                 memset(&params, 0, sizeof(params));
 558                 params.queue_id = rx_queue_id / edev->num_hwfns;
 559                 params.vport_id = 0;
 560                 params.stats_id = params.vport_id;
 561                 params.p_sb = fp->sb_info;
 562                 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
 563                                 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
 564                 params.sb_idx = RX_PI;
 565                 hwfn_index = rx_queue_id % edev->num_hwfns;
 566                 p_hwfn = &edev->hwfns[hwfn_index];
 567                 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
 568                 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
 569                 memset(&ret_params, 0, sizeof(ret_params));
 570                 rc = ecore_eth_rx_queue_start(p_hwfn,
 571                                 p_hwfn->hw_info.opaque_fid,
 572                                 &params, fp->rxq->rx_buf_size,
 573                                 fp->rxq->rx_bd_ring.p_phys_addr,
 574                                 p_phys_table, page_cnt,
 575                                 &ret_params);
 576                 if (rc) {
 577                         DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
 578                                         rx_queue_id, rc);
 579                         return -1;
 580                 }
 581                 /* Update with the returned parameters */
 582                 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
 583                 fp->rxq->handle = ret_params.p_handle;
 584
 585                 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
 586                 qede_update_rx_prod(qdev, fp->rxq);
 587                 eth_dev->data->rx_queue_state[rx_queue_id] =
 588                         RTE_ETH_QUEUE_STATE_STARTED;
 589                 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
 590         } else {
 591                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 592                 rc = -EINVAL;
 593         }
 594
 595         return rc;
 596 }
 597
 598 static int
 599 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 600 {
 601         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 602         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 603         struct ecore_queue_start_common_params params;
 604         struct ecore_txq_start_ret_params ret_params;
 605         struct ecore_hwfn *p_hwfn;
 606         dma_addr_t p_phys_table;
 607         struct qede_tx_queue *txq;
 608         struct qede_fastpath *fp;
 609         uint16_t page_cnt;
 610         int hwfn_index;
 611         int rc;
 612
 613         if (tx_queue_id < eth_dev->data->nb_tx_queues) {
 614                 txq = eth_dev->data->tx_queues[tx_queue_id];
 615                 fp = &qdev->fp_array[tx_queue_id];
 616                 memset(&params, 0, sizeof(params));
 617                 params.queue_id = tx_queue_id / edev->num_hwfns;
 618                 params.vport_id = 0;
 619                 params.stats_id = params.vport_id;
 620                 params.p_sb = fp->sb_info;
 621                 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
 622                                 fp->txq->queue_id, fp->sb_info->igu_sb_id);
 623                 params.sb_idx = TX_PI(0); /* tc = 0 */
 624                 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 625                 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 626                 hwfn_index = tx_queue_id % edev->num_hwfns;
 627                 p_hwfn = &edev->hwfns[hwfn_index];
 628                 if (qdev->dev_info.is_legacy)
 629                         fp->txq->is_legacy = true;
 630                 rc = ecore_eth_tx_queue_start(p_hwfn,
 631                                 p_hwfn->hw_info.opaque_fid,
 632                                 &params, 0 /* tc */,
 633                                 p_phys_table, page_cnt,
 634                                 &ret_params);
 635                 if (rc != ECORE_SUCCESS) {
 636                         DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
 637                                         tx_queue_id, rc);
 638                         return -1;
 639                 }
 640                 txq->doorbell_addr = ret_params.p_doorbell;
 641                 txq->handle = ret_params.p_handle;
 642
 643                 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[TX_PI(0)];
 644                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
 645                                 DB_DEST_XCM);
 646                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 647                                 DB_AGG_CMD_SET);
 648                 SET_FIELD(txq->tx_db.data.params,
 649                                 ETH_DB_DATA_AGG_VAL_SEL,
 650                                 DQ_XCM_ETH_TX_BD_PROD_CMD);
 651                 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 652                 eth_dev->data->tx_queue_state[tx_queue_id] =
 653                         RTE_ETH_QUEUE_STATE_STARTED;
 654                 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
 655         } else {
 656                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 657                 rc = -EINVAL;
 658         }
 659
 660         return rc;
 661 }
 662
 663 static inline void
 664 qede_free_tx_pkt(struct qede_tx_queue *txq)
 665 {
 666         struct rte_mbuf *mbuf;
 667         uint16_t nb_segs;
 668         uint16_t idx;
 669
 670         idx = TX_CONS(txq);
 671         mbuf = txq->sw_tx_ring[idx].mbuf;
 672         if (mbuf) {
 673                 nb_segs = mbuf->nb_segs;
 674                 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
 675                 while (nb_segs) {
 676                         /* It's like consuming rxbuf in recv() */
 677                         ecore_chain_consume(&txq->tx_pbl);
 678                         txq->nb_tx_avail++;
 679                         nb_segs--;
 680                 }
 681                 rte_pktmbuf_free(mbuf);
 682                 txq->sw_tx_ring[idx].mbuf = NULL;
 683                 txq->sw_tx_cons++;
 684                 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
 685         } else {
 686                 ecore_chain_consume(&txq->tx_pbl);
 687                 txq->nb_tx_avail++;
 688         }
 689 }
 690
 691 static inline void
 692 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
 693                       struct qede_tx_queue *txq)
 694 {
 695         uint16_t hw_bd_cons;
 696 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 697         uint16_t sw_tx_cons;
 698 #endif
 699
 700         rte_compiler_barrier();
 701         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
 702 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 703         sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
 704         PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
 705                    abs(hw_bd_cons - sw_tx_cons));
 706 #endif
 707         while (hw_bd_cons !=  ecore_chain_get_cons_idx(&txq->tx_pbl))
 708                 qede_free_tx_pkt(txq);
 709 }
 710
 711 static int qede_drain_txq(struct qede_dev *qdev,
 712                           struct qede_tx_queue *txq, bool allow_drain)
 713 {
 714         struct ecore_dev *edev = &qdev->edev;
 715         int rc, cnt = 1000;
 716
 717         while (txq->sw_tx_cons != txq->sw_tx_prod) {
 718                 qede_process_tx_compl(edev, txq);
 719                 if (!cnt) {
 720                         if (allow_drain) {
 721                                 DP_ERR(edev, "Tx queue[%u] is stuck,"
 722                                           "requesting MCP to drain\n",
 723                                           txq->queue_id);
 724                                 rc = qdev->ops->common->drain(edev);
 725                                 if (rc)
 726                                         return rc;
 727                                 return qede_drain_txq(qdev, txq, false);
 728                         }
 729                         DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
 730                                   "PROD=%d, CONS=%d\n",
 731                                   txq->queue_id, txq->sw_tx_prod,
 732                                   txq->sw_tx_cons);
 733                         return -1;
 734                 }
 735                 cnt--;
 736                 DELAY(1000);
 737                 rte_compiler_barrier();
 738         }
 739
 740         /* FW finished processing, wait for HW to transmit all tx packets */
 741         DELAY(2000);
 742
 743         return 0;
 744 }
 745
 746 /* Stops a given TX queue in the HW */
 747 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 748 {
 749         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 750         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 751         struct ecore_hwfn *p_hwfn;
 752         struct qede_tx_queue *txq;
 753         int hwfn_index;
 754         int rc;
 755
 756         if (tx_queue_id < eth_dev->data->nb_tx_queues) {
 757                 txq = eth_dev->data->tx_queues[tx_queue_id];
 758                 /* Drain txq */
 759                 if (qede_drain_txq(qdev, txq, true))
 760                         return -1; /* For the lack of retcodes */
 761                 /* Stop txq */
 762                 hwfn_index = tx_queue_id % edev->num_hwfns;
 763                 p_hwfn = &edev->hwfns[hwfn_index];
 764                 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
 765                 if (rc != ECORE_SUCCESS) {
 766                         DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
 767                         return -1;
 768                 }
 769                 qede_tx_queue_release_mbufs(txq);
 770                 qede_tx_queue_reset(qdev, txq);
 771                 eth_dev->data->tx_queue_state[tx_queue_id] =
 772                         RTE_ETH_QUEUE_STATE_STOPPED;
 773                 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
 774         } else {
 775                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 776                 rc = -EINVAL;
 777         }
 778
 779         return rc;
 780 }
 781
 782 int qede_start_queues(struct rte_eth_dev *eth_dev)
 783 {
 784         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 785         uint8_t id;
 786         int rc = -1;
 787
 788         for_each_rss(id) {
 789                 rc = qede_rx_queue_start(eth_dev, id);
 790                 if (rc != ECORE_SUCCESS)
 791                         return -1;
 792         }
 793
 794         for_each_tss(id) {
 795                 rc = qede_tx_queue_start(eth_dev, id);
 796                 if (rc != ECORE_SUCCESS)
 797                         return -1;
 798         }
 799
 800         return rc;
 801 }
 802
 803 void qede_stop_queues(struct rte_eth_dev *eth_dev)
 804 {
 805         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 806         uint8_t id;
 807
 808         /* Stopping RX/TX queues */
 809         for_each_tss(id) {
 810                 qede_tx_queue_stop(eth_dev, id);
 811         }
 812
 813         for_each_rss(id) {
 814                 qede_rx_queue_stop(eth_dev, id);
 815         }
 816 }
 817
 818 static inline bool qede_tunn_exist(uint16_t flag)
 819 {
 820         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 821                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 822 }
 823
 824 static inline uint8_t qede_check_tunn_csum_l3(uint16_t flag)
 825 {
 826         return !!((PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
 827                 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT) & flag);
 828 }
 829
 830 /*
 831  * qede_check_tunn_csum_l4:
 832  * Returns:
 833  * 1 : If L4 csum is enabled AND if the validation has failed.
 834  * 0 : Otherwise
 835  */
 836 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 837 {
 838         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 839              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 840                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 841                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 842
 843         return 0;
 844 }
 845
 846 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 847 {
 848         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 849              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 850                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 851                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 852
 853         return 0;
 854 }
 855
 856 /* Returns outer L2, L3 and L4 packet_type for tunneled packets */
 857 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m)
 858 {
 859         uint32_t packet_type = RTE_PTYPE_UNKNOWN;
 860         struct ether_hdr *eth_hdr;
 861         struct ipv4_hdr *ipv4_hdr;
 862         struct ipv6_hdr *ipv6_hdr;
 863         struct vlan_hdr *vlan_hdr;
 864         uint16_t ethertype;
 865         bool vlan_tagged = 0;
 866         uint16_t len;
 867
 868         eth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);
 869         len = sizeof(struct ether_hdr);
 870         ethertype = rte_cpu_to_be_16(eth_hdr->ether_type);
 871
 872          /* Note: Valid only if VLAN stripping is disabled */
 873         if (ethertype == ETHER_TYPE_VLAN) {
 874                 vlan_tagged = 1;
 875                 vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1);
 876                 len += sizeof(struct vlan_hdr);
 877                 ethertype = rte_cpu_to_be_16(vlan_hdr->eth_proto);
 878         }
 879
 880         if (ethertype == ETHER_TYPE_IPv4) {
 881                 packet_type |= RTE_PTYPE_L3_IPV4;
 882                 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, len);
 883                 if (ipv4_hdr->next_proto_id == IPPROTO_TCP)
 884                         packet_type |= RTE_PTYPE_L4_TCP;
 885                 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP)
 886                         packet_type |= RTE_PTYPE_L4_UDP;
 887         } else if (ethertype == ETHER_TYPE_IPv6) {
 888                 packet_type |= RTE_PTYPE_L3_IPV6;
 889                 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *, len);
 890                 if (ipv6_hdr->proto == IPPROTO_TCP)
 891                         packet_type |= RTE_PTYPE_L4_TCP;
 892                 else if (ipv6_hdr->proto == IPPROTO_UDP)
 893                         packet_type |= RTE_PTYPE_L4_UDP;
 894         }
 895
 896         if (vlan_tagged)
 897                 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
 898         else
 899                 packet_type |= RTE_PTYPE_L2_ETHER;
 900
 901         return packet_type;
 902 }
 903
 904 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags)
 905 {
 906         uint16_t val;
 907
 908         /* Lookup table */
 909         static const uint32_t
 910         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 911                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4          |
 912                                        RTE_PTYPE_INNER_L2_ETHER,
 913                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6          |
 914                                        RTE_PTYPE_INNER_L2_ETHER,
 915                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4      |
 916                                            RTE_PTYPE_INNER_L4_TCP       |
 917                                            RTE_PTYPE_INNER_L2_ETHER,
 918                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6      |
 919                                            RTE_PTYPE_INNER_L4_TCP       |
 920                                            RTE_PTYPE_INNER_L2_ETHER,
 921                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4      |
 922                                            RTE_PTYPE_INNER_L4_UDP       |
 923                                            RTE_PTYPE_INNER_L2_ETHER,
 924                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6      |
 925                                            RTE_PTYPE_INNER_L4_UDP       |
 926                                            RTE_PTYPE_INNER_L2_ETHER,
 927                 /* Frags with no VLAN */
 928                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4     |
 929                                             RTE_PTYPE_INNER_L4_FRAG     |
 930                                             RTE_PTYPE_INNER_L2_ETHER,
 931                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6     |
 932                                             RTE_PTYPE_INNER_L4_FRAG     |
 933                                             RTE_PTYPE_INNER_L2_ETHER,
 934                 /* VLANs */
 935                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4     |
 936                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
 937                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6     |
 938                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
 939                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
 940                                                 RTE_PTYPE_INNER_L4_TCP  |
 941                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 942                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
 943                                                 RTE_PTYPE_INNER_L4_TCP  |
 944                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 945                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
 946                                                 RTE_PTYPE_INNER_L4_UDP  |
 947                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 948                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
 949                                                 RTE_PTYPE_INNER_L4_UDP  |
 950                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 951                 /* Frags with VLAN */
 952                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
 953                                                  RTE_PTYPE_INNER_L4_FRAG |
 954                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
 955                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
 956                                                  RTE_PTYPE_INNER_L4_FRAG |
 957                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
 958         };
 959
 960         /* Bits (0..3) provides L3/L4 protocol type */
 961         /* Bits (4,5) provides frag and VLAN info */
 962         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 963                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 964                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 965                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
 966                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
 967                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
 968                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
 969                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
 970
 971         if (val < QEDE_PKT_TYPE_MAX)
 972                 return ptype_lkup_tbl[val];
 973
 974         return RTE_PTYPE_UNKNOWN;
 975 }
 976
 977 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 978 {
 979         uint16_t val;
 980
 981         /* Lookup table */
 982         static const uint32_t
 983         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 984                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER,
 985                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER,
 986                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4    |
 987                                            RTE_PTYPE_L4_TCP     |
 988                                            RTE_PTYPE_L2_ETHER,
 989                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6    |
 990                                            RTE_PTYPE_L4_TCP     |
 991                                            RTE_PTYPE_L2_ETHER,
 992                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4    |
 993                                            RTE_PTYPE_L4_UDP     |
 994                                            RTE_PTYPE_L2_ETHER,
 995                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6    |
 996                                            RTE_PTYPE_L4_UDP     |
 997                                            RTE_PTYPE_L2_ETHER,
 998                 /* Frags with no VLAN */
 999                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4   |
1000                                             RTE_PTYPE_L4_FRAG   |
1001                                             RTE_PTYPE_L2_ETHER,
1002                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6   |
1003                                             RTE_PTYPE_L4_FRAG   |
1004                                             RTE_PTYPE_L2_ETHER,
1005                 /* VLANs */
1006                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4           |
1007                                             RTE_PTYPE_L2_ETHER_VLAN,
1008                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6           |
1009                                             RTE_PTYPE_L2_ETHER_VLAN,
1010                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4       |
1011                                                 RTE_PTYPE_L4_TCP        |
1012                                                 RTE_PTYPE_L2_ETHER_VLAN,
1013                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6       |
1014                                                 RTE_PTYPE_L4_TCP        |
1015                                                 RTE_PTYPE_L2_ETHER_VLAN,
1016                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4       |
1017                                                 RTE_PTYPE_L4_UDP        |
1018                                                 RTE_PTYPE_L2_ETHER_VLAN,
1019                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6       |
1020                                                 RTE_PTYPE_L4_UDP        |
1021                                                 RTE_PTYPE_L2_ETHER_VLAN,
1022                 /* Frags with VLAN */
1023                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4      |
1024                                                  RTE_PTYPE_L4_FRAG      |
1025                                                  RTE_PTYPE_L2_ETHER_VLAN,
1026                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6      |
1027                                                  RTE_PTYPE_L4_FRAG      |
1028                                                  RTE_PTYPE_L2_ETHER_VLAN,
1029         };
1030
1031         /* Bits (0..3) provides L3/L4 protocol type */
1032         /* Bits (4,5) provides frag and VLAN info */
1033         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1034                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1035                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1036                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1037                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1038                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1039                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1040                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1041
1042         if (val < QEDE_PKT_TYPE_MAX)
1043                 return ptype_lkup_tbl[val];
1044
1045         return RTE_PTYPE_UNKNOWN;
1046 }
1047
1048 static inline uint8_t
1049 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
1050 {
1051         struct ipv4_hdr *ip;
1052         uint16_t pkt_csum;
1053         uint16_t calc_csum;
1054         uint16_t val;
1055
1056         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1057                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
1058
1059         if (unlikely(val)) {
1060                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
1061                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
1062                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1063                                            sizeof(struct ether_hdr));
1064                         pkt_csum = ip->hdr_checksum;
1065                         ip->hdr_checksum = 0;
1066                         calc_csum = rte_ipv4_cksum(ip);
1067                         ip->hdr_checksum = pkt_csum;
1068                         return (calc_csum != pkt_csum);
1069                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
1070                         return 1;
1071                 }
1072         }
1073         return 0;
1074 }
1075
1076 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
1077 {
1078         ecore_chain_consume(&rxq->rx_bd_ring);
1079         rxq->sw_rx_cons++;
1080 }
1081
1082 static inline void
1083 qede_reuse_page(__rte_unused struct qede_dev *qdev,
1084                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
1085 {
1086         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
1087         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1088         struct qede_rx_entry *curr_prod;
1089         dma_addr_t new_mapping;
1090
1091         curr_prod = &rxq->sw_rx_ring[idx];
1092         *curr_prod = *curr_cons;
1093
1094         new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) +
1095                       curr_prod->page_offset;
1096
1097         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
1098         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
1099
1100         rxq->sw_rx_prod++;
1101 }
1102
1103 static inline void
1104 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
1105                         struct qede_dev *qdev, uint8_t count)
1106 {
1107         struct qede_rx_entry *curr_cons;
1108
1109         for (; count > 0; count--) {
1110                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
1111                 qede_reuse_page(qdev, rxq, curr_cons);
1112                 qede_rx_bd_ring_consume(rxq);
1113         }
1114 }
1115
1116 static inline void
1117 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
1118                                      struct qede_rx_queue *rxq,
1119                                      uint8_t agg_index, uint16_t len)
1120 {
1121         struct qede_agg_info *tpa_info;
1122         struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
1123         uint16_t cons_idx;
1124
1125         /* Under certain conditions it is possible that FW may not consume
1126          * additional or new BD. So decision to consume the BD must be made
1127          * based on len_list[0].
1128          */
1129         if (rte_le_to_cpu_16(len)) {
1130                 tpa_info = &rxq->tpa_info[agg_index];
1131                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1132                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
1133                 assert(curr_frag);
1134                 curr_frag->nb_segs = 1;
1135                 curr_frag->pkt_len = rte_le_to_cpu_16(len);
1136                 curr_frag->data_len = curr_frag->pkt_len;
1137                 tpa_info->tpa_tail->next = curr_frag;
1138                 tpa_info->tpa_tail = curr_frag;
1139                 qede_rx_bd_ring_consume(rxq);
1140                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1141                         PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
1142                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1143                         rxq->rx_alloc_errors++;
1144                 }
1145         }
1146 }
1147
1148 static inline void
1149 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
1150                              struct qede_rx_queue *rxq,
1151                              struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1152 {
1153         PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
1154                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
1155         /* only len_list[0] will have value */
1156         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1157                                              cqe->len_list[0]);
1158 }
1159
1160 static inline void
1161 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
1162                             struct qede_rx_queue *rxq,
1163                             struct eth_fast_path_rx_tpa_end_cqe *cqe)
1164 {
1165         struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
1166
1167         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1168                                              cqe->len_list[0]);
1169         /* Update total length and frags based on end TPA */
1170         rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
1171         /* TODO:  Add Sanity Checks */
1172         rx_mb->nb_segs = cqe->num_of_bds;
1173         rx_mb->pkt_len = cqe->total_packet_len;
1174
1175         PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1176                    " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1177                    rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1178                    rx_mb->pkt_len);
1179 }
1180
1181 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1182 {
1183         uint32_t val;
1184
1185         /* Lookup table */
1186         static const uint32_t
1187         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1188                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1189                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1190                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1191                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1192                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1193                                 RTE_PTYPE_TUNNEL_GENEVE,
1194                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1195                                 RTE_PTYPE_TUNNEL_GRE,
1196                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1197                                 RTE_PTYPE_TUNNEL_VXLAN,
1198                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1199                                 RTE_PTYPE_TUNNEL_GENEVE,
1200                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1201                                 RTE_PTYPE_TUNNEL_GRE,
1202                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1203                                 RTE_PTYPE_TUNNEL_VXLAN,
1204                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1205                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1206                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1207                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1208                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1209                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1210                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1211                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1212                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1213                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1214                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1215                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1216                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1217                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1218                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1219                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1220                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1221                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1222                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1223                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1224                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1225                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1226                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1227                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1228         };
1229
1230         /* Cover bits[4-0] to include tunn_type and next protocol */
1231         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1232                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1233                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1234                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1235
1236         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1237                 return ptype_tunn_lkup_tbl[val];
1238         else
1239                 return RTE_PTYPE_UNKNOWN;
1240 }
1241
1242 static inline int
1243 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
1244                      uint8_t num_segs, uint16_t pkt_len)
1245 {
1246         struct qede_rx_queue *rxq = p_rxq;
1247         struct qede_dev *qdev = rxq->qdev;
1248         register struct rte_mbuf *seg1 = NULL;
1249         register struct rte_mbuf *seg2 = NULL;
1250         uint16_t sw_rx_index;
1251         uint16_t cur_size;
1252
1253         seg1 = rx_mb;
1254         while (num_segs) {
1255                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1256                                                         pkt_len;
1257                 if (unlikely(!cur_size)) {
1258                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1259                                    " left for mapping jumbo\n", num_segs);
1260                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1261                         return -EINVAL;
1262                 }
1263                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1264                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1265                 qede_rx_bd_ring_consume(rxq);
1266                 pkt_len -= cur_size;
1267                 seg2->data_len = cur_size;
1268                 seg1->next = seg2;
1269                 seg1 = seg1->next;
1270                 num_segs--;
1271                 rxq->rx_segs++;
1272         }
1273
1274         return 0;
1275 }
1276
1277 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1278 static inline void
1279 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,
1280                  uint8_t bitfield)
1281 {
1282         PMD_RX_LOG(INFO, rxq,
1283                 "len 0x%04x bf 0x%04x hash_val 0x%x"
1284                 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s"
1285                 " inner_l2=%s inner_l3=%s inner_l4=%s\n",
1286                 m->data_len, bitfield, m->hash.rss,
1287                 (unsigned long)m->ol_flags,
1288                 rte_get_ptype_l2_name(m->packet_type),
1289                 rte_get_ptype_l3_name(m->packet_type),
1290                 rte_get_ptype_l4_name(m->packet_type),
1291                 rte_get_ptype_tunnel_name(m->packet_type),
1292                 rte_get_ptype_inner_l2_name(m->packet_type),
1293                 rte_get_ptype_inner_l3_name(m->packet_type),
1294                 rte_get_ptype_inner_l4_name(m->packet_type));
1295 }
1296 #endif
1297
1298 uint16_t
1299 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1300 {
1301         struct qede_rx_queue *rxq = p_rxq;
1302         struct qede_dev *qdev = rxq->qdev;
1303         struct ecore_dev *edev = &qdev->edev;
1304         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1305         uint16_t rx_pkt = 0;
1306         union eth_rx_cqe *cqe;
1307         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1308         register struct rte_mbuf *rx_mb = NULL;
1309         register struct rte_mbuf *seg1 = NULL;
1310         enum eth_rx_cqe_type cqe_type;
1311         uint16_t pkt_len = 0; /* Sum of all BD segments */
1312         uint16_t len; /* Length of first BD */
1313         uint8_t num_segs = 1;
1314         uint16_t preload_idx;
1315         uint16_t parse_flag;
1316 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1317         uint8_t bitfield_val;
1318 #endif
1319         uint8_t tunn_parse_flag;
1320         uint8_t j;
1321         struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1322         uint64_t ol_flags;
1323         uint32_t packet_type;
1324         uint16_t vlan_tci;
1325         bool tpa_start_flg;
1326         uint8_t offset, tpa_agg_idx, flags;
1327         struct qede_agg_info *tpa_info = NULL;
1328         uint32_t rss_hash;
1329
1330         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1331         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1332
1333         rte_rmb();
1334
1335         if (hw_comp_cons == sw_comp_cons)
1336                 return 0;
1337
1338         while (sw_comp_cons != hw_comp_cons) {
1339                 ol_flags = 0;
1340                 packet_type = RTE_PTYPE_UNKNOWN;
1341                 vlan_tci = 0;
1342                 tpa_start_flg = false;
1343                 rss_hash = 0;
1344
1345                 /* Get the CQE from the completion ring */
1346                 cqe =
1347                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1348                 cqe_type = cqe->fast_path_regular.type;
1349                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1350
1351                 switch (cqe_type) {
1352                 case ETH_RX_CQE_TYPE_REGULAR:
1353                         fp_cqe = &cqe->fast_path_regular;
1354                 break;
1355                 case ETH_RX_CQE_TYPE_TPA_START:
1356                         cqe_start_tpa = &cqe->fast_path_tpa_start;
1357                         tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1358                         tpa_start_flg = true;
1359                         /* Mark it as LRO packet */
1360                         ol_flags |= PKT_RX_LRO;
1361                         /* In split mode,  seg_len is same as len_on_first_bd
1362                          * and ext_bd_len_list will be empty since there are
1363                          * no additional buffers
1364                          */
1365                         PMD_RX_LOG(INFO, rxq,
1366                             "TPA start[%d] - len_on_first_bd %d header %d"
1367                             " [bd_list[0] %d], [seg_len %d]\n",
1368                             cqe_start_tpa->tpa_agg_index,
1369                             rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1370                             cqe_start_tpa->header_len,
1371                             rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]),
1372                             rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1373
1374                 break;
1375                 case ETH_RX_CQE_TYPE_TPA_CONT:
1376                         qede_rx_process_tpa_cont_cqe(qdev, rxq,
1377                                                      &cqe->fast_path_tpa_cont);
1378                         goto next_cqe;
1379                 case ETH_RX_CQE_TYPE_TPA_END:
1380                         qede_rx_process_tpa_end_cqe(qdev, rxq,
1381                                                     &cqe->fast_path_tpa_end);
1382                         tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1383                         tpa_info = &rxq->tpa_info[tpa_agg_idx];
1384                         rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1385                         goto tpa_end;
1386                 case ETH_RX_CQE_TYPE_SLOW_PATH:
1387                         PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1388                         ecore_eth_cqe_completion(
1389                                 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1390                                 (struct eth_slow_path_rx_cqe *)cqe);
1391                         /* fall-thru */
1392                 default:
1393                         goto next_cqe;
1394                 }
1395
1396                 /* Get the data from the SW ring */
1397                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1398                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1399                 assert(rx_mb != NULL);
1400
1401                 /* Handle regular CQE or TPA start CQE */
1402                 if (!tpa_start_flg) {
1403                         parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1404                         offset = fp_cqe->placement_offset;
1405                         len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1406                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1407                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1408                         rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1409 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1410                         bitfield_val = fp_cqe->bitfields;
1411 #endif
1412                 } else {
1413                         parse_flag =
1414                             rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1415                         offset = cqe_start_tpa->placement_offset;
1416                         /* seg_len = len_on_first_bd */
1417                         len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1418                         vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1419 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1420                         bitfield_val = cqe_start_tpa->bitfields;
1421 #endif
1422                         rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1423                 }
1424                 if (qede_tunn_exist(parse_flag)) {
1425                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1426                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1427                                 PMD_RX_LOG(ERR, rxq,
1428                                             "L4 csum failed, flags = 0x%x\n",
1429                                             parse_flag);
1430                                 rxq->rx_hw_errors++;
1431                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1432                         } else {
1433                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1434                         }
1435
1436                         if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1437                                 PMD_RX_LOG(ERR, rxq,
1438                                         "Outer L3 csum failed, flags = 0x%x\n",
1439                                         parse_flag);
1440                                   rxq->rx_hw_errors++;
1441                                   ol_flags |= PKT_RX_EIP_CKSUM_BAD;
1442                         } else {
1443                                   ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1444                         }
1445
1446                         if (tpa_start_flg)
1447                                 flags = cqe_start_tpa->tunnel_pars_flags.flags;
1448                         else
1449                                 flags = fp_cqe->tunnel_pars_flags.flags;
1450                         tunn_parse_flag = flags;
1451
1452                         /* Tunnel_type */
1453                         packet_type =
1454                                 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1455
1456                         /* Inner header */
1457                         packet_type |=
1458                               qede_rx_cqe_to_pkt_type_inner(parse_flag);
1459
1460                         /* Outer L3/L4 types is not available in CQE */
1461                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1462
1463                         /* Outer L3/L4 types is not available in CQE.
1464                          * Need to add offset to parse correctly,
1465                          */
1466                         rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1467                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1468                 } else {
1469                         packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1470                 }
1471
1472                 /* Common handling for non-tunnel packets and for inner
1473                  * headers in the case of tunnel.
1474                  */
1475                 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1476                         PMD_RX_LOG(ERR, rxq,
1477                                     "L4 csum failed, flags = 0x%x\n",
1478                                     parse_flag);
1479                         rxq->rx_hw_errors++;
1480                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
1481                 } else {
1482                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1483                 }
1484                 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1485                         PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1486                                    parse_flag);
1487                         rxq->rx_hw_errors++;
1488                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
1489                 } else {
1490                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1491                 }
1492
1493                 if (CQE_HAS_VLAN(parse_flag) ||
1494                     CQE_HAS_OUTER_VLAN(parse_flag)) {
1495                         /* Note: FW doesn't indicate Q-in-Q packet */
1496                         ol_flags |= PKT_RX_VLAN;
1497                         if (qdev->vlan_strip_flg) {
1498                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1499                                 rx_mb->vlan_tci = vlan_tci;
1500                         }
1501                 }
1502
1503                 /* RSS Hash */
1504                 if (qdev->rss_enable) {
1505                         ol_flags |= PKT_RX_RSS_HASH;
1506                         rx_mb->hash.rss = rss_hash;
1507                 }
1508
1509                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1510                         PMD_RX_LOG(ERR, rxq,
1511                                    "New buffer allocation failed,"
1512                                    "dropping incoming packet\n");
1513                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1514                         rte_eth_devices[rxq->port_id].
1515                             data->rx_mbuf_alloc_failed++;
1516                         rxq->rx_alloc_errors++;
1517                         break;
1518                 }
1519                 qede_rx_bd_ring_consume(rxq);
1520
1521                 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1522                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1523                                    " len on first: %04x Total Len: %04x",
1524                                    fp_cqe->bd_num, len, pkt_len);
1525                         num_segs = fp_cqe->bd_num - 1;
1526                         seg1 = rx_mb;
1527                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1528                                                  pkt_len - len))
1529                                 goto next_cqe;
1530                         for (j = 0; j < num_segs; j++) {
1531                                 if (qede_alloc_rx_buffer(rxq)) {
1532                                         PMD_RX_LOG(ERR, rxq,
1533                                                 "Buffer allocation failed");
1534                                         rte_eth_devices[rxq->port_id].
1535                                                 data->rx_mbuf_alloc_failed++;
1536                                         rxq->rx_alloc_errors++;
1537                                         break;
1538                                 }
1539                                 rxq->rx_segs++;
1540                         }
1541                 }
1542                 rxq->rx_segs++; /* for the first segment */
1543
1544                 /* Prefetch next mbuf while processing current one. */
1545                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1546                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1547
1548                 /* Update rest of the MBUF fields */
1549                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1550                 rx_mb->port = rxq->port_id;
1551                 rx_mb->ol_flags = ol_flags;
1552                 rx_mb->data_len = len;
1553                 rx_mb->packet_type = packet_type;
1554 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1555                 print_rx_bd_info(rx_mb, rxq, bitfield_val);
1556 #endif
1557                 if (!tpa_start_flg) {
1558                         rx_mb->nb_segs = fp_cqe->bd_num;
1559                         rx_mb->pkt_len = pkt_len;
1560                 } else {
1561                         /* store ref to the updated mbuf */
1562                         tpa_info->tpa_head = rx_mb;
1563                         tpa_info->tpa_tail = tpa_info->tpa_head;
1564                 }
1565                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1566 tpa_end:
1567                 if (!tpa_start_flg) {
1568                         rx_pkts[rx_pkt] = rx_mb;
1569                         rx_pkt++;
1570                 }
1571 next_cqe:
1572                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1573                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1574                 if (rx_pkt == nb_pkts) {
1575                         PMD_RX_LOG(DEBUG, rxq,
1576                                    "Budget reached nb_pkts=%u received=%u",
1577                                    rx_pkt, nb_pkts);
1578                         break;
1579                 }
1580         }
1581
1582         qede_update_rx_prod(qdev, rxq);
1583
1584         rxq->rcv_pkts += rx_pkt;
1585
1586         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1587
1588         return rx_pkt;
1589 }
1590
1591
1592 /* Populate scatter gather buffer descriptor fields */
1593 static inline uint16_t
1594 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1595                   struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3,
1596                   uint16_t start_seg)
1597 {
1598         struct qede_tx_queue *txq = p_txq;
1599         struct eth_tx_bd *tx_bd = NULL;
1600         dma_addr_t mapping;
1601         uint16_t nb_segs = 0;
1602
1603         /* Check for scattered buffers */
1604         while (m_seg) {
1605                 if (start_seg == 0) {
1606                         if (!*bd2) {
1607                                 *bd2 = (struct eth_tx_2nd_bd *)
1608                                         ecore_chain_produce(&txq->tx_pbl);
1609                                 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
1610                                 nb_segs++;
1611                         }
1612                         mapping = rte_mbuf_data_iova(m_seg);
1613                         QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
1614                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
1615                 } else if (start_seg == 1) {
1616                         if (!*bd3) {
1617                                 *bd3 = (struct eth_tx_3rd_bd *)
1618                                         ecore_chain_produce(&txq->tx_pbl);
1619                                 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
1620                                 nb_segs++;
1621                         }
1622                         mapping = rte_mbuf_data_iova(m_seg);
1623                         QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
1624                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
1625                 } else {
1626                         tx_bd = (struct eth_tx_bd *)
1627                                 ecore_chain_produce(&txq->tx_pbl);
1628                         memset(tx_bd, 0, sizeof(*tx_bd));
1629                         nb_segs++;
1630                         mapping = rte_mbuf_data_iova(m_seg);
1631                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1632                         PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
1633                 }
1634                 start_seg++;
1635                 m_seg = m_seg->next;
1636         }
1637
1638         /* Return total scattered buffers */
1639         return nb_segs;
1640 }
1641
1642 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1643 static inline void
1644 print_tx_bd_info(struct qede_tx_queue *txq,
1645                  struct eth_tx_1st_bd *bd1,
1646                  struct eth_tx_2nd_bd *bd2,
1647                  struct eth_tx_3rd_bd *bd3,
1648                  uint64_t tx_ol_flags)
1649 {
1650         char ol_buf[256] = { 0 }; /* for verbose prints */
1651
1652         if (bd1)
1653                 PMD_TX_LOG(INFO, txq,
1654                    "BD1: nbytes=0x%04x nbds=0x%04x bd_flags=0x%04x bf=0x%04x",
1655                    rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
1656                    bd1->data.bd_flags.bitfields,
1657                    rte_cpu_to_le_16(bd1->data.bitfields));
1658         if (bd2)
1659                 PMD_TX_LOG(INFO, txq,
1660                    "BD2: nbytes=0x%04x bf1=0x%04x bf2=0x%04x tunn_ip=0x%04x\n",
1661                    rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1,
1662                    bd2->data.bitfields2, bd2->data.tunn_ip_size);
1663         if (bd3)
1664                 PMD_TX_LOG(INFO, txq,
1665                    "BD3: nbytes=0x%04x bf=0x%04x MSS=0x%04x "
1666                    "tunn_l4_hdr_start_offset_w=0x%04x tunn_hdr_size=0x%04x\n",
1667                    rte_cpu_to_le_16(bd3->nbytes),
1668                    rte_cpu_to_le_16(bd3->data.bitfields),
1669                    rte_cpu_to_le_16(bd3->data.lso_mss),
1670                    bd3->data.tunn_l4_hdr_start_offset_w,
1671                    bd3->data.tunn_hdr_size_w);
1672
1673         rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
1674         PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
1675 }
1676 #endif
1677
1678 /* TX prepare to check packets meets TX conditions */
1679 uint16_t
1680 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1681 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
1682                     uint16_t nb_pkts)
1683 {
1684         struct qede_tx_queue *txq = p_txq;
1685 #else
1686 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
1687                     uint16_t nb_pkts)
1688 {
1689 #endif
1690         uint64_t ol_flags;
1691         struct rte_mbuf *m;
1692         uint16_t i;
1693 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1694         int ret;
1695 #endif
1696
1697         for (i = 0; i < nb_pkts; i++) {
1698                 m = tx_pkts[i];
1699                 ol_flags = m->ol_flags;
1700                 if (ol_flags & PKT_TX_TCP_SEG) {
1701                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
1702                                 rte_errno = -EINVAL;
1703                                 break;
1704                         }
1705                         /* TBD: confirm its ~9700B for both ? */
1706                         if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
1707                                 rte_errno = -EINVAL;
1708                                 break;
1709                         }
1710                 } else {
1711                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
1712                                 rte_errno = -EINVAL;
1713                                 break;
1714                         }
1715                 }
1716                 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
1717                         rte_errno = -ENOTSUP;
1718                         break;
1719                 }
1720
1721 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1722                 ret = rte_validate_tx_offload(m);
1723                 if (ret != 0) {
1724                         rte_errno = ret;
1725                         break;
1726                 }
1727 #endif
1728         }
1729
1730 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1731         if (unlikely(i != nb_pkts))
1732                 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
1733                            nb_pkts - i);
1734 #endif
1735         return i;
1736 }
1737
1738 #define MPLSINUDP_HDR_SIZE                      (12)
1739
1740 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1741 static inline void
1742 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
1743                                struct qede_tx_queue *txq)
1744 {
1745         if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
1746                 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
1747         if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
1748                 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
1749                 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
1750         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
1751                 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
1752                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1753         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
1754                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
1755                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1756 }
1757 #endif
1758
1759 uint16_t
1760 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1761 {
1762         struct qede_tx_queue *txq = p_txq;
1763         struct qede_dev *qdev = txq->qdev;
1764         struct ecore_dev *edev = &qdev->edev;
1765         struct rte_mbuf *mbuf;
1766         struct rte_mbuf *m_seg = NULL;
1767         uint16_t nb_tx_pkts;
1768         uint16_t bd_prod;
1769         uint16_t idx;
1770         uint16_t nb_frags;
1771         uint16_t nb_pkt_sent = 0;
1772         uint8_t nbds;
1773         bool lso_flg;
1774         bool mplsoudp_flg;
1775         __rte_unused bool tunn_flg;
1776         bool tunn_ipv6_ext_flg;
1777         struct eth_tx_1st_bd *bd1;
1778         struct eth_tx_2nd_bd *bd2;
1779         struct eth_tx_3rd_bd *bd3;
1780         uint64_t tx_ol_flags;
1781         uint16_t hdr_size;
1782         /* BD1 */
1783         uint16_t bd1_bf;
1784         uint8_t bd1_bd_flags_bf;
1785         uint16_t vlan;
1786         /* BD2 */
1787         uint16_t bd2_bf1;
1788         uint16_t bd2_bf2;
1789         /* BD3 */
1790         uint16_t mss;
1791         uint16_t bd3_bf;
1792
1793         uint8_t tunn_l4_hdr_start_offset;
1794         uint8_t tunn_hdr_size;
1795         uint8_t inner_l2_hdr_size;
1796         uint16_t inner_l4_hdr_offset;
1797
1798         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1799                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1800                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1801                 qede_process_tx_compl(edev, txq);
1802         }
1803
1804         nb_tx_pkts  = nb_pkts;
1805         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1806         while (nb_tx_pkts--) {
1807                 /* Init flags/values */
1808                 tunn_flg = false;
1809                 lso_flg = false;
1810                 nbds = 0;
1811                 vlan = 0;
1812                 bd1 = NULL;
1813                 bd2 = NULL;
1814                 bd3 = NULL;
1815                 hdr_size = 0;
1816                 bd1_bf = 0;
1817                 bd1_bd_flags_bf = 0;
1818                 bd2_bf1 = 0;
1819                 bd2_bf2 = 0;
1820                 mss = 0;
1821                 bd3_bf = 0;
1822                 mplsoudp_flg = false;
1823                 tunn_ipv6_ext_flg = false;
1824                 tunn_hdr_size = 0;
1825                 tunn_l4_hdr_start_offset = 0;
1826
1827                 mbuf = *tx_pkts++;
1828                 assert(mbuf);
1829
1830                 /* Check minimum TX BDS availability against available BDs */
1831                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
1832                         break;
1833
1834                 tx_ol_flags = mbuf->ol_flags;
1835                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1836
1837                 /* TX prepare would have already checked supported tunnel Tx
1838                  * offloads. Don't rely on pkt_type marked by Rx, instead use
1839                  * tx_ol_flags to decide.
1840                  */
1841                 tunn_flg = !!(tx_ol_flags & PKT_TX_TUNNEL_MASK);
1842
1843                 if (tunn_flg) {
1844                         /* Check against max which is Tunnel IPv6 + ext */
1845                         if (unlikely(txq->nb_tx_avail <
1846                                 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
1847                                         break;
1848
1849                         /* First indicate its a tunnel pkt */
1850                         bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1851                                   ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1852                         /* Legacy FW had flipped behavior in regard to this bit
1853                          * i.e. it needed to set to prevent FW from touching
1854                          * encapsulated packets when it didn't need to.
1855                          */
1856                         if (unlikely(txq->is_legacy)) {
1857                                 bd1_bf ^= 1 <<
1858                                         ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1859                         }
1860
1861                         /* Outer IP checksum offload */
1862                         if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
1863                                            PKT_TX_OUTER_IPV4)) {
1864                                 bd1_bd_flags_bf |=
1865                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1866                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1867                         }
1868
1869                         /**
1870                          * Currently, only inner checksum offload in MPLS-in-UDP
1871                          * tunnel with one MPLS label is supported. Both outer
1872                          * and inner layers  lengths need to be provided in
1873                          * mbuf.
1874                          */
1875                         if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1876                                                 PKT_TX_TUNNEL_MPLSINUDP) {
1877                                 mplsoudp_flg = true;
1878 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1879                                 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
1880 #endif
1881                                 /* Outer L4 offset in two byte words */
1882                                 tunn_l4_hdr_start_offset =
1883                                   (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
1884                                 /* Tunnel header size in two byte words */
1885                                 tunn_hdr_size = (mbuf->outer_l2_len +
1886                                                 mbuf->outer_l3_len +
1887                                                 MPLSINUDP_HDR_SIZE) / 2;
1888                                 /* Inner L2 header size in two byte words */
1889                                 inner_l2_hdr_size = (mbuf->l2_len -
1890                                                 MPLSINUDP_HDR_SIZE) / 2;
1891                                 /* Inner L4 header offset from the beggining
1892                                  * of inner packet in two byte words
1893                                  */
1894                                 inner_l4_hdr_offset = (mbuf->l2_len -
1895                                         MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
1896
1897                                 /* Inner L2 size and address type */
1898                                 bd2_bf1 |= (inner_l2_hdr_size &
1899                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
1900                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
1901                                 bd2_bf1 |= (UNICAST_ADDRESS &
1902                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
1903                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
1904                                 /* Treated as IPv6+Ext */
1905                                 bd2_bf1 |=
1906                                     1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
1907
1908                                 /* Mark inner IPv6 if present */
1909                                 if (tx_ol_flags & PKT_TX_IPV6)
1910                                         bd2_bf1 |=
1911                                                 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
1912
1913                                 /* Inner L4 offsets */
1914                                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1915                                      (tx_ol_flags & (PKT_TX_UDP_CKSUM |
1916                                                         PKT_TX_TCP_CKSUM))) {
1917                                         /* Determines if BD3 is needed */
1918                                         tunn_ipv6_ext_flg = true;
1919                                         if ((tx_ol_flags & PKT_TX_L4_MASK) ==
1920                                                         PKT_TX_UDP_CKSUM) {
1921                                                 bd2_bf1 |=
1922                                                         1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
1923                                         }
1924
1925                                         /* TODO other pseudo checksum modes are
1926                                          * not supported
1927                                          */
1928                                         bd2_bf1 |=
1929                                         ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
1930                                         ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
1931                                         bd2_bf2 |= (inner_l4_hdr_offset &
1932                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
1933                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
1934                                 }
1935                         } /* End MPLSoUDP */
1936                 } /* End Tunnel handling */
1937
1938                 if (tx_ol_flags & PKT_TX_TCP_SEG) {
1939                         lso_flg = true;
1940                         if (unlikely(txq->nb_tx_avail <
1941                                                 ETH_TX_MIN_BDS_PER_LSO_PKT))
1942                                 break;
1943                         /* For LSO, packet header and payload must reside on
1944                          * buffers pointed by different BDs. Using BD1 for HDR
1945                          * and BD2 onwards for data.
1946                          */
1947                         hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
1948                         if (tunn_flg)
1949                                 hdr_size += mbuf->outer_l2_len +
1950                                             mbuf->outer_l3_len;
1951
1952                         bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
1953                         bd1_bd_flags_bf |=
1954                                         1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1955                         /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
1956                         bd1_bd_flags_bf |=
1957                                         1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1958                         mss = rte_cpu_to_le_16(mbuf->tso_segsz);
1959                         /* Using one header BD */
1960                         bd3_bf |= rte_cpu_to_le_16(1 <<
1961                                         ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
1962                 } else {
1963                         if (unlikely(txq->nb_tx_avail <
1964                                         ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
1965                                 break;
1966                         bd1_bf |=
1967                                (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1968                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1969                 }
1970
1971                 /* Descriptor based VLAN insertion */
1972                 if (tx_ol_flags & PKT_TX_VLAN_PKT) {
1973                         vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1974                         bd1_bd_flags_bf |=
1975                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1976                 }
1977
1978                 /* Offload the IP checksum in the hardware */
1979                 if (tx_ol_flags & PKT_TX_IP_CKSUM) {
1980                         bd1_bd_flags_bf |=
1981                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1982                         /* There's no DPDK flag to request outer-L4 csum
1983                          * offload. But in the case of tunnel if inner L3 or L4
1984                          * csum offload is requested then we need to force
1985                          * recalculation of L4 tunnel header csum also.
1986                          */
1987                         if (tunn_flg && ((tx_ol_flags & PKT_TX_TUNNEL_MASK) !=
1988                                                         PKT_TX_TUNNEL_GRE)) {
1989                                 bd1_bd_flags_bf |=
1990                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1991                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1992                         }
1993                 }
1994
1995                 /* L4 checksum offload (tcp or udp) */
1996                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1997                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
1998                         bd1_bd_flags_bf |=
1999                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2000                         /* There's no DPDK flag to request outer-L4 csum
2001                          * offload. But in the case of tunnel if inner L3 or L4
2002                          * csum offload is requested then we need to force
2003                          * recalculation of L4 tunnel header csum also.
2004                          */
2005                         if (tunn_flg) {
2006                                 bd1_bd_flags_bf |=
2007                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2008                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2009                         }
2010                 }
2011
2012                 /* Fill the entry in the SW ring and the BDs in the FW ring */
2013                 idx = TX_PROD(txq);
2014                 txq->sw_tx_ring[idx].mbuf = mbuf;
2015
2016                 /* BD1 */
2017                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2018                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2019                 nbds++;
2020
2021                 /* Map MBUF linear data for DMA and set in the BD1 */
2022                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2023                                      mbuf->data_len);
2024                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2025                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2026                 bd1->data.vlan = vlan;
2027
2028                 if (lso_flg || mplsoudp_flg) {
2029                         bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
2030                                                         (&txq->tx_pbl);
2031                         memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
2032                         nbds++;
2033
2034                         /* BD1 */
2035                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2036                                              hdr_size);
2037                         /* BD2 */
2038                         QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
2039                                              rte_mbuf_data_iova(mbuf)),
2040                                              mbuf->data_len - hdr_size);
2041                         bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
2042                         if (mplsoudp_flg) {
2043                                 bd2->data.bitfields2 =
2044                                         rte_cpu_to_le_16(bd2_bf2);
2045                                 /* Outer L3 size */
2046                                 bd2->data.tunn_ip_size =
2047                                         rte_cpu_to_le_16(mbuf->outer_l3_len);
2048                         }
2049                         /* BD3 */
2050                         if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
2051                                 bd3 = (struct eth_tx_3rd_bd *)
2052                                         ecore_chain_produce(&txq->tx_pbl);
2053                                 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
2054                                 nbds++;
2055                                 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
2056                                 if (lso_flg)
2057                                         bd3->data.lso_mss = mss;
2058                                 if (mplsoudp_flg) {
2059                                         bd3->data.tunn_l4_hdr_start_offset_w =
2060                                                 tunn_l4_hdr_start_offset;
2061                                         bd3->data.tunn_hdr_size_w =
2062                                                 tunn_hdr_size;
2063                                 }
2064                         }
2065                 }
2066
2067                 /* Handle fragmented MBUF */
2068                 m_seg = mbuf->next;
2069
2070                 /* Encode scatter gather buffer descriptors if required */
2071                 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3, nbds - 1);
2072                 bd1->data.nbds = nbds + nb_frags;
2073
2074                 txq->nb_tx_avail -= bd1->data.nbds;
2075                 txq->sw_tx_prod++;
2076                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
2077                 bd_prod =
2078                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2079 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2080                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2081 #endif
2082                 nb_pkt_sent++;
2083                 txq->xmit_pkts++;
2084         }
2085
2086         /* Write value of prod idx into bd_prod */
2087         txq->tx_db.data.bd_prod = bd_prod;
2088         rte_wmb();
2089         rte_compiler_barrier();
2090         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2091         rte_wmb();
2092
2093         /* Check again for Tx completions */
2094         qede_process_tx_compl(edev, txq);
2095
2096         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2097                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2098
2099         return nb_pkt_sent;
2100 }
2101
2102 uint16_t
2103 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
2104                      __rte_unused struct rte_mbuf **pkts,
2105                      __rte_unused uint16_t nb_pkts)
2106 {
2107         return 0;
2108 }