drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_rxtx.h"
  10
  11 static bool gro_disable = 1;    /* mod_param */
  12
  13 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  14 {
  15         struct rte_mbuf *new_mb = NULL;
  16         struct eth_rx_bd *rx_bd;
  17         dma_addr_t mapping;
  18         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  19
  20         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  21         if (unlikely(!new_mb)) {
  22                 PMD_RX_LOG(ERR, rxq,
  23                            "Failed to allocate rx buffer "
  24                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  25                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  26                            rte_mempool_avail_count(rxq->mb_pool),
  27                            rte_mempool_in_use_count(rxq->mb_pool));
  28                 return -ENOMEM;
  29         }
  30         rxq->sw_rx_ring[idx].mbuf = new_mb;
  31         rxq->sw_rx_ring[idx].page_offset = 0;
  32         mapping = rte_mbuf_data_dma_addr_default(new_mb);
  33         /* Advance PROD and get BD pointer */
  34         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  35         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  36         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  37         rxq->sw_rx_prod++;
  38         return 0;
  39 }
  40
  41 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
  42 {
  43         uint16_t i;
  44
  45         if (rxq->sw_rx_ring != NULL) {
  46                 for (i = 0; i < rxq->nb_rx_desc; i++) {
  47                         if (rxq->sw_rx_ring[i].mbuf != NULL) {
  48                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
  49                                 rxq->sw_rx_ring[i].mbuf = NULL;
  50                         }
  51                 }
  52         }
  53 }
  54
  55 void qede_rx_queue_release(void *rx_queue)
  56 {
  57         struct qede_rx_queue *rxq = rx_queue;
  58
  59         if (rxq != NULL) {
  60                 qede_rx_queue_release_mbufs(rxq);
  61                 rte_free(rxq->sw_rx_ring);
  62                 rxq->sw_rx_ring = NULL;
  63                 rte_free(rxq);
  64                 rxq = NULL;
  65         }
  66 }
  67
  68 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
  69 {
  70         unsigned int i;
  71
  72         PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs\n", txq->nb_tx_desc);
  73
  74         if (txq->sw_tx_ring) {
  75                 for (i = 0; i < txq->nb_tx_desc; i++) {
  76                         if (txq->sw_tx_ring[i].mbuf) {
  77                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
  78                                 txq->sw_tx_ring[i].mbuf = NULL;
  79                         }
  80                 }
  81         }
  82 }
  83
  84 int
  85 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  86                     uint16_t nb_desc, unsigned int socket_id,
  87                     const struct rte_eth_rxconf *rx_conf,
  88                     struct rte_mempool *mp)
  89 {
  90         struct qede_dev *qdev = dev->data->dev_private;
  91         struct ecore_dev *edev = &qdev->edev;
  92         struct rte_eth_dev_data *eth_data = dev->data;
  93         struct qede_rx_queue *rxq;
  94         uint16_t pkt_len = (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len;
  95         size_t size;
  96         uint16_t data_size;
  97         int rc;
  98         int i;
  99
 100         PMD_INIT_FUNC_TRACE(edev);
 101
 102         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 103         if (!rte_is_power_of_2(nb_desc)) {
 104                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 105                           nb_desc);
 106                 return -EINVAL;
 107         }
 108
 109         /* Free memory prior to re-allocation if needed... */
 110         if (dev->data->rx_queues[queue_idx] != NULL) {
 111                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
 112                 dev->data->rx_queues[queue_idx] = NULL;
 113         }
 114
 115         /* First allocate the rx queue data structure */
 116         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 117                                  RTE_CACHE_LINE_SIZE, socket_id);
 118
 119         if (!rxq) {
 120                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 121                           socket_id);
 122                 return -ENOMEM;
 123         }
 124
 125         rxq->qdev = qdev;
 126         rxq->mb_pool = mp;
 127         rxq->nb_rx_desc = nb_desc;
 128         rxq->queue_id = queue_idx;
 129         rxq->port_id = dev->data->port_id;
 130
 131         /* Sanity check */
 132         data_size = (uint16_t)rte_pktmbuf_data_room_size(mp) -
 133                                 RTE_PKTMBUF_HEADROOM;
 134
 135         if (pkt_len > data_size && !dev->data->scattered_rx) {
 136                 DP_ERR(edev, "MTU %u should not exceed dataroom %u\n",
 137                        pkt_len, data_size);
 138                 rte_free(rxq);
 139                 return -EINVAL;
 140         }
 141
 142         if (dev->data->scattered_rx)
 143                 rxq->rx_buf_size = data_size;
 144         else
 145                 rxq->rx_buf_size = pkt_len + QEDE_ETH_OVERHEAD;
 146
 147         qdev->mtu = pkt_len;
 148
 149         DP_INFO(edev, "MTU = %u ; RX buffer = %u\n",
 150                 qdev->mtu, rxq->rx_buf_size);
 151
 152         if (pkt_len > ETHER_MAX_LEN) {
 153                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
 154                 DP_NOTICE(edev, false, "jumbo frame enabled\n");
 155         } else {
 156                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
 157         }
 158
 159         /* Allocate the parallel driver ring for Rx buffers */
 160         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 161         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 162                                              RTE_CACHE_LINE_SIZE, socket_id);
 163         if (!rxq->sw_rx_ring) {
 164                 DP_NOTICE(edev, false,
 165                           "Unable to alloc memory for sw_rx_ring on socket %u\n",
 166                           socket_id);
 167                 rte_free(rxq);
 168                 rxq = NULL;
 169                 return -ENOMEM;
 170         }
 171
 172         /* Allocate FW Rx ring  */
 173         rc = qdev->ops->common->chain_alloc(edev,
 174                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 175                                             ECORE_CHAIN_MODE_NEXT_PTR,
 176                                             ECORE_CHAIN_CNT_TYPE_U16,
 177                                             rxq->nb_rx_desc,
 178                                             sizeof(struct eth_rx_bd),
 179                                             &rxq->rx_bd_ring);
 180
 181         if (rc != ECORE_SUCCESS) {
 182                 DP_NOTICE(edev, false,
 183                           "Unable to alloc memory for rxbd ring on socket %u\n",
 184                           socket_id);
 185                 rte_free(rxq->sw_rx_ring);
 186                 rxq->sw_rx_ring = NULL;
 187                 rte_free(rxq);
 188                 rxq = NULL;
 189                 return -ENOMEM;
 190         }
 191
 192         /* Allocate FW completion ring */
 193         rc = qdev->ops->common->chain_alloc(edev,
 194                                             ECORE_CHAIN_USE_TO_CONSUME,
 195                                             ECORE_CHAIN_MODE_PBL,
 196                                             ECORE_CHAIN_CNT_TYPE_U16,
 197                                             rxq->nb_rx_desc,
 198                                             sizeof(union eth_rx_cqe),
 199                                             &rxq->rx_comp_ring);
 200
 201         if (rc != ECORE_SUCCESS) {
 202                 DP_NOTICE(edev, false,
 203                           "Unable to alloc memory for cqe ring on socket %u\n",
 204                           socket_id);
 205                 /* TBD: Freeing RX BD ring */
 206                 rte_free(rxq->sw_rx_ring);
 207                 rxq->sw_rx_ring = NULL;
 208                 rte_free(rxq);
 209                 return -ENOMEM;
 210         }
 211
 212         /* Allocate buffers for the Rx ring */
 213         for (i = 0; i < rxq->nb_rx_desc; i++) {
 214                 rc = qede_alloc_rx_buffer(rxq);
 215                 if (rc) {
 216                         DP_NOTICE(edev, false,
 217                                   "RX buffer allocation failed at idx=%d\n", i);
 218                         goto err4;
 219                 }
 220         }
 221
 222         dev->data->rx_queues[queue_idx] = rxq;
 223
 224         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 225                   queue_idx, nb_desc, qdev->mtu, socket_id);
 226
 227         return 0;
 228 err4:
 229         qede_rx_queue_release(rxq);
 230         return -ENOMEM;
 231 }
 232
 233 void qede_tx_queue_release(void *tx_queue)
 234 {
 235         struct qede_tx_queue *txq = tx_queue;
 236
 237         if (txq != NULL) {
 238                 qede_tx_queue_release_mbufs(txq);
 239                 if (txq->sw_tx_ring) {
 240                         rte_free(txq->sw_tx_ring);
 241                         txq->sw_tx_ring = NULL;
 242                 }
 243                 rte_free(txq);
 244         }
 245         txq = NULL;
 246 }
 247
 248 int
 249 qede_tx_queue_setup(struct rte_eth_dev *dev,
 250                     uint16_t queue_idx,
 251                     uint16_t nb_desc,
 252                     unsigned int socket_id,
 253                     const struct rte_eth_txconf *tx_conf)
 254 {
 255         struct qede_dev *qdev = dev->data->dev_private;
 256         struct ecore_dev *edev = &qdev->edev;
 257         struct qede_tx_queue *txq;
 258         int rc;
 259
 260         PMD_INIT_FUNC_TRACE(edev);
 261
 262         if (!rte_is_power_of_2(nb_desc)) {
 263                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 264                        nb_desc);
 265                 return -EINVAL;
 266         }
 267
 268         /* Free memory prior to re-allocation if needed... */
 269         if (dev->data->tx_queues[queue_idx] != NULL) {
 270                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 271                 dev->data->tx_queues[queue_idx] = NULL;
 272         }
 273
 274         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 275                                  RTE_CACHE_LINE_SIZE, socket_id);
 276
 277         if (txq == NULL) {
 278                 DP_ERR(edev,
 279                        "Unable to allocate memory for txq on socket %u",
 280                        socket_id);
 281                 return -ENOMEM;
 282         }
 283
 284         txq->nb_tx_desc = nb_desc;
 285         txq->qdev = qdev;
 286         txq->port_id = dev->data->port_id;
 287
 288         rc = qdev->ops->common->chain_alloc(edev,
 289                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 290                                             ECORE_CHAIN_MODE_PBL,
 291                                             ECORE_CHAIN_CNT_TYPE_U16,
 292                                             txq->nb_tx_desc,
 293                                             sizeof(union eth_tx_bd_types),
 294                                             &txq->tx_pbl);
 295         if (rc != ECORE_SUCCESS) {
 296                 DP_ERR(edev,
 297                        "Unable to allocate memory for txbd ring on socket %u",
 298                        socket_id);
 299                 qede_tx_queue_release(txq);
 300                 return -ENOMEM;
 301         }
 302
 303         /* Allocate software ring */
 304         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 305                                              (sizeof(struct qede_tx_entry) *
 306                                               txq->nb_tx_desc),
 307                                              RTE_CACHE_LINE_SIZE, socket_id);
 308
 309         if (!txq->sw_tx_ring) {
 310                 DP_ERR(edev,
 311                        "Unable to allocate memory for txbd ring on socket %u",
 312                        socket_id);
 313                 qede_tx_queue_release(txq);
 314                 return -ENOMEM;
 315         }
 316
 317         txq->queue_id = queue_idx;
 318
 319         txq->nb_tx_avail = txq->nb_tx_desc;
 320
 321         txq->tx_free_thresh =
 322             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 323             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 324
 325         dev->data->tx_queues[queue_idx] = txq;
 326
 327         DP_INFO(edev,
 328                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 329                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 330
 331         return 0;
 332 }
 333
 334 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
 335 static void qede_init_fp(struct qede_dev *qdev)
 336 {
 337         struct qede_fastpath *fp;
 338         uint8_t i, rss_id, tc;
 339         int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
 340
 341         memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
 342                                            sizeof(*qdev->fp_array)));
 343         memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
 344                                            sizeof(*qdev->sb_array)));
 345         for_each_queue(i) {
 346                 fp = &qdev->fp_array[i];
 347                 if (fp_rx) {
 348                         fp->type = QEDE_FASTPATH_RX;
 349                         fp_rx--;
 350                 } else{
 351                         fp->type = QEDE_FASTPATH_TX;
 352                 }
 353                 fp->qdev = qdev;
 354                 fp->id = i;
 355                 fp->sb_info = &qdev->sb_array[i];
 356                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
 357         }
 358
 359         qdev->gro_disable = gro_disable;
 360 }
 361
 362 void qede_free_fp_arrays(struct qede_dev *qdev)
 363 {
 364         /* It asseumes qede_free_mem_load() is called before */
 365         if (qdev->fp_array != NULL) {
 366                 rte_free(qdev->fp_array);
 367                 qdev->fp_array = NULL;
 368         }
 369
 370         if (qdev->sb_array != NULL) {
 371                 rte_free(qdev->sb_array);
 372                 qdev->sb_array = NULL;
 373         }
 374 }
 375
 376 int qede_alloc_fp_array(struct qede_dev *qdev)
 377 {
 378         struct qede_fastpath *fp;
 379         struct ecore_dev *edev = &qdev->edev;
 380         int i;
 381
 382         qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
 383                                     sizeof(*qdev->fp_array),
 384                                     RTE_CACHE_LINE_SIZE);
 385
 386         if (!qdev->fp_array) {
 387                 DP_ERR(edev, "fp array allocation failed\n");
 388                 return -ENOMEM;
 389         }
 390
 391         qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
 392                                     sizeof(*qdev->sb_array),
 393                                     RTE_CACHE_LINE_SIZE);
 394
 395         if (!qdev->sb_array) {
 396                 DP_ERR(edev, "sb array allocation failed\n");
 397                 rte_free(qdev->fp_array);
 398                 return -ENOMEM;
 399         }
 400
 401         return 0;
 402 }
 403
 404 /* This function allocates fast-path status block memory */
 405 static int
 406 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 407                   uint16_t sb_id)
 408 {
 409         struct ecore_dev *edev = &qdev->edev;
 410         struct status_block *sb_virt;
 411         dma_addr_t sb_phys;
 412         int rc;
 413
 414         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
 415
 416         if (!sb_virt) {
 417                 DP_ERR(edev, "Status block allocation failed\n");
 418                 return -ENOMEM;
 419         }
 420
 421         rc = qdev->ops->common->sb_init(edev, sb_info,
 422                                         sb_virt, sb_phys, sb_id,
 423                                         QED_SB_TYPE_L2_QUEUE);
 424         if (rc) {
 425                 DP_ERR(edev, "Status block initialization failed\n");
 426                 /* TBD: No dma_free_coherent possible */
 427                 return rc;
 428         }
 429
 430         return 0;
 431 }
 432
 433 int qede_alloc_fp_resc(struct qede_dev *qdev)
 434 {
 435         struct ecore_dev *edev = &qdev->edev;
 436         struct qede_fastpath *fp;
 437         uint32_t num_sbs;
 438         uint16_t i;
 439         uint16_t sb_idx;
 440         int rc;
 441
 442         if (IS_VF(edev))
 443                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 444         else
 445                 num_sbs = ecore_cxt_get_proto_cid_count
 446                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 447
 448         if (num_sbs == 0) {
 449                 DP_ERR(edev, "No status blocks available\n");
 450                 return -EINVAL;
 451         }
 452
 453         if (qdev->fp_array)
 454                 qede_free_fp_arrays(qdev);
 455
 456         rc = qede_alloc_fp_array(qdev);
 457         if (rc != 0)
 458                 return rc;
 459
 460         qede_init_fp(qdev);
 461
 462         for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
 463                 fp = &qdev->fp_array[i];
 464                 if (IS_VF(edev))
 465                         sb_idx = i % num_sbs;
 466                 else
 467                         sb_idx = i;
 468                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 469                         qede_free_fp_arrays(qdev);
 470                         return -ENOMEM;
 471                 }
 472         }
 473
 474         return 0;
 475 }
 476
 477 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 478 {
 479         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 480
 481         qede_free_mem_load(eth_dev);
 482         qede_free_fp_arrays(qdev);
 483 }
 484
 485 static inline void
 486 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
 487 {
 488         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 489         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 490         struct eth_rx_prod_data rx_prods = { 0 };
 491
 492         /* Update producers */
 493         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 494         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 495
 496         /* Make sure that the BD and SGE data is updated before updating the
 497          * producers since FW might read the BD/SGE right after the producer
 498          * is updated.
 499          */
 500         rte_wmb();
 501
 502         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 503                         (uint32_t *)&rx_prods);
 504
 505         /* mmiowb is needed to synchronize doorbell writes from more than one
 506          * processor. It guarantees that the write arrives to the device before
 507          * the napi lock is released and another qede_poll is called (possibly
 508          * on another CPU). Without this barrier, the next doorbell can bypass
 509          * this doorbell. This is applicable to IA64/Altix systems.
 510          */
 511         rte_wmb();
 512
 513         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u\n", bd_prod, cqe_prod);
 514 }
 515
 516 static inline uint32_t
 517 qede_rxfh_indir_default(uint32_t index, uint32_t n_rx_rings)
 518 {
 519         return index % n_rx_rings;
 520 }
 521
 522 static void qede_prandom_bytes(uint32_t *buff, size_t bytes)
 523 {
 524         unsigned int i;
 525
 526         srand((unsigned int)time(NULL));
 527
 528         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 529                 buff[i] = rand();
 530 }
 531
 532 static bool
 533 qede_check_vport_rss_enable(struct rte_eth_dev *eth_dev,
 534                             struct qed_update_vport_rss_params *rss_params)
 535 {
 536         struct rte_eth_rss_conf rss_conf;
 537         enum rte_eth_rx_mq_mode mode = eth_dev->data->dev_conf.rxmode.mq_mode;
 538         struct qede_dev *qdev = eth_dev->data->dev_private;
 539         struct ecore_dev *edev = &qdev->edev;
 540         uint8_t rss_caps;
 541         unsigned int i;
 542         uint64_t hf;
 543         uint32_t *key;
 544
 545         PMD_INIT_FUNC_TRACE(edev);
 546
 547         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 548         key = (uint32_t *)rss_conf.rss_key;
 549         hf = rss_conf.rss_hf;
 550
 551         /* Check if RSS conditions are met.
 552          * Note: Even though its meaningless to enable RSS with one queue, it
 553          * could be used to produce RSS Hash, so skipping that check.
 554          */
 555         if (!(mode & ETH_MQ_RX_RSS)) {
 556                 DP_INFO(edev, "RSS flag is not set\n");
 557                 return false;
 558         }
 559
 560         if (hf == 0) {
 561                 DP_INFO(edev, "Request to disable RSS\n");
 562                 return false;
 563         }
 564
 565         memset(rss_params, 0, sizeof(*rss_params));
 566
 567         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 568                 rss_params->rss_ind_table[i] = qede_rxfh_indir_default(i,
 569                                                         QEDE_RSS_COUNT(qdev));
 570
 571         if (!key)
 572                 qede_prandom_bytes(rss_params->rss_key,
 573                                    sizeof(rss_params->rss_key));
 574         else
 575                 memcpy(rss_params->rss_key, rss_conf.rss_key,
 576                        rss_conf.rss_key_len);
 577
 578         qede_init_rss_caps(&rss_caps, hf);
 579
 580         rss_params->rss_caps = rss_caps;
 581
 582         DP_INFO(edev, "RSS conditions are met\n");
 583
 584         return true;
 585 }
 586
 587 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
 588 {
 589         struct qede_dev *qdev = eth_dev->data->dev_private;
 590         struct ecore_dev *edev = &qdev->edev;
 591         struct ecore_queue_start_common_params q_params;
 592         struct qed_update_vport_rss_params *rss_params = &qdev->rss_params;
 593         struct qed_dev_info *qed_info = &qdev->dev_info.common;
 594         struct qed_update_vport_params vport_update_params;
 595         struct qede_tx_queue *txq;
 596         struct qede_fastpath *fp;
 597         dma_addr_t p_phys_table;
 598         int txq_index;
 599         uint16_t page_cnt;
 600         int vlan_removal_en = 1;
 601         int rc, tc, i;
 602
 603         for_each_queue(i) {
 604                 fp = &qdev->fp_array[i];
 605                 if (fp->type & QEDE_FASTPATH_RX) {
 606                         p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->
 607                                                                 rx_comp_ring);
 608                         page_cnt = ecore_chain_get_page_cnt(&fp->rxq->
 609                                                                 rx_comp_ring);
 610
 611                         memset(&q_params, 0, sizeof(q_params));
 612                         q_params.queue_id = i;
 613                         q_params.vport_id = 0;
 614                         q_params.sb = fp->sb_info->igu_sb_id;
 615                         q_params.sb_idx = RX_PI;
 616
 617                         ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 618
 619                         rc = qdev->ops->q_rx_start(edev, i, &q_params,
 620                                            fp->rxq->rx_buf_size,
 621                                            fp->rxq->rx_bd_ring.p_phys_addr,
 622                                            p_phys_table,
 623                                            page_cnt,
 624                                            &fp->rxq->hw_rxq_prod_addr);
 625                         if (rc) {
 626                                 DP_ERR(edev, "Start rxq #%d failed %d\n",
 627                                        fp->rxq->queue_id, rc);
 628                                 return rc;
 629                         }
 630
 631                         fp->rxq->hw_cons_ptr =
 632                                         &fp->sb_info->sb_virt->pi_array[RX_PI];
 633
 634                         qede_update_rx_prod(qdev, fp->rxq);
 635                 }
 636
 637                 if (!(fp->type & QEDE_FASTPATH_TX))
 638                         continue;
 639                 for (tc = 0; tc < qdev->num_tc; tc++) {
 640                         txq = fp->txqs[tc];
 641                         txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
 642
 643                         p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 644                         page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 645
 646                         memset(&q_params, 0, sizeof(q_params));
 647                         q_params.queue_id = txq->queue_id;
 648                         q_params.vport_id = 0;
 649                         q_params.sb = fp->sb_info->igu_sb_id;
 650                         q_params.sb_idx = TX_PI(tc);
 651
 652                         rc = qdev->ops->q_tx_start(edev, i, &q_params,
 653                                                    p_phys_table,
 654                                                    page_cnt, /* **pp_doorbell */
 655                                                    &txq->doorbell_addr);
 656                         if (rc) {
 657                                 DP_ERR(edev, "Start txq %u failed %d\n",
 658                                        txq_index, rc);
 659                                 return rc;
 660                         }
 661
 662                         txq->hw_cons_ptr =
 663                             &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
 664                         SET_FIELD(txq->tx_db.data.params,
 665                                   ETH_DB_DATA_DEST, DB_DEST_XCM);
 666                         SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 667                                   DB_AGG_CMD_SET);
 668                         SET_FIELD(txq->tx_db.data.params,
 669                                   ETH_DB_DATA_AGG_VAL_SEL,
 670                                   DQ_XCM_ETH_TX_BD_PROD_CMD);
 671
 672                         txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 673                 }
 674         }
 675
 676         /* Prepare and send the vport enable */
 677         memset(&vport_update_params, 0, sizeof(vport_update_params));
 678         /* Update MTU via vport update */
 679         vport_update_params.mtu = qdev->mtu;
 680         vport_update_params.vport_id = 0;
 681         vport_update_params.update_vport_active_flg = 1;
 682         vport_update_params.vport_active_flg = 1;
 683
 684         /* @DPDK */
 685         if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
 686                 /* TBD: Check SRIOV enabled for VF */
 687                 vport_update_params.update_tx_switching_flg = 1;
 688                 vport_update_params.tx_switching_flg = 1;
 689         }
 690
 691         if (qede_check_vport_rss_enable(eth_dev, rss_params)) {
 692                 vport_update_params.update_rss_flg = 1;
 693                 qdev->rss_enabled = 1;
 694         } else {
 695                 qdev->rss_enabled = 0;
 696         }
 697
 698         rte_memcpy(&vport_update_params.rss_params, rss_params,
 699                sizeof(*rss_params));
 700
 701         rc = qdev->ops->vport_update(edev, &vport_update_params);
 702         if (rc) {
 703                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 704                 return rc;
 705         }
 706
 707         return 0;
 708 }
 709
 710 #ifdef ENC_SUPPORTED
 711 static bool qede_tunn_exist(uint16_t flag)
 712 {
 713         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 714                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 715 }
 716
 717 static inline uint8_t qede_check_tunn_csum(uint16_t flag)
 718 {
 719         uint8_t tcsum = 0;
 720         uint16_t csum_flag = 0;
 721
 722         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 723              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 724                 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 725                     PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
 726
 727         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 728              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag) {
 729                 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 730                     PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
 731                 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
 732         }
 733
 734         csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
 735             PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
 736             PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 737             PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
 738
 739         if (csum_flag & flag)
 740                 return QEDE_CSUM_ERROR;
 741
 742         return QEDE_CSUM_UNNECESSARY | tcsum;
 743 }
 744 #else
 745 static inline uint8_t qede_tunn_exist(uint16_t flag)
 746 {
 747         return 0;
 748 }
 749
 750 static inline uint8_t qede_check_tunn_csum(uint16_t flag)
 751 {
 752         return 0;
 753 }
 754 #endif
 755
 756 static inline uint8_t qede_check_notunn_csum(uint16_t flag)
 757 {
 758         uint8_t csum = 0;
 759         uint16_t csum_flag = 0;
 760
 761         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 762              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag) {
 763                 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 764                     PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
 765                 csum = QEDE_CSUM_UNNECESSARY;
 766         }
 767
 768         csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 769             PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
 770
 771         if (csum_flag & flag)
 772                 return QEDE_CSUM_ERROR;
 773
 774         return csum;
 775 }
 776
 777 static inline uint8_t qede_check_csum(uint16_t flag)
 778 {
 779         if (likely(!qede_tunn_exist(flag)))
 780                 return qede_check_notunn_csum(flag);
 781         else
 782                 return qede_check_tunn_csum(flag);
 783 }
 784
 785 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
 786 {
 787         ecore_chain_consume(&rxq->rx_bd_ring);
 788         rxq->sw_rx_cons++;
 789 }
 790
 791 static inline void
 792 qede_reuse_page(struct qede_dev *qdev,
 793                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
 794 {
 795         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
 796         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 797         struct qede_rx_entry *curr_prod;
 798         dma_addr_t new_mapping;
 799
 800         curr_prod = &rxq->sw_rx_ring[idx];
 801         *curr_prod = *curr_cons;
 802
 803         new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
 804                       curr_prod->page_offset;
 805
 806         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
 807         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
 808
 809         rxq->sw_rx_prod++;
 810 }
 811
 812 static inline void
 813 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
 814                         struct qede_dev *qdev, uint8_t count)
 815 {
 816         struct qede_rx_entry *curr_cons;
 817
 818         for (; count > 0; count--) {
 819                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
 820                 qede_reuse_page(qdev, rxq, curr_cons);
 821                 qede_rx_bd_ring_consume(rxq);
 822         }
 823 }
 824
 825 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 826 {
 827         uint32_t p_type;
 828         /* TBD - L4 indications needed ? */
 829         uint16_t protocol = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 830                               PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) & flags);
 831
 832         /* protocol = 3 means LLC/SNAP over Ethernet */
 833         if (unlikely(protocol == 0 || protocol == 3))
 834                 p_type = RTE_PTYPE_UNKNOWN;
 835         else if (protocol == 1)
 836                 p_type = RTE_PTYPE_L3_IPV4;
 837         else if (protocol == 2)
 838                 p_type = RTE_PTYPE_L3_IPV6;
 839
 840         return RTE_PTYPE_L2_ETHER | p_type;
 841 }
 842
 843 int qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
 844                          int num_segs, uint16_t pkt_len)
 845 {
 846         struct qede_rx_queue *rxq = p_rxq;
 847         struct qede_dev *qdev = rxq->qdev;
 848         struct ecore_dev *edev = &qdev->edev;
 849         uint16_t sw_rx_index, cur_size;
 850
 851         register struct rte_mbuf *seg1 = NULL;
 852         register struct rte_mbuf *seg2 = NULL;
 853
 854         seg1 = rx_mb;
 855         while (num_segs) {
 856                 cur_size = pkt_len > rxq->rx_buf_size ?
 857                                 rxq->rx_buf_size : pkt_len;
 858                 if (!cur_size) {
 859                         PMD_RX_LOG(DEBUG, rxq,
 860                                    "SG packet, len and num BD mismatch\n");
 861                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
 862                         return -EINVAL;
 863                 }
 864
 865                 if (qede_alloc_rx_buffer(rxq)) {
 866                         uint8_t index;
 867
 868                         PMD_RX_LOG(DEBUG, rxq, "Buffer allocation failed\n");
 869                         index = rxq->port_id;
 870                         rte_eth_devices[index].data->rx_mbuf_alloc_failed++;
 871                         rxq->rx_alloc_errors++;
 872                         return -ENOMEM;
 873                 }
 874
 875                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 876                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
 877                 qede_rx_bd_ring_consume(rxq);
 878                 pkt_len -= cur_size;
 879                 seg2->data_len = cur_size;
 880                 seg1->next = seg2;
 881                 seg1 = seg1->next;
 882                 num_segs--;
 883                 rxq->rx_segs++;
 884                 continue;
 885         }
 886         seg1 = NULL;
 887
 888         if (pkt_len)
 889                 PMD_RX_LOG(DEBUG, rxq,
 890                            "Mapped all BDs of jumbo, but still have %d bytes\n",
 891                            pkt_len);
 892
 893         return ECORE_SUCCESS;
 894 }
 895
 896 uint16_t
 897 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 898 {
 899         struct qede_rx_queue *rxq = p_rxq;
 900         struct qede_dev *qdev = rxq->qdev;
 901         struct ecore_dev *edev = &qdev->edev;
 902         struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
 903         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
 904         uint16_t rx_pkt = 0;
 905         union eth_rx_cqe *cqe;
 906         struct eth_fast_path_rx_reg_cqe *fp_cqe;
 907         register struct rte_mbuf *rx_mb = NULL;
 908         register struct rte_mbuf *seg1 = NULL;
 909         enum eth_rx_cqe_type cqe_type;
 910         uint16_t len, pad, preload_idx, pkt_len, parse_flag;
 911         uint8_t csum_flag, num_segs;
 912         enum rss_hash_type htype;
 913         int ret;
 914
 915         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
 916         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
 917
 918         rte_rmb();
 919
 920         if (hw_comp_cons == sw_comp_cons)
 921                 return 0;
 922
 923         while (sw_comp_cons != hw_comp_cons) {
 924                 /* Get the CQE from the completion ring */
 925                 cqe =
 926                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
 927                 cqe_type = cqe->fast_path_regular.type;
 928
 929                 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
 930                         PMD_RX_LOG(DEBUG, rxq, "Got a slowath CQE\n");
 931
 932                         qdev->ops->eth_cqe_completion(edev, fp->id,
 933                                 (struct eth_slow_path_rx_cqe *)cqe);
 934                         goto next_cqe;
 935                 }
 936
 937                 /* Get the data from the SW ring */
 938                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 939                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
 940                 assert(rx_mb != NULL);
 941
 942                 /* non GRO */
 943                 fp_cqe = &cqe->fast_path_regular;
 944
 945                 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
 946                 pad = fp_cqe->placement_offset;
 947                 assert((len + pad) <= rx_mb->buf_len);
 948
 949                 PMD_RX_LOG(DEBUG, rxq,
 950                            "CQE type = 0x%x, flags = 0x%x, vlan = 0x%x"
 951                            " len = %u, parsing_flags = %d\n",
 952                            cqe_type, fp_cqe->bitfields,
 953                            rte_le_to_cpu_16(fp_cqe->vlan_tag),
 954                            len, rte_le_to_cpu_16(fp_cqe->pars_flags.flags));
 955
 956                 /* If this is an error packet then drop it */
 957                 parse_flag =
 958                     rte_le_to_cpu_16(cqe->fast_path_regular.pars_flags.flags);
 959                 csum_flag = qede_check_csum(parse_flag);
 960                 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
 961                         PMD_RX_LOG(ERR, rxq,
 962                                    "CQE in CONS = %u has error, flags = 0x%x "
 963                                    "dropping incoming packet\n",
 964                                    sw_comp_cons, parse_flag);
 965                         rxq->rx_hw_errors++;
 966                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
 967                         goto next_cqe;
 968                 }
 969
 970                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 971                         PMD_RX_LOG(ERR, rxq,
 972                                    "New buffer allocation failed,"
 973                                    "dropping incoming packet\n");
 974                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
 975                         rte_eth_devices[rxq->port_id].
 976                             data->rx_mbuf_alloc_failed++;
 977                         rxq->rx_alloc_errors++;
 978                         break;
 979                 }
 980
 981                 qede_rx_bd_ring_consume(rxq);
 982
 983                 if (fp_cqe->bd_num > 1) {
 984                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
 985                         num_segs = fp_cqe->bd_num - 1;
 986
 987                         rxq->rx_segs++;
 988
 989                         pkt_len -= len;
 990                         seg1 = rx_mb;
 991                         ret = qede_process_sg_pkts(p_rxq, seg1, num_segs,
 992                                                    pkt_len);
 993                         if (ret != ECORE_SUCCESS) {
 994                                 qede_recycle_rx_bd_ring(rxq, qdev,
 995                                                         fp_cqe->bd_num);
 996                                 goto next_cqe;
 997                         }
 998                 }
 999
1000                 /* Prefetch next mbuf while processing current one. */
1001                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1002                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1003
1004                 /* Update MBUF fields */
1005                 rx_mb->ol_flags = 0;
1006                 rx_mb->data_off = pad + RTE_PKTMBUF_HEADROOM;
1007                 rx_mb->nb_segs = fp_cqe->bd_num;
1008                 rx_mb->data_len = len;
1009                 rx_mb->pkt_len = fp_cqe->pkt_len;
1010                 rx_mb->port = rxq->port_id;
1011                 rx_mb->packet_type = qede_rx_cqe_to_pkt_type(parse_flag);
1012
1013                 htype = (uint8_t)GET_FIELD(fp_cqe->bitfields,
1014                                 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1015                 if (qdev->rss_enabled && htype) {
1016                         rx_mb->ol_flags |= PKT_RX_RSS_HASH;
1017                         rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
1018                         PMD_RX_LOG(DEBUG, rxq, "Hash result 0x%x\n",
1019                                    rx_mb->hash.rss);
1020                 }
1021
1022                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1023
1024                 if (CQE_HAS_VLAN(parse_flag)) {
1025                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1026                         rx_mb->ol_flags |= PKT_RX_VLAN_PKT;
1027                 }
1028
1029                 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1030                         /* FW does not provide indication of Outer VLAN tag,
1031                          * which is always stripped, so vlan_tci_outer is set
1032                          * to 0. Here vlan_tag represents inner VLAN tag.
1033                          */
1034                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1035                         rx_mb->ol_flags |= PKT_RX_QINQ_PKT;
1036                         rx_mb->vlan_tci_outer = 0;
1037                 }
1038
1039                 rx_pkts[rx_pkt] = rx_mb;
1040                 rx_pkt++;
1041 next_cqe:
1042                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1043                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1044                 if (rx_pkt == nb_pkts) {
1045                         PMD_RX_LOG(DEBUG, rxq,
1046                                    "Budget reached nb_pkts=%u received=%u\n",
1047                                    rx_pkt, nb_pkts);
1048                         break;
1049                 }
1050         }
1051
1052         qede_update_rx_prod(qdev, rxq);
1053
1054         rxq->rcv_pkts += rx_pkt;
1055
1056         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d\n", rx_pkt, rte_lcore_id());
1057
1058         return rx_pkt;
1059 }
1060
1061 static inline int
1062 qede_free_tx_pkt(struct ecore_dev *edev, struct qede_tx_queue *txq)
1063 {
1064         uint16_t nb_segs, idx = TX_CONS(txq);
1065         struct eth_tx_bd *tx_data_bd;
1066         struct rte_mbuf *mbuf = txq->sw_tx_ring[idx].mbuf;
1067
1068         if (unlikely(!mbuf)) {
1069                 PMD_TX_LOG(ERR, txq, "null mbuf\n");
1070                 PMD_TX_LOG(ERR, txq,
1071                            "tx_desc %u tx_avail %u tx_cons %u tx_prod %u\n",
1072                            txq->nb_tx_desc, txq->nb_tx_avail, idx,
1073                            TX_PROD(txq));
1074                 return -1;
1075         }
1076
1077         nb_segs = mbuf->nb_segs;
1078         while (nb_segs) {
1079                 /* It's like consuming rxbuf in recv() */
1080                 ecore_chain_consume(&txq->tx_pbl);
1081                 txq->nb_tx_avail++;
1082                 nb_segs--;
1083         }
1084         rte_pktmbuf_free(mbuf);
1085         txq->sw_tx_ring[idx].mbuf = NULL;
1086
1087         return 0;
1088 }
1089
1090 static inline uint16_t
1091 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
1092 {
1093         uint16_t tx_compl = 0;
1094         uint16_t hw_bd_cons;
1095
1096         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1097         rte_compiler_barrier();
1098
1099         while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) {
1100                 if (qede_free_tx_pkt(edev, txq)) {
1101                         PMD_TX_LOG(ERR, txq,
1102                                    "hw_bd_cons = %u, chain_cons = %u\n",
1103                                    hw_bd_cons,
1104                                    ecore_chain_get_cons_idx(&txq->tx_pbl));
1105                         break;
1106                 }
1107                 txq->sw_tx_cons++;      /* Making TXD available */
1108                 tx_compl++;
1109         }
1110
1111         PMD_TX_LOG(DEBUG, txq, "Tx compl %u sw_tx_cons %u avail %u\n",
1112                    tx_compl, txq->sw_tx_cons, txq->nb_tx_avail);
1113         return tx_compl;
1114 }
1115
1116 /* Populate scatter gather buffer descriptor fields */
1117 static inline uint16_t qede_encode_sg_bd(struct qede_tx_queue *p_txq,
1118                                          struct rte_mbuf *m_seg,
1119                                          uint16_t count,
1120                                          struct eth_tx_1st_bd *bd1)
1121 {
1122         struct qede_tx_queue *txq = p_txq;
1123         struct eth_tx_2nd_bd *bd2 = NULL;
1124         struct eth_tx_3rd_bd *bd3 = NULL;
1125         struct eth_tx_bd *tx_bd = NULL;
1126         uint16_t nb_segs = count;
1127         dma_addr_t mapping;
1128
1129         /* Check for scattered buffers */
1130         while (m_seg) {
1131                 if (nb_segs == 1) {
1132                         bd2 = (struct eth_tx_2nd_bd *)
1133                                 ecore_chain_produce(&txq->tx_pbl);
1134                         memset(bd2, 0, sizeof(*bd2));
1135                         mapping = rte_mbuf_data_dma_addr(m_seg);
1136                         bd2->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1137                         bd2->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1138                         bd2->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1139                 } else if (nb_segs == 2) {
1140                         bd3 = (struct eth_tx_3rd_bd *)
1141                                 ecore_chain_produce(&txq->tx_pbl);
1142                         memset(bd3, 0, sizeof(*bd3));
1143                         mapping = rte_mbuf_data_dma_addr(m_seg);
1144                         bd3->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1145                         bd3->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1146                         bd3->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1147                 } else {
1148                         tx_bd = (struct eth_tx_bd *)
1149                                 ecore_chain_produce(&txq->tx_pbl);
1150                         memset(tx_bd, 0, sizeof(*tx_bd));
1151                         mapping = rte_mbuf_data_dma_addr(m_seg);
1152                         tx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1153                         tx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1154                         tx_bd->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1155                 }
1156                 nb_segs++;
1157                 bd1->data.nbds = nb_segs;
1158                 m_seg = m_seg->next;
1159         }
1160
1161         /* Return total scattered buffers */
1162         return nb_segs;
1163 }
1164
1165 uint16_t
1166 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1167 {
1168         struct qede_tx_queue *txq = p_txq;
1169         struct qede_dev *qdev = txq->qdev;
1170         struct ecore_dev *edev = &qdev->edev;
1171         struct qede_fastpath *fp;
1172         struct eth_tx_1st_bd *bd1;
1173         struct rte_mbuf *m_seg = NULL;
1174         uint16_t nb_tx_pkts;
1175         uint16_t nb_pkt_sent = 0;
1176         uint16_t bd_prod;
1177         uint16_t idx;
1178         uint16_t tx_count;
1179         uint16_t nb_segs = 0;
1180
1181         fp = &qdev->fp_array[QEDE_RSS_COUNT(qdev) + txq->queue_id];
1182
1183         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1184                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u\n",
1185                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1186                 (void)qede_process_tx_compl(edev, txq);
1187         }
1188
1189         nb_tx_pkts = RTE_MIN(nb_pkts, (txq->nb_tx_avail /
1190                         ETH_TX_MAX_BDS_PER_NON_LSO_PACKET));
1191         if (unlikely(nb_tx_pkts == 0)) {
1192                 PMD_TX_LOG(DEBUG, txq, "Out of BDs nb_pkts=%u avail=%u\n",
1193                            nb_pkts, txq->nb_tx_avail);
1194                 return 0;
1195         }
1196
1197         tx_count = nb_tx_pkts;
1198         while (nb_tx_pkts--) {
1199                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1200                 idx = TX_PROD(txq);
1201                 struct rte_mbuf *mbuf = *tx_pkts++;
1202
1203                 txq->sw_tx_ring[idx].mbuf = mbuf;
1204                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1205                 /* Zero init struct fields */
1206                 bd1->data.bd_flags.bitfields = 0;
1207                 bd1->data.bitfields = 0;
1208
1209                 bd1->data.bd_flags.bitfields =
1210                         1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1211                 /* Map MBUF linear data for DMA and set in the first BD */
1212                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1213                                      mbuf->pkt_len);
1214
1215                 /* Descriptor based VLAN insertion */
1216                 if (mbuf->ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1217                         bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1218                         bd1->data.bd_flags.bitfields |=
1219                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1220                 }
1221
1222                 /* Offload the IP checksum in the hardware */
1223                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1224                         bd1->data.bd_flags.bitfields |=
1225                             1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1226                 }
1227
1228                 /* L4 checksum offload (tcp or udp) */
1229                 if (mbuf->ol_flags & (PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
1230                         bd1->data.bd_flags.bitfields |=
1231                             1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1232                         /* IPv6 + extn. -> later */
1233                 }
1234
1235                 /* Handle fragmented MBUF */
1236                 m_seg = mbuf->next;
1237                 nb_segs++;
1238                 bd1->data.nbds = nb_segs;
1239                 /* Encode scatter gather buffer descriptors if required */
1240                 nb_segs = qede_encode_sg_bd(txq, m_seg, nb_segs, bd1);
1241                 txq->nb_tx_avail = txq->nb_tx_avail - nb_segs;
1242                 nb_segs = 0;
1243                 txq->sw_tx_prod++;
1244                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1245                 bd_prod =
1246                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1247                 nb_pkt_sent++;
1248                 txq->xmit_pkts++;
1249         }
1250
1251         /* Write value of prod idx into bd_prod */
1252         txq->tx_db.data.bd_prod = bd_prod;
1253         rte_wmb();
1254         rte_compiler_barrier();
1255         DIRECT_REG_WR(edev, txq->doorbell_addr, txq->tx_db.raw);
1256         rte_wmb();
1257
1258         /* Check again for Tx completions */
1259         (void)qede_process_tx_compl(edev, txq);
1260
1261         PMD_TX_LOG(DEBUG, txq, "to_send=%u can_send=%u sent=%u core=%d\n",
1262                    nb_pkts, tx_count, nb_pkt_sent, rte_lcore_id());
1263
1264         return nb_pkt_sent;
1265 }
1266
1267 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1268 {
1269         struct qede_dev *qdev = eth_dev->data->dev_private;
1270         struct qede_fastpath *fp;
1271         uint8_t i, rss_id, txq_index, tc;
1272         int rxq = 0, txq = 0;
1273
1274         for_each_queue(i) {
1275                 fp = &qdev->fp_array[i];
1276                 if (fp->type & QEDE_FASTPATH_RX) {
1277                         fp->rxq = eth_dev->data->rx_queues[i];
1278                         fp->rxq->queue_id = rxq++;
1279                 }
1280
1281                 if (fp->type & QEDE_FASTPATH_TX) {
1282                         for (tc = 0; tc < qdev->num_tc; tc++) {
1283                                 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1284                                 fp->txqs[tc] =
1285                                         eth_dev->data->tx_queues[txq_index];
1286                                 fp->txqs[tc]->queue_id = txq_index;
1287                         }
1288                         txq++;
1289                 }
1290         }
1291 }
1292
1293 int qede_dev_start(struct rte_eth_dev *eth_dev)
1294 {
1295         struct qede_dev *qdev = eth_dev->data->dev_private;
1296         struct ecore_dev *edev = &qdev->edev;
1297         struct qed_link_output link_output;
1298         struct qede_fastpath *fp;
1299         int rc, i;
1300
1301         DP_INFO(edev, "Device state is %d\n", qdev->state);
1302
1303         if (qdev->state == QEDE_DEV_START) {
1304                 DP_INFO(edev, "Port is already started\n");
1305                 return 0;
1306         }
1307
1308         if (qdev->state == QEDE_DEV_CONFIG)
1309                 qede_init_fp_queue(eth_dev);
1310
1311         rc = qede_start_queues(eth_dev, true);
1312         if (rc) {
1313                 DP_ERR(edev, "Failed to start queues\n");
1314                 /* TBD: free */
1315                 return rc;
1316         }
1317
1318         /* Bring-up the link */
1319         qede_dev_set_link_state(eth_dev, true);
1320
1321         /* Reset ring */
1322         if (qede_reset_fp_rings(qdev))
1323                 return -ENOMEM;
1324
1325         /* Start/resume traffic */
1326         qdev->ops->fastpath_start(edev);
1327
1328         qdev->state = QEDE_DEV_START;
1329
1330         DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1331
1332         return 0;
1333 }
1334
1335 static int qede_drain_txq(struct qede_dev *qdev,
1336                           struct qede_tx_queue *txq, bool allow_drain)
1337 {
1338         struct ecore_dev *edev = &qdev->edev;
1339         int rc, cnt = 1000;
1340
1341         while (txq->sw_tx_cons != txq->sw_tx_prod) {
1342                 qede_process_tx_compl(edev, txq);
1343                 if (!cnt) {
1344                         if (allow_drain) {
1345                                 DP_NOTICE(edev, false,
1346                                           "Tx queue[%u] is stuck,"
1347                                           "requesting MCP to drain\n",
1348                                           txq->queue_id);
1349                                 rc = qdev->ops->common->drain(edev);
1350                                 if (rc)
1351                                         return rc;
1352                                 return qede_drain_txq(qdev, txq, false);
1353                         }
1354
1355                         DP_NOTICE(edev, false,
1356                                   "Timeout waiting for tx queue[%d]:"
1357                                   "PROD=%d, CONS=%d\n",
1358                                   txq->queue_id, txq->sw_tx_prod,
1359                                   txq->sw_tx_cons);
1360                         return -ENODEV;
1361                 }
1362                 cnt--;
1363                 DELAY(1000);
1364                 rte_compiler_barrier();
1365         }
1366
1367         /* FW finished processing, wait for HW to transmit all tx packets */
1368         DELAY(2000);
1369
1370         return 0;
1371 }
1372
1373 static int qede_stop_queues(struct qede_dev *qdev)
1374 {
1375         struct qed_update_vport_params vport_update_params;
1376         struct ecore_dev *edev = &qdev->edev;
1377         int rc, tc, i;
1378
1379         /* Disable the vport */
1380         memset(&vport_update_params, 0, sizeof(vport_update_params));
1381         vport_update_params.vport_id = 0;
1382         vport_update_params.update_vport_active_flg = 1;
1383         vport_update_params.vport_active_flg = 0;
1384         vport_update_params.update_rss_flg = 0;
1385
1386         DP_INFO(edev, "Deactivate vport\n");
1387
1388         rc = qdev->ops->vport_update(edev, &vport_update_params);
1389         if (rc) {
1390                 DP_ERR(edev, "Failed to update vport\n");
1391                 return rc;
1392         }
1393
1394         DP_INFO(edev, "Flushing tx queues\n");
1395
1396         /* Flush Tx queues. If needed, request drain from MCP */
1397         for_each_queue(i) {
1398                 struct qede_fastpath *fp = &qdev->fp_array[i];
1399
1400                 if (fp->type & QEDE_FASTPATH_TX) {
1401                         for (tc = 0; tc < qdev->num_tc; tc++) {
1402                                 struct qede_tx_queue *txq = fp->txqs[tc];
1403
1404                                 rc = qede_drain_txq(qdev, txq, true);
1405                                 if (rc)
1406                                         return rc;
1407                         }
1408                 }
1409         }
1410
1411         /* Stop all Queues in reverse order */
1412         for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1413                 struct qed_stop_rxq_params rx_params;
1414
1415                 /* Stop the Tx Queue(s) */
1416                 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1417                         for (tc = 0; tc < qdev->num_tc; tc++) {
1418                                 struct qed_stop_txq_params tx_params;
1419                                 u8 val;
1420
1421                                 tx_params.rss_id = i;
1422                                 val = qdev->fp_array[i].txqs[tc]->queue_id;
1423                                 tx_params.tx_queue_id = val;
1424
1425                                 DP_INFO(edev, "Stopping tx queues\n");
1426                                 rc = qdev->ops->q_tx_stop(edev, &tx_params);
1427                                 if (rc) {
1428                                         DP_ERR(edev, "Failed to stop TXQ #%d\n",
1429                                                tx_params.tx_queue_id);
1430                                         return rc;
1431                                 }
1432                         }
1433                 }
1434
1435                 /* Stop the Rx Queue */
1436                 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1437                         memset(&rx_params, 0, sizeof(rx_params));
1438                         rx_params.rss_id = i;
1439                         rx_params.rx_queue_id = qdev->fp_array[i].rxq->queue_id;
1440                         rx_params.eq_completion_only = 1;
1441
1442                         DP_INFO(edev, "Stopping rx queues\n");
1443
1444                         rc = qdev->ops->q_rx_stop(edev, &rx_params);
1445                         if (rc) {
1446                                 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1447                                 return rc;
1448                         }
1449                 }
1450         }
1451
1452         return 0;
1453 }
1454
1455 int qede_reset_fp_rings(struct qede_dev *qdev)
1456 {
1457         struct qede_fastpath *fp;
1458         struct qede_tx_queue *txq;
1459         uint8_t tc;
1460         uint16_t id, i;
1461
1462         for_each_queue(id) {
1463                 fp = &qdev->fp_array[id];
1464
1465                 if (fp->type & QEDE_FASTPATH_RX) {
1466                         DP_INFO(&qdev->edev,
1467                                 "Reset FP chain for RSS %u\n", id);
1468                         qede_rx_queue_release_mbufs(fp->rxq);
1469                         ecore_chain_reset(&fp->rxq->rx_bd_ring);
1470                         ecore_chain_reset(&fp->rxq->rx_comp_ring);
1471                         fp->rxq->sw_rx_prod = 0;
1472                         fp->rxq->sw_rx_cons = 0;
1473                         *fp->rxq->hw_cons_ptr = 0;
1474                         for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1475                                 if (qede_alloc_rx_buffer(fp->rxq)) {
1476                                         DP_ERR(&qdev->edev,
1477                                                "RX buffer allocation failed\n");
1478                                         return -ENOMEM;
1479                                 }
1480                         }
1481                 }
1482                 if (fp->type & QEDE_FASTPATH_TX) {
1483                         for (tc = 0; tc < qdev->num_tc; tc++) {
1484                                 txq = fp->txqs[tc];
1485                                 qede_tx_queue_release_mbufs(txq);
1486                                 ecore_chain_reset(&txq->tx_pbl);
1487                                 txq->sw_tx_cons = 0;
1488                                 txq->sw_tx_prod = 0;
1489                                 *txq->hw_cons_ptr = 0;
1490                         }
1491                 }
1492         }
1493
1494         return 0;
1495 }
1496
1497 /* This function frees all memory of a single fp */
1498 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1499 {
1500         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1501         struct qede_fastpath *fp;
1502         uint16_t txq_idx;
1503         uint8_t id;
1504         uint8_t tc;
1505
1506         for_each_queue(id) {
1507                 fp = &qdev->fp_array[id];
1508                 if (fp->type & QEDE_FASTPATH_RX) {
1509                         qede_rx_queue_release(fp->rxq);
1510                         eth_dev->data->rx_queues[id] = NULL;
1511                 } else {
1512                         for (tc = 0; tc < qdev->num_tc; tc++) {
1513                                 txq_idx = fp->txqs[tc]->queue_id;
1514                                 qede_tx_queue_release(fp->txqs[tc]);
1515                                 eth_dev->data->tx_queues[txq_idx] = NULL;
1516                         }
1517                 }
1518         }
1519 }
1520
1521 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1522 {
1523         struct qede_dev *qdev = eth_dev->data->dev_private;
1524         struct ecore_dev *edev = &qdev->edev;
1525
1526         DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1527
1528         if (qdev->state != QEDE_DEV_START) {
1529                 DP_INFO(edev, "Device not yet started\n");
1530                 return;
1531         }
1532
1533         if (qede_stop_queues(qdev))
1534                 DP_ERR(edev, "Didn't succeed to close queues\n");
1535
1536         DP_INFO(edev, "Stopped queues\n");
1537
1538         qdev->ops->fastpath_stop(edev);
1539
1540         /* Bring the link down */
1541         qede_dev_set_link_state(eth_dev, false);
1542
1543         qdev->state = QEDE_DEV_STOP;
1544
1545         DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");
1546 }