drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include <rte_net.h>
  10 #include "qede_rxtx.h"
  11
  12 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  13 {
  14         struct rte_mbuf *new_mb = NULL;
  15         struct eth_rx_bd *rx_bd;
  16         dma_addr_t mapping;
  17         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  18
  19         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  20         if (unlikely(!new_mb)) {
  21                 PMD_RX_LOG(ERR, rxq,
  22                            "Failed to allocate rx buffer "
  23                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  24                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  25                            rte_mempool_avail_count(rxq->mb_pool),
  26                            rte_mempool_in_use_count(rxq->mb_pool));
  27                 return -ENOMEM;
  28         }
  29         rxq->sw_rx_ring[idx].mbuf = new_mb;
  30         rxq->sw_rx_ring[idx].page_offset = 0;
  31         mapping = rte_mbuf_data_iova_default(new_mb);
  32         /* Advance PROD and get BD pointer */
  33         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  34         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  35         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  36         rxq->sw_rx_prod++;
  37         return 0;
  38 }
  39
  40 int
  41 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  42                     uint16_t nb_desc, unsigned int socket_id,
  43                     __rte_unused const struct rte_eth_rxconf *rx_conf,
  44                     struct rte_mempool *mp)
  45 {
  46         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
  47         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
  48         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  49         struct qede_rx_queue *rxq;
  50         uint16_t max_rx_pkt_len;
  51         uint16_t bufsz;
  52         size_t size;
  53         int rc;
  54
  55         PMD_INIT_FUNC_TRACE(edev);
  56
  57         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
  58         if (!rte_is_power_of_2(nb_desc)) {
  59                 DP_ERR(edev, "Ring size %u is not power of 2\n",
  60                           nb_desc);
  61                 return -EINVAL;
  62         }
  63
  64         /* Free memory prior to re-allocation if needed... */
  65         if (dev->data->rx_queues[queue_idx] != NULL) {
  66                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
  67                 dev->data->rx_queues[queue_idx] = NULL;
  68         }
  69
  70         /* First allocate the rx queue data structure */
  71         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
  72                                  RTE_CACHE_LINE_SIZE, socket_id);
  73
  74         if (!rxq) {
  75                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
  76                           socket_id);
  77                 return -ENOMEM;
  78         }
  79
  80         rxq->qdev = qdev;
  81         rxq->mb_pool = mp;
  82         rxq->nb_rx_desc = nb_desc;
  83         rxq->queue_id = queue_idx;
  84         rxq->port_id = dev->data->port_id;
  85
  86         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
  87
  88         /* Fix up RX buffer size */
  89         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
  90         if ((rxmode->enable_scatter)                    ||
  91             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
  92                 if (!dev->data->scattered_rx) {
  93                         DP_INFO(edev, "Forcing scatter-gather mode\n");
  94                         dev->data->scattered_rx = 1;
  95                 }
  96         }
  97
  98         if (dev->data->scattered_rx)
  99                 rxq->rx_buf_size = bufsz + ETHER_HDR_LEN +
 100                                    ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
 101         else
 102                 rxq->rx_buf_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
 103         /* Align to cache-line size if needed */
 104         rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
 105
 106         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 107                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 108
 109         /* Allocate the parallel driver ring for Rx buffers */
 110         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 111         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 112                                              RTE_CACHE_LINE_SIZE, socket_id);
 113         if (!rxq->sw_rx_ring) {
 114                 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
 115                        " socket %u\n", socket_id);
 116                 rte_free(rxq);
 117                 return -ENOMEM;
 118         }
 119
 120         /* Allocate FW Rx ring  */
 121         rc = qdev->ops->common->chain_alloc(edev,
 122                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 123                                             ECORE_CHAIN_MODE_NEXT_PTR,
 124                                             ECORE_CHAIN_CNT_TYPE_U16,
 125                                             rxq->nb_rx_desc,
 126                                             sizeof(struct eth_rx_bd),
 127                                             &rxq->rx_bd_ring,
 128                                             NULL);
 129
 130         if (rc != ECORE_SUCCESS) {
 131                 DP_ERR(edev, "Memory allocation fails for RX BD ring"
 132                        " on socket %u\n", socket_id);
 133                 rte_free(rxq->sw_rx_ring);
 134                 rte_free(rxq);
 135                 return -ENOMEM;
 136         }
 137
 138         /* Allocate FW completion ring */
 139         rc = qdev->ops->common->chain_alloc(edev,
 140                                             ECORE_CHAIN_USE_TO_CONSUME,
 141                                             ECORE_CHAIN_MODE_PBL,
 142                                             ECORE_CHAIN_CNT_TYPE_U16,
 143                                             rxq->nb_rx_desc,
 144                                             sizeof(union eth_rx_cqe),
 145                                             &rxq->rx_comp_ring,
 146                                             NULL);
 147
 148         if (rc != ECORE_SUCCESS) {
 149                 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
 150                        " on socket %u\n", socket_id);
 151                 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 152                 rte_free(rxq->sw_rx_ring);
 153                 rte_free(rxq);
 154                 return -ENOMEM;
 155         }
 156
 157         dev->data->rx_queues[queue_idx] = rxq;
 158         qdev->fp_array[queue_idx].rxq = rxq;
 159
 160         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 161                   queue_idx, nb_desc, rxq->rx_buf_size, socket_id);
 162
 163         return 0;
 164 }
 165
 166 static void
 167 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
 168                     struct qede_rx_queue *rxq)
 169 {
 170         DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
 171         ecore_chain_reset(&rxq->rx_bd_ring);
 172         ecore_chain_reset(&rxq->rx_comp_ring);
 173         rxq->sw_rx_prod = 0;
 174         rxq->sw_rx_cons = 0;
 175         *rxq->hw_cons_ptr = 0;
 176 }
 177
 178 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
 179 {
 180         uint16_t i;
 181
 182         if (rxq->sw_rx_ring) {
 183                 for (i = 0; i < rxq->nb_rx_desc; i++) {
 184                         if (rxq->sw_rx_ring[i].mbuf) {
 185                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
 186                                 rxq->sw_rx_ring[i].mbuf = NULL;
 187                         }
 188                 }
 189         }
 190 }
 191
 192 void qede_rx_queue_release(void *rx_queue)
 193 {
 194         struct qede_rx_queue *rxq = rx_queue;
 195         struct qede_dev *qdev = rxq->qdev;
 196         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 197
 198         PMD_INIT_FUNC_TRACE(edev);
 199
 200         if (rxq) {
 201                 qede_rx_queue_release_mbufs(rxq);
 202                 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 203                 qdev->ops->common->chain_free(edev, &rxq->rx_comp_ring);
 204                 rte_free(rxq->sw_rx_ring);
 205                 rte_free(rxq);
 206         }
 207 }
 208
 209 /* Stops a given RX queue in the HW */
 210 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 211 {
 212         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 213         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 214         struct ecore_hwfn *p_hwfn;
 215         struct qede_rx_queue *rxq;
 216         int hwfn_index;
 217         int rc;
 218
 219         if (rx_queue_id < eth_dev->data->nb_rx_queues) {
 220                 rxq = eth_dev->data->rx_queues[rx_queue_id];
 221                 hwfn_index = rx_queue_id % edev->num_hwfns;
 222                 p_hwfn = &edev->hwfns[hwfn_index];
 223                 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
 224                                 true, false);
 225                 if (rc != ECORE_SUCCESS) {
 226                         DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
 227                         return -1;
 228                 }
 229                 qede_rx_queue_release_mbufs(rxq);
 230                 qede_rx_queue_reset(qdev, rxq);
 231                 eth_dev->data->rx_queue_state[rx_queue_id] =
 232                         RTE_ETH_QUEUE_STATE_STOPPED;
 233                 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
 234         } else {
 235                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 236                 rc = -EINVAL;
 237         }
 238
 239         return rc;
 240 }
 241
 242 int
 243 qede_tx_queue_setup(struct rte_eth_dev *dev,
 244                     uint16_t queue_idx,
 245                     uint16_t nb_desc,
 246                     unsigned int socket_id,
 247                     const struct rte_eth_txconf *tx_conf)
 248 {
 249         struct qede_dev *qdev = dev->data->dev_private;
 250         struct ecore_dev *edev = &qdev->edev;
 251         struct qede_tx_queue *txq;
 252         int rc;
 253
 254         PMD_INIT_FUNC_TRACE(edev);
 255
 256         if (!rte_is_power_of_2(nb_desc)) {
 257                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 258                        nb_desc);
 259                 return -EINVAL;
 260         }
 261
 262         /* Free memory prior to re-allocation if needed... */
 263         if (dev->data->tx_queues[queue_idx] != NULL) {
 264                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 265                 dev->data->tx_queues[queue_idx] = NULL;
 266         }
 267
 268         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 269                                  RTE_CACHE_LINE_SIZE, socket_id);
 270
 271         if (txq == NULL) {
 272                 DP_ERR(edev,
 273                        "Unable to allocate memory for txq on socket %u",
 274                        socket_id);
 275                 return -ENOMEM;
 276         }
 277
 278         txq->nb_tx_desc = nb_desc;
 279         txq->qdev = qdev;
 280         txq->port_id = dev->data->port_id;
 281
 282         rc = qdev->ops->common->chain_alloc(edev,
 283                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 284                                             ECORE_CHAIN_MODE_PBL,
 285                                             ECORE_CHAIN_CNT_TYPE_U16,
 286                                             txq->nb_tx_desc,
 287                                             sizeof(union eth_tx_bd_types),
 288                                             &txq->tx_pbl,
 289                                             NULL);
 290         if (rc != ECORE_SUCCESS) {
 291                 DP_ERR(edev,
 292                        "Unable to allocate memory for txbd ring on socket %u",
 293                        socket_id);
 294                 qede_tx_queue_release(txq);
 295                 return -ENOMEM;
 296         }
 297
 298         /* Allocate software ring */
 299         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 300                                              (sizeof(struct qede_tx_entry) *
 301                                               txq->nb_tx_desc),
 302                                              RTE_CACHE_LINE_SIZE, socket_id);
 303
 304         if (!txq->sw_tx_ring) {
 305                 DP_ERR(edev,
 306                        "Unable to allocate memory for txbd ring on socket %u",
 307                        socket_id);
 308                 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 309                 qede_tx_queue_release(txq);
 310                 return -ENOMEM;
 311         }
 312
 313         txq->queue_id = queue_idx;
 314
 315         txq->nb_tx_avail = txq->nb_tx_desc;
 316
 317         txq->tx_free_thresh =
 318             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 319             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 320
 321         dev->data->tx_queues[queue_idx] = txq;
 322         qdev->fp_array[queue_idx].txq = txq;
 323
 324         DP_INFO(edev,
 325                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 326                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 327
 328         return 0;
 329 }
 330
 331 static void
 332 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
 333                     struct qede_tx_queue *txq)
 334 {
 335         DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
 336         ecore_chain_reset(&txq->tx_pbl);
 337         txq->sw_tx_cons = 0;
 338         txq->sw_tx_prod = 0;
 339         *txq->hw_cons_ptr = 0;
 340 }
 341
 342 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
 343 {
 344         uint16_t i;
 345
 346         if (txq->sw_tx_ring) {
 347                 for (i = 0; i < txq->nb_tx_desc; i++) {
 348                         if (txq->sw_tx_ring[i].mbuf) {
 349                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
 350                                 txq->sw_tx_ring[i].mbuf = NULL;
 351                         }
 352                 }
 353         }
 354 }
 355
 356 void qede_tx_queue_release(void *tx_queue)
 357 {
 358         struct qede_tx_queue *txq = tx_queue;
 359         struct qede_dev *qdev = txq->qdev;
 360         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 361
 362         PMD_INIT_FUNC_TRACE(edev);
 363
 364         if (txq) {
 365                 qede_tx_queue_release_mbufs(txq);
 366                 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 367                 rte_free(txq->sw_tx_ring);
 368                 rte_free(txq);
 369         }
 370 }
 371
 372 /* This function allocates fast-path status block memory */
 373 static int
 374 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 375                   uint16_t sb_id)
 376 {
 377         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 378         struct status_block_e4 *sb_virt;
 379         dma_addr_t sb_phys;
 380         int rc;
 381
 382         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
 383                                           sizeof(struct status_block_e4));
 384         if (!sb_virt) {
 385                 DP_ERR(edev, "Status block allocation failed\n");
 386                 return -ENOMEM;
 387         }
 388         rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
 389                                         sb_phys, sb_id);
 390         if (rc) {
 391                 DP_ERR(edev, "Status block initialization failed\n");
 392                 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
 393                                        sizeof(struct status_block_e4));
 394                 return rc;
 395         }
 396
 397         return 0;
 398 }
 399
 400 int qede_alloc_fp_resc(struct qede_dev *qdev)
 401 {
 402         struct ecore_dev *edev = &qdev->edev;
 403         struct qede_fastpath *fp;
 404         uint32_t num_sbs;
 405         uint16_t sb_idx;
 406
 407         if (IS_VF(edev))
 408                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 409         else
 410                 num_sbs = ecore_cxt_get_proto_cid_count
 411                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 412
 413         if (num_sbs == 0) {
 414                 DP_ERR(edev, "No status blocks available\n");
 415                 return -EINVAL;
 416         }
 417
 418         qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
 419                                 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
 420
 421         if (!qdev->fp_array) {
 422                 DP_ERR(edev, "fp array allocation failed\n");
 423                 return -ENOMEM;
 424         }
 425
 426         memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
 427                         sizeof(*qdev->fp_array));
 428
 429         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 430                 fp = &qdev->fp_array[sb_idx];
 431                 if (!fp)
 432                         continue;
 433                 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
 434                                 RTE_CACHE_LINE_SIZE);
 435                 if (!fp->sb_info) {
 436                         DP_ERR(edev, "FP sb_info allocation fails\n");
 437                         return -1;
 438                 }
 439                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 440                         DP_ERR(edev, "FP status block allocation fails\n");
 441                         return -1;
 442                 }
 443                 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
 444                                 fp->sb_info->igu_sb_id);
 445         }
 446
 447         return 0;
 448 }
 449
 450 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 451 {
 452         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 453         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 454         struct qede_fastpath *fp;
 455         uint16_t sb_idx;
 456         uint8_t i;
 457
 458         PMD_INIT_FUNC_TRACE(edev);
 459
 460         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 461                 fp = &qdev->fp_array[sb_idx];
 462                 if (!fp)
 463                         continue;
 464                 DP_INFO(edev, "Free sb_info index 0x%x\n",
 465                                 fp->sb_info->igu_sb_id);
 466                 if (fp->sb_info) {
 467                         OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
 468                                 fp->sb_info->sb_phys,
 469                                 sizeof(struct status_block_e4));
 470                         rte_free(fp->sb_info);
 471                         fp->sb_info = NULL;
 472                 }
 473         }
 474
 475         /* Free packet buffers and ring memories */
 476         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 477                 if (eth_dev->data->rx_queues[i]) {
 478                         qede_rx_queue_release(eth_dev->data->rx_queues[i]);
 479                         eth_dev->data->rx_queues[i] = NULL;
 480                 }
 481         }
 482
 483         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
 484                 if (eth_dev->data->tx_queues[i]) {
 485                         qede_tx_queue_release(eth_dev->data->tx_queues[i]);
 486                         eth_dev->data->tx_queues[i] = NULL;
 487                 }
 488         }
 489
 490         if (qdev->fp_array)
 491                 rte_free(qdev->fp_array);
 492         qdev->fp_array = NULL;
 493 }
 494
 495 static inline void
 496 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
 497                     struct qede_rx_queue *rxq)
 498 {
 499         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 500         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 501         struct eth_rx_prod_data rx_prods = { 0 };
 502
 503         /* Update producers */
 504         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 505         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 506
 507         /* Make sure that the BD and SGE data is updated before updating the
 508          * producers since FW might read the BD/SGE right after the producer
 509          * is updated.
 510          */
 511         rte_wmb();
 512
 513         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 514                         (uint32_t *)&rx_prods);
 515
 516         /* mmiowb is needed to synchronize doorbell writes from more than one
 517          * processor. It guarantees that the write arrives to the device before
 518          * the napi lock is released and another qede_poll is called (possibly
 519          * on another CPU). Without this barrier, the next doorbell can bypass
 520          * this doorbell. This is applicable to IA64/Altix systems.
 521          */
 522         rte_wmb();
 523
 524         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 525 }
 526
 527 /* Starts a given RX queue in HW */
 528 static int
 529 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 530 {
 531         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 532         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 533         struct ecore_queue_start_common_params params;
 534         struct ecore_rxq_start_ret_params ret_params;
 535         struct qede_rx_queue *rxq;
 536         struct qede_fastpath *fp;
 537         struct ecore_hwfn *p_hwfn;
 538         dma_addr_t p_phys_table;
 539         uint16_t page_cnt;
 540         uint16_t j;
 541         int hwfn_index;
 542         int rc;
 543
 544         if (rx_queue_id < eth_dev->data->nb_rx_queues) {
 545                 fp = &qdev->fp_array[rx_queue_id];
 546                 rxq = eth_dev->data->rx_queues[rx_queue_id];
 547                 /* Allocate buffers for the Rx ring */
 548                 for (j = 0; j < rxq->nb_rx_desc; j++) {
 549                         rc = qede_alloc_rx_buffer(rxq);
 550                         if (rc) {
 551                                 DP_ERR(edev, "RX buffer allocation failed"
 552                                                 " for rxq = %u\n", rx_queue_id);
 553                                 return -ENOMEM;
 554                         }
 555                 }
 556                 /* disable interrupts */
 557                 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 558                 /* Prepare ramrod */
 559                 memset(&params, 0, sizeof(params));
 560                 params.queue_id = rx_queue_id / edev->num_hwfns;
 561                 params.vport_id = 0;
 562                 params.stats_id = params.vport_id;
 563                 params.p_sb = fp->sb_info;
 564                 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
 565                                 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
 566                 params.sb_idx = RX_PI;
 567                 hwfn_index = rx_queue_id % edev->num_hwfns;
 568                 p_hwfn = &edev->hwfns[hwfn_index];
 569                 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
 570                 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
 571                 memset(&ret_params, 0, sizeof(ret_params));
 572                 rc = ecore_eth_rx_queue_start(p_hwfn,
 573                                 p_hwfn->hw_info.opaque_fid,
 574                                 &params, fp->rxq->rx_buf_size,
 575                                 fp->rxq->rx_bd_ring.p_phys_addr,
 576                                 p_phys_table, page_cnt,
 577                                 &ret_params);
 578                 if (rc) {
 579                         DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
 580                                         rx_queue_id, rc);
 581                         return -1;
 582                 }
 583                 /* Update with the returned parameters */
 584                 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
 585                 fp->rxq->handle = ret_params.p_handle;
 586
 587                 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
 588                 qede_update_rx_prod(qdev, fp->rxq);
 589                 eth_dev->data->rx_queue_state[rx_queue_id] =
 590                         RTE_ETH_QUEUE_STATE_STARTED;
 591                 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
 592         } else {
 593                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 594                 rc = -EINVAL;
 595         }
 596
 597         return rc;
 598 }
 599
 600 static int
 601 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 602 {
 603         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 604         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 605         struct ecore_queue_start_common_params params;
 606         struct ecore_txq_start_ret_params ret_params;
 607         struct ecore_hwfn *p_hwfn;
 608         dma_addr_t p_phys_table;
 609         struct qede_tx_queue *txq;
 610         struct qede_fastpath *fp;
 611         uint16_t page_cnt;
 612         int hwfn_index;
 613         int rc;
 614
 615         if (tx_queue_id < eth_dev->data->nb_tx_queues) {
 616                 txq = eth_dev->data->tx_queues[tx_queue_id];
 617                 fp = &qdev->fp_array[tx_queue_id];
 618                 memset(&params, 0, sizeof(params));
 619                 params.queue_id = tx_queue_id / edev->num_hwfns;
 620                 params.vport_id = 0;
 621                 params.stats_id = params.vport_id;
 622                 params.p_sb = fp->sb_info;
 623                 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
 624                                 fp->txq->queue_id, fp->sb_info->igu_sb_id);
 625                 params.sb_idx = TX_PI(0); /* tc = 0 */
 626                 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 627                 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 628                 hwfn_index = tx_queue_id % edev->num_hwfns;
 629                 p_hwfn = &edev->hwfns[hwfn_index];
 630                 if (qdev->dev_info.is_legacy)
 631                         fp->txq->is_legacy = true;
 632                 rc = ecore_eth_tx_queue_start(p_hwfn,
 633                                 p_hwfn->hw_info.opaque_fid,
 634                                 &params, 0 /* tc */,
 635                                 p_phys_table, page_cnt,
 636                                 &ret_params);
 637                 if (rc != ECORE_SUCCESS) {
 638                         DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
 639                                         tx_queue_id, rc);
 640                         return -1;
 641                 }
 642                 txq->doorbell_addr = ret_params.p_doorbell;
 643                 txq->handle = ret_params.p_handle;
 644
 645                 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[TX_PI(0)];
 646                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
 647                                 DB_DEST_XCM);
 648                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 649                                 DB_AGG_CMD_SET);
 650                 SET_FIELD(txq->tx_db.data.params,
 651                                 ETH_DB_DATA_AGG_VAL_SEL,
 652                                 DQ_XCM_ETH_TX_BD_PROD_CMD);
 653                 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 654                 eth_dev->data->tx_queue_state[tx_queue_id] =
 655                         RTE_ETH_QUEUE_STATE_STARTED;
 656                 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
 657         } else {
 658                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 659                 rc = -EINVAL;
 660         }
 661
 662         return rc;
 663 }
 664
 665 static inline void
 666 qede_free_tx_pkt(struct qede_tx_queue *txq)
 667 {
 668         struct rte_mbuf *mbuf;
 669         uint16_t nb_segs;
 670         uint16_t idx;
 671
 672         idx = TX_CONS(txq);
 673         mbuf = txq->sw_tx_ring[idx].mbuf;
 674         if (mbuf) {
 675                 nb_segs = mbuf->nb_segs;
 676                 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
 677                 while (nb_segs) {
 678                         /* It's like consuming rxbuf in recv() */
 679                         ecore_chain_consume(&txq->tx_pbl);
 680                         txq->nb_tx_avail++;
 681                         nb_segs--;
 682                 }
 683                 rte_pktmbuf_free(mbuf);
 684                 txq->sw_tx_ring[idx].mbuf = NULL;
 685                 txq->sw_tx_cons++;
 686                 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
 687         } else {
 688                 ecore_chain_consume(&txq->tx_pbl);
 689                 txq->nb_tx_avail++;
 690         }
 691 }
 692
 693 static inline void
 694 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
 695                       struct qede_tx_queue *txq)
 696 {
 697         uint16_t hw_bd_cons;
 698 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 699         uint16_t sw_tx_cons;
 700 #endif
 701
 702         rte_compiler_barrier();
 703         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
 704 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 705         sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
 706         PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
 707                    abs(hw_bd_cons - sw_tx_cons));
 708 #endif
 709         while (hw_bd_cons !=  ecore_chain_get_cons_idx(&txq->tx_pbl))
 710                 qede_free_tx_pkt(txq);
 711 }
 712
 713 static int qede_drain_txq(struct qede_dev *qdev,
 714                           struct qede_tx_queue *txq, bool allow_drain)
 715 {
 716         struct ecore_dev *edev = &qdev->edev;
 717         int rc, cnt = 1000;
 718
 719         while (txq->sw_tx_cons != txq->sw_tx_prod) {
 720                 qede_process_tx_compl(edev, txq);
 721                 if (!cnt) {
 722                         if (allow_drain) {
 723                                 DP_ERR(edev, "Tx queue[%u] is stuck,"
 724                                           "requesting MCP to drain\n",
 725                                           txq->queue_id);
 726                                 rc = qdev->ops->common->drain(edev);
 727                                 if (rc)
 728                                         return rc;
 729                                 return qede_drain_txq(qdev, txq, false);
 730                         }
 731                         DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
 732                                   "PROD=%d, CONS=%d\n",
 733                                   txq->queue_id, txq->sw_tx_prod,
 734                                   txq->sw_tx_cons);
 735                         return -1;
 736                 }
 737                 cnt--;
 738                 DELAY(1000);
 739                 rte_compiler_barrier();
 740         }
 741
 742         /* FW finished processing, wait for HW to transmit all tx packets */
 743         DELAY(2000);
 744
 745         return 0;
 746 }
 747
 748 /* Stops a given TX queue in the HW */
 749 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 750 {
 751         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 752         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 753         struct ecore_hwfn *p_hwfn;
 754         struct qede_tx_queue *txq;
 755         int hwfn_index;
 756         int rc;
 757
 758         if (tx_queue_id < eth_dev->data->nb_tx_queues) {
 759                 txq = eth_dev->data->tx_queues[tx_queue_id];
 760                 /* Drain txq */
 761                 if (qede_drain_txq(qdev, txq, true))
 762                         return -1; /* For the lack of retcodes */
 763                 /* Stop txq */
 764                 hwfn_index = tx_queue_id % edev->num_hwfns;
 765                 p_hwfn = &edev->hwfns[hwfn_index];
 766                 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
 767                 if (rc != ECORE_SUCCESS) {
 768                         DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
 769                         return -1;
 770                 }
 771                 qede_tx_queue_release_mbufs(txq);
 772                 qede_tx_queue_reset(qdev, txq);
 773                 eth_dev->data->tx_queue_state[tx_queue_id] =
 774                         RTE_ETH_QUEUE_STATE_STOPPED;
 775                 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
 776         } else {
 777                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 778                 rc = -EINVAL;
 779         }
 780
 781         return rc;
 782 }
 783
 784 int qede_start_queues(struct rte_eth_dev *eth_dev)
 785 {
 786         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 787         uint8_t id;
 788         int rc = -1;
 789
 790         for_each_rss(id) {
 791                 rc = qede_rx_queue_start(eth_dev, id);
 792                 if (rc != ECORE_SUCCESS)
 793                         return -1;
 794         }
 795
 796         for_each_tss(id) {
 797                 rc = qede_tx_queue_start(eth_dev, id);
 798                 if (rc != ECORE_SUCCESS)
 799                         return -1;
 800         }
 801
 802         return rc;
 803 }
 804
 805 void qede_stop_queues(struct rte_eth_dev *eth_dev)
 806 {
 807         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 808         uint8_t id;
 809
 810         /* Stopping RX/TX queues */
 811         for_each_tss(id) {
 812                 qede_tx_queue_stop(eth_dev, id);
 813         }
 814
 815         for_each_rss(id) {
 816                 qede_rx_queue_stop(eth_dev, id);
 817         }
 818 }
 819
 820 static inline bool qede_tunn_exist(uint16_t flag)
 821 {
 822         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 823                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 824 }
 825
 826 static inline uint8_t qede_check_tunn_csum_l3(uint16_t flag)
 827 {
 828         return !!((PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
 829                 PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT) & flag);
 830 }
 831
 832 /*
 833  * qede_check_tunn_csum_l4:
 834  * Returns:
 835  * 1 : If L4 csum is enabled AND if the validation has failed.
 836  * 0 : Otherwise
 837  */
 838 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 839 {
 840         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 841              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 842                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 843                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 844
 845         return 0;
 846 }
 847
 848 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 849 {
 850         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 851              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 852                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 853                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 854
 855         return 0;
 856 }
 857
 858 /* Returns outer L2, L3 and L4 packet_type for tunneled packets */
 859 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m)
 860 {
 861         uint32_t packet_type = RTE_PTYPE_UNKNOWN;
 862         struct ether_hdr *eth_hdr;
 863         struct ipv4_hdr *ipv4_hdr;
 864         struct ipv6_hdr *ipv6_hdr;
 865         struct vlan_hdr *vlan_hdr;
 866         uint16_t ethertype;
 867         bool vlan_tagged = 0;
 868         uint16_t len;
 869
 870         eth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);
 871         len = sizeof(struct ether_hdr);
 872         ethertype = rte_cpu_to_be_16(eth_hdr->ether_type);
 873
 874          /* Note: Valid only if VLAN stripping is disabled */
 875         if (ethertype == ETHER_TYPE_VLAN) {
 876                 vlan_tagged = 1;
 877                 vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1);
 878                 len += sizeof(struct vlan_hdr);
 879                 ethertype = rte_cpu_to_be_16(vlan_hdr->eth_proto);
 880         }
 881
 882         if (ethertype == ETHER_TYPE_IPv4) {
 883                 packet_type |= RTE_PTYPE_L3_IPV4;
 884                 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, len);
 885                 if (ipv4_hdr->next_proto_id == IPPROTO_TCP)
 886                         packet_type |= RTE_PTYPE_L4_TCP;
 887                 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP)
 888                         packet_type |= RTE_PTYPE_L4_UDP;
 889         } else if (ethertype == ETHER_TYPE_IPv6) {
 890                 packet_type |= RTE_PTYPE_L3_IPV6;
 891                 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *, len);
 892                 if (ipv6_hdr->proto == IPPROTO_TCP)
 893                         packet_type |= RTE_PTYPE_L4_TCP;
 894                 else if (ipv6_hdr->proto == IPPROTO_UDP)
 895                         packet_type |= RTE_PTYPE_L4_UDP;
 896         }
 897
 898         if (vlan_tagged)
 899                 packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
 900         else
 901                 packet_type |= RTE_PTYPE_L2_ETHER;
 902
 903         return packet_type;
 904 }
 905
 906 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags)
 907 {
 908         uint16_t val;
 909
 910         /* Lookup table */
 911         static const uint32_t
 912         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 913                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4          |
 914                                        RTE_PTYPE_INNER_L2_ETHER,
 915                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6          |
 916                                        RTE_PTYPE_INNER_L2_ETHER,
 917                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4      |
 918                                            RTE_PTYPE_INNER_L4_TCP       |
 919                                            RTE_PTYPE_INNER_L2_ETHER,
 920                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6      |
 921                                            RTE_PTYPE_INNER_L4_TCP       |
 922                                            RTE_PTYPE_INNER_L2_ETHER,
 923                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4      |
 924                                            RTE_PTYPE_INNER_L4_UDP       |
 925                                            RTE_PTYPE_INNER_L2_ETHER,
 926                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6      |
 927                                            RTE_PTYPE_INNER_L4_UDP       |
 928                                            RTE_PTYPE_INNER_L2_ETHER,
 929                 /* Frags with no VLAN */
 930                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4     |
 931                                             RTE_PTYPE_INNER_L4_FRAG     |
 932                                             RTE_PTYPE_INNER_L2_ETHER,
 933                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6     |
 934                                             RTE_PTYPE_INNER_L4_FRAG     |
 935                                             RTE_PTYPE_INNER_L2_ETHER,
 936                 /* VLANs */
 937                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4     |
 938                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
 939                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6     |
 940                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
 941                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
 942                                                 RTE_PTYPE_INNER_L4_TCP  |
 943                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 944                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
 945                                                 RTE_PTYPE_INNER_L4_TCP  |
 946                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 947                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
 948                                                 RTE_PTYPE_INNER_L4_UDP  |
 949                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 950                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
 951                                                 RTE_PTYPE_INNER_L4_UDP  |
 952                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 953                 /* Frags with VLAN */
 954                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
 955                                                  RTE_PTYPE_INNER_L4_FRAG |
 956                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
 957                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
 958                                                  RTE_PTYPE_INNER_L4_FRAG |
 959                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
 960         };
 961
 962         /* Bits (0..3) provides L3/L4 protocol type */
 963         /* Bits (4,5) provides frag and VLAN info */
 964         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 965                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 966                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 967                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
 968                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
 969                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
 970                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
 971                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
 972
 973         if (val < QEDE_PKT_TYPE_MAX)
 974                 return ptype_lkup_tbl[val];
 975
 976         return RTE_PTYPE_UNKNOWN;
 977 }
 978
 979 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 980 {
 981         uint16_t val;
 982
 983         /* Lookup table */
 984         static const uint32_t
 985         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 986                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER,
 987                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER,
 988                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4    |
 989                                            RTE_PTYPE_L4_TCP     |
 990                                            RTE_PTYPE_L2_ETHER,
 991                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6    |
 992                                            RTE_PTYPE_L4_TCP     |
 993                                            RTE_PTYPE_L2_ETHER,
 994                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4    |
 995                                            RTE_PTYPE_L4_UDP     |
 996                                            RTE_PTYPE_L2_ETHER,
 997                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6    |
 998                                            RTE_PTYPE_L4_UDP     |
 999                                            RTE_PTYPE_L2_ETHER,
1000                 /* Frags with no VLAN */
1001                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4   |
1002                                             RTE_PTYPE_L4_FRAG   |
1003                                             RTE_PTYPE_L2_ETHER,
1004                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6   |
1005                                             RTE_PTYPE_L4_FRAG   |
1006                                             RTE_PTYPE_L2_ETHER,
1007                 /* VLANs */
1008                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4           |
1009                                             RTE_PTYPE_L2_ETHER_VLAN,
1010                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6           |
1011                                             RTE_PTYPE_L2_ETHER_VLAN,
1012                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4       |
1013                                                 RTE_PTYPE_L4_TCP        |
1014                                                 RTE_PTYPE_L2_ETHER_VLAN,
1015                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6       |
1016                                                 RTE_PTYPE_L4_TCP        |
1017                                                 RTE_PTYPE_L2_ETHER_VLAN,
1018                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4       |
1019                                                 RTE_PTYPE_L4_UDP        |
1020                                                 RTE_PTYPE_L2_ETHER_VLAN,
1021                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6       |
1022                                                 RTE_PTYPE_L4_UDP        |
1023                                                 RTE_PTYPE_L2_ETHER_VLAN,
1024                 /* Frags with VLAN */
1025                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4      |
1026                                                  RTE_PTYPE_L4_FRAG      |
1027                                                  RTE_PTYPE_L2_ETHER_VLAN,
1028                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6      |
1029                                                  RTE_PTYPE_L4_FRAG      |
1030                                                  RTE_PTYPE_L2_ETHER_VLAN,
1031         };
1032
1033         /* Bits (0..3) provides L3/L4 protocol type */
1034         /* Bits (4,5) provides frag and VLAN info */
1035         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1036                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1037                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1038                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1039                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1040                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1041                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1042                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1043
1044         if (val < QEDE_PKT_TYPE_MAX)
1045                 return ptype_lkup_tbl[val];
1046
1047         return RTE_PTYPE_UNKNOWN;
1048 }
1049
1050 static inline uint8_t
1051 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
1052 {
1053         struct ipv4_hdr *ip;
1054         uint16_t pkt_csum;
1055         uint16_t calc_csum;
1056         uint16_t val;
1057
1058         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1059                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
1060
1061         if (unlikely(val)) {
1062                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
1063                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
1064                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1065                                            sizeof(struct ether_hdr));
1066                         pkt_csum = ip->hdr_checksum;
1067                         ip->hdr_checksum = 0;
1068                         calc_csum = rte_ipv4_cksum(ip);
1069                         ip->hdr_checksum = pkt_csum;
1070                         return (calc_csum != pkt_csum);
1071                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
1072                         return 1;
1073                 }
1074         }
1075         return 0;
1076 }
1077
1078 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
1079 {
1080         ecore_chain_consume(&rxq->rx_bd_ring);
1081         rxq->sw_rx_cons++;
1082 }
1083
1084 static inline void
1085 qede_reuse_page(__rte_unused struct qede_dev *qdev,
1086                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
1087 {
1088         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
1089         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1090         struct qede_rx_entry *curr_prod;
1091         dma_addr_t new_mapping;
1092
1093         curr_prod = &rxq->sw_rx_ring[idx];
1094         *curr_prod = *curr_cons;
1095
1096         new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) +
1097                       curr_prod->page_offset;
1098
1099         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
1100         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
1101
1102         rxq->sw_rx_prod++;
1103 }
1104
1105 static inline void
1106 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
1107                         struct qede_dev *qdev, uint8_t count)
1108 {
1109         struct qede_rx_entry *curr_cons;
1110
1111         for (; count > 0; count--) {
1112                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
1113                 qede_reuse_page(qdev, rxq, curr_cons);
1114                 qede_rx_bd_ring_consume(rxq);
1115         }
1116 }
1117
1118 static inline void
1119 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
1120                                      struct qede_rx_queue *rxq,
1121                                      uint8_t agg_index, uint16_t len)
1122 {
1123         struct qede_agg_info *tpa_info;
1124         struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
1125         uint16_t cons_idx;
1126
1127         /* Under certain conditions it is possible that FW may not consume
1128          * additional or new BD. So decision to consume the BD must be made
1129          * based on len_list[0].
1130          */
1131         if (rte_le_to_cpu_16(len)) {
1132                 tpa_info = &rxq->tpa_info[agg_index];
1133                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1134                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
1135                 assert(curr_frag);
1136                 curr_frag->nb_segs = 1;
1137                 curr_frag->pkt_len = rte_le_to_cpu_16(len);
1138                 curr_frag->data_len = curr_frag->pkt_len;
1139                 tpa_info->tpa_tail->next = curr_frag;
1140                 tpa_info->tpa_tail = curr_frag;
1141                 qede_rx_bd_ring_consume(rxq);
1142                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1143                         PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
1144                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1145                         rxq->rx_alloc_errors++;
1146                 }
1147         }
1148 }
1149
1150 static inline void
1151 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
1152                              struct qede_rx_queue *rxq,
1153                              struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1154 {
1155         PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
1156                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
1157         /* only len_list[0] will have value */
1158         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1159                                              cqe->len_list[0]);
1160 }
1161
1162 static inline void
1163 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
1164                             struct qede_rx_queue *rxq,
1165                             struct eth_fast_path_rx_tpa_end_cqe *cqe)
1166 {
1167         struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
1168
1169         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1170                                              cqe->len_list[0]);
1171         /* Update total length and frags based on end TPA */
1172         rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
1173         /* TODO:  Add Sanity Checks */
1174         rx_mb->nb_segs = cqe->num_of_bds;
1175         rx_mb->pkt_len = cqe->total_packet_len;
1176
1177         PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1178                    " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1179                    rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1180                    rx_mb->pkt_len);
1181 }
1182
1183 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1184 {
1185         uint32_t val;
1186
1187         /* Lookup table */
1188         static const uint32_t
1189         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1190                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1191                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1192                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1193                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1194                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1195                                 RTE_PTYPE_TUNNEL_GENEVE,
1196                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1197                                 RTE_PTYPE_TUNNEL_GRE,
1198                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1199                                 RTE_PTYPE_TUNNEL_VXLAN,
1200                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1201                                 RTE_PTYPE_TUNNEL_GENEVE,
1202                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1203                                 RTE_PTYPE_TUNNEL_GRE,
1204                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1205                                 RTE_PTYPE_TUNNEL_VXLAN,
1206                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1207                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1208                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1209                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1210                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1211                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1212                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1213                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1214                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1215                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1216                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1217                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1218                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1219                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1220                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1221                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1222                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1223                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1224                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1225                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1226                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1227                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1228                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1229                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1230         };
1231
1232         /* Cover bits[4-0] to include tunn_type and next protocol */
1233         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1234                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1235                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1236                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1237
1238         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1239                 return ptype_tunn_lkup_tbl[val];
1240         else
1241                 return RTE_PTYPE_UNKNOWN;
1242 }
1243
1244 static inline int
1245 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
1246                      uint8_t num_segs, uint16_t pkt_len)
1247 {
1248         struct qede_rx_queue *rxq = p_rxq;
1249         struct qede_dev *qdev = rxq->qdev;
1250         register struct rte_mbuf *seg1 = NULL;
1251         register struct rte_mbuf *seg2 = NULL;
1252         uint16_t sw_rx_index;
1253         uint16_t cur_size;
1254
1255         seg1 = rx_mb;
1256         while (num_segs) {
1257                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1258                                                         pkt_len;
1259                 if (unlikely(!cur_size)) {
1260                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1261                                    " left for mapping jumbo\n", num_segs);
1262                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1263                         return -EINVAL;
1264                 }
1265                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1266                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1267                 qede_rx_bd_ring_consume(rxq);
1268                 pkt_len -= cur_size;
1269                 seg2->data_len = cur_size;
1270                 seg1->next = seg2;
1271                 seg1 = seg1->next;
1272                 num_segs--;
1273                 rxq->rx_segs++;
1274         }
1275
1276         return 0;
1277 }
1278
1279 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1280 static inline void
1281 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,
1282                  uint8_t bitfield)
1283 {
1284         PMD_RX_LOG(INFO, rxq,
1285                 "len 0x%04x bf 0x%04x hash_val 0x%x"
1286                 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s"
1287                 " inner_l2=%s inner_l3=%s inner_l4=%s\n",
1288                 m->data_len, bitfield, m->hash.rss,
1289                 (unsigned long)m->ol_flags,
1290                 rte_get_ptype_l2_name(m->packet_type),
1291                 rte_get_ptype_l3_name(m->packet_type),
1292                 rte_get_ptype_l4_name(m->packet_type),
1293                 rte_get_ptype_tunnel_name(m->packet_type),
1294                 rte_get_ptype_inner_l2_name(m->packet_type),
1295                 rte_get_ptype_inner_l3_name(m->packet_type),
1296                 rte_get_ptype_inner_l4_name(m->packet_type));
1297 }
1298 #endif
1299
1300 uint16_t
1301 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1302 {
1303         struct qede_rx_queue *rxq = p_rxq;
1304         struct qede_dev *qdev = rxq->qdev;
1305         struct ecore_dev *edev = &qdev->edev;
1306         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1307         uint16_t rx_pkt = 0;
1308         union eth_rx_cqe *cqe;
1309         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1310         register struct rte_mbuf *rx_mb = NULL;
1311         register struct rte_mbuf *seg1 = NULL;
1312         enum eth_rx_cqe_type cqe_type;
1313         uint16_t pkt_len = 0; /* Sum of all BD segments */
1314         uint16_t len; /* Length of first BD */
1315         uint8_t num_segs = 1;
1316         uint16_t preload_idx;
1317         uint16_t parse_flag;
1318 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1319         uint8_t bitfield_val;
1320 #endif
1321         uint8_t tunn_parse_flag;
1322         uint8_t j;
1323         struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1324         uint64_t ol_flags;
1325         uint32_t packet_type;
1326         uint16_t vlan_tci;
1327         bool tpa_start_flg;
1328         uint8_t offset, tpa_agg_idx, flags;
1329         struct qede_agg_info *tpa_info = NULL;
1330         uint32_t rss_hash;
1331
1332         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1333         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1334
1335         rte_rmb();
1336
1337         if (hw_comp_cons == sw_comp_cons)
1338                 return 0;
1339
1340         while (sw_comp_cons != hw_comp_cons) {
1341                 ol_flags = 0;
1342                 packet_type = RTE_PTYPE_UNKNOWN;
1343                 vlan_tci = 0;
1344                 tpa_start_flg = false;
1345                 rss_hash = 0;
1346
1347                 /* Get the CQE from the completion ring */
1348                 cqe =
1349                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1350                 cqe_type = cqe->fast_path_regular.type;
1351                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1352
1353                 switch (cqe_type) {
1354                 case ETH_RX_CQE_TYPE_REGULAR:
1355                         fp_cqe = &cqe->fast_path_regular;
1356                 break;
1357                 case ETH_RX_CQE_TYPE_TPA_START:
1358                         cqe_start_tpa = &cqe->fast_path_tpa_start;
1359                         tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1360                         tpa_start_flg = true;
1361                         /* Mark it as LRO packet */
1362                         ol_flags |= PKT_RX_LRO;
1363                         /* In split mode,  seg_len is same as len_on_first_bd
1364                          * and ext_bd_len_list will be empty since there are
1365                          * no additional buffers
1366                          */
1367                         PMD_RX_LOG(INFO, rxq,
1368                             "TPA start[%d] - len_on_first_bd %d header %d"
1369                             " [bd_list[0] %d], [seg_len %d]\n",
1370                             cqe_start_tpa->tpa_agg_index,
1371                             rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1372                             cqe_start_tpa->header_len,
1373                             rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]),
1374                             rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1375
1376                 break;
1377                 case ETH_RX_CQE_TYPE_TPA_CONT:
1378                         qede_rx_process_tpa_cont_cqe(qdev, rxq,
1379                                                      &cqe->fast_path_tpa_cont);
1380                         goto next_cqe;
1381                 case ETH_RX_CQE_TYPE_TPA_END:
1382                         qede_rx_process_tpa_end_cqe(qdev, rxq,
1383                                                     &cqe->fast_path_tpa_end);
1384                         tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1385                         tpa_info = &rxq->tpa_info[tpa_agg_idx];
1386                         rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1387                         goto tpa_end;
1388                 case ETH_RX_CQE_TYPE_SLOW_PATH:
1389                         PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1390                         ecore_eth_cqe_completion(
1391                                 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1392                                 (struct eth_slow_path_rx_cqe *)cqe);
1393                         /* fall-thru */
1394                 default:
1395                         goto next_cqe;
1396                 }
1397
1398                 /* Get the data from the SW ring */
1399                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1400                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1401                 assert(rx_mb != NULL);
1402
1403                 /* Handle regular CQE or TPA start CQE */
1404                 if (!tpa_start_flg) {
1405                         parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1406                         offset = fp_cqe->placement_offset;
1407                         len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1408                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1409                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1410                         rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1411 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1412                         bitfield_val = fp_cqe->bitfields;
1413 #endif
1414                 } else {
1415                         parse_flag =
1416                             rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1417                         offset = cqe_start_tpa->placement_offset;
1418                         /* seg_len = len_on_first_bd */
1419                         len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1420                         vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1421 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1422                         bitfield_val = cqe_start_tpa->bitfields;
1423 #endif
1424                         rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1425                 }
1426                 if (qede_tunn_exist(parse_flag)) {
1427                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1428                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1429                                 PMD_RX_LOG(ERR, rxq,
1430                                             "L4 csum failed, flags = 0x%x\n",
1431                                             parse_flag);
1432                                 rxq->rx_hw_errors++;
1433                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1434                         } else {
1435                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1436                         }
1437
1438                         if (unlikely(qede_check_tunn_csum_l3(parse_flag))) {
1439                                 PMD_RX_LOG(ERR, rxq,
1440                                         "Outer L3 csum failed, flags = 0x%x\n",
1441                                         parse_flag);
1442                                   rxq->rx_hw_errors++;
1443                                   ol_flags |= PKT_RX_EIP_CKSUM_BAD;
1444                         } else {
1445                                   ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1446                         }
1447
1448                         if (tpa_start_flg)
1449                                 flags = cqe_start_tpa->tunnel_pars_flags.flags;
1450                         else
1451                                 flags = fp_cqe->tunnel_pars_flags.flags;
1452                         tunn_parse_flag = flags;
1453
1454                         /* Tunnel_type */
1455                         packet_type =
1456                                 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1457
1458                         /* Inner header */
1459                         packet_type |=
1460                               qede_rx_cqe_to_pkt_type_inner(parse_flag);
1461
1462                         /* Outer L3/L4 types is not available in CQE */
1463                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1464
1465                         /* Outer L3/L4 types is not available in CQE.
1466                          * Need to add offset to parse correctly,
1467                          */
1468                         rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1469                         packet_type |= qede_rx_cqe_to_pkt_type_outer(rx_mb);
1470                 } else {
1471                         packet_type |= qede_rx_cqe_to_pkt_type(parse_flag);
1472                 }
1473
1474                 /* Common handling for non-tunnel packets and for inner
1475                  * headers in the case of tunnel.
1476                  */
1477                 if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1478                         PMD_RX_LOG(ERR, rxq,
1479                                     "L4 csum failed, flags = 0x%x\n",
1480                                     parse_flag);
1481                         rxq->rx_hw_errors++;
1482                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
1483                 } else {
1484                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1485                 }
1486                 if (unlikely(qede_check_notunn_csum_l3(rx_mb, parse_flag))) {
1487                         PMD_RX_LOG(ERR, rxq, "IP csum failed, flags = 0x%x\n",
1488                                    parse_flag);
1489                         rxq->rx_hw_errors++;
1490                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
1491                 } else {
1492                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1493                 }
1494
1495                 if (CQE_HAS_VLAN(parse_flag) ||
1496                     CQE_HAS_OUTER_VLAN(parse_flag)) {
1497                         /* Note: FW doesn't indicate Q-in-Q packet */
1498                         ol_flags |= PKT_RX_VLAN;
1499                         if (qdev->vlan_strip_flg) {
1500                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1501                                 rx_mb->vlan_tci = vlan_tci;
1502                         }
1503                 }
1504
1505                 /* RSS Hash */
1506                 if (qdev->rss_enable) {
1507                         ol_flags |= PKT_RX_RSS_HASH;
1508                         rx_mb->hash.rss = rss_hash;
1509                 }
1510
1511                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1512                         PMD_RX_LOG(ERR, rxq,
1513                                    "New buffer allocation failed,"
1514                                    "dropping incoming packet\n");
1515                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1516                         rte_eth_devices[rxq->port_id].
1517                             data->rx_mbuf_alloc_failed++;
1518                         rxq->rx_alloc_errors++;
1519                         break;
1520                 }
1521                 qede_rx_bd_ring_consume(rxq);
1522
1523                 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1524                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1525                                    " len on first: %04x Total Len: %04x",
1526                                    fp_cqe->bd_num, len, pkt_len);
1527                         num_segs = fp_cqe->bd_num - 1;
1528                         seg1 = rx_mb;
1529                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1530                                                  pkt_len - len))
1531                                 goto next_cqe;
1532                         for (j = 0; j < num_segs; j++) {
1533                                 if (qede_alloc_rx_buffer(rxq)) {
1534                                         PMD_RX_LOG(ERR, rxq,
1535                                                 "Buffer allocation failed");
1536                                         rte_eth_devices[rxq->port_id].
1537                                                 data->rx_mbuf_alloc_failed++;
1538                                         rxq->rx_alloc_errors++;
1539                                         break;
1540                                 }
1541                                 rxq->rx_segs++;
1542                         }
1543                 }
1544                 rxq->rx_segs++; /* for the first segment */
1545
1546                 /* Prefetch next mbuf while processing current one. */
1547                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1548                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1549
1550                 /* Update rest of the MBUF fields */
1551                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1552                 rx_mb->port = rxq->port_id;
1553                 rx_mb->ol_flags = ol_flags;
1554                 rx_mb->data_len = len;
1555                 rx_mb->packet_type = packet_type;
1556 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1557                 print_rx_bd_info(rx_mb, rxq, bitfield_val);
1558 #endif
1559                 if (!tpa_start_flg) {
1560                         rx_mb->nb_segs = fp_cqe->bd_num;
1561                         rx_mb->pkt_len = pkt_len;
1562                 } else {
1563                         /* store ref to the updated mbuf */
1564                         tpa_info->tpa_head = rx_mb;
1565                         tpa_info->tpa_tail = tpa_info->tpa_head;
1566                 }
1567                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1568 tpa_end:
1569                 if (!tpa_start_flg) {
1570                         rx_pkts[rx_pkt] = rx_mb;
1571                         rx_pkt++;
1572                 }
1573 next_cqe:
1574                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1575                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1576                 if (rx_pkt == nb_pkts) {
1577                         PMD_RX_LOG(DEBUG, rxq,
1578                                    "Budget reached nb_pkts=%u received=%u",
1579                                    rx_pkt, nb_pkts);
1580                         break;
1581                 }
1582         }
1583
1584         qede_update_rx_prod(qdev, rxq);
1585
1586         rxq->rcv_pkts += rx_pkt;
1587
1588         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1589
1590         return rx_pkt;
1591 }
1592
1593
1594 /* Populate scatter gather buffer descriptor fields */
1595 static inline uint16_t
1596 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1597                   struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3,
1598                   uint16_t start_seg)
1599 {
1600         struct qede_tx_queue *txq = p_txq;
1601         struct eth_tx_bd *tx_bd = NULL;
1602         dma_addr_t mapping;
1603         uint16_t nb_segs = 0;
1604
1605         /* Check for scattered buffers */
1606         while (m_seg) {
1607                 if (start_seg == 0) {
1608                         if (!*bd2) {
1609                                 *bd2 = (struct eth_tx_2nd_bd *)
1610                                         ecore_chain_produce(&txq->tx_pbl);
1611                                 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
1612                                 nb_segs++;
1613                         }
1614                         mapping = rte_mbuf_data_iova(m_seg);
1615                         QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
1616                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
1617                 } else if (start_seg == 1) {
1618                         if (!*bd3) {
1619                                 *bd3 = (struct eth_tx_3rd_bd *)
1620                                         ecore_chain_produce(&txq->tx_pbl);
1621                                 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
1622                                 nb_segs++;
1623                         }
1624                         mapping = rte_mbuf_data_iova(m_seg);
1625                         QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
1626                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
1627                 } else {
1628                         tx_bd = (struct eth_tx_bd *)
1629                                 ecore_chain_produce(&txq->tx_pbl);
1630                         memset(tx_bd, 0, sizeof(*tx_bd));
1631                         nb_segs++;
1632                         mapping = rte_mbuf_data_iova(m_seg);
1633                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1634                         PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
1635                 }
1636                 start_seg++;
1637                 m_seg = m_seg->next;
1638         }
1639
1640         /* Return total scattered buffers */
1641         return nb_segs;
1642 }
1643
1644 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1645 static inline void
1646 print_tx_bd_info(struct qede_tx_queue *txq,
1647                  struct eth_tx_1st_bd *bd1,
1648                  struct eth_tx_2nd_bd *bd2,
1649                  struct eth_tx_3rd_bd *bd3,
1650                  uint64_t tx_ol_flags)
1651 {
1652         char ol_buf[256] = { 0 }; /* for verbose prints */
1653
1654         if (bd1)
1655                 PMD_TX_LOG(INFO, txq,
1656                    "BD1: nbytes=0x%04x nbds=0x%04x bd_flags=0x%04x bf=0x%04x",
1657                    rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
1658                    bd1->data.bd_flags.bitfields,
1659                    rte_cpu_to_le_16(bd1->data.bitfields));
1660         if (bd2)
1661                 PMD_TX_LOG(INFO, txq,
1662                    "BD2: nbytes=0x%04x bf1=0x%04x bf2=0x%04x tunn_ip=0x%04x\n",
1663                    rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1,
1664                    bd2->data.bitfields2, bd2->data.tunn_ip_size);
1665         if (bd3)
1666                 PMD_TX_LOG(INFO, txq,
1667                    "BD3: nbytes=0x%04x bf=0x%04x MSS=0x%04x "
1668                    "tunn_l4_hdr_start_offset_w=0x%04x tunn_hdr_size=0x%04x\n",
1669                    rte_cpu_to_le_16(bd3->nbytes),
1670                    rte_cpu_to_le_16(bd3->data.bitfields),
1671                    rte_cpu_to_le_16(bd3->data.lso_mss),
1672                    bd3->data.tunn_l4_hdr_start_offset_w,
1673                    bd3->data.tunn_hdr_size_w);
1674
1675         rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
1676         PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
1677 }
1678 #endif
1679
1680 /* TX prepare to check packets meets TX conditions */
1681 uint16_t
1682 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1683 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
1684                     uint16_t nb_pkts)
1685 {
1686         struct qede_tx_queue *txq = p_txq;
1687 #else
1688 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
1689                     uint16_t nb_pkts)
1690 {
1691 #endif
1692         uint64_t ol_flags;
1693         struct rte_mbuf *m;
1694         uint16_t i;
1695 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1696         int ret;
1697 #endif
1698
1699         for (i = 0; i < nb_pkts; i++) {
1700                 m = tx_pkts[i];
1701                 ol_flags = m->ol_flags;
1702                 if (ol_flags & PKT_TX_TCP_SEG) {
1703                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
1704                                 rte_errno = -EINVAL;
1705                                 break;
1706                         }
1707                         /* TBD: confirm its ~9700B for both ? */
1708                         if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
1709                                 rte_errno = -EINVAL;
1710                                 break;
1711                         }
1712                 } else {
1713                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
1714                                 rte_errno = -EINVAL;
1715                                 break;
1716                         }
1717                 }
1718                 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
1719                         rte_errno = -ENOTSUP;
1720                         break;
1721                 }
1722
1723 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1724                 ret = rte_validate_tx_offload(m);
1725                 if (ret != 0) {
1726                         rte_errno = ret;
1727                         break;
1728                 }
1729 #endif
1730         }
1731
1732 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1733         if (unlikely(i != nb_pkts))
1734                 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
1735                            nb_pkts - i);
1736 #endif
1737         return i;
1738 }
1739
1740 #define MPLSINUDP_HDR_SIZE                      (12)
1741
1742 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1743 static inline void
1744 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
1745                                struct qede_tx_queue *txq)
1746 {
1747         if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
1748                 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
1749         if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
1750                 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
1751                 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
1752         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
1753                 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
1754                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1755         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
1756                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
1757                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1758 }
1759 #endif
1760
1761 uint16_t
1762 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1763 {
1764         struct qede_tx_queue *txq = p_txq;
1765         struct qede_dev *qdev = txq->qdev;
1766         struct ecore_dev *edev = &qdev->edev;
1767         struct rte_mbuf *mbuf;
1768         struct rte_mbuf *m_seg = NULL;
1769         uint16_t nb_tx_pkts;
1770         uint16_t bd_prod;
1771         uint16_t idx;
1772         uint16_t nb_frags;
1773         uint16_t nb_pkt_sent = 0;
1774         uint8_t nbds;
1775         bool lso_flg;
1776         bool mplsoudp_flg;
1777         __rte_unused bool tunn_flg;
1778         bool tunn_ipv6_ext_flg;
1779         struct eth_tx_1st_bd *bd1;
1780         struct eth_tx_2nd_bd *bd2;
1781         struct eth_tx_3rd_bd *bd3;
1782         uint64_t tx_ol_flags;
1783         uint16_t hdr_size;
1784         /* BD1 */
1785         uint16_t bd1_bf;
1786         uint8_t bd1_bd_flags_bf;
1787         uint16_t vlan;
1788         /* BD2 */
1789         uint16_t bd2_bf1;
1790         uint16_t bd2_bf2;
1791         /* BD3 */
1792         uint16_t mss;
1793         uint16_t bd3_bf;
1794
1795         uint8_t tunn_l4_hdr_start_offset;
1796         uint8_t tunn_hdr_size;
1797         uint8_t inner_l2_hdr_size;
1798         uint16_t inner_l4_hdr_offset;
1799
1800         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1801                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1802                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1803                 qede_process_tx_compl(edev, txq);
1804         }
1805
1806         nb_tx_pkts  = nb_pkts;
1807         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1808         while (nb_tx_pkts--) {
1809                 /* Init flags/values */
1810                 tunn_flg = false;
1811                 lso_flg = false;
1812                 nbds = 0;
1813                 vlan = 0;
1814                 bd1 = NULL;
1815                 bd2 = NULL;
1816                 bd3 = NULL;
1817                 hdr_size = 0;
1818                 bd1_bf = 0;
1819                 bd1_bd_flags_bf = 0;
1820                 bd2_bf1 = 0;
1821                 bd2_bf2 = 0;
1822                 mss = 0;
1823                 bd3_bf = 0;
1824                 mplsoudp_flg = false;
1825                 tunn_ipv6_ext_flg = false;
1826                 tunn_hdr_size = 0;
1827                 tunn_l4_hdr_start_offset = 0;
1828
1829                 mbuf = *tx_pkts++;
1830                 assert(mbuf);
1831
1832                 /* Check minimum TX BDS availability against available BDs */
1833                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
1834                         break;
1835
1836                 tx_ol_flags = mbuf->ol_flags;
1837                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1838
1839                 /* TX prepare would have already checked supported tunnel Tx
1840                  * offloads. Don't rely on pkt_type marked by Rx, instead use
1841                  * tx_ol_flags to decide.
1842                  */
1843                 if (((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1844                                                 PKT_TX_TUNNEL_VXLAN) ||
1845                     ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1846                                                 PKT_TX_TUNNEL_MPLSINUDP)) {
1847                         /* Check against max which is Tunnel IPv6 + ext */
1848                         if (unlikely(txq->nb_tx_avail <
1849                                 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
1850                                         break;
1851                         tunn_flg = true;
1852                         /* First indicate its a tunnel pkt */
1853                         bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1854                                   ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1855                         /* Legacy FW had flipped behavior in regard to this bit
1856                          * i.e. it needed to set to prevent FW from touching
1857                          * encapsulated packets when it didn't need to.
1858                          */
1859                         if (unlikely(txq->is_legacy)) {
1860                                 bd1_bf ^= 1 <<
1861                                         ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1862                         }
1863
1864                         /* Outer IP checksum offload */
1865                         if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
1866                                            PKT_TX_OUTER_IPV4)) {
1867                                 bd1_bd_flags_bf |=
1868                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1869                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1870                         }
1871
1872                         /**
1873                          * Currently, only inner checksum offload in MPLS-in-UDP
1874                          * tunnel with one MPLS label is supported. Both outer
1875                          * and inner layers  lengths need to be provided in
1876                          * mbuf.
1877                          */
1878                         if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1879                                                 PKT_TX_TUNNEL_MPLSINUDP) {
1880                                 mplsoudp_flg = true;
1881 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1882                                 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
1883 #endif
1884                                 /* Outer L4 offset in two byte words */
1885                                 tunn_l4_hdr_start_offset =
1886                                   (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
1887                                 /* Tunnel header size in two byte words */
1888                                 tunn_hdr_size = (mbuf->outer_l2_len +
1889                                                 mbuf->outer_l3_len +
1890                                                 MPLSINUDP_HDR_SIZE) / 2;
1891                                 /* Inner L2 header size in two byte words */
1892                                 inner_l2_hdr_size = (mbuf->l2_len -
1893                                                 MPLSINUDP_HDR_SIZE) / 2;
1894                                 /* Inner L4 header offset from the beggining
1895                                  * of inner packet in two byte words
1896                                  */
1897                                 inner_l4_hdr_offset = (mbuf->l2_len -
1898                                         MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
1899
1900                                 /* Inner L2 size and address type */
1901                                 bd2_bf1 |= (inner_l2_hdr_size &
1902                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
1903                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
1904                                 bd2_bf1 |= (UNICAST_ADDRESS &
1905                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
1906                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
1907                                 /* Treated as IPv6+Ext */
1908                                 bd2_bf1 |=
1909                                     1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
1910
1911                                 /* Mark inner IPv6 if present */
1912                                 if (tx_ol_flags & PKT_TX_IPV6)
1913                                         bd2_bf1 |=
1914                                                 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
1915
1916                                 /* Inner L4 offsets */
1917                                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1918                                      (tx_ol_flags & (PKT_TX_UDP_CKSUM |
1919                                                         PKT_TX_TCP_CKSUM))) {
1920                                         /* Determines if BD3 is needed */
1921                                         tunn_ipv6_ext_flg = true;
1922                                         if ((tx_ol_flags & PKT_TX_L4_MASK) ==
1923                                                         PKT_TX_UDP_CKSUM) {
1924                                                 bd2_bf1 |=
1925                                                         1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
1926                                         }
1927
1928                                         /* TODO other pseudo checksum modes are
1929                                          * not supported
1930                                          */
1931                                         bd2_bf1 |=
1932                                         ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
1933                                         ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
1934                                         bd2_bf2 |= (inner_l4_hdr_offset &
1935                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
1936                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
1937                                 }
1938                         } /* End MPLSoUDP */
1939                 } /* End Tunnel handling */
1940
1941                 if (tx_ol_flags & PKT_TX_TCP_SEG) {
1942                         lso_flg = true;
1943                         if (unlikely(txq->nb_tx_avail <
1944                                                 ETH_TX_MIN_BDS_PER_LSO_PKT))
1945                                 break;
1946                         /* For LSO, packet header and payload must reside on
1947                          * buffers pointed by different BDs. Using BD1 for HDR
1948                          * and BD2 onwards for data.
1949                          */
1950                         hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
1951                         if (tunn_flg)
1952                                 hdr_size += mbuf->outer_l2_len +
1953                                             mbuf->outer_l3_len;
1954
1955                         bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
1956                         bd1_bd_flags_bf |=
1957                                         1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1958                         /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
1959                         bd1_bd_flags_bf |=
1960                                         1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1961                         mss = rte_cpu_to_le_16(mbuf->tso_segsz);
1962                         /* Using one header BD */
1963                         bd3_bf |= rte_cpu_to_le_16(1 <<
1964                                         ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
1965                 } else {
1966                         if (unlikely(txq->nb_tx_avail <
1967                                         ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
1968                                 break;
1969                         bd1_bf |=
1970                                (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1971                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1972                 }
1973
1974                 /* Descriptor based VLAN insertion */
1975                 if (tx_ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1976                         vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1977                         bd1_bd_flags_bf |=
1978                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1979                 }
1980
1981                 /* Offload the IP checksum in the hardware */
1982                 if (tx_ol_flags & PKT_TX_IP_CKSUM) {
1983                         bd1_bd_flags_bf |=
1984                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1985                         /* There's no DPDK flag to request outer-L4 csum
1986                          * offload. But in the case of tunnel if inner L3 or L4
1987                          * csum offload is requested then we need to force
1988                          * recalculation of L4 tunnel header csum also.
1989                          */
1990                         if (tunn_flg) {
1991                                 bd1_bd_flags_bf |=
1992                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1993                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1994                         }
1995                 }
1996
1997                 /* L4 checksum offload (tcp or udp) */
1998                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1999                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
2000                         bd1_bd_flags_bf |=
2001                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
2002                         /* There's no DPDK flag to request outer-L4 csum
2003                          * offload. But in the case of tunnel if inner L3 or L4
2004                          * csum offload is requested then we need to force
2005                          * recalculation of L4 tunnel header csum also.
2006                          */
2007                         if (tunn_flg) {
2008                                 bd1_bd_flags_bf |=
2009                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
2010                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
2011                         }
2012                 }
2013
2014                 /* Fill the entry in the SW ring and the BDs in the FW ring */
2015                 idx = TX_PROD(txq);
2016                 txq->sw_tx_ring[idx].mbuf = mbuf;
2017
2018                 /* BD1 */
2019                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
2020                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
2021                 nbds++;
2022
2023                 /* Map MBUF linear data for DMA and set in the BD1 */
2024                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2025                                      mbuf->data_len);
2026                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
2027                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
2028                 bd1->data.vlan = vlan;
2029
2030                 if (lso_flg || mplsoudp_flg) {
2031                         bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
2032                                                         (&txq->tx_pbl);
2033                         memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
2034                         nbds++;
2035
2036                         /* BD1 */
2037                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
2038                                              hdr_size);
2039                         /* BD2 */
2040                         QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
2041                                              rte_mbuf_data_iova(mbuf)),
2042                                              mbuf->data_len - hdr_size);
2043                         bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
2044                         if (mplsoudp_flg) {
2045                                 bd2->data.bitfields2 =
2046                                         rte_cpu_to_le_16(bd2_bf2);
2047                                 /* Outer L3 size */
2048                                 bd2->data.tunn_ip_size =
2049                                         rte_cpu_to_le_16(mbuf->outer_l3_len);
2050                         }
2051                         /* BD3 */
2052                         if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
2053                                 bd3 = (struct eth_tx_3rd_bd *)
2054                                         ecore_chain_produce(&txq->tx_pbl);
2055                                 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
2056                                 nbds++;
2057                                 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
2058                                 if (lso_flg)
2059                                         bd3->data.lso_mss = mss;
2060                                 if (mplsoudp_flg) {
2061                                         bd3->data.tunn_l4_hdr_start_offset_w =
2062                                                 tunn_l4_hdr_start_offset;
2063                                         bd3->data.tunn_hdr_size_w =
2064                                                 tunn_hdr_size;
2065                                 }
2066                         }
2067                 }
2068
2069                 /* Handle fragmented MBUF */
2070                 m_seg = mbuf->next;
2071
2072                 /* Encode scatter gather buffer descriptors if required */
2073                 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3, nbds - 1);
2074                 bd1->data.nbds = nbds + nb_frags;
2075
2076                 txq->nb_tx_avail -= bd1->data.nbds;
2077                 txq->sw_tx_prod++;
2078                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
2079                 bd_prod =
2080                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2081 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2082                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2083 #endif
2084                 nb_pkt_sent++;
2085                 txq->xmit_pkts++;
2086         }
2087
2088         /* Write value of prod idx into bd_prod */
2089         txq->tx_db.data.bd_prod = bd_prod;
2090         rte_wmb();
2091         rte_compiler_barrier();
2092         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2093         rte_wmb();
2094
2095         /* Check again for Tx completions */
2096         qede_process_tx_compl(edev, txq);
2097
2098         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2099                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2100
2101         return nb_pkt_sent;
2102 }
2103
2104 uint16_t
2105 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
2106                      __rte_unused struct rte_mbuf **pkts,
2107                      __rte_unused uint16_t nb_pkts)
2108 {
2109         return 0;
2110 }