2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
13 #include "qede_ethdev.h"
15 /* Ring Descriptors */
16 #define RX_RING_SIZE_POW 16 /* 64K */
17 #define RX_RING_SIZE (1ULL << RX_RING_SIZE_POW)
18 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
19 #define NUM_RX_BDS_MIN 128
20 #define NUM_RX_BDS_DEF NUM_RX_BDS_MAX
21 #define NUM_RX_BDS(q) (q->nb_rx_desc - 1)
23 #define TX_RING_SIZE_POW 16 /* 64K */
24 #define TX_RING_SIZE (1ULL << TX_RING_SIZE_POW)
25 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
26 #define NUM_TX_BDS_MIN 128
27 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
28 #define NUM_TX_BDS(q) (q->nb_tx_desc - 1)
30 #define TX_CONS(txq) (txq->sw_tx_cons & NUM_TX_BDS(txq))
31 #define TX_PROD(txq) (txq->sw_tx_prod & NUM_TX_BDS(txq))
33 #define QEDE_DEFAULT_TX_FREE_THRESH 32
35 #define QEDE_CSUM_ERROR (1 << 0)
36 #define QEDE_CSUM_UNNECESSARY (1 << 1)
37 #define QEDE_TUNN_CSUM_UNNECESSARY (1 << 2)
39 #define QEDE_BD_SET_ADDR_LEN(bd, maddr, len) \
41 (bd)->addr.hi = rte_cpu_to_le_32(U64_HI(maddr)); \
42 (bd)->addr.lo = rte_cpu_to_le_32(U64_LO(maddr)); \
43 (bd)->nbytes = rte_cpu_to_le_16(len); \
44 /* FW 8.10.x specific change */ \
45 (bd)->data.bitfields = ((len) & \
46 ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) \
47 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT; \
50 #define CQE_HAS_VLAN(flags) \
51 ((flags) & (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK \
52 << PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT))
54 #define CQE_HAS_OUTER_VLAN(flags) \
55 ((flags) & (PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK \
56 << PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT))
58 #define QEDE_MIN_RX_BUFF_SIZE (1024)
59 #define QEDE_VLAN_TAG_SIZE (4)
60 #define QEDE_LLC_SNAP_HDR_LEN (8)
62 /* Max supported alignment is 256 (8 shift)
63 * minimal alignment shift 6 is optimal for 57xxx HW performance
65 #define QEDE_L1_CACHE_SHIFT 6
66 #define QEDE_RX_ALIGN_SHIFT (RTE_MAX(6, RTE_MIN(8, QEDE_L1_CACHE_SHIFT)))
67 #define QEDE_FW_RX_ALIGN_END (1UL << QEDE_RX_ALIGN_SHIFT)
68 #define QEDE_CEIL_TO_CACHE_LINE_SIZE(n) (((n) + (QEDE_FW_RX_ALIGN_END - 1)) & \
69 ~(QEDE_FW_RX_ALIGN_END - 1))
70 /* Note: QEDE_LLC_SNAP_HDR_LEN is optional */
71 #define QEDE_ETH_OVERHEAD (((2 * QEDE_VLAN_TAG_SIZE)) - (ETHER_CRC_LEN) \
72 + (QEDE_LLC_SNAP_HDR_LEN))
74 /* TBD: Excluding IPV6 */
75 #define QEDE_RSS_OFFLOAD_ALL (ETH_RSS_IPV4 | ETH_RSS_NONFRAG_IPV4_TCP | \
76 ETH_RSS_NONFRAG_IPV4_UDP)
78 #define QEDE_TXQ_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS)
82 #define for_each_queue(i) for (i = 0; i < qdev->num_queues; i++)
85 * RX BD descriptor ring
87 struct qede_rx_entry {
88 struct rte_mbuf *mbuf;
90 /* allows expansion .. */
94 * Structure associated with each RX queue.
96 struct qede_rx_queue {
97 struct rte_mempool *mb_pool;
98 struct ecore_chain rx_bd_ring;
99 struct ecore_chain rx_comp_ring;
100 uint16_t *hw_cons_ptr;
101 void OSAL_IOMEM *hw_rxq_prod_addr;
102 struct qede_rx_entry *sw_rx_ring;
108 uint16_t rx_buf_size;
111 uint64_t rx_hw_errors;
112 uint64_t rx_alloc_errors;
113 struct qede_dev *qdev;
117 * TX BD descriptor ring
119 struct qede_tx_entry {
120 struct rte_mbuf *mbuf;
125 struct eth_db_data data;
129 struct qede_tx_queue {
130 struct ecore_chain tx_pbl;
131 struct qede_tx_entry *sw_tx_ring;
133 uint16_t nb_tx_avail;
134 uint16_t tx_free_thresh;
136 uint16_t *hw_cons_ptr;
139 void OSAL_IOMEM *doorbell_addr;
140 volatile union db_prod tx_db;
143 struct qede_dev *qdev;
146 struct qede_fastpath {
147 struct qede_dev *qdev;
150 struct ecore_sb_info *sb_info;
151 struct qede_rx_queue *rxq;
152 struct qede_tx_queue *txqs[MAX_NUM_TC];
157 * RX/TX function prototypes
159 int qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
160 uint16_t nb_desc, unsigned int socket_id,
161 const struct rte_eth_rxconf *rx_conf,
162 struct rte_mempool *mp);
164 int qede_tx_queue_setup(struct rte_eth_dev *dev,
167 unsigned int socket_id,
168 const struct rte_eth_txconf *tx_conf);
170 void qede_rx_queue_release(void *rx_queue);
172 void qede_tx_queue_release(void *tx_queue);
174 int qede_dev_start(struct rte_eth_dev *eth_dev);
176 void qede_dev_stop(struct rte_eth_dev *eth_dev);
178 int qede_reset_fp_rings(struct qede_dev *qdev);
180 void qede_free_fp_arrays(struct qede_dev *qdev);
182 void qede_free_mem_load(struct rte_eth_dev *eth_dev);
184 uint16_t qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
187 uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts,
190 uint16_t qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
191 __rte_unused struct rte_mbuf **pkts,
192 __rte_unused uint16_t nb_pkts);
194 /* Fastpath resource alloc/dealloc helpers */
195 int qede_alloc_fp_resc(struct qede_dev *qdev);
197 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev);
199 #endif /* _QEDE_RXTX_H_ */