1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2015-2018 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
15 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
16 #define EF10_MAX_PIOBUF_NBUFS (16)
18 #if EFSYS_OPT_HUNTINGTON
19 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
20 # error "EF10_MAX_PIOBUF_NBUFS too small"
22 #endif /* EFSYS_OPT_HUNTINGTON */
24 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
25 # error "EF10_MAX_PIOBUF_NBUFS too small"
27 #endif /* EFSYS_OPT_MEDFORD */
28 #if EFSYS_OPT_MEDFORD2
29 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
30 # error "EF10_MAX_PIOBUF_NBUFS too small"
32 #endif /* EFSYS_OPT_MEDFORD2 */
37 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
38 * possibly be increased, or the write size reported by newer firmware used
41 #define EF10_NVRAM_CHUNK 0x80
44 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
45 * to an 8 descriptor boundary.
47 #define EF10_RX_WPTR_ALIGN 8
50 * Max byte offset into the packet the TCP header must start for the hardware
51 * to be able to parse the packet correctly.
53 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
55 /* Invalid RSS context handle */
56 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
61 __checkReturn efx_rc_t
69 __checkReturn efx_rc_t
72 __in unsigned int index,
73 __in efsys_mem_t *esmp,
84 __checkReturn efx_rc_t
87 __in unsigned int count);
94 __checkReturn efx_rc_t
97 __in unsigned int us);
101 ef10_ev_qstats_update(
103 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
104 #endif /* EFSYS_OPT_QSTATS */
107 ef10_ev_rxlabel_init(
110 __in unsigned int label,
111 __in efx_rxq_type_t type);
114 ef10_ev_rxlabel_fini(
116 __in unsigned int label);
120 __checkReturn efx_rc_t
123 __in efx_intr_type_t type,
124 __in efsys_mem_t *esmp);
128 __in efx_nic_t *enp);
132 __in efx_nic_t *enp);
135 ef10_intr_disable_unlocked(
136 __in efx_nic_t *enp);
138 __checkReturn efx_rc_t
141 __in unsigned int level);
144 ef10_intr_status_line(
146 __out boolean_t *fatalp,
147 __out uint32_t *qmaskp);
150 ef10_intr_status_message(
152 __in unsigned int message,
153 __out boolean_t *fatalp);
157 __in efx_nic_t *enp);
160 __in efx_nic_t *enp);
164 extern __checkReturn efx_rc_t
166 __in efx_nic_t *enp);
168 extern __checkReturn efx_rc_t
169 ef10_nic_set_drv_limits(
170 __inout efx_nic_t *enp,
171 __in efx_drv_limits_t *edlp);
173 extern __checkReturn efx_rc_t
174 ef10_nic_get_vi_pool(
176 __out uint32_t *vi_countp);
178 extern __checkReturn efx_rc_t
179 ef10_nic_get_bar_region(
181 __in efx_nic_region_t region,
182 __out uint32_t *offsetp,
183 __out size_t *sizep);
185 extern __checkReturn efx_rc_t
187 __in efx_nic_t *enp);
189 extern __checkReturn efx_rc_t
191 __in efx_nic_t *enp);
193 extern __checkReturn boolean_t
194 ef10_nic_hw_unavailable(
195 __in efx_nic_t *enp);
198 ef10_nic_set_hw_unavailable(
199 __in efx_nic_t *enp);
203 extern __checkReturn efx_rc_t
204 ef10_nic_register_test(
205 __in efx_nic_t *enp);
207 #endif /* EFSYS_OPT_DIAG */
211 __in efx_nic_t *enp);
215 __in efx_nic_t *enp);
220 extern __checkReturn efx_rc_t
223 __out efx_link_mode_t *link_modep);
225 extern __checkReturn efx_rc_t
228 __out boolean_t *mac_upp);
230 extern __checkReturn efx_rc_t
232 __in efx_nic_t *enp);
234 extern __checkReturn efx_rc_t
236 __in efx_nic_t *enp);
238 extern __checkReturn efx_rc_t
243 extern __checkReturn efx_rc_t
244 ef10_mac_reconfigure(
245 __in efx_nic_t *enp);
247 extern __checkReturn efx_rc_t
248 ef10_mac_multicast_list_set(
249 __in efx_nic_t *enp);
251 extern __checkReturn efx_rc_t
252 ef10_mac_filter_default_rxq_set(
255 __in boolean_t using_rss);
258 ef10_mac_filter_default_rxq_clear(
259 __in efx_nic_t *enp);
261 #if EFSYS_OPT_LOOPBACK
263 extern __checkReturn efx_rc_t
264 ef10_mac_loopback_set(
266 __in efx_link_mode_t link_mode,
267 __in efx_loopback_type_t loopback_type);
269 #endif /* EFSYS_OPT_LOOPBACK */
271 #if EFSYS_OPT_MAC_STATS
273 extern __checkReturn efx_rc_t
274 ef10_mac_stats_get_mask(
276 __inout_bcount(mask_size) uint32_t *maskp,
277 __in size_t mask_size);
279 extern __checkReturn efx_rc_t
280 ef10_mac_stats_update(
282 __in efsys_mem_t *esmp,
283 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
284 __inout_opt uint32_t *generationp);
286 #endif /* EFSYS_OPT_MAC_STATS */
293 extern __checkReturn efx_rc_t
296 __in const efx_mcdi_transport_t *mtp);
300 __in efx_nic_t *enp);
303 ef10_mcdi_send_request(
305 __in_bcount(hdr_len) void *hdrp,
307 __in_bcount(sdu_len) void *sdup,
308 __in size_t sdu_len);
310 extern __checkReturn boolean_t
311 ef10_mcdi_poll_response(
312 __in efx_nic_t *enp);
315 ef10_mcdi_read_response(
317 __out_bcount(length) void *bufferp,
322 ef10_mcdi_poll_reboot(
323 __in efx_nic_t *enp);
325 extern __checkReturn efx_rc_t
326 ef10_mcdi_feature_supported(
328 __in efx_mcdi_feature_id_t id,
329 __out boolean_t *supportedp);
332 ef10_mcdi_get_timeout(
334 __in efx_mcdi_req_t *emrp,
335 __out uint32_t *timeoutp);
337 #endif /* EFSYS_OPT_MCDI */
341 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
343 extern __checkReturn efx_rc_t
344 ef10_nvram_buf_read_tlv(
346 __in_bcount(max_seg_size) caddr_t seg_data,
347 __in size_t max_seg_size,
349 __deref_out_bcount_opt(*sizep) caddr_t *datap,
350 __out size_t *sizep);
352 extern __checkReturn efx_rc_t
353 ef10_nvram_buf_write_tlv(
354 __inout_bcount(partn_size) caddr_t partn_data,
355 __in size_t partn_size,
357 __in_bcount(tag_size) caddr_t tag_data,
358 __in size_t tag_size,
359 __out size_t *total_lengthp);
361 extern __checkReturn efx_rc_t
362 ef10_nvram_partn_read_tlv(
366 __deref_out_bcount_opt(*sizep) caddr_t *datap,
367 __out size_t *sizep);
369 extern __checkReturn efx_rc_t
370 ef10_nvram_partn_write_tlv(
374 __in_bcount(size) caddr_t data,
377 extern __checkReturn efx_rc_t
378 ef10_nvram_partn_write_segment_tlv(
382 __in_bcount(size) caddr_t data,
384 __in boolean_t all_segments);
386 extern __checkReturn efx_rc_t
387 ef10_nvram_partn_lock(
389 __in uint32_t partn);
391 extern __checkReturn efx_rc_t
392 ef10_nvram_partn_unlock(
395 __out_opt uint32_t *resultp);
397 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
403 extern __checkReturn efx_rc_t
405 __in efx_nic_t *enp);
407 #endif /* EFSYS_OPT_DIAG */
409 extern __checkReturn efx_rc_t
410 ef10_nvram_type_to_partn(
412 __in efx_nvram_type_t type,
413 __out uint32_t *partnp);
415 extern __checkReturn efx_rc_t
416 ef10_nvram_partn_size(
419 __out size_t *sizep);
421 extern __checkReturn efx_rc_t
422 ef10_nvram_partn_rw_start(
425 __out size_t *chunk_sizep);
427 extern __checkReturn efx_rc_t
428 ef10_nvram_partn_read_mode(
431 __in unsigned int offset,
432 __out_bcount(size) caddr_t data,
436 extern __checkReturn efx_rc_t
437 ef10_nvram_partn_read(
440 __in unsigned int offset,
441 __out_bcount(size) caddr_t data,
444 extern __checkReturn efx_rc_t
445 ef10_nvram_partn_read_backup(
448 __in unsigned int offset,
449 __out_bcount(size) caddr_t data,
452 extern __checkReturn efx_rc_t
453 ef10_nvram_partn_erase(
456 __in unsigned int offset,
459 extern __checkReturn efx_rc_t
460 ef10_nvram_partn_write(
463 __in unsigned int offset,
464 __in_bcount(size) caddr_t data,
467 extern __checkReturn efx_rc_t
468 ef10_nvram_partn_rw_finish(
471 __out_opt uint32_t *verify_resultp);
473 extern __checkReturn efx_rc_t
474 ef10_nvram_partn_get_version(
477 __out uint32_t *subtypep,
478 __out_ecount(4) uint16_t version[4]);
480 extern __checkReturn efx_rc_t
481 ef10_nvram_partn_set_version(
484 __in_ecount(4) uint16_t version[4]);
486 extern __checkReturn efx_rc_t
487 ef10_nvram_buffer_validate(
489 __in_bcount(buffer_size)
491 __in size_t buffer_size);
494 ef10_nvram_buffer_init(
495 __out_bcount(buffer_size)
497 __in size_t buffer_size);
499 extern __checkReturn efx_rc_t
500 ef10_nvram_buffer_create(
501 __in uint32_t partn_type,
502 __out_bcount(buffer_size)
504 __in size_t buffer_size);
506 extern __checkReturn efx_rc_t
507 ef10_nvram_buffer_find_item_start(
508 __in_bcount(buffer_size)
510 __in size_t buffer_size,
511 __out uint32_t *startp);
513 extern __checkReturn efx_rc_t
514 ef10_nvram_buffer_find_end(
515 __in_bcount(buffer_size)
517 __in size_t buffer_size,
518 __in uint32_t offset,
519 __out uint32_t *endp);
521 extern __checkReturn __success(return != B_FALSE) boolean_t
522 ef10_nvram_buffer_find_item(
523 __in_bcount(buffer_size)
525 __in size_t buffer_size,
526 __in uint32_t offset,
527 __out uint32_t *startp,
528 __out uint32_t *lengthp);
530 extern __checkReturn efx_rc_t
531 ef10_nvram_buffer_peek_item(
532 __in_bcount(buffer_size)
534 __in size_t buffer_size,
535 __in uint32_t offset,
536 __out uint32_t *tagp,
537 __out uint32_t *lengthp,
538 __out uint32_t *value_offsetp);
540 extern __checkReturn efx_rc_t
541 ef10_nvram_buffer_get_item(
542 __in_bcount(buffer_size)
544 __in size_t buffer_size,
545 __in uint32_t offset,
546 __in uint32_t length,
547 __out uint32_t *tagp,
548 __out_bcount_part(value_max_size, *lengthp)
550 __in size_t value_max_size,
551 __out uint32_t *lengthp);
553 extern __checkReturn efx_rc_t
554 ef10_nvram_buffer_insert_item(
555 __in_bcount(buffer_size)
557 __in size_t buffer_size,
558 __in uint32_t offset,
560 __in_bcount(length) caddr_t valuep,
561 __in uint32_t length,
562 __out uint32_t *lengthp);
564 extern __checkReturn efx_rc_t
565 ef10_nvram_buffer_modify_item(
566 __in_bcount(buffer_size)
568 __in size_t buffer_size,
569 __in uint32_t offset,
571 __in_bcount(length) caddr_t valuep,
572 __in uint32_t length,
573 __out uint32_t *lengthp);
575 extern __checkReturn efx_rc_t
576 ef10_nvram_buffer_delete_item(
577 __in_bcount(buffer_size)
579 __in size_t buffer_size,
580 __in uint32_t offset,
581 __in uint32_t length,
584 extern __checkReturn efx_rc_t
585 ef10_nvram_buffer_finish(
586 __in_bcount(buffer_size)
588 __in size_t buffer_size);
590 #endif /* EFSYS_OPT_NVRAM */
595 typedef struct ef10_link_state_s {
596 efx_phy_link_state_t epls;
597 #if EFSYS_OPT_LOOPBACK
598 efx_loopback_type_t els_loopback;
600 boolean_t els_mac_up;
606 __in efx_qword_t *eqp,
607 __out efx_link_mode_t *link_modep);
609 extern __checkReturn efx_rc_t
612 __out ef10_link_state_t *elsp);
614 extern __checkReturn efx_rc_t
619 extern __checkReturn efx_rc_t
620 ef10_phy_reconfigure(
621 __in efx_nic_t *enp);
623 extern __checkReturn efx_rc_t
625 __in efx_nic_t *enp);
627 extern __checkReturn efx_rc_t
630 __out uint32_t *ouip);
632 extern __checkReturn efx_rc_t
633 ef10_phy_link_state_get(
635 __out efx_phy_link_state_t *eplsp);
637 #if EFSYS_OPT_PHY_STATS
639 extern __checkReturn efx_rc_t
640 ef10_phy_stats_update(
642 __in efsys_mem_t *esmp,
643 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
645 #endif /* EFSYS_OPT_PHY_STATS */
649 extern __checkReturn efx_rc_t
650 ef10_bist_enable_offline(
651 __in efx_nic_t *enp);
653 extern __checkReturn efx_rc_t
656 __in efx_bist_type_t type);
658 extern __checkReturn efx_rc_t
661 __in efx_bist_type_t type,
662 __out efx_bist_result_t *resultp,
663 __out_opt __drv_when(count > 0, __notnull)
664 uint32_t *value_maskp,
665 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
666 unsigned long *valuesp,
672 __in efx_bist_type_t type);
674 #endif /* EFSYS_OPT_BIST */
678 extern __checkReturn efx_rc_t
680 __in efx_nic_t *enp);
684 __in efx_nic_t *enp);
686 extern __checkReturn efx_rc_t
689 __in unsigned int index,
690 __in unsigned int label,
691 __in efsys_mem_t *esmp,
697 __out unsigned int *addedp);
701 __in efx_txq_t *etp);
703 extern __checkReturn efx_rc_t
706 __in_ecount(ndescs) efx_buffer_t *ebp,
707 __in unsigned int ndescs,
708 __in unsigned int completed,
709 __inout unsigned int *addedp);
714 __in unsigned int added,
715 __in unsigned int pushed);
717 #if EFSYS_OPT_RX_PACKED_STREAM
719 ef10_rx_qpush_ps_credits(
720 __in efx_rxq_t *erp);
722 extern __checkReturn uint8_t *
723 ef10_rx_qps_packet_info(
725 __in uint8_t *buffer,
726 __in uint32_t buffer_length,
727 __in uint32_t current_offset,
728 __out uint16_t *lengthp,
729 __out uint32_t *next_offsetp,
730 __out uint32_t *timestamp);
733 extern __checkReturn efx_rc_t
736 __in unsigned int ns);
738 extern __checkReturn efx_rc_t
740 __in efx_txq_t *etp);
744 __in efx_txq_t *etp);
746 extern __checkReturn efx_rc_t
748 __in efx_txq_t *etp);
751 ef10_tx_qpio_disable(
752 __in efx_txq_t *etp);
754 extern __checkReturn efx_rc_t
757 __in_ecount(buf_length) uint8_t *buffer,
758 __in size_t buf_length,
759 __in size_t pio_buf_offset);
761 extern __checkReturn efx_rc_t
764 __in size_t pkt_length,
765 __in unsigned int completed,
766 __inout unsigned int *addedp);
768 extern __checkReturn efx_rc_t
771 __in_ecount(n) efx_desc_t *ed,
773 __in unsigned int completed,
774 __inout unsigned int *addedp);
777 ef10_tx_qdesc_dma_create(
779 __in efsys_dma_addr_t addr,
782 __out efx_desc_t *edp);
785 ef10_tx_qdesc_tso_create(
787 __in uint16_t ipv4_id,
788 __in uint32_t tcp_seq,
789 __in uint8_t tcp_flags,
790 __out efx_desc_t *edp);
793 ef10_tx_qdesc_tso2_create(
795 __in uint16_t ipv4_id,
796 __in uint16_t outer_ipv4_id,
797 __in uint32_t tcp_seq,
798 __in uint16_t tcp_mss,
799 __out_ecount(count) efx_desc_t *edp,
803 ef10_tx_qdesc_vlantci_create(
805 __in uint16_t vlan_tci,
806 __out efx_desc_t *edp);
809 ef10_tx_qdesc_checksum_create(
812 __out efx_desc_t *edp);
817 ef10_tx_qstats_update(
819 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
821 #endif /* EFSYS_OPT_QSTATS */
823 typedef uint32_t efx_piobuf_handle_t;
825 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
827 extern __checkReturn efx_rc_t
829 __inout efx_nic_t *enp,
830 __out uint32_t *bufnump,
831 __out efx_piobuf_handle_t *handlep,
832 __out uint32_t *blknump,
833 __out uint32_t *offsetp,
834 __out size_t *sizep);
836 extern __checkReturn efx_rc_t
838 __inout efx_nic_t *enp,
839 __in uint32_t bufnum,
840 __in uint32_t blknum);
842 extern __checkReturn efx_rc_t
844 __inout efx_nic_t *enp,
845 __in uint32_t vi_index,
846 __in efx_piobuf_handle_t handle);
848 extern __checkReturn efx_rc_t
850 __inout efx_nic_t *enp,
851 __in uint32_t vi_index);
858 extern __checkReturn efx_rc_t
860 __in efx_nic_t *enp);
862 extern __checkReturn efx_rc_t
865 __out size_t *sizep);
867 extern __checkReturn efx_rc_t
870 __out_bcount(size) caddr_t data,
873 extern __checkReturn efx_rc_t
876 __in_bcount(size) caddr_t data,
879 extern __checkReturn efx_rc_t
882 __in_bcount(size) caddr_t data,
885 extern __checkReturn efx_rc_t
888 __in_bcount(size) caddr_t data,
890 __inout efx_vpd_value_t *evvp);
892 extern __checkReturn efx_rc_t
895 __in_bcount(size) caddr_t data,
897 __in efx_vpd_value_t *evvp);
899 extern __checkReturn efx_rc_t
902 __in_bcount(size) caddr_t data,
904 __out efx_vpd_value_t *evvp,
905 __inout unsigned int *contp);
907 extern __checkReturn efx_rc_t
910 __in_bcount(size) caddr_t data,
915 __in efx_nic_t *enp);
917 #endif /* EFSYS_OPT_VPD */
922 extern __checkReturn efx_rc_t
924 __in efx_nic_t *enp);
926 #if EFSYS_OPT_RX_SCATTER
927 extern __checkReturn efx_rc_t
928 ef10_rx_scatter_enable(
930 __in unsigned int buf_size);
931 #endif /* EFSYS_OPT_RX_SCATTER */
934 #if EFSYS_OPT_RX_SCALE
936 extern __checkReturn efx_rc_t
937 ef10_rx_scale_context_alloc(
939 __in efx_rx_scale_context_type_t type,
940 __in uint32_t num_queues,
941 __out uint32_t *rss_contextp);
943 extern __checkReturn efx_rc_t
944 ef10_rx_scale_context_free(
946 __in uint32_t rss_context);
948 extern __checkReturn efx_rc_t
949 ef10_rx_scale_mode_set(
951 __in uint32_t rss_context,
952 __in efx_rx_hash_alg_t alg,
953 __in efx_rx_hash_type_t type,
954 __in boolean_t insert);
956 extern __checkReturn efx_rc_t
957 ef10_rx_scale_key_set(
959 __in uint32_t rss_context,
960 __in_ecount(n) uint8_t *key,
963 extern __checkReturn efx_rc_t
964 ef10_rx_scale_tbl_set(
966 __in uint32_t rss_context,
967 __in_ecount(n) unsigned int *table,
970 extern __checkReturn uint32_t
973 __in efx_rx_hash_alg_t func,
974 __in uint8_t *buffer);
976 #endif /* EFSYS_OPT_RX_SCALE */
978 extern __checkReturn efx_rc_t
979 ef10_rx_prefix_pktlen(
981 __in uint8_t *buffer,
982 __out uint16_t *lengthp);
987 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
989 __in unsigned int ndescs,
990 __in unsigned int completed,
991 __in unsigned int added);
996 __in unsigned int added,
997 __inout unsigned int *pushedp);
999 extern __checkReturn efx_rc_t
1001 __in efx_rxq_t *erp);
1005 __in efx_rxq_t *erp);
1007 union efx_rxq_type_data_u;
1009 extern __checkReturn efx_rc_t
1011 __in efx_nic_t *enp,
1012 __in unsigned int index,
1013 __in unsigned int label,
1014 __in efx_rxq_type_t type,
1015 __in const union efx_rxq_type_data_u *type_data,
1016 __in efsys_mem_t *esmp,
1019 __in unsigned int flags,
1020 __in efx_evq_t *eep,
1021 __in efx_rxq_t *erp);
1025 __in efx_rxq_t *erp);
1029 __in efx_nic_t *enp);
1031 #if EFSYS_OPT_FILTER
1033 typedef struct ef10_filter_handle_s {
1036 } ef10_filter_handle_t;
1038 typedef struct ef10_filter_entry_s {
1039 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1040 ef10_filter_handle_t efe_handle;
1041 } ef10_filter_entry_t;
1044 * BUSY flag indicates that an update is in progress.
1045 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1047 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1048 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1049 #define EFX_EF10_FILTER_FLAGS 3U
1052 * Size of the hash table used by the driver. Doesn't need to be the
1053 * same size as the hardware's table.
1055 #define EFX_EF10_FILTER_TBL_ROWS 8192
1057 /* Only need to allow for one directed and one unknown unicast filter */
1058 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1060 /* Allow for the broadcast address to be added to the multicast list */
1061 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1064 * For encapsulated packets, there is one filter each for each combination of
1065 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1066 * multicast inner frames.
1068 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1070 typedef struct ef10_filter_table_s {
1071 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1072 efx_rxq_t *eft_default_rxq;
1073 boolean_t eft_using_rss;
1074 uint32_t eft_unicst_filter_indexes[
1075 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1076 uint32_t eft_unicst_filter_count;
1077 uint32_t eft_mulcst_filter_indexes[
1078 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1079 uint32_t eft_mulcst_filter_count;
1080 boolean_t eft_using_all_mulcst;
1081 uint32_t eft_encap_filter_indexes[
1082 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1083 uint32_t eft_encap_filter_count;
1084 } ef10_filter_table_t;
1086 __checkReturn efx_rc_t
1088 __in efx_nic_t *enp);
1092 __in efx_nic_t *enp);
1094 __checkReturn efx_rc_t
1095 ef10_filter_restore(
1096 __in efx_nic_t *enp);
1098 __checkReturn efx_rc_t
1100 __in efx_nic_t *enp,
1101 __inout efx_filter_spec_t *spec,
1102 __in boolean_t may_replace);
1104 __checkReturn efx_rc_t
1106 __in efx_nic_t *enp,
1107 __inout efx_filter_spec_t *spec);
1109 extern __checkReturn efx_rc_t
1110 ef10_filter_supported_filters(
1111 __in efx_nic_t *enp,
1112 __out_ecount(buffer_length) uint32_t *buffer,
1113 __in size_t buffer_length,
1114 __out size_t *list_lengthp);
1116 extern __checkReturn efx_rc_t
1117 ef10_filter_reconfigure(
1118 __in efx_nic_t *enp,
1119 __in_ecount(6) uint8_t const *mac_addr,
1120 __in boolean_t all_unicst,
1121 __in boolean_t mulcst,
1122 __in boolean_t all_mulcst,
1123 __in boolean_t brdcst,
1124 __in_ecount(6*count) uint8_t const *addrs,
1125 __in uint32_t count);
1128 ef10_filter_get_default_rxq(
1129 __in efx_nic_t *enp,
1130 __out efx_rxq_t **erpp,
1131 __out boolean_t *using_rss);
1134 ef10_filter_default_rxq_set(
1135 __in efx_nic_t *enp,
1136 __in efx_rxq_t *erp,
1137 __in boolean_t using_rss);
1140 ef10_filter_default_rxq_clear(
1141 __in efx_nic_t *enp);
1144 #endif /* EFSYS_OPT_FILTER */
1146 extern __checkReturn efx_rc_t
1147 efx_mcdi_get_function_info(
1148 __in efx_nic_t *enp,
1149 __out uint32_t *pfp,
1150 __out_opt uint32_t *vfp);
1152 extern __checkReturn efx_rc_t
1153 efx_mcdi_privilege_mask(
1154 __in efx_nic_t *enp,
1157 __out uint32_t *maskp);
1159 extern __checkReturn efx_rc_t
1160 efx_mcdi_get_port_assignment(
1161 __in efx_nic_t *enp,
1162 __out uint32_t *portp);
1164 extern __checkReturn efx_rc_t
1165 efx_mcdi_get_port_modes(
1166 __in efx_nic_t *enp,
1167 __out uint32_t *modesp,
1168 __out_opt uint32_t *current_modep,
1169 __out_opt uint32_t *default_modep);
1171 extern __checkReturn efx_rc_t
1172 ef10_nic_get_port_mode_bandwidth(
1173 __in efx_nic_t *enp,
1174 __out uint32_t *bandwidth_mbpsp);
1176 extern __checkReturn efx_rc_t
1177 efx_mcdi_get_mac_address_pf(
1178 __in efx_nic_t *enp,
1179 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1181 extern __checkReturn efx_rc_t
1182 efx_mcdi_get_mac_address_vf(
1183 __in efx_nic_t *enp,
1184 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1186 extern __checkReturn efx_rc_t
1188 __in efx_nic_t *enp,
1189 __out uint32_t *sys_freqp,
1190 __out uint32_t *dpcpu_freqp);
1193 extern __checkReturn efx_rc_t
1194 efx_mcdi_get_rxdp_config(
1195 __in efx_nic_t *enp,
1196 __out uint32_t *end_paddingp);
1198 extern __checkReturn efx_rc_t
1199 efx_mcdi_get_vector_cfg(
1200 __in efx_nic_t *enp,
1201 __out_opt uint32_t *vec_basep,
1202 __out_opt uint32_t *pf_nvecp,
1203 __out_opt uint32_t *vf_nvecp);
1205 extern __checkReturn efx_rc_t
1206 ef10_get_privilege_mask(
1207 __in efx_nic_t *enp,
1208 __out uint32_t *maskp);
1210 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1212 extern __checkReturn efx_rc_t
1213 efx_mcdi_get_nic_global(
1214 __in efx_nic_t *enp,
1216 __out uint32_t *valuep);
1218 extern __checkReturn efx_rc_t
1219 efx_mcdi_set_nic_global(
1220 __in efx_nic_t *enp,
1222 __in uint32_t value);
1224 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1227 #if EFSYS_OPT_RX_PACKED_STREAM
1229 /* Data space per credit in packed stream mode */
1230 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1233 * Received packets are always aligned at this boundary. Also there always
1234 * exists a gap of this size between packets.
1235 * (see SF-112241-TC, 4.5)
1237 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1240 * Size of a pseudo-header prepended to received packets
1241 * in packed stream mode
1243 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1245 /* Minimum space for packet in packed stream mode */
1246 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1247 P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1249 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1250 EFX_RX_PACKED_STREAM_ALIGNMENT)
1252 /* Maximum number of credits */
1253 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1255 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1257 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1260 * Maximum DMA length and buffer stride alignment.
1261 * (see SF-119419-TC, 3.2)
1263 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1271 #endif /* _SYS_EF10_IMPL_H */