2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
33 #if EFSYS_OPT_MON_MCDI
37 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
39 #include "ef10_tlv_layout.h"
41 __checkReturn efx_rc_t
42 efx_mcdi_get_port_assignment(
44 __out uint32_t *portp)
47 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
48 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
51 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
52 enp->en_family == EFX_FAMILY_MEDFORD);
54 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
55 req.emr_in_buf = payload;
56 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
57 req.emr_out_buf = payload;
58 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
60 efx_mcdi_execute(enp, &req);
62 if (req.emr_rc != 0) {
67 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
72 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
79 EFSYS_PROBE1(fail1, efx_rc_t, rc);
84 __checkReturn efx_rc_t
85 efx_mcdi_get_port_modes(
87 __out uint32_t *modesp,
88 __out_opt uint32_t *current_modep)
91 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN,
92 MC_CMD_GET_PORT_MODES_OUT_LEN);
95 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
96 enp->en_family == EFX_FAMILY_MEDFORD);
98 req.emr_cmd = MC_CMD_GET_PORT_MODES;
99 req.emr_in_buf = payload;
100 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
101 req.emr_out_buf = payload;
102 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
104 efx_mcdi_execute(enp, &req);
106 if (req.emr_rc != 0) {
112 * Require only Modes and DefaultMode fields, unless the current mode
113 * was requested (CurrentMode field was added for Medford).
115 if (req.emr_out_length_used <
116 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
120 if ((current_modep != NULL) && (req.emr_out_length_used <
121 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
126 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
128 if (current_modep != NULL) {
129 *current_modep = MCDI_OUT_DWORD(req,
130 GET_PORT_MODES_OUT_CURRENT_MODE);
140 EFSYS_PROBE1(fail1, efx_rc_t, rc);
145 __checkReturn efx_rc_t
146 ef10_nic_get_port_mode_bandwidth(
147 __in uint32_t port_mode,
148 __out uint32_t *bandwidth_mbpsp)
154 case TLV_PORT_MODE_10G:
157 case TLV_PORT_MODE_10G_10G:
158 bandwidth = 10000 * 2;
160 case TLV_PORT_MODE_10G_10G_10G_10G:
161 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
162 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
163 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
164 bandwidth = 10000 * 4;
166 case TLV_PORT_MODE_40G:
169 case TLV_PORT_MODE_40G_40G:
170 bandwidth = 40000 * 2;
172 case TLV_PORT_MODE_40G_10G_10G:
173 case TLV_PORT_MODE_10G_10G_40G:
174 bandwidth = 40000 + (10000 * 2);
181 *bandwidth_mbpsp = bandwidth;
186 EFSYS_PROBE1(fail1, efx_rc_t, rc);
191 static __checkReturn efx_rc_t
192 efx_mcdi_vadaptor_alloc(
194 __in uint32_t port_id)
197 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN,
198 MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
201 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
203 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
204 req.emr_in_buf = payload;
205 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
206 req.emr_out_buf = payload;
207 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
209 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
210 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
211 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
212 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
214 efx_mcdi_execute(enp, &req);
216 if (req.emr_rc != 0) {
224 EFSYS_PROBE1(fail1, efx_rc_t, rc);
229 static __checkReturn efx_rc_t
230 efx_mcdi_vadaptor_free(
232 __in uint32_t port_id)
235 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN,
236 MC_CMD_VADAPTOR_FREE_OUT_LEN);
239 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
240 req.emr_in_buf = payload;
241 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
242 req.emr_out_buf = payload;
243 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
245 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
247 efx_mcdi_execute(enp, &req);
249 if (req.emr_rc != 0) {
257 EFSYS_PROBE1(fail1, efx_rc_t, rc);
262 __checkReturn efx_rc_t
263 efx_mcdi_get_mac_address_pf(
265 __out_ecount_opt(6) uint8_t mac_addrp[6])
268 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
269 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
272 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
273 enp->en_family == EFX_FAMILY_MEDFORD);
275 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
276 req.emr_in_buf = payload;
277 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
278 req.emr_out_buf = payload;
279 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
281 efx_mcdi_execute(enp, &req);
283 if (req.emr_rc != 0) {
288 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
293 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
298 if (mac_addrp != NULL) {
301 addrp = MCDI_OUT2(req, uint8_t,
302 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
304 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
314 EFSYS_PROBE1(fail1, efx_rc_t, rc);
319 __checkReturn efx_rc_t
320 efx_mcdi_get_mac_address_vf(
322 __out_ecount_opt(6) uint8_t mac_addrp[6])
325 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
326 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
329 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
330 enp->en_family == EFX_FAMILY_MEDFORD);
332 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
333 req.emr_in_buf = payload;
334 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
335 req.emr_out_buf = payload;
336 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
338 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
339 EVB_PORT_ID_ASSIGNED);
341 efx_mcdi_execute(enp, &req);
343 if (req.emr_rc != 0) {
348 if (req.emr_out_length_used <
349 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
354 if (MCDI_OUT_DWORD(req,
355 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
360 if (mac_addrp != NULL) {
363 addrp = MCDI_OUT2(req, uint8_t,
364 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
366 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
376 EFSYS_PROBE1(fail1, efx_rc_t, rc);
381 __checkReturn efx_rc_t
384 __out uint32_t *sys_freqp,
385 __out uint32_t *dpcpu_freqp)
388 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN,
389 MC_CMD_GET_CLOCK_OUT_LEN);
392 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
393 enp->en_family == EFX_FAMILY_MEDFORD);
395 req.emr_cmd = MC_CMD_GET_CLOCK;
396 req.emr_in_buf = payload;
397 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
398 req.emr_out_buf = payload;
399 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
401 efx_mcdi_execute(enp, &req);
403 if (req.emr_rc != 0) {
408 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
413 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
414 if (*sys_freqp == 0) {
418 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
419 if (*dpcpu_freqp == 0) {
433 EFSYS_PROBE1(fail1, efx_rc_t, rc);
438 __checkReturn efx_rc_t
439 efx_mcdi_get_vector_cfg(
441 __out_opt uint32_t *vec_basep,
442 __out_opt uint32_t *pf_nvecp,
443 __out_opt uint32_t *vf_nvecp)
446 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN,
447 MC_CMD_GET_VECTOR_CFG_OUT_LEN);
450 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
451 req.emr_in_buf = payload;
452 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
453 req.emr_out_buf = payload;
454 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
456 efx_mcdi_execute(enp, &req);
458 if (req.emr_rc != 0) {
463 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
468 if (vec_basep != NULL)
469 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
470 if (pf_nvecp != NULL)
471 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
472 if (vf_nvecp != NULL)
473 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
480 EFSYS_PROBE1(fail1, efx_rc_t, rc);
485 static __checkReturn efx_rc_t
488 __in uint32_t min_vi_count,
489 __in uint32_t max_vi_count,
490 __out uint32_t *vi_basep,
491 __out uint32_t *vi_countp,
492 __out uint32_t *vi_shiftp)
495 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN,
496 MC_CMD_ALLOC_VIS_EXT_OUT_LEN);
499 if (vi_countp == NULL) {
504 req.emr_cmd = MC_CMD_ALLOC_VIS;
505 req.emr_in_buf = payload;
506 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
507 req.emr_out_buf = payload;
508 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
510 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
511 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
513 efx_mcdi_execute(enp, &req);
515 if (req.emr_rc != 0) {
520 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
525 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
526 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
528 /* Report VI_SHIFT if available (always zero for Huntington) */
529 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
532 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
541 EFSYS_PROBE1(fail1, efx_rc_t, rc);
547 static __checkReturn efx_rc_t
554 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
555 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
557 req.emr_cmd = MC_CMD_FREE_VIS;
558 req.emr_in_buf = NULL;
559 req.emr_in_length = 0;
560 req.emr_out_buf = NULL;
561 req.emr_out_length = 0;
563 efx_mcdi_execute_quiet(enp, &req);
565 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
566 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
574 EFSYS_PROBE1(fail1, efx_rc_t, rc);
580 static __checkReturn efx_rc_t
581 efx_mcdi_alloc_piobuf(
583 __out efx_piobuf_handle_t *handlep)
586 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN,
587 MC_CMD_ALLOC_PIOBUF_OUT_LEN);
590 if (handlep == NULL) {
595 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
596 req.emr_in_buf = payload;
597 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
598 req.emr_out_buf = payload;
599 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
601 efx_mcdi_execute_quiet(enp, &req);
603 if (req.emr_rc != 0) {
608 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
613 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
622 EFSYS_PROBE1(fail1, efx_rc_t, rc);
627 static __checkReturn efx_rc_t
628 efx_mcdi_free_piobuf(
630 __in efx_piobuf_handle_t handle)
633 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN,
634 MC_CMD_FREE_PIOBUF_OUT_LEN);
637 req.emr_cmd = MC_CMD_FREE_PIOBUF;
638 req.emr_in_buf = payload;
639 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
640 req.emr_out_buf = payload;
641 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
643 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
645 efx_mcdi_execute_quiet(enp, &req);
647 if (req.emr_rc != 0) {
655 EFSYS_PROBE1(fail1, efx_rc_t, rc);
660 static __checkReturn efx_rc_t
661 efx_mcdi_link_piobuf(
663 __in uint32_t vi_index,
664 __in efx_piobuf_handle_t handle)
667 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN,
668 MC_CMD_LINK_PIOBUF_OUT_LEN);
671 req.emr_cmd = MC_CMD_LINK_PIOBUF;
672 req.emr_in_buf = payload;
673 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
674 req.emr_out_buf = payload;
675 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
677 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
678 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
680 efx_mcdi_execute(enp, &req);
682 if (req.emr_rc != 0) {
690 EFSYS_PROBE1(fail1, efx_rc_t, rc);
695 static __checkReturn efx_rc_t
696 efx_mcdi_unlink_piobuf(
698 __in uint32_t vi_index)
701 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN,
702 MC_CMD_UNLINK_PIOBUF_OUT_LEN);
705 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
706 req.emr_in_buf = payload;
707 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
708 req.emr_out_buf = payload;
709 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
711 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
713 efx_mcdi_execute_quiet(enp, &req);
715 if (req.emr_rc != 0) {
723 EFSYS_PROBE1(fail1, efx_rc_t, rc);
729 ef10_nic_alloc_piobufs(
731 __in uint32_t max_piobuf_count)
733 efx_piobuf_handle_t *handlep;
736 EFSYS_ASSERT3U(max_piobuf_count, <=,
737 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
739 enp->en_arch.ef10.ena_piobuf_count = 0;
741 for (i = 0; i < max_piobuf_count; i++) {
742 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
744 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
747 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
748 enp->en_arch.ef10.ena_piobuf_count++;
754 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
755 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
757 (void) efx_mcdi_free_piobuf(enp, *handlep);
758 *handlep = EFX_PIOBUF_HANDLE_INVALID;
760 enp->en_arch.ef10.ena_piobuf_count = 0;
765 ef10_nic_free_piobufs(
768 efx_piobuf_handle_t *handlep;
771 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
772 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
774 (void) efx_mcdi_free_piobuf(enp, *handlep);
775 *handlep = EFX_PIOBUF_HANDLE_INVALID;
777 enp->en_arch.ef10.ena_piobuf_count = 0;
780 /* Sub-allocate a block from a piobuf */
781 __checkReturn efx_rc_t
783 __inout efx_nic_t *enp,
784 __out uint32_t *bufnump,
785 __out efx_piobuf_handle_t *handlep,
786 __out uint32_t *blknump,
787 __out uint32_t *offsetp,
790 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
791 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
792 uint32_t blk_per_buf;
796 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
797 enp->en_family == EFX_FAMILY_MEDFORD);
798 EFSYS_ASSERT(bufnump);
799 EFSYS_ASSERT(handlep);
800 EFSYS_ASSERT(blknump);
801 EFSYS_ASSERT(offsetp);
804 if ((edcp->edc_pio_alloc_size == 0) ||
805 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
809 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
811 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
812 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
817 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
818 for (blk = 0; blk < blk_per_buf; blk++) {
819 if ((*map & (1u << blk)) == 0) {
829 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
832 *sizep = edcp->edc_pio_alloc_size;
833 *offsetp = blk * (*sizep);
840 EFSYS_PROBE1(fail1, efx_rc_t, rc);
845 /* Free a piobuf sub-allocated block */
846 __checkReturn efx_rc_t
848 __inout efx_nic_t *enp,
849 __in uint32_t bufnum,
850 __in uint32_t blknum)
855 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
856 (blknum >= (8 * sizeof (*map)))) {
861 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
862 if ((*map & (1u << blknum)) == 0) {
866 *map &= ~(1u << blknum);
873 EFSYS_PROBE1(fail1, efx_rc_t, rc);
878 __checkReturn efx_rc_t
880 __inout efx_nic_t *enp,
881 __in uint32_t vi_index,
882 __in efx_piobuf_handle_t handle)
884 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
887 __checkReturn efx_rc_t
889 __inout efx_nic_t *enp,
890 __in uint32_t vi_index)
892 return (efx_mcdi_unlink_piobuf(enp, vi_index));
895 static __checkReturn efx_rc_t
896 ef10_mcdi_get_pf_count(
898 __out uint32_t *pf_countp)
901 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN,
902 MC_CMD_GET_PF_COUNT_OUT_LEN);
905 req.emr_cmd = MC_CMD_GET_PF_COUNT;
906 req.emr_in_buf = payload;
907 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
908 req.emr_out_buf = payload;
909 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
911 efx_mcdi_execute(enp, &req);
913 if (req.emr_rc != 0) {
918 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
923 *pf_countp = *MCDI_OUT(req, uint8_t,
924 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
926 EFSYS_ASSERT(*pf_countp != 0);
933 EFSYS_PROBE1(fail1, efx_rc_t, rc);
938 __checkReturn efx_rc_t
939 ef10_get_datapath_caps(
942 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
948 if ((rc = efx_mcdi_get_capabilities(enp, &flags, NULL, NULL,
949 &flags2, &tso2nc)) != 0)
952 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
955 #define CAP_FLAG(flags1, field) \
956 ((flags1) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
958 #define CAP_FLAG2(flags2, field) \
959 ((flags2) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
962 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
963 * We only support the 14 byte prefix here.
965 if (CAP_FLAG(flags, RX_PREFIX_LEN_14) == 0) {
969 encp->enc_rx_prefix_size = 14;
971 /* Check if the firmware supports TSO */
972 encp->enc_fw_assisted_tso_enabled =
973 CAP_FLAG(flags, TX_TSO) ? B_TRUE : B_FALSE;
975 /* Check if the firmware supports FATSOv2 */
976 encp->enc_fw_assisted_tso_v2_enabled =
977 CAP_FLAG2(flags2, TX_TSO_V2) ? B_TRUE : B_FALSE;
979 /* Get the number of TSO contexts (FATSOv2) */
980 encp->enc_fw_assisted_tso_v2_n_contexts =
981 CAP_FLAG2(flags2, TX_TSO_V2) ? tso2nc : 0;
983 /* Check if the firmware has vadapter/vport/vswitch support */
984 encp->enc_datapath_cap_evb =
985 CAP_FLAG(flags, EVB) ? B_TRUE : B_FALSE;
987 /* Check if the firmware supports VLAN insertion */
988 encp->enc_hw_tx_insert_vlan_enabled =
989 CAP_FLAG(flags, TX_VLAN_INSERTION) ? B_TRUE : B_FALSE;
991 /* Check if the firmware supports RX event batching */
992 encp->enc_rx_batching_enabled =
993 CAP_FLAG(flags, RX_BATCHING) ? B_TRUE : B_FALSE;
996 * Even if batching isn't reported as supported, we may still get
997 * batched events (see bug61153).
999 encp->enc_rx_batch_max = 16;
1001 /* Check if the firmware supports disabling scatter on RXQs */
1002 encp->enc_rx_disable_scatter_supported =
1003 CAP_FLAG(flags, RX_DISABLE_SCATTER) ? B_TRUE : B_FALSE;
1005 /* Check if the firmware supports packed stream mode */
1006 encp->enc_rx_packed_stream_supported =
1007 CAP_FLAG(flags, RX_PACKED_STREAM) ? B_TRUE : B_FALSE;
1010 * Check if the firmware supports configurable buffer sizes
1011 * for packed stream mode (otherwise buffer size is 1Mbyte)
1013 encp->enc_rx_var_packed_stream_supported =
1014 CAP_FLAG(flags, RX_PACKED_STREAM_VAR_BUFFERS) ? B_TRUE : B_FALSE;
1016 /* Check if the firmware supports set mac with running filters */
1017 encp->enc_allow_set_mac_with_installed_filters =
1018 CAP_FLAG(flags, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED) ?
1022 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1023 * specifying which parameters to configure.
1025 encp->enc_enhanced_set_mac_supported =
1026 CAP_FLAG(flags, SET_MAC_ENHANCED) ? B_TRUE : B_FALSE;
1029 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1030 * us to let the firmware choose the settings to use on an EVQ.
1032 encp->enc_init_evq_v2_supported =
1033 CAP_FLAG2(flags2, INIT_EVQ_V2) ? B_TRUE : B_FALSE;
1036 * Check if firmware-verified NVRAM updates must be used.
1038 * The firmware trusted installer requires all NVRAM updates to use
1039 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1040 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1041 * partition and report the result).
1043 encp->enc_fw_verified_nvram_update_required =
1044 CAP_FLAG2(flags2, NVRAM_UPDATE_REPORT_VERIFY_RESULT) ?
1048 * Check if firmware provides packet memory and Rx datapath
1051 encp->enc_pm_and_rxdp_counters =
1052 CAP_FLAG(flags, PM_AND_RXDP_COUNTERS) ? B_TRUE : B_FALSE;
1055 * Check if the 40G MAC hardware is capable of reporting
1056 * statistics for Tx size bins.
1058 encp->enc_mac_stats_40g_tx_size_bins =
1059 CAP_FLAG2(flags2, MAC_STATS_40G_TX_SIZE_BINS) ? B_TRUE : B_FALSE;
1062 * Check if firmware supports VXLAN and NVGRE tunnels.
1063 * The capability indicates Geneve protocol support as well.
1065 if (CAP_FLAG(flags, VXLAN_NVGRE))
1066 encp->enc_tunnel_encapsulations_supported =
1067 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1068 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1069 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1079 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1085 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1086 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1087 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1088 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1089 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1090 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1091 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1092 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1093 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1094 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1095 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1096 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1098 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1101 __checkReturn efx_rc_t
1102 ef10_get_privilege_mask(
1103 __in efx_nic_t *enp,
1104 __out uint32_t *maskp)
1106 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1110 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1115 /* Fallback for old firmware without privilege mask support */
1116 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1117 /* Assume PF has admin privilege */
1118 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1120 /* VF is always unprivileged by default */
1121 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1130 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1137 * Table of mapping schemes from port number to the number of the external
1138 * connector on the board. The external numbering does not distinguish
1139 * off-board separated outputs such as from multi-headed cables.
1141 * The count of adjacent port numbers that map to each external port
1142 * and the offset in the numbering, is determined by the chip family and
1143 * current port mode.
1145 * For the Huntington family, the current port mode cannot be discovered,
1146 * so the mapping used is instead the last match in the table to the full
1147 * set of port modes to which the NIC can be configured. Therefore the
1148 * ordering of entries in the the mapping table is significant.
1151 efx_family_t family;
1152 uint32_t modes_mask;
1155 } __ef10_external_port_mappings[] = {
1156 /* Supported modes with 1 output per external port */
1158 EFX_FAMILY_HUNTINGTON,
1159 (1 << TLV_PORT_MODE_10G) |
1160 (1 << TLV_PORT_MODE_10G_10G) |
1161 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1167 (1 << TLV_PORT_MODE_10G) |
1168 (1 << TLV_PORT_MODE_10G_10G),
1172 /* Supported modes with 2 outputs per external port */
1174 EFX_FAMILY_HUNTINGTON,
1175 (1 << TLV_PORT_MODE_40G) |
1176 (1 << TLV_PORT_MODE_40G_40G) |
1177 (1 << TLV_PORT_MODE_40G_10G_10G) |
1178 (1 << TLV_PORT_MODE_10G_10G_40G),
1184 (1 << TLV_PORT_MODE_40G) |
1185 (1 << TLV_PORT_MODE_40G_40G) |
1186 (1 << TLV_PORT_MODE_40G_10G_10G) |
1187 (1 << TLV_PORT_MODE_10G_10G_40G) |
1188 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
1192 /* Supported modes with 4 outputs per external port */
1195 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1196 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
1202 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1208 __checkReturn efx_rc_t
1209 ef10_external_port_mapping(
1210 __in efx_nic_t *enp,
1212 __out uint8_t *external_portp)
1216 uint32_t port_modes;
1219 int32_t count = 1; /* Default 1-1 mapping */
1220 int32_t offset = 1; /* Default starting external port number */
1222 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t)) != 0) {
1224 * No current port mode information
1225 * - infer mapping from available modes
1227 if ((rc = efx_mcdi_get_port_modes(enp,
1228 &port_modes, NULL)) != 0) {
1230 * No port mode information available
1231 * - use default mapping
1236 /* Only need to scan the current mode */
1237 port_modes = 1 << current;
1241 * Infer the internal port -> external port mapping from
1242 * the possible port modes for this NIC.
1244 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1245 if (__ef10_external_port_mappings[i].family !=
1248 matches = (__ef10_external_port_mappings[i].modes_mask &
1251 count = __ef10_external_port_mappings[i].count;
1252 offset = __ef10_external_port_mappings[i].offset;
1253 port_modes &= ~matches;
1257 if (port_modes != 0) {
1258 /* Some advertised modes are not supported */
1265 * Scale as required by last matched mode and then convert to
1266 * correctly offset numbering
1268 *external_portp = (uint8_t)((port / count) + offset);
1272 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1278 __checkReturn efx_rc_t
1280 __in efx_nic_t *enp)
1282 const efx_nic_ops_t *enop = enp->en_enop;
1283 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1284 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1287 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1288 enp->en_family == EFX_FAMILY_MEDFORD);
1290 /* Read and clear any assertion state */
1291 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1294 /* Exit the assertion handler */
1295 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1299 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1302 if ((rc = enop->eno_board_cfg(enp)) != 0)
1307 * Set default driver config limits (based on board config).
1309 * FIXME: For now allocate a fixed number of VIs which is likely to be
1310 * sufficient and small enough to allow multiple functions on the same
1313 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1314 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1316 /* The client driver must configure and enable PIO buffer support */
1317 edcp->edc_max_piobuf_count = 0;
1318 edcp->edc_pio_alloc_size = 0;
1320 #if EFSYS_OPT_MAC_STATS
1321 /* Wipe the MAC statistics */
1322 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1326 #if EFSYS_OPT_LOOPBACK
1327 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1331 #if EFSYS_OPT_MON_STATS
1332 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1333 /* Unprivileged functions do not have access to sensors */
1339 encp->enc_features = enp->en_features;
1343 #if EFSYS_OPT_MON_STATS
1347 #if EFSYS_OPT_LOOPBACK
1351 #if EFSYS_OPT_MAC_STATS
1362 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1367 __checkReturn efx_rc_t
1368 ef10_nic_set_drv_limits(
1369 __inout efx_nic_t *enp,
1370 __in efx_drv_limits_t *edlp)
1372 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1373 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1374 uint32_t min_evq_count, max_evq_count;
1375 uint32_t min_rxq_count, max_rxq_count;
1376 uint32_t min_txq_count, max_txq_count;
1384 /* Get minimum required and maximum usable VI limits */
1385 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1386 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1387 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1389 edcp->edc_min_vi_count =
1390 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1392 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1393 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1394 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1396 edcp->edc_max_vi_count =
1397 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1400 * Check limits for sub-allocated piobuf blocks.
1401 * PIO is optional, so don't fail if the limits are incorrect.
1403 if ((encp->enc_piobuf_size == 0) ||
1404 (encp->enc_piobuf_limit == 0) ||
1405 (edlp->edl_min_pio_alloc_size == 0) ||
1406 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1408 edcp->edc_max_piobuf_count = 0;
1409 edcp->edc_pio_alloc_size = 0;
1411 uint32_t blk_size, blk_count, blks_per_piobuf;
1414 MAX(edlp->edl_min_pio_alloc_size,
1415 encp->enc_piobuf_min_alloc_size);
1417 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1418 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1420 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1422 /* A zero max pio alloc count means unlimited */
1423 if ((edlp->edl_max_pio_alloc_count > 0) &&
1424 (edlp->edl_max_pio_alloc_count < blk_count)) {
1425 blk_count = edlp->edl_max_pio_alloc_count;
1428 edcp->edc_pio_alloc_size = blk_size;
1429 edcp->edc_max_piobuf_count =
1430 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1436 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1442 __checkReturn efx_rc_t
1444 __in efx_nic_t *enp)
1447 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN,
1448 MC_CMD_ENTITY_RESET_OUT_LEN);
1451 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1452 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1454 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1457 req.emr_cmd = MC_CMD_ENTITY_RESET;
1458 req.emr_in_buf = payload;
1459 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1460 req.emr_out_buf = payload;
1461 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1463 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1464 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1466 efx_mcdi_execute(enp, &req);
1468 if (req.emr_rc != 0) {
1473 /* Clear RX/TX DMA queue errors */
1474 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1483 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1488 __checkReturn efx_rc_t
1490 __in efx_nic_t *enp)
1492 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1493 uint32_t min_vi_count, max_vi_count;
1494 uint32_t vi_count, vi_base, vi_shift;
1500 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1501 enp->en_family == EFX_FAMILY_MEDFORD);
1503 /* Enable reporting of some events (e.g. link change) */
1504 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1507 /* Allocate (optional) on-chip PIO buffers */
1508 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1511 * For best performance, PIO writes should use a write-combined
1512 * (WC) memory mapping. Using a separate WC mapping for the PIO
1513 * aperture of each VI would be a burden to drivers (and not
1514 * possible if the host page size is >4Kbyte).
1516 * To avoid this we use a single uncached (UC) mapping for VI
1517 * register access, and a single WC mapping for extra VIs used
1520 * Each piobuf must be linked to a VI in the WC mapping, and to
1521 * each VI that is using a sub-allocated block from the piobuf.
1523 min_vi_count = edcp->edc_min_vi_count;
1525 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1527 /* Ensure that the previously attached driver's VIs are freed */
1528 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1532 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1533 * fails then retrying the request for fewer VI resources may succeed.
1536 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1537 &vi_base, &vi_count, &vi_shift)) != 0)
1540 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1542 if (vi_count < min_vi_count) {
1547 enp->en_arch.ef10.ena_vi_base = vi_base;
1548 enp->en_arch.ef10.ena_vi_count = vi_count;
1549 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1551 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1552 /* Not enough extra VIs to map piobufs */
1553 ef10_nic_free_piobufs(enp);
1556 enp->en_arch.ef10.ena_pio_write_vi_base =
1557 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1559 /* Save UC memory mapping details */
1560 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1561 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1562 enp->en_arch.ef10.ena_uc_mem_map_size =
1563 (ER_DZ_TX_PIOBUF_STEP *
1564 enp->en_arch.ef10.ena_pio_write_vi_base);
1566 enp->en_arch.ef10.ena_uc_mem_map_size =
1567 (ER_DZ_TX_PIOBUF_STEP *
1568 enp->en_arch.ef10.ena_vi_count);
1571 /* Save WC memory mapping details */
1572 enp->en_arch.ef10.ena_wc_mem_map_offset =
1573 enp->en_arch.ef10.ena_uc_mem_map_offset +
1574 enp->en_arch.ef10.ena_uc_mem_map_size;
1576 enp->en_arch.ef10.ena_wc_mem_map_size =
1577 (ER_DZ_TX_PIOBUF_STEP *
1578 enp->en_arch.ef10.ena_piobuf_count);
1580 /* Link piobufs to extra VIs in WC mapping */
1581 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1582 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1583 rc = efx_mcdi_link_piobuf(enp,
1584 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1585 enp->en_arch.ef10.ena_piobuf_handle[i]);
1592 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1594 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1595 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1596 * retry the request several times after waiting a while. The wait time
1597 * between retries starts small (10ms) and exponentially increases.
1598 * Total wait time is a little over two seconds. Retry logic in the
1599 * client driver may mean this whole loop is repeated if it continues to
1604 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1605 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1608 * Do not retry alloc for PF, or for other errors on
1614 /* VF startup before PF is ready. Retry allocation. */
1616 /* Too many attempts */
1620 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1621 EFSYS_SLEEP(delay_us);
1623 if (delay_us < 500000)
1627 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1628 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1643 ef10_nic_free_piobufs(enp);
1646 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1651 __checkReturn efx_rc_t
1652 ef10_nic_get_vi_pool(
1653 __in efx_nic_t *enp,
1654 __out uint32_t *vi_countp)
1656 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1657 enp->en_family == EFX_FAMILY_MEDFORD);
1660 * Report VIs that the client driver can use.
1661 * Do not include VIs used for PIO buffer writes.
1663 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1668 __checkReturn efx_rc_t
1669 ef10_nic_get_bar_region(
1670 __in efx_nic_t *enp,
1671 __in efx_nic_region_t region,
1672 __out uint32_t *offsetp,
1673 __out size_t *sizep)
1677 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1678 enp->en_family == EFX_FAMILY_MEDFORD);
1681 * TODO: Specify host memory mapping alignment and granularity
1682 * in efx_drv_limits_t so that they can be taken into account
1683 * when allocating extra VIs for PIO writes.
1687 /* UC mapped memory BAR region for VI registers */
1688 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1689 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1692 case EFX_REGION_PIO_WRITE_VI:
1693 /* WC mapped memory BAR region for piobuf writes */
1694 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1695 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1706 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1713 __in efx_nic_t *enp)
1718 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1719 enp->en_vport_id = 0;
1721 /* Unlink piobufs from extra VIs in WC mapping */
1722 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1723 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1724 rc = efx_mcdi_unlink_piobuf(enp,
1725 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1731 ef10_nic_free_piobufs(enp);
1733 (void) efx_mcdi_free_vis(enp);
1734 enp->en_arch.ef10.ena_vi_count = 0;
1739 __in efx_nic_t *enp)
1741 #if EFSYS_OPT_MON_STATS
1742 mcdi_mon_cfg_free(enp);
1743 #endif /* EFSYS_OPT_MON_STATS */
1744 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1749 __checkReturn efx_rc_t
1750 ef10_nic_register_test(
1751 __in efx_nic_t *enp)
1756 _NOTE(ARGUNUSED(enp))
1757 _NOTE(CONSTANTCONDITION)
1767 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1772 #endif /* EFSYS_OPT_DIAG */
1775 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */