2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
38 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
40 (_etp)->et_stat[_stat]++; \
41 _NOTE(CONSTANTCONDITION) \
44 #define EFX_TX_QSTAT_INCR(_etp, _stat)
47 static __checkReturn efx_rc_t
51 __in uint32_t target_evq,
53 __in uint32_t instance,
55 __in efsys_mem_t *esmp)
58 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
59 MC_CMD_INIT_TXQ_OUT_LEN);
60 efx_qword_t *dma_addr;
66 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
67 EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
69 npages = EFX_TXQ_NBUFS(size);
70 if (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) {
75 req.emr_cmd = MC_CMD_INIT_TXQ;
76 req.emr_in_buf = payload;
77 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
78 req.emr_out_buf = payload;
79 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
81 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
82 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
83 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
84 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
86 MCDI_IN_POPULATE_DWORD_7(req, INIT_TXQ_IN_FLAGS,
87 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
88 INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
89 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
90 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
91 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
92 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0,
93 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
94 INIT_TXQ_IN_CRC_MODE, 0,
95 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
97 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
98 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
100 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
101 addr = EFSYS_MEM_ADDR(esmp);
103 for (i = 0; i < npages; i++) {
104 EFX_POPULATE_QWORD_2(*dma_addr,
105 EFX_DWORD_1, (uint32_t)(addr >> 32),
106 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
109 addr += EFX_BUF_SIZE;
112 efx_mcdi_execute(enp, &req);
114 if (req.emr_rc != 0) {
124 EFSYS_PROBE1(fail1, efx_rc_t, rc);
129 static __checkReturn efx_rc_t
132 __in uint32_t instance)
135 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_TXQ_IN_LEN,
136 MC_CMD_FINI_TXQ_OUT_LEN);
139 req.emr_cmd = MC_CMD_FINI_TXQ;
140 req.emr_in_buf = payload;
141 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
142 req.emr_out_buf = payload;
143 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
145 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
147 efx_mcdi_execute_quiet(enp, &req);
149 if (req.emr_rc != 0) {
158 * EALREADY is not an error, but indicates that the MC has rebooted and
159 * that the TXQ has already been destroyed.
162 EFSYS_PROBE1(fail1, efx_rc_t, rc);
167 __checkReturn efx_rc_t
171 _NOTE(ARGUNUSED(enp))
179 _NOTE(ARGUNUSED(enp))
182 __checkReturn efx_rc_t
185 __in unsigned int index,
186 __in unsigned int label,
187 __in efsys_mem_t *esmp,
193 __out unsigned int *addedp)
200 if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
205 * A previous user of this TX queue may have written a descriptor to the
206 * TX push collector, but not pushed the doorbell (e.g. after a crash).
207 * The next doorbell write would then push the stale descriptor.
209 * Ensure the (per network port) TX push collector is cleared by writing
210 * a no-op TX option descriptor. See bug29981 for details.
213 EFX_POPULATE_QWORD_4(desc,
214 ESF_DZ_TX_DESC_IS_OPT, 1,
215 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
216 ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
217 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
218 ESF_DZ_TX_OPTION_IP_CSUM,
219 (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0);
221 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
222 ef10_tx_qpush(etp, *addedp, 0);
227 EFSYS_PROBE1(fail1, efx_rc_t, rc);
237 _NOTE(ARGUNUSED(etp))
241 __checkReturn efx_rc_t
245 efx_nic_t *enp = etp->et_enp;
246 efx_piobuf_handle_t handle;
249 if (etp->et_pio_size != 0) {
254 /* Sub-allocate a PIO block from a piobuf */
255 if ((rc = ef10_nic_pio_alloc(enp,
260 &etp->et_pio_size)) != 0) {
263 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
265 /* Link the piobuf to this TXQ */
266 if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
271 * et_pio_offset is the offset of the sub-allocated block within the
272 * hardware PIO buffer. It is used as the buffer address in the PIO
275 * et_pio_write_offset is the offset of the sub-allocated block from the
276 * start of the write-combined memory mapping, and is used for writing
277 * data into the PIO buffer.
279 etp->et_pio_write_offset =
280 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
281 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
287 (void) ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
290 etp->et_pio_size = 0;
292 EFSYS_PROBE1(fail1, efx_rc_t, rc);
298 ef10_tx_qpio_disable(
301 efx_nic_t *enp = etp->et_enp;
303 if (etp->et_pio_size != 0) {
304 /* Unlink the piobuf from this TXQ */
305 if (ef10_nic_pio_unlink(enp, etp->et_index) != 0)
308 /* Free the sub-allocated PIO block */
309 (void) ef10_nic_pio_free(enp, etp->et_pio_bufnum,
311 etp->et_pio_size = 0;
312 etp->et_pio_write_offset = 0;
316 __checkReturn efx_rc_t
319 __in_ecount(length) uint8_t *buffer,
323 efx_nic_t *enp = etp->et_enp;
324 efsys_bar_t *esbp = enp->en_esbp;
325 uint32_t write_offset;
326 uint32_t write_offset_limit;
330 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
332 if (etp->et_pio_size == 0) {
336 if (offset + length > etp->et_pio_size) {
342 * Writes to PIO buffers must be 64 bit aligned, and multiples of
345 write_offset = etp->et_pio_write_offset + offset;
346 write_offset_limit = write_offset + length;
347 eqp = (efx_qword_t *)buffer;
348 while (write_offset < write_offset_limit) {
349 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
351 write_offset += sizeof (efx_qword_t);
359 EFSYS_PROBE1(fail1, efx_rc_t, rc);
364 __checkReturn efx_rc_t
367 __in size_t pkt_length,
368 __in unsigned int completed,
369 __inout unsigned int *addedp)
371 efx_qword_t pio_desc;
374 unsigned int added = *addedp;
378 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
383 if (etp->et_pio_size == 0) {
388 id = added++ & etp->et_mask;
389 offset = id * sizeof (efx_qword_t);
391 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
392 unsigned int, id, uint32_t, etp->et_pio_offset,
395 EFX_POPULATE_QWORD_5(pio_desc,
396 ESF_DZ_TX_DESC_IS_OPT, 1,
397 ESF_DZ_TX_OPTION_TYPE, 1,
398 ESF_DZ_TX_PIO_CONT, 0,
399 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
400 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
402 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
404 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
412 EFSYS_PROBE1(fail1, efx_rc_t, rc);
417 __checkReturn efx_rc_t
420 __in_ecount(n) efx_buffer_t *eb,
422 __in unsigned int completed,
423 __inout unsigned int *addedp)
425 unsigned int added = *addedp;
429 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
434 for (i = 0; i < n; i++) {
435 efx_buffer_t *ebp = &eb[i];
436 efsys_dma_addr_t addr = ebp->eb_addr;
437 size_t size = ebp->eb_size;
438 boolean_t eop = ebp->eb_eop;
443 /* No limitations on boundary crossing */
445 etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
447 id = added++ & etp->et_mask;
448 offset = id * sizeof (efx_qword_t);
450 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
451 unsigned int, id, efsys_dma_addr_t, addr,
452 size_t, size, boolean_t, eop);
454 EFX_POPULATE_QWORD_5(qword,
455 ESF_DZ_TX_KER_TYPE, 0,
456 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
457 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
458 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
459 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
461 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
464 EFX_TX_QSTAT_INCR(etp, TX_POST);
470 EFSYS_PROBE1(fail1, efx_rc_t, rc);
476 * This improves performance by pushing a TX descriptor at the same time as the
477 * doorbell. The descriptor must be added to the TXQ, so that can be used if the
478 * hardware decides not to use the pushed descriptor.
483 __in unsigned int added,
484 __in unsigned int pushed)
486 efx_nic_t *enp = etp->et_enp;
493 wptr = added & etp->et_mask;
494 id = pushed & etp->et_mask;
495 offset = id * sizeof (efx_qword_t);
497 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
498 EFX_POPULATE_OWORD_3(oword,
499 ERF_DZ_TX_DESC_WPTR, wptr,
500 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
501 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
503 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
504 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1, wptr, id);
505 EFSYS_PIO_WRITE_BARRIER();
506 EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG, etp->et_index,
510 __checkReturn efx_rc_t
513 __in_ecount(n) efx_desc_t *ed,
515 __in unsigned int completed,
516 __inout unsigned int *addedp)
518 unsigned int added = *addedp;
522 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
527 for (i = 0; i < n; i++) {
528 efx_desc_t *edp = &ed[i];
532 id = added++ & etp->et_mask;
533 offset = id * sizeof (efx_desc_t);
535 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
538 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
539 unsigned int, added, unsigned int, n);
541 EFX_TX_QSTAT_INCR(etp, TX_POST);
547 EFSYS_PROBE1(fail1, efx_rc_t, rc);
553 ef10_tx_qdesc_dma_create(
555 __in efsys_dma_addr_t addr,
558 __out efx_desc_t *edp)
560 /* No limitations on boundary crossing */
561 EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
563 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
564 efsys_dma_addr_t, addr,
565 size_t, size, boolean_t, eop);
567 EFX_POPULATE_QWORD_5(edp->ed_eq,
568 ESF_DZ_TX_KER_TYPE, 0,
569 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
570 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
571 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
572 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
576 ef10_tx_qdesc_tso_create(
578 __in uint16_t ipv4_id,
579 __in uint32_t tcp_seq,
580 __in uint8_t tcp_flags,
581 __out efx_desc_t *edp)
583 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
584 uint16_t, ipv4_id, uint32_t, tcp_seq,
587 EFX_POPULATE_QWORD_5(edp->ed_eq,
588 ESF_DZ_TX_DESC_IS_OPT, 1,
589 ESF_DZ_TX_OPTION_TYPE,
590 ESE_DZ_TX_OPTION_DESC_TSO,
591 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
592 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
593 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
597 ef10_tx_qdesc_tso2_create(
599 __in uint16_t ipv4_id,
600 __in uint32_t tcp_seq,
601 __in uint16_t tcp_mss,
602 __out_ecount(count) efx_desc_t *edp,
605 EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
606 uint16_t, ipv4_id, uint32_t, tcp_seq,
609 EFSYS_ASSERT(count >= EFX_TX_FATSOV2_OPT_NDESCS);
611 EFX_POPULATE_QWORD_5(edp[0].ed_eq,
612 ESF_DZ_TX_DESC_IS_OPT, 1,
613 ESF_DZ_TX_OPTION_TYPE,
614 ESE_DZ_TX_OPTION_DESC_TSO,
615 ESF_DZ_TX_TSO_OPTION_TYPE,
616 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
617 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
618 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
619 EFX_POPULATE_QWORD_4(edp[1].ed_eq,
620 ESF_DZ_TX_DESC_IS_OPT, 1,
621 ESF_DZ_TX_OPTION_TYPE,
622 ESE_DZ_TX_OPTION_DESC_TSO,
623 ESF_DZ_TX_TSO_OPTION_TYPE,
624 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
625 ESF_DZ_TX_TSO_TCP_MSS, tcp_mss);
629 ef10_tx_qdesc_vlantci_create(
632 __out efx_desc_t *edp)
634 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
637 EFX_POPULATE_QWORD_4(edp->ed_eq,
638 ESF_DZ_TX_DESC_IS_OPT, 1,
639 ESF_DZ_TX_OPTION_TYPE,
640 ESE_DZ_TX_OPTION_DESC_VLAN,
641 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
642 ESF_DZ_TX_VLAN_TAG1, tci);
646 __checkReturn efx_rc_t
649 __in unsigned int ns)
654 _NOTE(ARGUNUSED(etp, ns))
655 _NOTE(CONSTANTCONDITION)
665 EFSYS_PROBE1(fail1, efx_rc_t, rc);
670 __checkReturn efx_rc_t
674 efx_nic_t *enp = etp->et_enp;
677 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
684 * EALREADY is not an error, but indicates that the MC has rebooted and
685 * that the TXQ has already been destroyed. Callers need to know that
686 * the TXQ flush has completed to avoid waiting until timeout for a
687 * flush done event that will not be delivered.
690 EFSYS_PROBE1(fail1, efx_rc_t, rc);
700 _NOTE(ARGUNUSED(etp))
706 ef10_tx_qstats_update(
708 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
712 for (id = 0; id < TX_NQSTATS; id++) {
713 efsys_stat_t *essp = &stat[id];
715 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
716 etp->et_stat[id] = 0;
720 #endif /* EFSYS_OPT_QSTATS */
722 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */