drivers/net/sfc/base/efx_ev.c

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #include "efx.h"
  32 #include "efx_impl.h"
  33 #if EFSYS_OPT_MON_MCDI
  34 #include "mcdi_mon.h"
  35 #endif
  36
  37 #if EFSYS_OPT_QSTATS
  38 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
  39         do {                                                            \
  40                 (_eep)->ee_stat[_stat]++;                               \
  41         _NOTE(CONSTANTCONDITION)                                        \
  42         } while (B_FALSE)
  43 #else
  44 #define EFX_EV_QSTAT_INCR(_eep, _stat)
  45 #endif
  46
  47 #define EFX_EV_PRESENT(_qword)                                          \
  48         (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&        \
  49         EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
  50
  51
  52
  53 #if EFSYS_OPT_SIENA
  54
  55 static  __checkReturn   efx_rc_t
  56 siena_ev_init(
  57         __in            efx_nic_t *enp);
  58
  59 static                  void
  60 siena_ev_fini(
  61         __in            efx_nic_t *enp);
  62
  63 static  __checkReturn   efx_rc_t
  64 siena_ev_qcreate(
  65         __in            efx_nic_t *enp,
  66         __in            unsigned int index,
  67         __in            efsys_mem_t *esmp,
  68         __in            size_t n,
  69         __in            uint32_t id,
  70         __in            uint32_t us,
  71         __in            uint32_t flags,
  72         __in            efx_evq_t *eep);
  73
  74 static                  void
  75 siena_ev_qdestroy(
  76         __in            efx_evq_t *eep);
  77
  78 static  __checkReturn   efx_rc_t
  79 siena_ev_qprime(
  80         __in            efx_evq_t *eep,
  81         __in            unsigned int count);
  82
  83 static                  void
  84 siena_ev_qpost(
  85         __in    efx_evq_t *eep,
  86         __in    uint16_t data);
  87
  88 static  __checkReturn   efx_rc_t
  89 siena_ev_qmoderate(
  90         __in            efx_evq_t *eep,
  91         __in            unsigned int us);
  92
  93 #if EFSYS_OPT_QSTATS
  94 static                  void
  95 siena_ev_qstats_update(
  96         __in                            efx_evq_t *eep,
  97         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
  98
  99 #endif
 100
 101 #endif /* EFSYS_OPT_SIENA */
 102
 103 #if EFSYS_OPT_SIENA
 104 static const efx_ev_ops_t       __efx_ev_siena_ops = {
 105         siena_ev_init,                          /* eevo_init */
 106         siena_ev_fini,                          /* eevo_fini */
 107         siena_ev_qcreate,                       /* eevo_qcreate */
 108         siena_ev_qdestroy,                      /* eevo_qdestroy */
 109         siena_ev_qprime,                        /* eevo_qprime */
 110         siena_ev_qpost,                         /* eevo_qpost */
 111         siena_ev_qmoderate,                     /* eevo_qmoderate */
 112 #if EFSYS_OPT_QSTATS
 113         siena_ev_qstats_update,                 /* eevo_qstats_update */
 114 #endif
 115 };
 116 #endif /* EFSYS_OPT_SIENA */
 117
 118 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 119 static const efx_ev_ops_t       __efx_ev_ef10_ops = {
 120         ef10_ev_init,                           /* eevo_init */
 121         ef10_ev_fini,                           /* eevo_fini */
 122         ef10_ev_qcreate,                        /* eevo_qcreate */
 123         ef10_ev_qdestroy,                       /* eevo_qdestroy */
 124         ef10_ev_qprime,                         /* eevo_qprime */
 125         ef10_ev_qpost,                          /* eevo_qpost */
 126         ef10_ev_qmoderate,                      /* eevo_qmoderate */
 127 #if EFSYS_OPT_QSTATS
 128         ef10_ev_qstats_update,                  /* eevo_qstats_update */
 129 #endif
 130 };
 131 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 132
 133
 134         __checkReturn   efx_rc_t
 135 efx_ev_init(
 136         __in            efx_nic_t *enp)
 137 {
 138         const efx_ev_ops_t *eevop;
 139         efx_rc_t rc;
 140
 141         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 142         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 143
 144         if (enp->en_mod_flags & EFX_MOD_EV) {
 145                 rc = EINVAL;
 146                 goto fail1;
 147         }
 148
 149         switch (enp->en_family) {
 150 #if EFSYS_OPT_SIENA
 151         case EFX_FAMILY_SIENA:
 152                 eevop = &__efx_ev_siena_ops;
 153                 break;
 154 #endif /* EFSYS_OPT_SIENA */
 155
 156 #if EFSYS_OPT_HUNTINGTON
 157         case EFX_FAMILY_HUNTINGTON:
 158                 eevop = &__efx_ev_ef10_ops;
 159                 break;
 160 #endif /* EFSYS_OPT_HUNTINGTON */
 161
 162 #if EFSYS_OPT_MEDFORD
 163         case EFX_FAMILY_MEDFORD:
 164                 eevop = &__efx_ev_ef10_ops;
 165                 break;
 166 #endif /* EFSYS_OPT_MEDFORD */
 167
 168         default:
 169                 EFSYS_ASSERT(0);
 170                 rc = ENOTSUP;
 171                 goto fail1;
 172         }
 173
 174         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 175
 176         if ((rc = eevop->eevo_init(enp)) != 0)
 177                 goto fail2;
 178
 179         enp->en_eevop = eevop;
 180         enp->en_mod_flags |= EFX_MOD_EV;
 181         return (0);
 182
 183 fail2:
 184         EFSYS_PROBE(fail2);
 185
 186 fail1:
 187         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 188
 189         enp->en_eevop = NULL;
 190         enp->en_mod_flags &= ~EFX_MOD_EV;
 191         return (rc);
 192 }
 193
 194                 void
 195 efx_ev_fini(
 196         __in    efx_nic_t *enp)
 197 {
 198         const efx_ev_ops_t *eevop = enp->en_eevop;
 199
 200         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 201         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 202         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 203         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 204         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 205         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 206
 207         eevop->eevo_fini(enp);
 208
 209         enp->en_eevop = NULL;
 210         enp->en_mod_flags &= ~EFX_MOD_EV;
 211 }
 212
 213
 214         __checkReturn   efx_rc_t
 215 efx_ev_qcreate(
 216         __in            efx_nic_t *enp,
 217         __in            unsigned int index,
 218         __in            efsys_mem_t *esmp,
 219         __in            size_t n,
 220         __in            uint32_t id,
 221         __in            uint32_t us,
 222         __in            uint32_t flags,
 223         __deref_out     efx_evq_t **eepp)
 224 {
 225         const efx_ev_ops_t *eevop = enp->en_eevop;
 226         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 227         efx_evq_t *eep;
 228         efx_rc_t rc;
 229
 230         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 231         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 232
 233         EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
 234
 235         switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
 236         case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
 237                 break;
 238         case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
 239                 if (us != 0) {
 240                         rc = EINVAL;
 241                         goto fail1;
 242                 }
 243                 break;
 244         default:
 245                 rc = EINVAL;
 246                 goto fail2;
 247         }
 248
 249         /* Allocate an EVQ object */
 250         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
 251         if (eep == NULL) {
 252                 rc = ENOMEM;
 253                 goto fail3;
 254         }
 255
 256         eep->ee_magic = EFX_EVQ_MAGIC;
 257         eep->ee_enp = enp;
 258         eep->ee_index = index;
 259         eep->ee_mask = n - 1;
 260         eep->ee_flags = flags;
 261         eep->ee_esmp = esmp;
 262
 263         /*
 264          * Set outputs before the queue is created because interrupts may be
 265          * raised for events immediately after the queue is created, before the
 266          * function call below returns. See bug58606.
 267          *
 268          * The eepp pointer passed in by the client must therefore point to data
 269          * shared with the client's event processing context.
 270          */
 271         enp->en_ev_qcount++;
 272         *eepp = eep;
 273
 274         if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,
 275             eep)) != 0)
 276                 goto fail4;
 277
 278         return (0);
 279
 280 fail4:
 281         EFSYS_PROBE(fail4);
 282
 283         *eepp = NULL;
 284         enp->en_ev_qcount--;
 285         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 286 fail3:
 287         EFSYS_PROBE(fail3);
 288 fail2:
 289         EFSYS_PROBE(fail2);
 290 fail1:
 291         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 292         return (rc);
 293 }
 294
 295                 void
 296 efx_ev_qdestroy(
 297         __in    efx_evq_t *eep)
 298 {
 299         efx_nic_t *enp = eep->ee_enp;
 300         const efx_ev_ops_t *eevop = enp->en_eevop;
 301
 302         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 303
 304         EFSYS_ASSERT(enp->en_ev_qcount != 0);
 305         --enp->en_ev_qcount;
 306
 307         eevop->eevo_qdestroy(eep);
 308
 309         /* Free the EVQ object */
 310         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 311 }
 312
 313         __checkReturn   efx_rc_t
 314 efx_ev_qprime(
 315         __in            efx_evq_t *eep,
 316         __in            unsigned int count)
 317 {
 318         efx_nic_t *enp = eep->ee_enp;
 319         const efx_ev_ops_t *eevop = enp->en_eevop;
 320         efx_rc_t rc;
 321
 322         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 323
 324         if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
 325                 rc = EINVAL;
 326                 goto fail1;
 327         }
 328
 329         if ((rc = eevop->eevo_qprime(eep, count)) != 0)
 330                 goto fail2;
 331
 332         return (0);
 333
 334 fail2:
 335         EFSYS_PROBE(fail2);
 336 fail1:
 337         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 338         return (rc);
 339 }
 340
 341         __checkReturn   boolean_t
 342 efx_ev_qpending(
 343         __in            efx_evq_t *eep,
 344         __in            unsigned int count)
 345 {
 346         size_t offset;
 347         efx_qword_t qword;
 348
 349         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 350
 351         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 352         EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
 353
 354         return (EFX_EV_PRESENT(qword));
 355 }
 356
 357 #if EFSYS_OPT_EV_PREFETCH
 358
 359                         void
 360 efx_ev_qprefetch(
 361         __in            efx_evq_t *eep,
 362         __in            unsigned int count)
 363 {
 364         unsigned int offset;
 365
 366         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 367
 368         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 369         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 370 }
 371
 372 #endif  /* EFSYS_OPT_EV_PREFETCH */
 373
 374 #define EFX_EV_BATCH    8
 375
 376                         void
 377 efx_ev_qpoll(
 378         __in            efx_evq_t *eep,
 379         __inout         unsigned int *countp,
 380         __in            const efx_ev_callbacks_t *eecp,
 381         __in_opt        void *arg)
 382 {
 383         efx_qword_t ev[EFX_EV_BATCH];
 384         unsigned int batch;
 385         unsigned int total;
 386         unsigned int count;
 387         unsigned int index;
 388         size_t offset;
 389
 390         /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
 391         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
 392         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
 393
 394         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
 395         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
 396         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
 397         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
 398             FSE_AZ_EV_CODE_DRV_GEN_EV);
 399 #if EFSYS_OPT_MCDI
 400         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
 401             FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
 402 #endif
 403
 404         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 405         EFSYS_ASSERT(countp != NULL);
 406         EFSYS_ASSERT(eecp != NULL);
 407
 408         count = *countp;
 409         do {
 410                 /* Read up until the end of the batch period */
 411                 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
 412                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 413                 for (total = 0; total < batch; ++total) {
 414                         EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
 415
 416                         if (!EFX_EV_PRESENT(ev[total]))
 417                                 break;
 418
 419                         EFSYS_PROBE3(event, unsigned int, eep->ee_index,
 420                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
 421                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
 422
 423                         offset += sizeof (efx_qword_t);
 424                 }
 425
 426 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
 427                 /*
 428                  * Prefetch the next batch when we get within PREFETCH_PERIOD
 429                  * of a completed batch. If the batch is smaller, then prefetch
 430                  * immediately.
 431                  */
 432                 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
 433                         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 434 #endif  /* EFSYS_OPT_EV_PREFETCH */
 435
 436                 /* Process the batch of events */
 437                 for (index = 0; index < total; ++index) {
 438                         boolean_t should_abort;
 439                         uint32_t code;
 440
 441 #if EFSYS_OPT_EV_PREFETCH
 442                         /* Prefetch if we've now reached the batch period */
 443                         if (total == batch &&
 444                             index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
 445                                 offset = (count + batch) & eep->ee_mask;
 446                                 offset *= sizeof (efx_qword_t);
 447
 448                                 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 449                         }
 450 #endif  /* EFSYS_OPT_EV_PREFETCH */
 451
 452                         EFX_EV_QSTAT_INCR(eep, EV_ALL);
 453
 454                         code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
 455                         switch (code) {
 456                         case FSE_AZ_EV_CODE_RX_EV:
 457                                 should_abort = eep->ee_rx(eep,
 458                                     &(ev[index]), eecp, arg);
 459                                 break;
 460                         case FSE_AZ_EV_CODE_TX_EV:
 461                                 should_abort = eep->ee_tx(eep,
 462                                     &(ev[index]), eecp, arg);
 463                                 break;
 464                         case FSE_AZ_EV_CODE_DRIVER_EV:
 465                                 should_abort = eep->ee_driver(eep,
 466                                     &(ev[index]), eecp, arg);
 467                                 break;
 468                         case FSE_AZ_EV_CODE_DRV_GEN_EV:
 469                                 should_abort = eep->ee_drv_gen(eep,
 470                                     &(ev[index]), eecp, arg);
 471                                 break;
 472 #if EFSYS_OPT_MCDI
 473                         case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
 474                                 should_abort = eep->ee_mcdi(eep,
 475                                     &(ev[index]), eecp, arg);
 476                                 break;
 477 #endif
 478                         case FSE_AZ_EV_CODE_GLOBAL_EV:
 479                                 if (eep->ee_global) {
 480                                         should_abort = eep->ee_global(eep,
 481                                             &(ev[index]), eecp, arg);
 482                                         break;
 483                                 }
 484                                 /* else fallthrough */
 485                         default:
 486                                 EFSYS_PROBE3(bad_event,
 487                                     unsigned int, eep->ee_index,
 488                                     uint32_t,
 489                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
 490                                     uint32_t,
 491                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
 492
 493                                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 494                                 (void) eecp->eec_exception(arg,
 495                                         EFX_EXCEPTION_EV_ERROR, code);
 496                                 should_abort = B_TRUE;
 497                         }
 498                         if (should_abort) {
 499                                 /* Ignore subsequent events */
 500                                 total = index + 1;
 501                                 break;
 502                         }
 503                 }
 504
 505                 /*
 506                  * Now that the hardware has most likely moved onto dma'ing
 507                  * into the next cache line, clear the processed events. Take
 508                  * care to only clear out events that we've processed
 509                  */
 510                 EFX_SET_QWORD(ev[0]);
 511                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 512                 for (index = 0; index < total; ++index) {
 513                         EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
 514                         offset += sizeof (efx_qword_t);
 515                 }
 516
 517                 count += total;
 518
 519         } while (total == batch);
 520
 521         *countp = count;
 522 }
 523
 524                         void
 525 efx_ev_qpost(
 526         __in    efx_evq_t *eep,
 527         __in    uint16_t data)
 528 {
 529         efx_nic_t *enp = eep->ee_enp;
 530         const efx_ev_ops_t *eevop = enp->en_eevop;
 531
 532         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 533
 534         EFSYS_ASSERT(eevop != NULL &&
 535             eevop->eevo_qpost != NULL);
 536
 537         eevop->eevo_qpost(eep, data);
 538 }
 539
 540         __checkReturn   efx_rc_t
 541 efx_ev_usecs_to_ticks(
 542         __in            efx_nic_t *enp,
 543         __in            unsigned int us,
 544         __out           unsigned int *ticksp)
 545 {
 546         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 547         unsigned int ticks;
 548
 549         /* Convert microseconds to a timer tick count */
 550         if (us == 0)
 551                 ticks = 0;
 552         else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
 553                 ticks = 1;      /* Never round down to zero */
 554         else
 555                 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
 556
 557         *ticksp = ticks;
 558         return (0);
 559 }
 560
 561         __checkReturn   efx_rc_t
 562 efx_ev_qmoderate(
 563         __in            efx_evq_t *eep,
 564         __in            unsigned int us)
 565 {
 566         efx_nic_t *enp = eep->ee_enp;
 567         const efx_ev_ops_t *eevop = enp->en_eevop;
 568         efx_rc_t rc;
 569
 570         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 571
 572         if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
 573             EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
 574                 rc = EINVAL;
 575                 goto fail1;
 576         }
 577
 578         if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
 579                 goto fail2;
 580
 581         return (0);
 582
 583 fail2:
 584         EFSYS_PROBE(fail2);
 585 fail1:
 586         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 587         return (rc);
 588 }
 589
 590 #if EFSYS_OPT_QSTATS
 591                                         void
 592 efx_ev_qstats_update(
 593         __in                            efx_evq_t *eep,
 594         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
 595
 596 {       efx_nic_t *enp = eep->ee_enp;
 597         const efx_ev_ops_t *eevop = enp->en_eevop;
 598
 599         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 600
 601         eevop->eevo_qstats_update(eep, stat);
 602 }
 603
 604 #endif  /* EFSYS_OPT_QSTATS */
 605
 606 #if EFSYS_OPT_SIENA
 607
 608 static  __checkReturn   efx_rc_t
 609 siena_ev_init(
 610         __in            efx_nic_t *enp)
 611 {
 612         efx_oword_t oword;
 613
 614         /*
 615          * Program the event queue for receive and transmit queue
 616          * flush events.
 617          */
 618         EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
 619         EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
 620         EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
 621
 622         return (0);
 623
 624 }
 625
 626 static  __checkReturn   boolean_t
 627 siena_ev_rx_not_ok(
 628         __in            efx_evq_t *eep,
 629         __in            efx_qword_t *eqp,
 630         __in            uint32_t label,
 631         __in            uint32_t id,
 632         __inout         uint16_t *flagsp)
 633 {
 634         boolean_t ignore = B_FALSE;
 635
 636         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
 637                 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
 638                 EFSYS_PROBE(tobe_disc);
 639                 /*
 640                  * Assume this is a unicast address mismatch, unless below
 641                  * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
 642                  * EV_RX_PAUSE_FRM_ERR is set.
 643                  */
 644                 (*flagsp) |= EFX_ADDR_MISMATCH;
 645         }
 646
 647         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
 648                 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
 649                 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
 650                 (*flagsp) |= EFX_DISCARD;
 651
 652 #if EFSYS_OPT_RX_SCATTER
 653                 /*
 654                  * Lookout for payload queue ran dry errors and ignore them.
 655                  *
 656                  * Sadly for the header/data split cases, the descriptor
 657                  * pointer in this event refers to the header queue and
 658                  * therefore cannot be easily detected as duplicate.
 659                  * So we drop these and rely on the receive processing seeing
 660                  * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
 661                  * the partially received packet.
 662                  */
 663                 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
 664                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
 665                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
 666                         ignore = B_TRUE;
 667 #endif  /* EFSYS_OPT_RX_SCATTER */
 668         }
 669
 670         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
 671                 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
 672                 EFSYS_PROBE(crc_err);
 673                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 674                 (*flagsp) |= EFX_DISCARD;
 675         }
 676
 677         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
 678                 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
 679                 EFSYS_PROBE(pause_frm_err);
 680                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 681                 (*flagsp) |= EFX_DISCARD;
 682         }
 683
 684         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
 685                 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
 686                 EFSYS_PROBE(owner_id_err);
 687                 (*flagsp) |= EFX_DISCARD;
 688         }
 689
 690         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
 691                 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
 692                 EFSYS_PROBE(ipv4_err);
 693                 (*flagsp) &= ~EFX_CKSUM_IPV4;
 694         }
 695
 696         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
 697                 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
 698                 EFSYS_PROBE(udp_chk_err);
 699                 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
 700         }
 701
 702         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
 703                 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
 704
 705                 /*
 706                  * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
 707                  * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
 708                  * condition.
 709                  */
 710                 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
 711         }
 712
 713         return (ignore);
 714 }
 715
 716 static  __checkReturn   boolean_t
 717 siena_ev_rx(
 718         __in            efx_evq_t *eep,
 719         __in            efx_qword_t *eqp,
 720         __in            const efx_ev_callbacks_t *eecp,
 721         __in_opt        void *arg)
 722 {
 723         uint32_t id;
 724         uint32_t size;
 725         uint32_t label;
 726         boolean_t ok;
 727 #if EFSYS_OPT_RX_SCATTER
 728         boolean_t sop;
 729         boolean_t jumbo_cont;
 730 #endif  /* EFSYS_OPT_RX_SCATTER */
 731         uint32_t hdr_type;
 732         boolean_t is_v6;
 733         uint16_t flags;
 734         boolean_t ignore;
 735         boolean_t should_abort;
 736
 737         EFX_EV_QSTAT_INCR(eep, EV_RX);
 738
 739         /* Basic packet information */
 740         id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
 741         size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
 742         label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
 743         ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
 744
 745 #if EFSYS_OPT_RX_SCATTER
 746         sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
 747         jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
 748 #endif  /* EFSYS_OPT_RX_SCATTER */
 749
 750         hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
 751
 752         is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
 753
 754         /*
 755          * If packet is marked as OK and packet type is TCP/IP or
 756          * UDP/IP or other IP, then we can rely on the hardware checksums.
 757          */
 758         switch (hdr_type) {
 759         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
 760                 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
 761                 if (is_v6) {
 762                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
 763                         flags |= EFX_PKT_IPV6;
 764                 } else {
 765                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
 766                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 767                 }
 768                 break;
 769
 770         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
 771                 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
 772                 if (is_v6) {
 773                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
 774                         flags |= EFX_PKT_IPV6;
 775                 } else {
 776                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
 777                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 778                 }
 779                 break;
 780
 781         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
 782                 if (is_v6) {
 783                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
 784                         flags = EFX_PKT_IPV6;
 785                 } else {
 786                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
 787                         flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 788                 }
 789                 break;
 790
 791         case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
 792                 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
 793                 flags = 0;
 794                 break;
 795
 796         default:
 797                 EFSYS_ASSERT(B_FALSE);
 798                 flags = 0;
 799                 break;
 800         }
 801
 802 #if EFSYS_OPT_RX_SCATTER
 803         /* Report scatter and header/lookahead split buffer flags */
 804         if (sop)
 805                 flags |= EFX_PKT_START;
 806         if (jumbo_cont)
 807                 flags |= EFX_PKT_CONT;
 808 #endif  /* EFSYS_OPT_RX_SCATTER */
 809
 810         /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
 811         if (!ok) {
 812                 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
 813                 if (ignore) {
 814                         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 815                             uint32_t, size, uint16_t, flags);
 816
 817                         return (B_FALSE);
 818                 }
 819         }
 820
 821         /* If we're not discarding the packet then it is ok */
 822         if (~flags & EFX_DISCARD)
 823                 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
 824
 825         /* Detect multicast packets that didn't match the filter */
 826         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
 827                 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
 828
 829                 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
 830                         EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
 831                 } else {
 832                         EFSYS_PROBE(mcast_mismatch);
 833                         flags |= EFX_ADDR_MISMATCH;
 834                 }
 835         } else {
 836                 flags |= EFX_PKT_UNICAST;
 837         }
 838
 839         /*
 840          * The packet parser in Siena can abort parsing packets under
 841          * certain error conditions, setting the PKT_NOT_PARSED bit
 842          * (which clears PKT_OK). If this is set, then don't trust
 843          * the PKT_TYPE field.
 844          */
 845         if (!ok) {
 846                 uint32_t parse_err;
 847
 848                 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
 849                 if (parse_err != 0)
 850                         flags |= EFX_CHECK_VLAN;
 851         }
 852
 853         if (~flags & EFX_CHECK_VLAN) {
 854                 uint32_t pkt_type;
 855
 856                 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
 857                 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
 858                         flags |= EFX_PKT_VLAN_TAGGED;
 859         }
 860
 861         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 862             uint32_t, size, uint16_t, flags);
 863
 864         EFSYS_ASSERT(eecp->eec_rx != NULL);
 865         should_abort = eecp->eec_rx(arg, label, id, size, flags);
 866
 867         return (should_abort);
 868 }
 869
 870 static  __checkReturn   boolean_t
 871 siena_ev_tx(
 872         __in            efx_evq_t *eep,
 873         __in            efx_qword_t *eqp,
 874         __in            const efx_ev_callbacks_t *eecp,
 875         __in_opt        void *arg)
 876 {
 877         uint32_t id;
 878         uint32_t label;
 879         boolean_t should_abort;
 880
 881         EFX_EV_QSTAT_INCR(eep, EV_TX);
 882
 883         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
 884             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
 885             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
 886             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
 887
 888                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
 889                 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
 890
 891                 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
 892
 893                 EFSYS_ASSERT(eecp->eec_tx != NULL);
 894                 should_abort = eecp->eec_tx(arg, label, id);
 895
 896                 return (should_abort);
 897         }
 898
 899         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
 900                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 901                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 902                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 903
 904         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
 905                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
 906
 907         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
 908                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
 909
 910         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
 911                 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
 912
 913         EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
 914         return (B_FALSE);
 915 }
 916
 917 static  __checkReturn   boolean_t
 918 siena_ev_global(
 919         __in            efx_evq_t *eep,
 920         __in            efx_qword_t *eqp,
 921         __in            const efx_ev_callbacks_t *eecp,
 922         __in_opt        void *arg)
 923 {
 924         _NOTE(ARGUNUSED(eqp, eecp, arg))
 925
 926         EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
 927
 928         return (B_FALSE);
 929 }
 930
 931 static  __checkReturn   boolean_t
 932 siena_ev_driver(
 933         __in            efx_evq_t *eep,
 934         __in            efx_qword_t *eqp,
 935         __in            const efx_ev_callbacks_t *eecp,
 936         __in_opt        void *arg)
 937 {
 938         boolean_t should_abort;
 939
 940         EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
 941         should_abort = B_FALSE;
 942
 943         switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
 944         case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
 945                 uint32_t txq_index;
 946
 947                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
 948
 949                 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 950
 951                 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
 952
 953                 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
 954                 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
 955
 956                 break;
 957         }
 958         case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
 959                 uint32_t rxq_index;
 960                 uint32_t failed;
 961
 962                 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
 963                 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
 964
 965                 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
 966                 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
 967
 968                 if (failed) {
 969                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
 970
 971                         EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
 972
 973                         should_abort = eecp->eec_rxq_flush_failed(arg,
 974                                                                     rxq_index);
 975                 } else {
 976                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
 977
 978                         EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
 979
 980                         should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
 981                 }
 982
 983                 break;
 984         }
 985         case FSE_AZ_EVQ_INIT_DONE_EV:
 986                 EFSYS_ASSERT(eecp->eec_initialized != NULL);
 987                 should_abort = eecp->eec_initialized(arg);
 988
 989                 break;
 990
 991         case FSE_AZ_EVQ_NOT_EN_EV:
 992                 EFSYS_PROBE(evq_not_en);
 993                 break;
 994
 995         case FSE_AZ_SRM_UPD_DONE_EV: {
 996                 uint32_t code;
 997
 998                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
 999
1000                 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1001
1002                 EFSYS_ASSERT(eecp->eec_sram != NULL);
1003                 should_abort = eecp->eec_sram(arg, code);
1004
1005                 break;
1006         }
1007         case FSE_AZ_WAKE_UP_EV: {
1008                 uint32_t id;
1009
1010                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1011
1012                 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1013                 should_abort = eecp->eec_wake_up(arg, id);
1014
1015                 break;
1016         }
1017         case FSE_AZ_TX_PKT_NON_TCP_UDP:
1018                 EFSYS_PROBE(tx_pkt_non_tcp_udp);
1019                 break;
1020
1021         case FSE_AZ_TIMER_EV: {
1022                 uint32_t id;
1023
1024                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1025
1026                 EFSYS_ASSERT(eecp->eec_timer != NULL);
1027                 should_abort = eecp->eec_timer(arg, id);
1028
1029                 break;
1030         }
1031         case FSE_AZ_RX_DSC_ERROR_EV:
1032                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
1033
1034                 EFSYS_PROBE(rx_dsc_error);
1035
1036                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1037                 should_abort = eecp->eec_exception(arg,
1038                         EFX_EXCEPTION_RX_DSC_ERROR, 0);
1039
1040                 break;
1041
1042         case FSE_AZ_TX_DSC_ERROR_EV:
1043                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1044
1045                 EFSYS_PROBE(tx_dsc_error);
1046
1047                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1048                 should_abort = eecp->eec_exception(arg,
1049                         EFX_EXCEPTION_TX_DSC_ERROR, 0);
1050
1051                 break;
1052
1053         default:
1054                 break;
1055         }
1056
1057         return (should_abort);
1058 }
1059
1060 static  __checkReturn   boolean_t
1061 siena_ev_drv_gen(
1062         __in            efx_evq_t *eep,
1063         __in            efx_qword_t *eqp,
1064         __in            const efx_ev_callbacks_t *eecp,
1065         __in_opt        void *arg)
1066 {
1067         uint32_t data;
1068         boolean_t should_abort;
1069
1070         EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1071
1072         data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1073         if (data >= ((uint32_t)1 << 16)) {
1074                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1075                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1076                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1077                 return (B_TRUE);
1078         }
1079
1080         EFSYS_ASSERT(eecp->eec_software != NULL);
1081         should_abort = eecp->eec_software(arg, (uint16_t)data);
1082
1083         return (should_abort);
1084 }
1085
1086 #if EFSYS_OPT_MCDI
1087
1088 static  __checkReturn   boolean_t
1089 siena_ev_mcdi(
1090         __in            efx_evq_t *eep,
1091         __in            efx_qword_t *eqp,
1092         __in            const efx_ev_callbacks_t *eecp,
1093         __in_opt        void *arg)
1094 {
1095         efx_nic_t *enp = eep->ee_enp;
1096         unsigned int code;
1097         boolean_t should_abort = B_FALSE;
1098
1099         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1100
1101         if (enp->en_family != EFX_FAMILY_SIENA)
1102                 goto out;
1103
1104         EFSYS_ASSERT(eecp->eec_link_change != NULL);
1105         EFSYS_ASSERT(eecp->eec_exception != NULL);
1106 #if EFSYS_OPT_MON_STATS
1107         EFSYS_ASSERT(eecp->eec_monitor != NULL);
1108 #endif
1109
1110         EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1111
1112         code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1113         switch (code) {
1114         case MCDI_EVENT_CODE_BADSSERT:
1115                 efx_mcdi_ev_death(enp, EINTR);
1116                 break;
1117
1118         case MCDI_EVENT_CODE_CMDDONE:
1119                 efx_mcdi_ev_cpl(enp,
1120                     MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1121                     MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1122                     MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1123                 break;
1124
1125         case MCDI_EVENT_CODE_LINKCHANGE: {
1126                 efx_link_mode_t link_mode;
1127
1128                 siena_phy_link_ev(enp, eqp, &link_mode);
1129                 should_abort = eecp->eec_link_change(arg, link_mode);
1130                 break;
1131         }
1132         case MCDI_EVENT_CODE_SENSOREVT: {
1133 #if EFSYS_OPT_MON_STATS
1134                 efx_mon_stat_t id;
1135                 efx_mon_stat_value_t value;
1136                 efx_rc_t rc;
1137
1138                 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1139                         should_abort = eecp->eec_monitor(arg, id, value);
1140                 else if (rc == ENOTSUP) {
1141                         should_abort = eecp->eec_exception(arg,
1142                                 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1143                                 MCDI_EV_FIELD(eqp, DATA));
1144                 } else
1145                         EFSYS_ASSERT(rc == ENODEV);     /* Wrong port */
1146 #else
1147                 should_abort = B_FALSE;
1148 #endif
1149                 break;
1150         }
1151         case MCDI_EVENT_CODE_SCHEDERR:
1152                 /* Informational only */
1153                 break;
1154
1155         case MCDI_EVENT_CODE_REBOOT:
1156                 efx_mcdi_ev_death(enp, EIO);
1157                 break;
1158
1159         case MCDI_EVENT_CODE_MAC_STATS_DMA:
1160 #if EFSYS_OPT_MAC_STATS
1161                 if (eecp->eec_mac_stats != NULL) {
1162                         eecp->eec_mac_stats(arg,
1163                             MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1164                 }
1165 #endif
1166                 break;
1167
1168         case MCDI_EVENT_CODE_FWALERT: {
1169                 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1170
1171                 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1172                         should_abort = eecp->eec_exception(arg,
1173                                 EFX_EXCEPTION_FWALERT_SRAM,
1174                                 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1175                 else
1176                         should_abort = eecp->eec_exception(arg,
1177                                 EFX_EXCEPTION_UNKNOWN_FWALERT,
1178                                 MCDI_EV_FIELD(eqp, DATA));
1179                 break;
1180         }
1181
1182         default:
1183                 EFSYS_PROBE1(mc_pcol_error, int, code);
1184                 break;
1185         }
1186
1187 out:
1188         return (should_abort);
1189 }
1190
1191 #endif  /* EFSYS_OPT_MCDI */
1192
1193 static  __checkReturn   efx_rc_t
1194 siena_ev_qprime(
1195         __in            efx_evq_t *eep,
1196         __in            unsigned int count)
1197 {
1198         efx_nic_t *enp = eep->ee_enp;
1199         uint32_t rptr;
1200         efx_dword_t dword;
1201
1202         rptr = count & eep->ee_mask;
1203
1204         EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1205
1206         EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1207                             &dword, B_FALSE);
1208
1209         return (0);
1210 }
1211
1212 static          void
1213 siena_ev_qpost(
1214         __in    efx_evq_t *eep,
1215         __in    uint16_t data)
1216 {
1217         efx_nic_t *enp = eep->ee_enp;
1218         efx_qword_t ev;
1219         efx_oword_t oword;
1220
1221         EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1222             FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1223
1224         EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1225             EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1226             EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1227
1228         EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1229 }
1230
1231 static  __checkReturn   efx_rc_t
1232 siena_ev_qmoderate(
1233         __in            efx_evq_t *eep,
1234         __in            unsigned int us)
1235 {
1236         efx_nic_t *enp = eep->ee_enp;
1237         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1238         unsigned int locked;
1239         efx_dword_t dword;
1240         efx_rc_t rc;
1241
1242         if (us > encp->enc_evq_timer_max_us) {
1243                 rc = EINVAL;
1244                 goto fail1;
1245         }
1246
1247         /* If the value is zero then disable the timer */
1248         if (us == 0) {
1249                 EFX_POPULATE_DWORD_2(dword,
1250                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1251                     FRF_CZ_TC_TIMER_VAL, 0);
1252         } else {
1253                 unsigned int ticks;
1254
1255                 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1256                         goto fail2;
1257
1258                 EFSYS_ASSERT(ticks > 0);
1259                 EFX_POPULATE_DWORD_2(dword,
1260                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1261                     FRF_CZ_TC_TIMER_VAL, ticks - 1);
1262         }
1263
1264         locked = (eep->ee_index == 0) ? 1 : 0;
1265
1266         EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1267             eep->ee_index, &dword, locked);
1268
1269         return (0);
1270
1271 fail2:
1272         EFSYS_PROBE(fail2);
1273 fail1:
1274         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1275
1276         return (rc);
1277 }
1278
1279 static  __checkReturn   efx_rc_t
1280 siena_ev_qcreate(
1281         __in            efx_nic_t *enp,
1282         __in            unsigned int index,
1283         __in            efsys_mem_t *esmp,
1284         __in            size_t n,
1285         __in            uint32_t id,
1286         __in            uint32_t us,
1287         __in            uint32_t flags,
1288         __in            efx_evq_t *eep)
1289 {
1290         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1291         uint32_t size;
1292         efx_oword_t oword;
1293         efx_rc_t rc;
1294         boolean_t notify_mode;
1295
1296         _NOTE(ARGUNUSED(esmp))
1297
1298         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1299         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1300
1301         if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1302                 rc = EINVAL;
1303                 goto fail1;
1304         }
1305         if (index >= encp->enc_evq_limit) {
1306                 rc = EINVAL;
1307                 goto fail2;
1308         }
1309 #if EFSYS_OPT_RX_SCALE
1310         if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1311             index >= EFX_MAXRSS_LEGACY) {
1312                 rc = EINVAL;
1313                 goto fail3;
1314         }
1315 #endif
1316         for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1317             size++)
1318                 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1319                         break;
1320         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1321                 rc = EINVAL;
1322                 goto fail4;
1323         }
1324
1325         /* Set up the handler table */
1326         eep->ee_rx      = siena_ev_rx;
1327         eep->ee_tx      = siena_ev_tx;
1328         eep->ee_driver  = siena_ev_driver;
1329         eep->ee_global  = siena_ev_global;
1330         eep->ee_drv_gen = siena_ev_drv_gen;
1331 #if EFSYS_OPT_MCDI
1332         eep->ee_mcdi    = siena_ev_mcdi;
1333 #endif  /* EFSYS_OPT_MCDI */
1334
1335         notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1336             EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1337
1338         /* Set up the new event queue */
1339         EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1340             FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1341             FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1342         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1343
1344         EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1345             FRF_AZ_EVQ_BUF_BASE_ID, id);
1346
1347         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1348
1349         /* Set initial interrupt moderation */
1350         siena_ev_qmoderate(eep, us);
1351
1352         return (0);
1353
1354 fail4:
1355         EFSYS_PROBE(fail4);
1356 #if EFSYS_OPT_RX_SCALE
1357 fail3:
1358         EFSYS_PROBE(fail3);
1359 #endif
1360 fail2:
1361         EFSYS_PROBE(fail2);
1362 fail1:
1363         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1364
1365         return (rc);
1366 }
1367
1368 #endif /* EFSYS_OPT_SIENA */
1369
1370 #if EFSYS_OPT_QSTATS
1371 #if EFSYS_OPT_NAMES
1372 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1373 static const char * const __efx_ev_qstat_name[] = {
1374         "all",
1375         "rx",
1376         "rx_ok",
1377         "rx_frm_trunc",
1378         "rx_tobe_disc",
1379         "rx_pause_frm_err",
1380         "rx_buf_owner_id_err",
1381         "rx_ipv4_hdr_chksum_err",
1382         "rx_tcp_udp_chksum_err",
1383         "rx_eth_crc_err",
1384         "rx_ip_frag_err",
1385         "rx_mcast_pkt",
1386         "rx_mcast_hash_match",
1387         "rx_tcp_ipv4",
1388         "rx_tcp_ipv6",
1389         "rx_udp_ipv4",
1390         "rx_udp_ipv6",
1391         "rx_other_ipv4",
1392         "rx_other_ipv6",
1393         "rx_non_ip",
1394         "rx_batch",
1395         "tx",
1396         "tx_wq_ff_full",
1397         "tx_pkt_err",
1398         "tx_pkt_too_big",
1399         "tx_unexpected",
1400         "global",
1401         "global_mnt",
1402         "driver",
1403         "driver_srm_upd_done",
1404         "driver_tx_descq_fls_done",
1405         "driver_rx_descq_fls_done",
1406         "driver_rx_descq_fls_failed",
1407         "driver_rx_dsc_error",
1408         "driver_tx_dsc_error",
1409         "drv_gen",
1410         "mcdi_response",
1411 };
1412 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1413
1414                 const char *
1415 efx_ev_qstat_name(
1416         __in    efx_nic_t *enp,
1417         __in    unsigned int id)
1418 {
1419         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1420         EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1421
1422         return (__efx_ev_qstat_name[id]);
1423 }
1424 #endif  /* EFSYS_OPT_NAMES */
1425 #endif  /* EFSYS_OPT_QSTATS */
1426
1427 #if EFSYS_OPT_SIENA
1428
1429 #if EFSYS_OPT_QSTATS
1430 static                                  void
1431 siena_ev_qstats_update(
1432         __in                            efx_evq_t *eep,
1433         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
1434 {
1435         unsigned int id;
1436
1437         for (id = 0; id < EV_NQSTATS; id++) {
1438                 efsys_stat_t *essp = &stat[id];
1439
1440                 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1441                 eep->ee_stat[id] = 0;
1442         }
1443 }
1444 #endif  /* EFSYS_OPT_QSTATS */
1445
1446 static          void
1447 siena_ev_qdestroy(
1448         __in    efx_evq_t *eep)
1449 {
1450         efx_nic_t *enp = eep->ee_enp;
1451         efx_oword_t oword;
1452
1453         /* Purge event queue */
1454         EFX_ZERO_OWORD(oword);
1455
1456         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1457             eep->ee_index, &oword, B_TRUE);
1458
1459         EFX_ZERO_OWORD(oword);
1460         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1461 }
1462
1463 static          void
1464 siena_ev_fini(
1465         __in    efx_nic_t *enp)
1466 {
1467         _NOTE(ARGUNUSED(enp))
1468 }
1469
1470 #endif /* EFSYS_OPT_SIENA */