drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 #if EFSYS_OPT_QSTATS
 101         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 102 #endif
 103 } efx_ev_ops_t;
 104
 105 typedef struct efx_tx_ops_s {
 106         efx_rc_t        (*etxo_init)(efx_nic_t *);
 107         void            (*etxo_fini)(efx_nic_t *);
 108         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 109                                         unsigned int, unsigned int,
 110                                         efsys_mem_t *, size_t,
 111                                         uint32_t, uint16_t,
 112                                         efx_evq_t *, efx_txq_t *,
 113                                         unsigned int *);
 114         void            (*etxo_qdestroy)(efx_txq_t *);
 115         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 119         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 120         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 121         void            (*etxo_qenable)(efx_txq_t *);
 122         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 123         void            (*etxo_qpio_disable)(efx_txq_t *);
 124         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 125                                            size_t);
 126         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 127                                            unsigned int *);
 128         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 129                                       unsigned int, unsigned int,
 130                                       unsigned int *);
 131         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 132                                                 size_t, boolean_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint8_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint16_t,
 139                                                 efx_desc_t *, int);
 140         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 141                                                 efx_desc_t *);
 142 #if EFSYS_OPT_QSTATS
 143         void            (*etxo_qstats_update)(efx_txq_t *,
 144                                               efsys_stat_t *);
 145 #endif
 146 } efx_tx_ops_t;
 147
 148 typedef struct efx_rx_ops_s {
 149         efx_rc_t        (*erxo_init)(efx_nic_t *);
 150         void            (*erxo_fini)(efx_nic_t *);
 151 #if EFSYS_OPT_RX_SCATTER
 152         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 153 #endif
 154 #if EFSYS_OPT_RX_SCALE
 155         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 156                                                efx_rx_hash_type_t, boolean_t);
 157         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 158         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 159                                               size_t);
 160         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 161                                             uint8_t *);
 162 #endif /* EFSYS_OPT_RX_SCALE */
 163         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 164                                               uint16_t *);
 165         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 166                                       unsigned int, unsigned int,
 167                                       unsigned int);
 168         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 169 #if EFSYS_OPT_RX_PACKED_STREAM
 170         void            (*erxo_qps_update_credits)(efx_rxq_t *);
 171         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 172                                                 uint32_t, uint32_t,
 173                                                 uint16_t *, uint32_t *, uint32_t *);
 174 #endif
 175         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 176         void            (*erxo_qenable)(efx_rxq_t *);
 177         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 178                                         unsigned int, efx_rxq_type_t,
 179                                         efsys_mem_t *, size_t, uint32_t,
 180                                         efx_evq_t *, efx_rxq_t *);
 181         void            (*erxo_qdestroy)(efx_rxq_t *);
 182 } efx_rx_ops_t;
 183
 184 typedef struct efx_mac_ops_s {
 185         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 186         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 187         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 188         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 189         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 190         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 191         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 192         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 193                                                       efx_rxq_t *, boolean_t);
 194         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 195 #if EFSYS_OPT_LOOPBACK
 196         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 197                                             efx_loopback_type_t);
 198 #endif  /* EFSYS_OPT_LOOPBACK */
 199 #if EFSYS_OPT_MAC_STATS
 200         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 201         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 202         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 203         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 204                                               uint16_t, boolean_t);
 205         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 206                                             efsys_stat_t *, uint32_t *);
 207 #endif  /* EFSYS_OPT_MAC_STATS */
 208 } efx_mac_ops_t;
 209
 210 typedef struct efx_phy_ops_s {
 211         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 212         efx_rc_t        (*epo_reset)(efx_nic_t *);
 213         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 214         efx_rc_t        (*epo_verify)(efx_nic_t *);
 215         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 216 #if EFSYS_OPT_PHY_STATS
 217         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 218                                             uint32_t *);
 219 #endif  /* EFSYS_OPT_PHY_STATS */
 220 #if EFSYS_OPT_BIST
 221         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 222         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 223         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 224                                          efx_bist_result_t *, uint32_t *,
 225                                          unsigned long *, size_t);
 226         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 227 #endif  /* EFSYS_OPT_BIST */
 228 } efx_phy_ops_t;
 229
 230 #if EFSYS_OPT_FILTER
 231 typedef struct efx_filter_ops_s {
 232         efx_rc_t        (*efo_init)(efx_nic_t *);
 233         void            (*efo_fini)(efx_nic_t *);
 234         efx_rc_t        (*efo_restore)(efx_nic_t *);
 235         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 236                                    boolean_t may_replace);
 237         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 238         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 239                                    size_t, size_t *);
 240         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 241                                    boolean_t, boolean_t, boolean_t,
 242                                    uint8_t const *, uint32_t);
 243 } efx_filter_ops_t;
 244
 245 extern  __checkReturn   efx_rc_t
 246 efx_filter_reconfigure(
 247         __in                            efx_nic_t *enp,
 248         __in_ecount(6)                  uint8_t const *mac_addr,
 249         __in                            boolean_t all_unicst,
 250         __in                            boolean_t mulcst,
 251         __in                            boolean_t all_mulcst,
 252         __in                            boolean_t brdcst,
 253         __in_ecount(6*count)            uint8_t const *addrs,
 254         __in                            uint32_t count);
 255
 256 #endif /* EFSYS_OPT_FILTER */
 257
 258
 259 typedef struct efx_port_s {
 260         efx_mac_type_t          ep_mac_type;
 261         uint32_t                ep_phy_type;
 262         uint8_t                 ep_port;
 263         uint32_t                ep_mac_pdu;
 264         uint8_t                 ep_mac_addr[6];
 265         efx_link_mode_t         ep_link_mode;
 266         boolean_t               ep_all_unicst;
 267         boolean_t               ep_mulcst;
 268         boolean_t               ep_all_mulcst;
 269         boolean_t               ep_brdcst;
 270         unsigned int            ep_fcntl;
 271         boolean_t               ep_fcntl_autoneg;
 272         efx_oword_t             ep_multicst_hash[2];
 273         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 274                                                     EFX_MAC_MULTICAST_LIST_MAX];
 275         uint32_t                ep_mulcst_addr_count;
 276 #if EFSYS_OPT_LOOPBACK
 277         efx_loopback_type_t     ep_loopback_type;
 278         efx_link_mode_t         ep_loopback_link_mode;
 279 #endif  /* EFSYS_OPT_LOOPBACK */
 280 #if EFSYS_OPT_PHY_FLAGS
 281         uint32_t                ep_phy_flags;
 282 #endif  /* EFSYS_OPT_PHY_FLAGS */
 283 #if EFSYS_OPT_PHY_LED_CONTROL
 284         efx_phy_led_mode_t      ep_phy_led_mode;
 285 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 286         efx_phy_media_type_t    ep_fixed_port_type;
 287         efx_phy_media_type_t    ep_module_type;
 288         uint32_t                ep_adv_cap_mask;
 289         uint32_t                ep_lp_cap_mask;
 290         uint32_t                ep_default_adv_cap_mask;
 291         uint32_t                ep_phy_cap_mask;
 292         boolean_t               ep_mac_drain;
 293         boolean_t               ep_mac_stats_pending;
 294 #if EFSYS_OPT_BIST
 295         efx_bist_type_t         ep_current_bist;
 296 #endif
 297         const efx_mac_ops_t     *ep_emop;
 298         const efx_phy_ops_t     *ep_epop;
 299 } efx_port_t;
 300
 301 typedef struct efx_mon_ops_s {
 302 #if EFSYS_OPT_MON_STATS
 303         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 304                                             efx_mon_stat_value_t *);
 305 #endif  /* EFSYS_OPT_MON_STATS */
 306 } efx_mon_ops_t;
 307
 308 typedef struct efx_mon_s {
 309         efx_mon_type_t          em_type;
 310         const efx_mon_ops_t     *em_emop;
 311 } efx_mon_t;
 312
 313 typedef struct efx_intr_ops_s {
 314         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 315         void            (*eio_enable)(efx_nic_t *);
 316         void            (*eio_disable)(efx_nic_t *);
 317         void            (*eio_disable_unlocked)(efx_nic_t *);
 318         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 319         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 320         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 321                                  boolean_t *);
 322         void            (*eio_fatal)(efx_nic_t *);
 323         void            (*eio_fini)(efx_nic_t *);
 324 } efx_intr_ops_t;
 325
 326 typedef struct efx_intr_s {
 327         const efx_intr_ops_t    *ei_eiop;
 328         efsys_mem_t             *ei_esmp;
 329         efx_intr_type_t         ei_type;
 330         unsigned int            ei_level;
 331 } efx_intr_t;
 332
 333 typedef struct efx_nic_ops_s {
 334         efx_rc_t        (*eno_probe)(efx_nic_t *);
 335         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 336         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 337         efx_rc_t        (*eno_reset)(efx_nic_t *);
 338         efx_rc_t        (*eno_init)(efx_nic_t *);
 339         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 340         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 341                                         uint32_t *, size_t *);
 342 #if EFSYS_OPT_DIAG
 343         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 344 #endif  /* EFSYS_OPT_DIAG */
 345         void            (*eno_fini)(efx_nic_t *);
 346         void            (*eno_unprobe)(efx_nic_t *);
 347 } efx_nic_ops_t;
 348
 349 #ifndef EFX_TXQ_LIMIT_TARGET
 350 #define EFX_TXQ_LIMIT_TARGET 259
 351 #endif
 352 #ifndef EFX_RXQ_LIMIT_TARGET
 353 #define EFX_RXQ_LIMIT_TARGET 512
 354 #endif
 355 #ifndef EFX_TXQ_DC_SIZE
 356 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 357 #endif
 358 #ifndef EFX_RXQ_DC_SIZE
 359 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 360 #endif
 361
 362 #if EFSYS_OPT_FILTER
 363
 364 #if EFSYS_OPT_SIENA
 365
 366 typedef struct siena_filter_spec_s {
 367         uint8_t         sfs_type;
 368         uint32_t        sfs_flags;
 369         uint32_t        sfs_dmaq_id;
 370         uint32_t        sfs_dword[3];
 371 } siena_filter_spec_t;
 372
 373 typedef enum siena_filter_type_e {
 374         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 375         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 376         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 377         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 378         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 379         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 380
 381         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 382         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 383         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 384         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 385         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 386         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 387
 388         EFX_SIENA_FILTER_NTYPES
 389 } siena_filter_type_t;
 390
 391 typedef enum siena_filter_tbl_id_e {
 392         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 393         EFX_SIENA_FILTER_TBL_RX_MAC,
 394         EFX_SIENA_FILTER_TBL_TX_IP,
 395         EFX_SIENA_FILTER_TBL_TX_MAC,
 396         EFX_SIENA_FILTER_NTBLS
 397 } siena_filter_tbl_id_t;
 398
 399 typedef struct siena_filter_tbl_s {
 400         int                     sft_size;       /* number of entries */
 401         int                     sft_used;       /* active count */
 402         uint32_t                *sft_bitmap;    /* active bitmap */
 403         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 404 } siena_filter_tbl_t;
 405
 406 typedef struct siena_filter_s {
 407         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 408         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 409 } siena_filter_t;
 410
 411 #endif  /* EFSYS_OPT_SIENA */
 412
 413 typedef struct efx_filter_s {
 414 #if EFSYS_OPT_SIENA
 415         siena_filter_t          *ef_siena_filter;
 416 #endif /* EFSYS_OPT_SIENA */
 417 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 418         ef10_filter_table_t     *ef_ef10_filter_table;
 419 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 420 } efx_filter_t;
 421
 422 #if EFSYS_OPT_SIENA
 423
 424 extern                  void
 425 siena_filter_tbl_clear(
 426         __in            efx_nic_t *enp,
 427         __in            siena_filter_tbl_id_t tbl);
 428
 429 #endif  /* EFSYS_OPT_SIENA */
 430
 431 #endif  /* EFSYS_OPT_FILTER */
 432
 433 #if EFSYS_OPT_MCDI
 434
 435 typedef struct efx_mcdi_ops_s {
 436         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 437         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 438                                         void *, size_t);
 439         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 440         boolean_t       (*emco_poll_response)(efx_nic_t *);
 441         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 442         void            (*emco_fini)(efx_nic_t *);
 443         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 444                                             efx_mcdi_feature_id_t, boolean_t *);
 445         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 446                                             uint32_t *);
 447 } efx_mcdi_ops_t;
 448
 449 typedef struct efx_mcdi_s {
 450         const efx_mcdi_ops_t            *em_emcop;
 451         const efx_mcdi_transport_t      *em_emtp;
 452         efx_mcdi_iface_t                em_emip;
 453 } efx_mcdi_t;
 454
 455 #endif /* EFSYS_OPT_MCDI */
 456
 457 #if EFSYS_OPT_NVRAM
 458 typedef struct efx_nvram_ops_s {
 459 #if EFSYS_OPT_DIAG
 460         efx_rc_t        (*envo_test)(efx_nic_t *);
 461 #endif  /* EFSYS_OPT_DIAG */
 462         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 463                                             uint32_t *);
 464         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 465         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 466         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 467                                             unsigned int, caddr_t, size_t);
 468         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 469                                             unsigned int, size_t);
 470         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 471                                             unsigned int, caddr_t, size_t);
 472         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 473         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 474                                             uint32_t *, uint16_t *);
 475         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 476                                             uint16_t *);
 477         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 478                                             caddr_t, size_t);
 479 } efx_nvram_ops_t;
 480 #endif /* EFSYS_OPT_NVRAM */
 481
 482 #if EFSYS_OPT_VPD
 483 typedef struct efx_vpd_ops_s {
 484         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 485         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 486         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 487         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 488         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 489         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 490                                         efx_vpd_value_t *);
 491         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 492                                         efx_vpd_value_t *);
 493         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 494                                         efx_vpd_value_t *, unsigned int *);
 495         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 496         void            (*evpdo_fini)(efx_nic_t *);
 497 } efx_vpd_ops_t;
 498 #endif  /* EFSYS_OPT_VPD */
 499
 500 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 501
 502         __checkReturn           efx_rc_t
 503 efx_mcdi_nvram_partitions(
 504         __in                    efx_nic_t *enp,
 505         __out_bcount(size)      caddr_t data,
 506         __in                    size_t size,
 507         __out                   unsigned int *npartnp);
 508
 509         __checkReturn           efx_rc_t
 510 efx_mcdi_nvram_metadata(
 511         __in                    efx_nic_t *enp,
 512         __in                    uint32_t partn,
 513         __out                   uint32_t *subtypep,
 514         __out_ecount(4)         uint16_t version[4],
 515         __out_bcount_opt(size)  char *descp,
 516         __in                    size_t size);
 517
 518         __checkReturn           efx_rc_t
 519 efx_mcdi_nvram_info(
 520         __in                    efx_nic_t *enp,
 521         __in                    uint32_t partn,
 522         __out_opt               size_t *sizep,
 523         __out_opt               uint32_t *addressp,
 524         __out_opt               uint32_t *erase_sizep,
 525         __out_opt               uint32_t *write_sizep);
 526
 527         __checkReturn           efx_rc_t
 528 efx_mcdi_nvram_update_start(
 529         __in                    efx_nic_t *enp,
 530         __in                    uint32_t partn);
 531
 532         __checkReturn           efx_rc_t
 533 efx_mcdi_nvram_read(
 534         __in                    efx_nic_t *enp,
 535         __in                    uint32_t partn,
 536         __in                    uint32_t offset,
 537         __out_bcount(size)      caddr_t data,
 538         __in                    size_t size,
 539         __in                    uint32_t mode);
 540
 541         __checkReturn           efx_rc_t
 542 efx_mcdi_nvram_erase(
 543         __in                    efx_nic_t *enp,
 544         __in                    uint32_t partn,
 545         __in                    uint32_t offset,
 546         __in                    size_t size);
 547
 548         __checkReturn           efx_rc_t
 549 efx_mcdi_nvram_write(
 550         __in                    efx_nic_t *enp,
 551         __in                    uint32_t partn,
 552         __in                    uint32_t offset,
 553         __out_bcount(size)      caddr_t data,
 554         __in                    size_t size);
 555
 556         __checkReturn           efx_rc_t
 557 efx_mcdi_nvram_update_finish(
 558         __in                    efx_nic_t *enp,
 559         __in                    uint32_t partn,
 560         __in                    boolean_t reboot,
 561         __out_opt               uint32_t *resultp);
 562
 563 #if EFSYS_OPT_DIAG
 564
 565         __checkReturn           efx_rc_t
 566 efx_mcdi_nvram_test(
 567         __in                    efx_nic_t *enp,
 568         __in                    uint32_t partn);
 569
 570 #endif  /* EFSYS_OPT_DIAG */
 571
 572 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 573
 574 #if EFSYS_OPT_LICENSING
 575
 576 typedef struct efx_lic_ops_s {
 577         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 578         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 579         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 580         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 581                                       size_t *, uint8_t *);
 582         efx_rc_t        (*elo_find_start)
 583                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 584         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 585                                 uint32_t, uint32_t *);
 586         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 587                                 uint32_t, uint32_t *, uint32_t *);
 588         boolean_t       (*elo_validate_key)(efx_nic_t *,
 589                                 caddr_t, uint32_t);
 590         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 591                                 caddr_t, size_t, uint32_t, uint32_t,
 592                                 caddr_t, size_t, uint32_t *);
 593         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 594                                 caddr_t, size_t, uint32_t,
 595                                 caddr_t, uint32_t, uint32_t *);
 596         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 597                                 caddr_t, size_t, uint32_t,
 598                                 uint32_t, uint32_t, uint32_t *);
 599         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 600                                 caddr_t, size_t);
 601         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 602                                 caddr_t, size_t);
 603 } efx_lic_ops_t;
 604
 605 #endif
 606
 607 typedef struct efx_drv_cfg_s {
 608         uint32_t                edc_min_vi_count;
 609         uint32_t                edc_max_vi_count;
 610
 611         uint32_t                edc_max_piobuf_count;
 612         uint32_t                edc_pio_alloc_size;
 613 } efx_drv_cfg_t;
 614
 615 struct efx_nic_s {
 616         uint32_t                en_magic;
 617         efx_family_t            en_family;
 618         uint32_t                en_features;
 619         efsys_identifier_t      *en_esip;
 620         efsys_lock_t            *en_eslp;
 621         efsys_bar_t             *en_esbp;
 622         unsigned int            en_mod_flags;
 623         unsigned int            en_reset_flags;
 624         efx_nic_cfg_t           en_nic_cfg;
 625         efx_drv_cfg_t           en_drv_cfg;
 626         efx_port_t              en_port;
 627         efx_mon_t               en_mon;
 628         efx_intr_t              en_intr;
 629         uint32_t                en_ev_qcount;
 630         uint32_t                en_rx_qcount;
 631         uint32_t                en_tx_qcount;
 632         const efx_nic_ops_t     *en_enop;
 633         const efx_ev_ops_t      *en_eevop;
 634         const efx_tx_ops_t      *en_etxop;
 635         const efx_rx_ops_t      *en_erxop;
 636 #if EFSYS_OPT_FILTER
 637         efx_filter_t            en_filter;
 638         const efx_filter_ops_t  *en_efop;
 639 #endif  /* EFSYS_OPT_FILTER */
 640 #if EFSYS_OPT_MCDI
 641         efx_mcdi_t              en_mcdi;
 642 #endif  /* EFSYS_OPT_MCDI */
 643 #if EFSYS_OPT_NVRAM
 644         efx_nvram_type_t        en_nvram_locked;
 645         const efx_nvram_ops_t   *en_envop;
 646 #endif  /* EFSYS_OPT_NVRAM */
 647 #if EFSYS_OPT_VPD
 648         const efx_vpd_ops_t     *en_evpdop;
 649 #endif  /* EFSYS_OPT_VPD */
 650 #if EFSYS_OPT_RX_SCALE
 651         efx_rx_hash_support_t   en_hash_support;
 652         efx_rx_scale_support_t  en_rss_support;
 653         uint32_t                en_rss_context;
 654 #endif  /* EFSYS_OPT_RX_SCALE */
 655         uint32_t                en_vport_id;
 656 #if EFSYS_OPT_LICENSING
 657         const efx_lic_ops_t     *en_elop;
 658         boolean_t               en_licensing_supported;
 659 #endif
 660         union {
 661 #if EFSYS_OPT_SIENA
 662                 struct {
 663 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 664                         unsigned int            enu_partn_mask;
 665 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 666 #if EFSYS_OPT_VPD
 667                         caddr_t                 enu_svpd;
 668                         size_t                  enu_svpd_length;
 669 #endif  /* EFSYS_OPT_VPD */
 670                         int                     enu_unused;
 671                 } siena;
 672 #endif  /* EFSYS_OPT_SIENA */
 673                 int     enu_unused;
 674         } en_u;
 675 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 676         union en_arch {
 677                 struct {
 678                         int                     ena_vi_base;
 679                         int                     ena_vi_count;
 680                         int                     ena_vi_shift;
 681 #if EFSYS_OPT_VPD
 682                         caddr_t                 ena_svpd;
 683                         size_t                  ena_svpd_length;
 684 #endif  /* EFSYS_OPT_VPD */
 685                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 686                         uint32_t                ena_piobuf_count;
 687                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 688                         uint32_t                ena_pio_write_vi_base;
 689                         /* Memory BAR mapping regions */
 690                         uint32_t                ena_uc_mem_map_offset;
 691                         size_t                  ena_uc_mem_map_size;
 692                         uint32_t                ena_wc_mem_map_offset;
 693                         size_t                  ena_wc_mem_map_size;
 694                 } ef10;
 695         } en_arch;
 696 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 697 };
 698
 699
 700 #define EFX_NIC_MAGIC   0x02121996
 701
 702 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 703     const efx_ev_callbacks_t *, void *);
 704
 705 typedef struct efx_evq_rxq_state_s {
 706         unsigned int                    eers_rx_read_ptr;
 707         unsigned int                    eers_rx_mask;
 708 #if EFSYS_OPT_RX_PACKED_STREAM
 709         unsigned int                    eers_rx_stream_npackets;
 710         boolean_t                       eers_rx_packed_stream;
 711         unsigned int                    eers_rx_packed_stream_credits;
 712 #endif
 713 } efx_evq_rxq_state_t;
 714
 715 struct efx_evq_s {
 716         uint32_t                        ee_magic;
 717         efx_nic_t                       *ee_enp;
 718         unsigned int                    ee_index;
 719         unsigned int                    ee_mask;
 720         efsys_mem_t                     *ee_esmp;
 721 #if EFSYS_OPT_QSTATS
 722         uint32_t                        ee_stat[EV_NQSTATS];
 723 #endif  /* EFSYS_OPT_QSTATS */
 724
 725         efx_ev_handler_t                ee_rx;
 726         efx_ev_handler_t                ee_tx;
 727         efx_ev_handler_t                ee_driver;
 728         efx_ev_handler_t                ee_global;
 729         efx_ev_handler_t                ee_drv_gen;
 730 #if EFSYS_OPT_MCDI
 731         efx_ev_handler_t                ee_mcdi;
 732 #endif  /* EFSYS_OPT_MCDI */
 733
 734         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 735
 736         uint32_t                        ee_flags;
 737 };
 738
 739 #define EFX_EVQ_MAGIC   0x08081997
 740
 741 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 742
 743 struct efx_rxq_s {
 744         uint32_t                        er_magic;
 745         efx_nic_t                       *er_enp;
 746         efx_evq_t                       *er_eep;
 747         unsigned int                    er_index;
 748         unsigned int                    er_label;
 749         unsigned int                    er_mask;
 750         efsys_mem_t                     *er_esmp;
 751 };
 752
 753 #define EFX_RXQ_MAGIC   0x15022005
 754
 755 struct efx_txq_s {
 756         uint32_t                        et_magic;
 757         efx_nic_t                       *et_enp;
 758         unsigned int                    et_index;
 759         unsigned int                    et_mask;
 760         efsys_mem_t                     *et_esmp;
 761 #if EFSYS_OPT_HUNTINGTON
 762         uint32_t                        et_pio_bufnum;
 763         uint32_t                        et_pio_blknum;
 764         uint32_t                        et_pio_write_offset;
 765         uint32_t                        et_pio_offset;
 766         size_t                          et_pio_size;
 767 #endif
 768 #if EFSYS_OPT_QSTATS
 769         uint32_t                        et_stat[TX_NQSTATS];
 770 #endif  /* EFSYS_OPT_QSTATS */
 771 };
 772
 773 #define EFX_TXQ_MAGIC   0x05092005
 774
 775 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 776         do {                                                            \
 777                 (_dst)[0] = (_src)[0];                                  \
 778                 (_dst)[1] = (_src)[1];                                  \
 779                 (_dst)[2] = (_src)[2];                                  \
 780                 (_dst)[3] = (_src)[3];                                  \
 781                 (_dst)[4] = (_src)[4];                                  \
 782                 (_dst)[5] = (_src)[5];                                  \
 783         _NOTE(CONSTANTCONDITION)                                        \
 784         } while (B_FALSE)
 785
 786 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 787         do {                                                            \
 788                 uint16_t *_d = (uint16_t *)(_dst);                      \
 789                 _d[0] = 0xffff;                                         \
 790                 _d[1] = 0xffff;                                         \
 791                 _d[2] = 0xffff;                                         \
 792         _NOTE(CONSTANTCONDITION)                                        \
 793         } while (B_FALSE)
 794
 795 #if EFSYS_OPT_CHECK_REG
 796 #define EFX_CHECK_REG(_enp, _reg)                                       \
 797         do {                                                            \
 798                 const char *name = #_reg;                               \
 799                 char min = name[4];                                     \
 800                 char max = name[5];                                     \
 801                 char rev;                                               \
 802                                                                         \
 803                 switch ((_enp)->en_family) {                            \
 804                 case EFX_FAMILY_SIENA:                                  \
 805                         rev = 'C';                                      \
 806                         break;                                          \
 807                                                                         \
 808                 case EFX_FAMILY_HUNTINGTON:                             \
 809                         rev = 'D';                                      \
 810                         break;                                          \
 811                                                                         \
 812                 case EFX_FAMILY_MEDFORD:                                \
 813                         rev = 'E';                                      \
 814                         break;                                          \
 815                                                                         \
 816                 default:                                                \
 817                         rev = '?';                                      \
 818                         break;                                          \
 819                 }                                                       \
 820                                                                         \
 821                 EFSYS_ASSERT3S(rev, >=, min);                           \
 822                 EFSYS_ASSERT3S(rev, <=, max);                           \
 823                                                                         \
 824         _NOTE(CONSTANTCONDITION)                                        \
 825         } while (B_FALSE)
 826 #else
 827 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 828         _NOTE(CONSTANTCONDITION)                                        \
 829         } while (B_FALSE)
 830 #endif
 831
 832 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 833         do {                                                            \
 834                 EFX_CHECK_REG((_enp), (_reg));                          \
 835                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 836                     (_edp), (_lock));                                   \
 837                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 838                     uint32_t, _reg ## _OFST,                            \
 839                     uint32_t, (_edp)->ed_u32[0]);                       \
 840         _NOTE(CONSTANTCONDITION)                                        \
 841         } while (B_FALSE)
 842
 843 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 844         do {                                                            \
 845                 EFX_CHECK_REG((_enp), (_reg));                          \
 846                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 847                     uint32_t, _reg ## _OFST,                            \
 848                     uint32_t, (_edp)->ed_u32[0]);                       \
 849                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 850                     (_edp), (_lock));                                   \
 851         _NOTE(CONSTANTCONDITION)                                        \
 852         } while (B_FALSE)
 853
 854 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 855         do {                                                            \
 856                 EFX_CHECK_REG((_enp), (_reg));                          \
 857                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 858                     (_eqp));                                            \
 859                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 860                     uint32_t, _reg ## _OFST,                            \
 861                     uint32_t, (_eqp)->eq_u32[1],                        \
 862                     uint32_t, (_eqp)->eq_u32[0]);                       \
 863         _NOTE(CONSTANTCONDITION)                                        \
 864         } while (B_FALSE)
 865
 866 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 867         do {                                                            \
 868                 EFX_CHECK_REG((_enp), (_reg));                          \
 869                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 870                     uint32_t, _reg ## _OFST,                            \
 871                     uint32_t, (_eqp)->eq_u32[1],                        \
 872                     uint32_t, (_eqp)->eq_u32[0]);                       \
 873                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 874                     (_eqp));                                            \
 875         _NOTE(CONSTANTCONDITION)                                        \
 876         } while (B_FALSE)
 877
 878 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 879         do {                                                            \
 880                 EFX_CHECK_REG((_enp), (_reg));                          \
 881                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 882                     (_eop), B_TRUE);                                    \
 883                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 884                     uint32_t, _reg ## _OFST,                            \
 885                     uint32_t, (_eop)->eo_u32[3],                        \
 886                     uint32_t, (_eop)->eo_u32[2],                        \
 887                     uint32_t, (_eop)->eo_u32[1],                        \
 888                     uint32_t, (_eop)->eo_u32[0]);                       \
 889         _NOTE(CONSTANTCONDITION)                                        \
 890         } while (B_FALSE)
 891
 892 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 893         do {                                                            \
 894                 EFX_CHECK_REG((_enp), (_reg));                          \
 895                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 896                     uint32_t, _reg ## _OFST,                            \
 897                     uint32_t, (_eop)->eo_u32[3],                        \
 898                     uint32_t, (_eop)->eo_u32[2],                        \
 899                     uint32_t, (_eop)->eo_u32[1],                        \
 900                     uint32_t, (_eop)->eo_u32[0]);                       \
 901                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 902                     (_eop), B_TRUE);                                    \
 903         _NOTE(CONSTANTCONDITION)                                        \
 904         } while (B_FALSE)
 905
 906 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 907         do {                                                            \
 908                 EFX_CHECK_REG((_enp), (_reg));                          \
 909                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 910                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 911                     (_edp), (_lock));                                   \
 912                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 913                     uint32_t, (_index),                                 \
 914                     uint32_t, _reg ## _OFST,                            \
 915                     uint32_t, (_edp)->ed_u32[0]);                       \
 916         _NOTE(CONSTANTCONDITION)                                        \
 917         } while (B_FALSE)
 918
 919 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 920         do {                                                            \
 921                 EFX_CHECK_REG((_enp), (_reg));                          \
 922                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 923                     uint32_t, (_index),                                 \
 924                     uint32_t, _reg ## _OFST,                            \
 925                     uint32_t, (_edp)->ed_u32[0]);                       \
 926                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 927                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 928                     (_edp), (_lock));                                   \
 929         _NOTE(CONSTANTCONDITION)                                        \
 930         } while (B_FALSE)
 931
 932 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 933         do {                                                            \
 934                 EFX_CHECK_REG((_enp), (_reg));                          \
 935                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 936                     uint32_t, (_index),                                 \
 937                     uint32_t, _reg ## _OFST,                            \
 938                     uint32_t, (_edp)->ed_u32[0]);                       \
 939                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 940                     (_reg ## _OFST +                                    \
 941                     (2 * sizeof (efx_dword_t)) +                        \
 942                     ((_index) * _reg ## _STEP)),                        \
 943                     (_edp), (_lock));                                   \
 944         _NOTE(CONSTANTCONDITION)                                        \
 945         } while (B_FALSE)
 946
 947 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 948         do {                                                            \
 949                 EFX_CHECK_REG((_enp), (_reg));                          \
 950                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 951                     uint32_t, (_index),                                 \
 952                     uint32_t, _reg ## _OFST,                            \
 953                     uint32_t, (_edp)->ed_u32[0]);                       \
 954                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 955                     (_reg ## _OFST +                                    \
 956                     (3 * sizeof (efx_dword_t)) +                        \
 957                     ((_index) * _reg ## _STEP)),                        \
 958                     (_edp), (_lock));                                   \
 959         _NOTE(CONSTANTCONDITION)                                        \
 960         } while (B_FALSE)
 961
 962 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 963         do {                                                            \
 964                 EFX_CHECK_REG((_enp), (_reg));                          \
 965                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 966                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 967                     (_eqp));                                            \
 968                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 969                     uint32_t, (_index),                                 \
 970                     uint32_t, _reg ## _OFST,                            \
 971                     uint32_t, (_eqp)->eq_u32[1],                        \
 972                     uint32_t, (_eqp)->eq_u32[0]);                       \
 973         _NOTE(CONSTANTCONDITION)                                        \
 974         } while (B_FALSE)
 975
 976 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 977         do {                                                            \
 978                 EFX_CHECK_REG((_enp), (_reg));                          \
 979                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 980                     uint32_t, (_index),                                 \
 981                     uint32_t, _reg ## _OFST,                            \
 982                     uint32_t, (_eqp)->eq_u32[1],                        \
 983                     uint32_t, (_eqp)->eq_u32[0]);                       \
 984                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 985                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 986                     (_eqp));                                            \
 987         _NOTE(CONSTANTCONDITION)                                        \
 988         } while (B_FALSE)
 989
 990 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 991         do {                                                            \
 992                 EFX_CHECK_REG((_enp), (_reg));                          \
 993                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 994                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 995                     (_eop), (_lock));                                   \
 996                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 997                     uint32_t, (_index),                                 \
 998                     uint32_t, _reg ## _OFST,                            \
 999                     uint32_t, (_eop)->eo_u32[3],                        \
1000                     uint32_t, (_eop)->eo_u32[2],                        \
1001                     uint32_t, (_eop)->eo_u32[1],                        \
1002                     uint32_t, (_eop)->eo_u32[0]);                       \
1003         _NOTE(CONSTANTCONDITION)                                        \
1004         } while (B_FALSE)
1005
1006 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1007         do {                                                            \
1008                 EFX_CHECK_REG((_enp), (_reg));                          \
1009                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1010                     uint32_t, (_index),                                 \
1011                     uint32_t, _reg ## _OFST,                            \
1012                     uint32_t, (_eop)->eo_u32[3],                        \
1013                     uint32_t, (_eop)->eo_u32[2],                        \
1014                     uint32_t, (_eop)->eo_u32[1],                        \
1015                     uint32_t, (_eop)->eo_u32[0]);                       \
1016                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1017                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1018                     (_eop), (_lock));                                   \
1019         _NOTE(CONSTANTCONDITION)                                        \
1020         } while (B_FALSE)
1021
1022 /*
1023  * Allow drivers to perform optimised 128-bit doorbell writes.
1024  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1025  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1026  * the need for locking in the host, and are the only ones known to be safe to
1027  * use 128-bites write with.
1028  */
1029 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1030         do {                                                            \
1031                 EFX_CHECK_REG((_enp), (_reg));                          \
1032                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1033                     const char *,                                       \
1034                     #_reg,                                              \
1035                     uint32_t, (_index),                                 \
1036                     uint32_t, _reg ## _OFST,                            \
1037                     uint32_t, (_eop)->eo_u32[3],                        \
1038                     uint32_t, (_eop)->eo_u32[2],                        \
1039                     uint32_t, (_eop)->eo_u32[1],                        \
1040                     uint32_t, (_eop)->eo_u32[0]);                       \
1041                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1042                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1043                     (_eop));                                            \
1044         _NOTE(CONSTANTCONDITION)                                        \
1045         } while (B_FALSE)
1046
1047 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1048         do {                                                            \
1049                 unsigned int _new = (_wptr);                            \
1050                 unsigned int _old = (_owptr);                           \
1051                                                                         \
1052                 if ((_new) >= (_old))                                   \
1053                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1054                             (_old) * sizeof (efx_desc_t),               \
1055                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1056                 else                                                    \
1057                         /*                                              \
1058                          * It is cheaper to sync entire map than sync   \
1059                          * two parts especially when offset/size are    \
1060                          * ignored and entire map is synced in any case.\
1061                          */                                             \
1062                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1063                             0,                                          \
1064                             (_entries) * sizeof (efx_desc_t));          \
1065         _NOTE(CONSTANTCONDITION)                                        \
1066         } while (B_FALSE)
1067
1068 extern  __checkReturn   efx_rc_t
1069 efx_nic_biu_test(
1070         __in            efx_nic_t *enp);
1071
1072 extern  __checkReturn   efx_rc_t
1073 efx_mac_select(
1074         __in            efx_nic_t *enp);
1075
1076 extern  void
1077 efx_mac_multicast_hash_compute(
1078         __in_ecount(6*count)            uint8_t const *addrs,
1079         __in                            int count,
1080         __out                           efx_oword_t *hash_low,
1081         __out                           efx_oword_t *hash_high);
1082
1083 extern  __checkReturn   efx_rc_t
1084 efx_phy_probe(
1085         __in            efx_nic_t *enp);
1086
1087 extern                  void
1088 efx_phy_unprobe(
1089         __in            efx_nic_t *enp);
1090
1091 #if EFSYS_OPT_VPD
1092
1093 /* VPD utility functions */
1094
1095 extern  __checkReturn           efx_rc_t
1096 efx_vpd_hunk_length(
1097         __in_bcount(size)       caddr_t data,
1098         __in                    size_t size,
1099         __out                   size_t *lengthp);
1100
1101 extern  __checkReturn           efx_rc_t
1102 efx_vpd_hunk_verify(
1103         __in_bcount(size)       caddr_t data,
1104         __in                    size_t size,
1105         __out_opt               boolean_t *cksummedp);
1106
1107 extern  __checkReturn           efx_rc_t
1108 efx_vpd_hunk_reinit(
1109         __in_bcount(size)       caddr_t data,
1110         __in                    size_t size,
1111         __in                    boolean_t wantpid);
1112
1113 extern  __checkReturn           efx_rc_t
1114 efx_vpd_hunk_get(
1115         __in_bcount(size)       caddr_t data,
1116         __in                    size_t size,
1117         __in                    efx_vpd_tag_t tag,
1118         __in                    efx_vpd_keyword_t keyword,
1119         __out                   unsigned int *payloadp,
1120         __out                   uint8_t *paylenp);
1121
1122 extern  __checkReturn                   efx_rc_t
1123 efx_vpd_hunk_next(
1124         __in_bcount(size)               caddr_t data,
1125         __in                            size_t size,
1126         __out                           efx_vpd_tag_t *tagp,
1127         __out                           efx_vpd_keyword_t *keyword,
1128         __out_opt                       unsigned int *payloadp,
1129         __out_opt                       uint8_t *paylenp,
1130         __inout                         unsigned int *contp);
1131
1132 extern  __checkReturn           efx_rc_t
1133 efx_vpd_hunk_set(
1134         __in_bcount(size)       caddr_t data,
1135         __in                    size_t size,
1136         __in                    efx_vpd_value_t *evvp);
1137
1138 #endif  /* EFSYS_OPT_VPD */
1139
1140 #if EFSYS_OPT_DIAG
1141
1142 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1143
1144 typedef struct efx_register_set_s {
1145         unsigned int            address;
1146         unsigned int            step;
1147         unsigned int            rows;
1148         efx_oword_t             mask;
1149 } efx_register_set_t;
1150
1151 extern  __checkReturn   efx_rc_t
1152 efx_nic_test_registers(
1153         __in            efx_nic_t *enp,
1154         __in            efx_register_set_t *rsp,
1155         __in            size_t count);
1156
1157 extern  __checkReturn   efx_rc_t
1158 efx_nic_test_tables(
1159         __in            efx_nic_t *enp,
1160         __in            efx_register_set_t *rsp,
1161         __in            efx_pattern_type_t pattern,
1162         __in            size_t count);
1163
1164 #endif  /* EFSYS_OPT_DIAG */
1165
1166 #if EFSYS_OPT_MCDI
1167
1168 extern  __checkReturn           efx_rc_t
1169 efx_mcdi_set_workaround(
1170         __in                    efx_nic_t *enp,
1171         __in                    uint32_t type,
1172         __in                    boolean_t enabled,
1173         __out_opt               uint32_t *flagsp);
1174
1175 extern  __checkReturn           efx_rc_t
1176 efx_mcdi_get_workarounds(
1177         __in                    efx_nic_t *enp,
1178         __out_opt               uint32_t *implementedp,
1179         __out_opt               uint32_t *enabledp);
1180
1181 #endif /* EFSYS_OPT_MCDI */
1182
1183 #if EFSYS_OPT_MAC_STATS
1184
1185 /*
1186  * Closed range of stats (i.e. the first and the last are included).
1187  * The last must be greater or equal (if the range is one item only) to
1188  * the first.
1189  */
1190 struct efx_mac_stats_range {
1191         efx_mac_stat_t          first;
1192         efx_mac_stat_t          last;
1193 };
1194
1195 extern                                  efx_rc_t
1196 efx_mac_stats_mask_add_ranges(
1197         __inout_bcount(mask_size)       uint32_t *maskp,
1198         __in                            size_t mask_size,
1199         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1200         __in                            unsigned int rng_count);
1201
1202 #endif  /* EFSYS_OPT_MAC_STATS */
1203
1204 #ifdef  __cplusplus
1205 }
1206 #endif
1207
1208 #endif  /* _SYS_EFX_IMPL_H */