drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13
  14 /* FIXME: Add definition for driver generated software events */
  15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  17 #endif
  18
  19
  20 #if EFSYS_OPT_SIENA
  21 #include "siena_impl.h"
  22 #endif  /* EFSYS_OPT_SIENA */
  23
  24 #if EFSYS_OPT_HUNTINGTON
  25 #include "hunt_impl.h"
  26 #endif  /* EFSYS_OPT_HUNTINGTON */
  27
  28 #if EFSYS_OPT_MEDFORD
  29 #include "medford_impl.h"
  30 #endif  /* EFSYS_OPT_MEDFORD */
  31
  32 #if EFSYS_OPT_MEDFORD2
  33 #include "medford2_impl.h"
  34 #endif  /* EFSYS_OPT_MEDFORD2 */
  35
  36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
  37 #include "ef10_impl.h"
  38 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
  39
  40 #ifdef  __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 #define EFX_MOD_MCDI            0x00000001
  45 #define EFX_MOD_PROBE           0x00000002
  46 #define EFX_MOD_NVRAM           0x00000004
  47 #define EFX_MOD_VPD             0x00000008
  48 #define EFX_MOD_NIC             0x00000010
  49 #define EFX_MOD_INTR            0x00000020
  50 #define EFX_MOD_EV              0x00000040
  51 #define EFX_MOD_RX              0x00000080
  52 #define EFX_MOD_TX              0x00000100
  53 #define EFX_MOD_PORT            0x00000200
  54 #define EFX_MOD_MON             0x00000400
  55 #define EFX_MOD_FILTER          0x00001000
  56 #define EFX_MOD_LIC             0x00002000
  57 #define EFX_MOD_TUNNEL          0x00004000
  58
  59 #define EFX_RESET_PHY           0x00000001
  60 #define EFX_RESET_RXQ_ERR       0x00000002
  61 #define EFX_RESET_TXQ_ERR       0x00000004
  62
  63 typedef enum efx_mac_type_e {
  64         EFX_MAC_INVALID = 0,
  65         EFX_MAC_SIENA,
  66         EFX_MAC_HUNTINGTON,
  67         EFX_MAC_MEDFORD,
  68         EFX_MAC_MEDFORD2,
  69         EFX_MAC_NTYPES
  70 } efx_mac_type_t;
  71
  72 typedef struct efx_ev_ops_s {
  73         efx_rc_t        (*eevo_init)(efx_nic_t *);
  74         void            (*eevo_fini)(efx_nic_t *);
  75         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  76                                           efsys_mem_t *, size_t, uint32_t,
  77                                           uint32_t, uint32_t, efx_evq_t *);
  78         void            (*eevo_qdestroy)(efx_evq_t *);
  79         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  80         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  81         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  82 #if EFSYS_OPT_QSTATS
  83         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  84 #endif
  85 } efx_ev_ops_t;
  86
  87 typedef struct efx_tx_ops_s {
  88         efx_rc_t        (*etxo_init)(efx_nic_t *);
  89         void            (*etxo_fini)(efx_nic_t *);
  90         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  91                                         unsigned int, unsigned int,
  92                                         efsys_mem_t *, size_t,
  93                                         uint32_t, uint16_t,
  94                                         efx_evq_t *, efx_txq_t *,
  95                                         unsigned int *);
  96         void            (*etxo_qdestroy)(efx_txq_t *);
  97         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
  98                                       unsigned int, unsigned int,
  99                                       unsigned int *);
 100         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 101         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 102         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 103         void            (*etxo_qenable)(efx_txq_t *);
 104         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 105         void            (*etxo_qpio_disable)(efx_txq_t *);
 106         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 107                                            size_t);
 108         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 109                                            unsigned int *);
 110         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 111                                       unsigned int, unsigned int,
 112                                       unsigned int *);
 113         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 114                                                 size_t, boolean_t,
 115                                                 efx_desc_t *);
 116         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 117                                                 uint32_t, uint8_t,
 118                                                 efx_desc_t *);
 119         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 120                                                 uint16_t, uint32_t, uint16_t,
 121                                                 efx_desc_t *, int);
 122         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 123                                                 efx_desc_t *);
 124         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 125                                                 efx_desc_t *);
 126 #if EFSYS_OPT_QSTATS
 127         void            (*etxo_qstats_update)(efx_txq_t *,
 128                                               efsys_stat_t *);
 129 #endif
 130 } efx_tx_ops_t;
 131
 132 typedef union efx_rxq_type_data_u {
 133         /* Dummy member to have non-empty union if no options are enabled */
 134         uint32_t        ertd_dummy;
 135 #if EFSYS_OPT_RX_PACKED_STREAM
 136         struct {
 137                 uint32_t        eps_buf_size;
 138         } ertd_packed_stream;
 139 #endif
 140 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 141         struct {
 142                 uint32_t        eessb_bufs_per_desc;
 143                 uint32_t        eessb_max_dma_len;
 144                 uint32_t        eessb_buf_stride;
 145                 uint32_t        eessb_hol_block_timeout;
 146         } ertd_es_super_buffer;
 147 #endif
 148 } efx_rxq_type_data_t;
 149
 150 typedef struct efx_rx_ops_s {
 151         efx_rc_t        (*erxo_init)(efx_nic_t *);
 152         void            (*erxo_fini)(efx_nic_t *);
 153 #if EFSYS_OPT_RX_SCATTER
 154         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 155 #endif
 156 #if EFSYS_OPT_RX_SCALE
 157         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 158                                                     efx_rx_scale_context_type_t,
 159                                                     uint32_t, uint32_t *);
 160         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 161         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 162                                                efx_rx_hash_alg_t,
 163                                                efx_rx_hash_type_t, boolean_t);
 164         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 165                                               uint8_t *, size_t);
 166         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 167                                               unsigned int *, size_t);
 168         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 169                                             uint8_t *);
 170 #endif /* EFSYS_OPT_RX_SCALE */
 171         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 172                                               uint16_t *);
 173         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 174                                       unsigned int, unsigned int,
 175                                       unsigned int);
 176         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 177 #if EFSYS_OPT_RX_PACKED_STREAM
 178         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 179         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 180                                                 uint32_t, uint32_t,
 181                                                 uint16_t *, uint32_t *, uint32_t *);
 182 #endif
 183         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 184         void            (*erxo_qenable)(efx_rxq_t *);
 185         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 186                                         unsigned int, efx_rxq_type_t,
 187                                         const efx_rxq_type_data_t *,
 188                                         efsys_mem_t *, size_t, uint32_t,
 189                                         unsigned int,
 190                                         efx_evq_t *, efx_rxq_t *);
 191         void            (*erxo_qdestroy)(efx_rxq_t *);
 192 } efx_rx_ops_t;
 193
 194 typedef struct efx_mac_ops_s {
 195         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 196         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 197         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 198         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 199         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 200         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 201         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 202         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 203                                                       efx_rxq_t *, boolean_t);
 204         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 205 #if EFSYS_OPT_LOOPBACK
 206         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 207                                             efx_loopback_type_t);
 208 #endif  /* EFSYS_OPT_LOOPBACK */
 209 #if EFSYS_OPT_MAC_STATS
 210         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 211         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 212         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 213         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 214                                               uint16_t, boolean_t);
 215         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 216                                             efsys_stat_t *, uint32_t *);
 217 #endif  /* EFSYS_OPT_MAC_STATS */
 218 } efx_mac_ops_t;
 219
 220 typedef struct efx_phy_ops_s {
 221         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 222         efx_rc_t        (*epo_reset)(efx_nic_t *);
 223         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 224         efx_rc_t        (*epo_verify)(efx_nic_t *);
 225         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 226 #if EFSYS_OPT_PHY_STATS
 227         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 228                                             uint32_t *);
 229 #endif  /* EFSYS_OPT_PHY_STATS */
 230 #if EFSYS_OPT_BIST
 231         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 232         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 233         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 234                                          efx_bist_result_t *, uint32_t *,
 235                                          unsigned long *, size_t);
 236         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 237 #endif  /* EFSYS_OPT_BIST */
 238 } efx_phy_ops_t;
 239
 240 #if EFSYS_OPT_FILTER
 241 typedef struct efx_filter_ops_s {
 242         efx_rc_t        (*efo_init)(efx_nic_t *);
 243         void            (*efo_fini)(efx_nic_t *);
 244         efx_rc_t        (*efo_restore)(efx_nic_t *);
 245         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 246                                    boolean_t may_replace);
 247         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 248         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 249                                    size_t, size_t *);
 250         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 251                                    boolean_t, boolean_t, boolean_t,
 252                                    uint8_t const *, uint32_t);
 253 } efx_filter_ops_t;
 254
 255 extern  __checkReturn   efx_rc_t
 256 efx_filter_reconfigure(
 257         __in                            efx_nic_t *enp,
 258         __in_ecount(6)                  uint8_t const *mac_addr,
 259         __in                            boolean_t all_unicst,
 260         __in                            boolean_t mulcst,
 261         __in                            boolean_t all_mulcst,
 262         __in                            boolean_t brdcst,
 263         __in_ecount(6*count)            uint8_t const *addrs,
 264         __in                            uint32_t count);
 265
 266 #endif /* EFSYS_OPT_FILTER */
 267
 268 #if EFSYS_OPT_TUNNEL
 269 typedef struct efx_tunnel_ops_s {
 270         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 271         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 272 } efx_tunnel_ops_t;
 273 #endif /* EFSYS_OPT_TUNNEL */
 274
 275 typedef struct efx_port_s {
 276         efx_mac_type_t          ep_mac_type;
 277         uint32_t                ep_phy_type;
 278         uint8_t                 ep_port;
 279         uint32_t                ep_mac_pdu;
 280         uint8_t                 ep_mac_addr[6];
 281         efx_link_mode_t         ep_link_mode;
 282         boolean_t               ep_all_unicst;
 283         boolean_t               ep_mulcst;
 284         boolean_t               ep_all_mulcst;
 285         boolean_t               ep_brdcst;
 286         unsigned int            ep_fcntl;
 287         boolean_t               ep_fcntl_autoneg;
 288         efx_oword_t             ep_multicst_hash[2];
 289         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 290                                                     EFX_MAC_MULTICAST_LIST_MAX];
 291         uint32_t                ep_mulcst_addr_count;
 292 #if EFSYS_OPT_LOOPBACK
 293         efx_loopback_type_t     ep_loopback_type;
 294         efx_link_mode_t         ep_loopback_link_mode;
 295 #endif  /* EFSYS_OPT_LOOPBACK */
 296 #if EFSYS_OPT_PHY_FLAGS
 297         uint32_t                ep_phy_flags;
 298 #endif  /* EFSYS_OPT_PHY_FLAGS */
 299 #if EFSYS_OPT_PHY_LED_CONTROL
 300         efx_phy_led_mode_t      ep_phy_led_mode;
 301 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 302         efx_phy_media_type_t    ep_fixed_port_type;
 303         efx_phy_media_type_t    ep_module_type;
 304         uint32_t                ep_adv_cap_mask;
 305         uint32_t                ep_lp_cap_mask;
 306         uint32_t                ep_default_adv_cap_mask;
 307         uint32_t                ep_phy_cap_mask;
 308         boolean_t               ep_mac_drain;
 309 #if EFSYS_OPT_BIST
 310         efx_bist_type_t         ep_current_bist;
 311 #endif
 312         const efx_mac_ops_t     *ep_emop;
 313         const efx_phy_ops_t     *ep_epop;
 314 } efx_port_t;
 315
 316 typedef struct efx_mon_ops_s {
 317 #if EFSYS_OPT_MON_STATS
 318         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 319                                             efx_mon_stat_value_t *);
 320 #endif  /* EFSYS_OPT_MON_STATS */
 321 } efx_mon_ops_t;
 322
 323 typedef struct efx_mon_s {
 324         efx_mon_type_t          em_type;
 325         const efx_mon_ops_t     *em_emop;
 326 } efx_mon_t;
 327
 328 typedef struct efx_intr_ops_s {
 329         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 330         void            (*eio_enable)(efx_nic_t *);
 331         void            (*eio_disable)(efx_nic_t *);
 332         void            (*eio_disable_unlocked)(efx_nic_t *);
 333         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 334         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 335         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 336                                  boolean_t *);
 337         void            (*eio_fatal)(efx_nic_t *);
 338         void            (*eio_fini)(efx_nic_t *);
 339 } efx_intr_ops_t;
 340
 341 typedef struct efx_intr_s {
 342         const efx_intr_ops_t    *ei_eiop;
 343         efsys_mem_t             *ei_esmp;
 344         efx_intr_type_t         ei_type;
 345         unsigned int            ei_level;
 346 } efx_intr_t;
 347
 348 typedef struct efx_nic_ops_s {
 349         efx_rc_t        (*eno_probe)(efx_nic_t *);
 350         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 351         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 352         efx_rc_t        (*eno_reset)(efx_nic_t *);
 353         efx_rc_t        (*eno_init)(efx_nic_t *);
 354         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 355         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 356                                         uint32_t *, size_t *);
 357 #if EFSYS_OPT_DIAG
 358         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 359 #endif  /* EFSYS_OPT_DIAG */
 360         void            (*eno_fini)(efx_nic_t *);
 361         void            (*eno_unprobe)(efx_nic_t *);
 362 } efx_nic_ops_t;
 363
 364 #ifndef EFX_TXQ_LIMIT_TARGET
 365 #define EFX_TXQ_LIMIT_TARGET 259
 366 #endif
 367 #ifndef EFX_RXQ_LIMIT_TARGET
 368 #define EFX_RXQ_LIMIT_TARGET 512
 369 #endif
 370
 371
 372 #if EFSYS_OPT_FILTER
 373
 374 #if EFSYS_OPT_SIENA
 375
 376 typedef struct siena_filter_spec_s {
 377         uint8_t         sfs_type;
 378         uint32_t        sfs_flags;
 379         uint32_t        sfs_dmaq_id;
 380         uint32_t        sfs_dword[3];
 381 } siena_filter_spec_t;
 382
 383 typedef enum siena_filter_type_e {
 384         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 385         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 386         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 387         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 388         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 389         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 390
 391         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 392         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 393         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 394         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 395         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 396         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 397
 398         EFX_SIENA_FILTER_NTYPES
 399 } siena_filter_type_t;
 400
 401 typedef enum siena_filter_tbl_id_e {
 402         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 403         EFX_SIENA_FILTER_TBL_RX_MAC,
 404         EFX_SIENA_FILTER_TBL_TX_IP,
 405         EFX_SIENA_FILTER_TBL_TX_MAC,
 406         EFX_SIENA_FILTER_NTBLS
 407 } siena_filter_tbl_id_t;
 408
 409 typedef struct siena_filter_tbl_s {
 410         int                     sft_size;       /* number of entries */
 411         int                     sft_used;       /* active count */
 412         uint32_t                *sft_bitmap;    /* active bitmap */
 413         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 414 } siena_filter_tbl_t;
 415
 416 typedef struct siena_filter_s {
 417         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 418         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 419 } siena_filter_t;
 420
 421 #endif  /* EFSYS_OPT_SIENA */
 422
 423 typedef struct efx_filter_s {
 424 #if EFSYS_OPT_SIENA
 425         siena_filter_t          *ef_siena_filter;
 426 #endif /* EFSYS_OPT_SIENA */
 427 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 428         ef10_filter_table_t     *ef_ef10_filter_table;
 429 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 430 } efx_filter_t;
 431
 432 #if EFSYS_OPT_SIENA
 433
 434 extern                  void
 435 siena_filter_tbl_clear(
 436         __in            efx_nic_t *enp,
 437         __in            siena_filter_tbl_id_t tbl);
 438
 439 #endif  /* EFSYS_OPT_SIENA */
 440
 441 #endif  /* EFSYS_OPT_FILTER */
 442
 443 #if EFSYS_OPT_MCDI
 444
 445 #define EFX_TUNNEL_MAXNENTRIES  (16)
 446
 447 #if EFSYS_OPT_TUNNEL
 448
 449 typedef struct efx_tunnel_udp_entry_s {
 450         uint16_t                        etue_port; /* host/cpu-endian */
 451         uint16_t                        etue_protocol;
 452 } efx_tunnel_udp_entry_t;
 453
 454 typedef struct efx_tunnel_cfg_s {
 455         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 456         unsigned int            etc_udp_entries_num;
 457 } efx_tunnel_cfg_t;
 458
 459 #endif /* EFSYS_OPT_TUNNEL */
 460
 461 typedef struct efx_mcdi_ops_s {
 462         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 463         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 464                                         void *, size_t);
 465         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 466         boolean_t       (*emco_poll_response)(efx_nic_t *);
 467         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 468         void            (*emco_fini)(efx_nic_t *);
 469         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 470                                             efx_mcdi_feature_id_t, boolean_t *);
 471         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 472                                             uint32_t *);
 473 } efx_mcdi_ops_t;
 474
 475 typedef struct efx_mcdi_s {
 476         const efx_mcdi_ops_t            *em_emcop;
 477         const efx_mcdi_transport_t      *em_emtp;
 478         efx_mcdi_iface_t                em_emip;
 479 } efx_mcdi_t;
 480
 481 #endif /* EFSYS_OPT_MCDI */
 482
 483 #if EFSYS_OPT_NVRAM
 484
 485 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 486 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 487
 488 typedef struct efx_nvram_ops_s {
 489 #if EFSYS_OPT_DIAG
 490         efx_rc_t        (*envo_test)(efx_nic_t *);
 491 #endif  /* EFSYS_OPT_DIAG */
 492         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 493                                             uint32_t *);
 494         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 495         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 496         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 497                                             unsigned int, caddr_t, size_t);
 498         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 499                                             unsigned int, caddr_t, size_t);
 500         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 501                                             unsigned int, size_t);
 502         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 503                                             unsigned int, caddr_t, size_t);
 504         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 505                                             uint32_t *);
 506         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 507                                             uint32_t *, uint16_t *);
 508         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 509                                             uint16_t *);
 510         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 511                                             caddr_t, size_t);
 512 } efx_nvram_ops_t;
 513 #endif /* EFSYS_OPT_NVRAM */
 514
 515 #if EFSYS_OPT_VPD
 516 typedef struct efx_vpd_ops_s {
 517         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 518         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 519         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 520         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 521         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 522         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 523                                         efx_vpd_value_t *);
 524         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 525                                         efx_vpd_value_t *);
 526         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 527                                         efx_vpd_value_t *, unsigned int *);
 528         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 529         void            (*evpdo_fini)(efx_nic_t *);
 530 } efx_vpd_ops_t;
 531 #endif  /* EFSYS_OPT_VPD */
 532
 533 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 534
 535         __checkReturn           efx_rc_t
 536 efx_mcdi_nvram_partitions(
 537         __in                    efx_nic_t *enp,
 538         __out_bcount(size)      caddr_t data,
 539         __in                    size_t size,
 540         __out                   unsigned int *npartnp);
 541
 542         __checkReturn           efx_rc_t
 543 efx_mcdi_nvram_metadata(
 544         __in                    efx_nic_t *enp,
 545         __in                    uint32_t partn,
 546         __out                   uint32_t *subtypep,
 547         __out_ecount(4)         uint16_t version[4],
 548         __out_bcount_opt(size)  char *descp,
 549         __in                    size_t size);
 550
 551         __checkReturn           efx_rc_t
 552 efx_mcdi_nvram_info(
 553         __in                    efx_nic_t *enp,
 554         __in                    uint32_t partn,
 555         __out_opt               size_t *sizep,
 556         __out_opt               uint32_t *addressp,
 557         __out_opt               uint32_t *erase_sizep,
 558         __out_opt               uint32_t *write_sizep);
 559
 560         __checkReturn           efx_rc_t
 561 efx_mcdi_nvram_update_start(
 562         __in                    efx_nic_t *enp,
 563         __in                    uint32_t partn);
 564
 565         __checkReturn           efx_rc_t
 566 efx_mcdi_nvram_read(
 567         __in                    efx_nic_t *enp,
 568         __in                    uint32_t partn,
 569         __in                    uint32_t offset,
 570         __out_bcount(size)      caddr_t data,
 571         __in                    size_t size,
 572         __in                    uint32_t mode);
 573
 574         __checkReturn           efx_rc_t
 575 efx_mcdi_nvram_erase(
 576         __in                    efx_nic_t *enp,
 577         __in                    uint32_t partn,
 578         __in                    uint32_t offset,
 579         __in                    size_t size);
 580
 581         __checkReturn           efx_rc_t
 582 efx_mcdi_nvram_write(
 583         __in                    efx_nic_t *enp,
 584         __in                    uint32_t partn,
 585         __in                    uint32_t offset,
 586         __out_bcount(size)      caddr_t data,
 587         __in                    size_t size);
 588
 589         __checkReturn           efx_rc_t
 590 efx_mcdi_nvram_update_finish(
 591         __in                    efx_nic_t *enp,
 592         __in                    uint32_t partn,
 593         __in                    boolean_t reboot,
 594         __out_opt               uint32_t *verify_resultp);
 595
 596 #if EFSYS_OPT_DIAG
 597
 598         __checkReturn           efx_rc_t
 599 efx_mcdi_nvram_test(
 600         __in                    efx_nic_t *enp,
 601         __in                    uint32_t partn);
 602
 603 #endif  /* EFSYS_OPT_DIAG */
 604
 605 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 606
 607 #if EFSYS_OPT_LICENSING
 608
 609 typedef struct efx_lic_ops_s {
 610         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 611         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 612         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 613         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 614                                       size_t *, uint8_t *);
 615         efx_rc_t        (*elo_find_start)
 616                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 617         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 618                                 uint32_t, uint32_t *);
 619         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 620                                 uint32_t, uint32_t *, uint32_t *);
 621         boolean_t       (*elo_validate_key)(efx_nic_t *,
 622                                 caddr_t, uint32_t);
 623         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 624                                 caddr_t, size_t, uint32_t, uint32_t,
 625                                 caddr_t, size_t, uint32_t *);
 626         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 627                                 caddr_t, size_t, uint32_t,
 628                                 caddr_t, uint32_t, uint32_t *);
 629         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 630                                 caddr_t, size_t, uint32_t,
 631                                 uint32_t, uint32_t, uint32_t *);
 632         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 633                                 caddr_t, size_t);
 634         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 635                                 caddr_t, size_t);
 636 } efx_lic_ops_t;
 637
 638 #endif
 639
 640 typedef struct efx_drv_cfg_s {
 641         uint32_t                edc_min_vi_count;
 642         uint32_t                edc_max_vi_count;
 643
 644         uint32_t                edc_max_piobuf_count;
 645         uint32_t                edc_pio_alloc_size;
 646 } efx_drv_cfg_t;
 647
 648 struct efx_nic_s {
 649         uint32_t                en_magic;
 650         efx_family_t            en_family;
 651         uint32_t                en_features;
 652         efsys_identifier_t      *en_esip;
 653         efsys_lock_t            *en_eslp;
 654         efsys_bar_t             *en_esbp;
 655         unsigned int            en_mod_flags;
 656         unsigned int            en_reset_flags;
 657         efx_nic_cfg_t           en_nic_cfg;
 658         efx_drv_cfg_t           en_drv_cfg;
 659         efx_port_t              en_port;
 660         efx_mon_t               en_mon;
 661         efx_intr_t              en_intr;
 662         uint32_t                en_ev_qcount;
 663         uint32_t                en_rx_qcount;
 664         uint32_t                en_tx_qcount;
 665         const efx_nic_ops_t     *en_enop;
 666         const efx_ev_ops_t      *en_eevop;
 667         const efx_tx_ops_t      *en_etxop;
 668         const efx_rx_ops_t      *en_erxop;
 669         efx_fw_variant_t        efv;
 670 #if EFSYS_OPT_FILTER
 671         efx_filter_t            en_filter;
 672         const efx_filter_ops_t  *en_efop;
 673 #endif  /* EFSYS_OPT_FILTER */
 674 #if EFSYS_OPT_TUNNEL
 675         efx_tunnel_cfg_t        en_tunnel_cfg;
 676         const efx_tunnel_ops_t  *en_etop;
 677 #endif /* EFSYS_OPT_TUNNEL */
 678 #if EFSYS_OPT_MCDI
 679         efx_mcdi_t              en_mcdi;
 680 #endif  /* EFSYS_OPT_MCDI */
 681 #if EFSYS_OPT_NVRAM
 682         uint32_t                en_nvram_partn_locked;
 683         const efx_nvram_ops_t   *en_envop;
 684 #endif  /* EFSYS_OPT_NVRAM */
 685 #if EFSYS_OPT_VPD
 686         const efx_vpd_ops_t     *en_evpdop;
 687 #endif  /* EFSYS_OPT_VPD */
 688 #if EFSYS_OPT_RX_SCALE
 689         efx_rx_hash_support_t           en_hash_support;
 690         efx_rx_scale_context_type_t     en_rss_context_type;
 691         uint32_t                        en_rss_context;
 692 #endif  /* EFSYS_OPT_RX_SCALE */
 693         uint32_t                en_vport_id;
 694 #if EFSYS_OPT_LICENSING
 695         const efx_lic_ops_t     *en_elop;
 696         boolean_t               en_licensing_supported;
 697 #endif
 698         union {
 699 #if EFSYS_OPT_SIENA
 700                 struct {
 701 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 702                         unsigned int            enu_partn_mask;
 703 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 704 #if EFSYS_OPT_VPD
 705                         caddr_t                 enu_svpd;
 706                         size_t                  enu_svpd_length;
 707 #endif  /* EFSYS_OPT_VPD */
 708                         int                     enu_unused;
 709                 } siena;
 710 #endif  /* EFSYS_OPT_SIENA */
 711                 int     enu_unused;
 712         } en_u;
 713 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
 714         union en_arch {
 715                 struct {
 716                         int                     ena_vi_base;
 717                         int                     ena_vi_count;
 718                         int                     ena_vi_shift;
 719 #if EFSYS_OPT_VPD
 720                         caddr_t                 ena_svpd;
 721                         size_t                  ena_svpd_length;
 722 #endif  /* EFSYS_OPT_VPD */
 723                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 724                         uint32_t                ena_piobuf_count;
 725                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 726                         uint32_t                ena_pio_write_vi_base;
 727                         /* Memory BAR mapping regions */
 728                         uint32_t                ena_uc_mem_map_offset;
 729                         size_t                  ena_uc_mem_map_size;
 730                         uint32_t                ena_wc_mem_map_offset;
 731                         size_t                  ena_wc_mem_map_size;
 732                 } ef10;
 733         } en_arch;
 734 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
 735 };
 736
 737
 738 #define EFX_NIC_MAGIC   0x02121996
 739
 740 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 741     const efx_ev_callbacks_t *, void *);
 742
 743 typedef struct efx_evq_rxq_state_s {
 744         unsigned int                    eers_rx_read_ptr;
 745         unsigned int                    eers_rx_mask;
 746 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 747         unsigned int                    eers_rx_stream_npackets;
 748         boolean_t                       eers_rx_packed_stream;
 749 #endif
 750 #if EFSYS_OPT_RX_PACKED_STREAM
 751         unsigned int                    eers_rx_packed_stream_credits;
 752 #endif
 753 } efx_evq_rxq_state_t;
 754
 755 struct efx_evq_s {
 756         uint32_t                        ee_magic;
 757         efx_nic_t                       *ee_enp;
 758         unsigned int                    ee_index;
 759         unsigned int                    ee_mask;
 760         efsys_mem_t                     *ee_esmp;
 761 #if EFSYS_OPT_QSTATS
 762         uint32_t                        ee_stat[EV_NQSTATS];
 763 #endif  /* EFSYS_OPT_QSTATS */
 764
 765         efx_ev_handler_t                ee_rx;
 766         efx_ev_handler_t                ee_tx;
 767         efx_ev_handler_t                ee_driver;
 768         efx_ev_handler_t                ee_global;
 769         efx_ev_handler_t                ee_drv_gen;
 770 #if EFSYS_OPT_MCDI
 771         efx_ev_handler_t                ee_mcdi;
 772 #endif  /* EFSYS_OPT_MCDI */
 773
 774         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 775
 776         uint32_t                        ee_flags;
 777 };
 778
 779 #define EFX_EVQ_MAGIC   0x08081997
 780
 781 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 782
 783 struct efx_rxq_s {
 784         uint32_t                        er_magic;
 785         efx_nic_t                       *er_enp;
 786         efx_evq_t                       *er_eep;
 787         unsigned int                    er_index;
 788         unsigned int                    er_label;
 789         unsigned int                    er_mask;
 790         efsys_mem_t                     *er_esmp;
 791         efx_evq_rxq_state_t             *er_ev_qstate;
 792 };
 793
 794 #define EFX_RXQ_MAGIC   0x15022005
 795
 796 struct efx_txq_s {
 797         uint32_t                        et_magic;
 798         efx_nic_t                       *et_enp;
 799         unsigned int                    et_index;
 800         unsigned int                    et_mask;
 801         efsys_mem_t                     *et_esmp;
 802 #if EFSYS_OPT_HUNTINGTON
 803         uint32_t                        et_pio_bufnum;
 804         uint32_t                        et_pio_blknum;
 805         uint32_t                        et_pio_write_offset;
 806         uint32_t                        et_pio_offset;
 807         size_t                          et_pio_size;
 808 #endif
 809 #if EFSYS_OPT_QSTATS
 810         uint32_t                        et_stat[TX_NQSTATS];
 811 #endif  /* EFSYS_OPT_QSTATS */
 812 };
 813
 814 #define EFX_TXQ_MAGIC   0x05092005
 815
 816 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 817         do {                                                            \
 818                 (_dst)[0] = (_src)[0];                                  \
 819                 (_dst)[1] = (_src)[1];                                  \
 820                 (_dst)[2] = (_src)[2];                                  \
 821                 (_dst)[3] = (_src)[3];                                  \
 822                 (_dst)[4] = (_src)[4];                                  \
 823                 (_dst)[5] = (_src)[5];                                  \
 824         _NOTE(CONSTANTCONDITION)                                        \
 825         } while (B_FALSE)
 826
 827 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 828         do {                                                            \
 829                 uint16_t *_d = (uint16_t *)(_dst);                      \
 830                 _d[0] = 0xffff;                                         \
 831                 _d[1] = 0xffff;                                         \
 832                 _d[2] = 0xffff;                                         \
 833         _NOTE(CONSTANTCONDITION)                                        \
 834         } while (B_FALSE)
 835
 836 #if EFSYS_OPT_CHECK_REG
 837 #define EFX_CHECK_REG(_enp, _reg)                                       \
 838         do {                                                            \
 839                 const char *name = #_reg;                               \
 840                 char min = name[4];                                     \
 841                 char max = name[5];                                     \
 842                 char rev;                                               \
 843                                                                         \
 844                 switch ((_enp)->en_family) {                            \
 845                 case EFX_FAMILY_SIENA:                                  \
 846                         rev = 'C';                                      \
 847                         break;                                          \
 848                                                                         \
 849                 case EFX_FAMILY_HUNTINGTON:                             \
 850                         rev = 'D';                                      \
 851                         break;                                          \
 852                                                                         \
 853                 case EFX_FAMILY_MEDFORD:                                \
 854                         rev = 'E';                                      \
 855                         break;                                          \
 856                                                                         \
 857                 case EFX_FAMILY_MEDFORD2:                               \
 858                         rev = 'F';                                      \
 859                         break;                                          \
 860                                                                         \
 861                 default:                                                \
 862                         rev = '?';                                      \
 863                         break;                                          \
 864                 }                                                       \
 865                                                                         \
 866                 EFSYS_ASSERT3S(rev, >=, min);                           \
 867                 EFSYS_ASSERT3S(rev, <=, max);                           \
 868                                                                         \
 869         _NOTE(CONSTANTCONDITION)                                        \
 870         } while (B_FALSE)
 871 #else
 872 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 873         _NOTE(CONSTANTCONDITION)                                        \
 874         } while (B_FALSE)
 875 #endif
 876
 877 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 878         do {                                                            \
 879                 EFX_CHECK_REG((_enp), (_reg));                          \
 880                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 881                     (_edp), (_lock));                                   \
 882                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 883                     uint32_t, _reg ## _OFST,                            \
 884                     uint32_t, (_edp)->ed_u32[0]);                       \
 885         _NOTE(CONSTANTCONDITION)                                        \
 886         } while (B_FALSE)
 887
 888 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 889         do {                                                            \
 890                 EFX_CHECK_REG((_enp), (_reg));                          \
 891                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 892                     uint32_t, _reg ## _OFST,                            \
 893                     uint32_t, (_edp)->ed_u32[0]);                       \
 894                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 895                     (_edp), (_lock));                                   \
 896         _NOTE(CONSTANTCONDITION)                                        \
 897         } while (B_FALSE)
 898
 899 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 900         do {                                                            \
 901                 EFX_CHECK_REG((_enp), (_reg));                          \
 902                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 903                     (_eqp));                                            \
 904                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 905                     uint32_t, _reg ## _OFST,                            \
 906                     uint32_t, (_eqp)->eq_u32[1],                        \
 907                     uint32_t, (_eqp)->eq_u32[0]);                       \
 908         _NOTE(CONSTANTCONDITION)                                        \
 909         } while (B_FALSE)
 910
 911 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 912         do {                                                            \
 913                 EFX_CHECK_REG((_enp), (_reg));                          \
 914                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 915                     uint32_t, _reg ## _OFST,                            \
 916                     uint32_t, (_eqp)->eq_u32[1],                        \
 917                     uint32_t, (_eqp)->eq_u32[0]);                       \
 918                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 919                     (_eqp));                                            \
 920         _NOTE(CONSTANTCONDITION)                                        \
 921         } while (B_FALSE)
 922
 923 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 924         do {                                                            \
 925                 EFX_CHECK_REG((_enp), (_reg));                          \
 926                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 927                     (_eop), B_TRUE);                                    \
 928                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 929                     uint32_t, _reg ## _OFST,                            \
 930                     uint32_t, (_eop)->eo_u32[3],                        \
 931                     uint32_t, (_eop)->eo_u32[2],                        \
 932                     uint32_t, (_eop)->eo_u32[1],                        \
 933                     uint32_t, (_eop)->eo_u32[0]);                       \
 934         _NOTE(CONSTANTCONDITION)                                        \
 935         } while (B_FALSE)
 936
 937 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 938         do {                                                            \
 939                 EFX_CHECK_REG((_enp), (_reg));                          \
 940                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 941                     uint32_t, _reg ## _OFST,                            \
 942                     uint32_t, (_eop)->eo_u32[3],                        \
 943                     uint32_t, (_eop)->eo_u32[2],                        \
 944                     uint32_t, (_eop)->eo_u32[1],                        \
 945                     uint32_t, (_eop)->eo_u32[0]);                       \
 946                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 947                     (_eop), B_TRUE);                                    \
 948         _NOTE(CONSTANTCONDITION)                                        \
 949         } while (B_FALSE)
 950
 951 /*
 952  * Accessors for memory BAR non-VI tables.
 953  *
 954  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
 955  * to ensure the correct runtime VI window size is used on Medford2.
 956  *
 957  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
 958  */
 959
 960 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 961         do {                                                            \
 962                 EFX_CHECK_REG((_enp), (_reg));                          \
 963                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 964                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 965                     (_edp), (_lock));                                   \
 966                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 967                     uint32_t, (_index),                                 \
 968                     uint32_t, _reg ## _OFST,                            \
 969                     uint32_t, (_edp)->ed_u32[0]);                       \
 970         _NOTE(CONSTANTCONDITION)                                        \
 971         } while (B_FALSE)
 972
 973 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 974         do {                                                            \
 975                 EFX_CHECK_REG((_enp), (_reg));                          \
 976                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 977                     uint32_t, (_index),                                 \
 978                     uint32_t, _reg ## _OFST,                            \
 979                     uint32_t, (_edp)->ed_u32[0]);                       \
 980                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 981                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 982                     (_edp), (_lock));                                   \
 983         _NOTE(CONSTANTCONDITION)                                        \
 984         } while (B_FALSE)
 985
 986 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 987         do {                                                            \
 988                 EFX_CHECK_REG((_enp), (_reg));                          \
 989                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 990                     uint32_t, (_index),                                 \
 991                     uint32_t, _reg ## _OFST,                            \
 992                     uint32_t, (_edp)->ed_u32[0]);                       \
 993                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 994                     (_reg ## _OFST +                                    \
 995                     (3 * sizeof (efx_dword_t)) +                        \
 996                     ((_index) * _reg ## _STEP)),                        \
 997                     (_edp), (_lock));                                   \
 998         _NOTE(CONSTANTCONDITION)                                        \
 999         } while (B_FALSE)
1000
1001 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1002         do {                                                            \
1003                 EFX_CHECK_REG((_enp), (_reg));                          \
1004                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1005                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1006                     (_eqp));                                            \
1007                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1008                     uint32_t, (_index),                                 \
1009                     uint32_t, _reg ## _OFST,                            \
1010                     uint32_t, (_eqp)->eq_u32[1],                        \
1011                     uint32_t, (_eqp)->eq_u32[0]);                       \
1012         _NOTE(CONSTANTCONDITION)                                        \
1013         } while (B_FALSE)
1014
1015 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1016         do {                                                            \
1017                 EFX_CHECK_REG((_enp), (_reg));                          \
1018                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1019                     uint32_t, (_index),                                 \
1020                     uint32_t, _reg ## _OFST,                            \
1021                     uint32_t, (_eqp)->eq_u32[1],                        \
1022                     uint32_t, (_eqp)->eq_u32[0]);                       \
1023                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1024                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1025                     (_eqp));                                            \
1026         _NOTE(CONSTANTCONDITION)                                        \
1027         } while (B_FALSE)
1028
1029 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1030         do {                                                            \
1031                 EFX_CHECK_REG((_enp), (_reg));                          \
1032                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1033                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1034                     (_eop), (_lock));                                   \
1035                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1036                     uint32_t, (_index),                                 \
1037                     uint32_t, _reg ## _OFST,                            \
1038                     uint32_t, (_eop)->eo_u32[3],                        \
1039                     uint32_t, (_eop)->eo_u32[2],                        \
1040                     uint32_t, (_eop)->eo_u32[1],                        \
1041                     uint32_t, (_eop)->eo_u32[0]);                       \
1042         _NOTE(CONSTANTCONDITION)                                        \
1043         } while (B_FALSE)
1044
1045 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1046         do {                                                            \
1047                 EFX_CHECK_REG((_enp), (_reg));                          \
1048                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1049                     uint32_t, (_index),                                 \
1050                     uint32_t, _reg ## _OFST,                            \
1051                     uint32_t, (_eop)->eo_u32[3],                        \
1052                     uint32_t, (_eop)->eo_u32[2],                        \
1053                     uint32_t, (_eop)->eo_u32[1],                        \
1054                     uint32_t, (_eop)->eo_u32[0]);                       \
1055                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1056                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1057                     (_eop), (_lock));                                   \
1058         _NOTE(CONSTANTCONDITION)                                        \
1059         } while (B_FALSE)
1060
1061 /*
1062  * Accessors for memory BAR per-VI registers.
1063  *
1064  * The VI window size is 8KB for Medford and all earlier controllers.
1065  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1066  */
1067
1068 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1069         do {                                                            \
1070                 EFX_CHECK_REG((_enp), (_reg));                          \
1071                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1072                     ((_reg ## _OFST) +                                  \
1073                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1074                     (_edp), (_lock));                                   \
1075                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1076                     uint32_t, (_index),                                 \
1077                     uint32_t, _reg ## _OFST,                            \
1078                     uint32_t, (_edp)->ed_u32[0]);                       \
1079         _NOTE(CONSTANTCONDITION)                                        \
1080         } while (B_FALSE)
1081
1082 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1083         do {                                                            \
1084                 EFX_CHECK_REG((_enp), (_reg));                          \
1085                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1086                     uint32_t, (_index),                                 \
1087                     uint32_t, _reg ## _OFST,                            \
1088                     uint32_t, (_edp)->ed_u32[0]);                       \
1089                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1090                     ((_reg ## _OFST) +                                  \
1091                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1092                     (_edp), (_lock));                                   \
1093         _NOTE(CONSTANTCONDITION)                                        \
1094         } while (B_FALSE)
1095
1096 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1097         do {                                                            \
1098                 EFX_CHECK_REG((_enp), (_reg));                          \
1099                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1100                     uint32_t, (_index),                                 \
1101                     uint32_t, _reg ## _OFST,                            \
1102                     uint32_t, (_edp)->ed_u32[0]);                       \
1103                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1104                     ((_reg ## _OFST) +                                  \
1105                     (2 * sizeof (efx_dword_t)) +                        \
1106                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1107                     (_edp), (_lock));                                   \
1108         _NOTE(CONSTANTCONDITION)                                        \
1109         } while (B_FALSE)
1110
1111 /*
1112  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1113  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1114  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1115  * the need for locking in the host, and are the only ones known to be safe to
1116  * use 128-bites write with.
1117  */
1118 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1119         do {                                                            \
1120                 EFX_CHECK_REG((_enp), (_reg));                          \
1121                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1122                     const char *, #_reg,                                \
1123                     uint32_t, (_index),                                 \
1124                     uint32_t, _reg ## _OFST,                            \
1125                     uint32_t, (_eop)->eo_u32[3],                        \
1126                     uint32_t, (_eop)->eo_u32[2],                        \
1127                     uint32_t, (_eop)->eo_u32[1],                        \
1128                     uint32_t, (_eop)->eo_u32[0]);                       \
1129                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1130                     (_reg ## _OFST +                                    \
1131                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1132                     (_eop));                                            \
1133         _NOTE(CONSTANTCONDITION)                                        \
1134         } while (B_FALSE)
1135
1136 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1137         do {                                                            \
1138                 unsigned int _new = (_wptr);                            \
1139                 unsigned int _old = (_owptr);                           \
1140                                                                         \
1141                 if ((_new) >= (_old))                                   \
1142                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1143                             (_old) * sizeof (efx_desc_t),               \
1144                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1145                 else                                                    \
1146                         /*                                              \
1147                          * It is cheaper to sync entire map than sync   \
1148                          * two parts especially when offset/size are    \
1149                          * ignored and entire map is synced in any case.\
1150                          */                                             \
1151                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1152                             0,                                          \
1153                             (_entries) * sizeof (efx_desc_t));          \
1154         _NOTE(CONSTANTCONDITION)                                        \
1155         } while (B_FALSE)
1156
1157 extern  __checkReturn   efx_rc_t
1158 efx_mac_select(
1159         __in            efx_nic_t *enp);
1160
1161 extern  void
1162 efx_mac_multicast_hash_compute(
1163         __in_ecount(6*count)            uint8_t const *addrs,
1164         __in                            int count,
1165         __out                           efx_oword_t *hash_low,
1166         __out                           efx_oword_t *hash_high);
1167
1168 extern  __checkReturn   efx_rc_t
1169 efx_phy_probe(
1170         __in            efx_nic_t *enp);
1171
1172 extern                  void
1173 efx_phy_unprobe(
1174         __in            efx_nic_t *enp);
1175
1176 #if EFSYS_OPT_VPD
1177
1178 /* VPD utility functions */
1179
1180 extern  __checkReturn           efx_rc_t
1181 efx_vpd_hunk_length(
1182         __in_bcount(size)       caddr_t data,
1183         __in                    size_t size,
1184         __out                   size_t *lengthp);
1185
1186 extern  __checkReturn           efx_rc_t
1187 efx_vpd_hunk_verify(
1188         __in_bcount(size)       caddr_t data,
1189         __in                    size_t size,
1190         __out_opt               boolean_t *cksummedp);
1191
1192 extern  __checkReturn           efx_rc_t
1193 efx_vpd_hunk_reinit(
1194         __in_bcount(size)       caddr_t data,
1195         __in                    size_t size,
1196         __in                    boolean_t wantpid);
1197
1198 extern  __checkReturn           efx_rc_t
1199 efx_vpd_hunk_get(
1200         __in_bcount(size)       caddr_t data,
1201         __in                    size_t size,
1202         __in                    efx_vpd_tag_t tag,
1203         __in                    efx_vpd_keyword_t keyword,
1204         __out                   unsigned int *payloadp,
1205         __out                   uint8_t *paylenp);
1206
1207 extern  __checkReturn                   efx_rc_t
1208 efx_vpd_hunk_next(
1209         __in_bcount(size)               caddr_t data,
1210         __in                            size_t size,
1211         __out                           efx_vpd_tag_t *tagp,
1212         __out                           efx_vpd_keyword_t *keyword,
1213         __out_opt                       unsigned int *payloadp,
1214         __out_opt                       uint8_t *paylenp,
1215         __inout                         unsigned int *contp);
1216
1217 extern  __checkReturn           efx_rc_t
1218 efx_vpd_hunk_set(
1219         __in_bcount(size)       caddr_t data,
1220         __in                    size_t size,
1221         __in                    efx_vpd_value_t *evvp);
1222
1223 #endif  /* EFSYS_OPT_VPD */
1224
1225 #if EFSYS_OPT_MCDI
1226
1227 extern  __checkReturn           efx_rc_t
1228 efx_mcdi_set_workaround(
1229         __in                    efx_nic_t *enp,
1230         __in                    uint32_t type,
1231         __in                    boolean_t enabled,
1232         __out_opt               uint32_t *flagsp);
1233
1234 extern  __checkReturn           efx_rc_t
1235 efx_mcdi_get_workarounds(
1236         __in                    efx_nic_t *enp,
1237         __out_opt               uint32_t *implementedp,
1238         __out_opt               uint32_t *enabledp);
1239
1240 #endif /* EFSYS_OPT_MCDI */
1241
1242 #if EFSYS_OPT_MAC_STATS
1243
1244 /*
1245  * Closed range of stats (i.e. the first and the last are included).
1246  * The last must be greater or equal (if the range is one item only) to
1247  * the first.
1248  */
1249 struct efx_mac_stats_range {
1250         efx_mac_stat_t          first;
1251         efx_mac_stat_t          last;
1252 };
1253
1254 extern                                  efx_rc_t
1255 efx_mac_stats_mask_add_ranges(
1256         __inout_bcount(mask_size)       uint32_t *maskp,
1257         __in                            size_t mask_size,
1258         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1259         __in                            unsigned int rng_count);
1260
1261 #endif  /* EFSYS_OPT_MAC_STATS */
1262
1263 #ifdef  __cplusplus
1264 }
1265 #endif
1266
1267 #endif  /* _SYS_EFX_IMPL_H */