drivers/net/sfc/base/efx_impl.h

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #ifndef _SYS_EFX_IMPL_H
  32 #define _SYS_EFX_IMPL_H
  33
  34 #include "efx.h"
  35 #include "efx_regs.h"
  36 #include "efx_regs_ef10.h"
  37
  38 /* FIXME: Add definition for driver generated software events */
  39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  41 #endif
  42
  43
  44 #if EFSYS_OPT_SIENA
  45 #include "siena_impl.h"
  46 #endif  /* EFSYS_OPT_SIENA */
  47
  48 #if EFSYS_OPT_HUNTINGTON
  49 #include "hunt_impl.h"
  50 #endif  /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53 #include "medford_impl.h"
  54 #endif  /* EFSYS_OPT_MEDFORD */
  55
  56 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  57 #include "ef10_impl.h"
  58 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  59
  60 #ifdef  __cplusplus
  61 extern "C" {
  62 #endif
  63
  64 #define EFX_MOD_MCDI            0x00000001
  65 #define EFX_MOD_PROBE           0x00000002
  66 #define EFX_MOD_NVRAM           0x00000004
  67 #define EFX_MOD_VPD             0x00000008
  68 #define EFX_MOD_NIC             0x00000010
  69 #define EFX_MOD_INTR            0x00000020
  70 #define EFX_MOD_EV              0x00000040
  71 #define EFX_MOD_RX              0x00000080
  72 #define EFX_MOD_TX              0x00000100
  73 #define EFX_MOD_PORT            0x00000200
  74 #define EFX_MOD_MON             0x00000400
  75 #define EFX_MOD_FILTER          0x00001000
  76 #define EFX_MOD_LIC             0x00002000
  77
  78 #define EFX_RESET_PHY           0x00000001
  79 #define EFX_RESET_RXQ_ERR       0x00000002
  80 #define EFX_RESET_TXQ_ERR       0x00000004
  81
  82 typedef enum efx_mac_type_e {
  83         EFX_MAC_INVALID = 0,
  84         EFX_MAC_SIENA,
  85         EFX_MAC_HUNTINGTON,
  86         EFX_MAC_MEDFORD,
  87         EFX_MAC_NTYPES
  88 } efx_mac_type_t;
  89
  90 typedef struct efx_ev_ops_s {
  91         efx_rc_t        (*eevo_init)(efx_nic_t *);
  92         void            (*eevo_fini)(efx_nic_t *);
  93         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  94                                           efsys_mem_t *, size_t, uint32_t,
  95                                           uint32_t, uint32_t, efx_evq_t *);
  96         void            (*eevo_qdestroy)(efx_evq_t *);
  97         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  98         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  99         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 100 #if EFSYS_OPT_QSTATS
 101         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 102 #endif
 103 } efx_ev_ops_t;
 104
 105 typedef struct efx_tx_ops_s {
 106         efx_rc_t        (*etxo_init)(efx_nic_t *);
 107         void            (*etxo_fini)(efx_nic_t *);
 108         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 109                                         unsigned int, unsigned int,
 110                                         efsys_mem_t *, size_t,
 111                                         uint32_t, uint16_t,
 112                                         efx_evq_t *, efx_txq_t *,
 113                                         unsigned int *);
 114         void            (*etxo_qdestroy)(efx_txq_t *);
 115         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 116                                       unsigned int, unsigned int,
 117                                       unsigned int *);
 118         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 119         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 120         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 121         void            (*etxo_qenable)(efx_txq_t *);
 122         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 123         void            (*etxo_qpio_disable)(efx_txq_t *);
 124         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 125                                            size_t);
 126         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 127                                            unsigned int *);
 128         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 129                                       unsigned int, unsigned int,
 130                                       unsigned int *);
 131         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 132                                                 size_t, boolean_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 135                                                 uint32_t, uint8_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint16_t,
 139                                                 efx_desc_t *, int);
 140         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 141                                                 efx_desc_t *);
 142 #if EFSYS_OPT_QSTATS
 143         void            (*etxo_qstats_update)(efx_txq_t *,
 144                                               efsys_stat_t *);
 145 #endif
 146 } efx_tx_ops_t;
 147
 148 typedef struct efx_rx_ops_s {
 149         efx_rc_t        (*erxo_init)(efx_nic_t *);
 150         void            (*erxo_fini)(efx_nic_t *);
 151 #if EFSYS_OPT_RX_SCATTER
 152         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 153 #endif
 154 #if EFSYS_OPT_RX_SCALE
 155         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 156                                                     efx_rx_scale_context_type_t,
 157                                                     uint32_t, uint32_t *);
 158         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 159         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 160                                                efx_rx_hash_alg_t,
 161                                                efx_rx_hash_type_t, boolean_t);
 162         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 163                                               uint8_t *, size_t);
 164         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 165                                               unsigned int *, size_t);
 166         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 167                                             uint8_t *);
 168 #endif /* EFSYS_OPT_RX_SCALE */
 169         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 170                                               uint16_t *);
 171         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 172                                       unsigned int, unsigned int,
 173                                       unsigned int);
 174         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 175 #if EFSYS_OPT_RX_PACKED_STREAM
 176         void            (*erxo_qps_update_credits)(efx_rxq_t *);
 177         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 178                                                 uint32_t, uint32_t,
 179                                                 uint16_t *, uint32_t *, uint32_t *);
 180 #endif
 181         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 182         void            (*erxo_qenable)(efx_rxq_t *);
 183         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 184                                         unsigned int, efx_rxq_type_t,
 185                                         efsys_mem_t *, size_t, uint32_t,
 186                                         efx_evq_t *, efx_rxq_t *);
 187         void            (*erxo_qdestroy)(efx_rxq_t *);
 188 } efx_rx_ops_t;
 189
 190 typedef struct efx_mac_ops_s {
 191         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 192         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 193         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 194         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 195         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 196         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 197         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 198         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 199                                                       efx_rxq_t *, boolean_t);
 200         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 201 #if EFSYS_OPT_LOOPBACK
 202         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 203                                             efx_loopback_type_t);
 204 #endif  /* EFSYS_OPT_LOOPBACK */
 205 #if EFSYS_OPT_MAC_STATS
 206         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 207         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 208         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 209         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 210                                               uint16_t, boolean_t);
 211         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 212                                             efsys_stat_t *, uint32_t *);
 213 #endif  /* EFSYS_OPT_MAC_STATS */
 214 } efx_mac_ops_t;
 215
 216 typedef struct efx_phy_ops_s {
 217         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 218         efx_rc_t        (*epo_reset)(efx_nic_t *);
 219         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 220         efx_rc_t        (*epo_verify)(efx_nic_t *);
 221         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 222 #if EFSYS_OPT_PHY_STATS
 223         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 224                                             uint32_t *);
 225 #endif  /* EFSYS_OPT_PHY_STATS */
 226 #if EFSYS_OPT_BIST
 227         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 228         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 229         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 230                                          efx_bist_result_t *, uint32_t *,
 231                                          unsigned long *, size_t);
 232         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 233 #endif  /* EFSYS_OPT_BIST */
 234 } efx_phy_ops_t;
 235
 236 #if EFSYS_OPT_FILTER
 237 typedef struct efx_filter_ops_s {
 238         efx_rc_t        (*efo_init)(efx_nic_t *);
 239         void            (*efo_fini)(efx_nic_t *);
 240         efx_rc_t        (*efo_restore)(efx_nic_t *);
 241         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 242                                    boolean_t may_replace);
 243         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 244         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 245                                    size_t, size_t *);
 246         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 247                                    boolean_t, boolean_t, boolean_t,
 248                                    uint8_t const *, uint32_t);
 249 } efx_filter_ops_t;
 250
 251 extern  __checkReturn   efx_rc_t
 252 efx_filter_reconfigure(
 253         __in                            efx_nic_t *enp,
 254         __in_ecount(6)                  uint8_t const *mac_addr,
 255         __in                            boolean_t all_unicst,
 256         __in                            boolean_t mulcst,
 257         __in                            boolean_t all_mulcst,
 258         __in                            boolean_t brdcst,
 259         __in_ecount(6*count)            uint8_t const *addrs,
 260         __in                            uint32_t count);
 261
 262 #endif /* EFSYS_OPT_FILTER */
 263
 264
 265 typedef struct efx_port_s {
 266         efx_mac_type_t          ep_mac_type;
 267         uint32_t                ep_phy_type;
 268         uint8_t                 ep_port;
 269         uint32_t                ep_mac_pdu;
 270         uint8_t                 ep_mac_addr[6];
 271         efx_link_mode_t         ep_link_mode;
 272         boolean_t               ep_all_unicst;
 273         boolean_t               ep_mulcst;
 274         boolean_t               ep_all_mulcst;
 275         boolean_t               ep_brdcst;
 276         unsigned int            ep_fcntl;
 277         boolean_t               ep_fcntl_autoneg;
 278         efx_oword_t             ep_multicst_hash[2];
 279         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 280                                                     EFX_MAC_MULTICAST_LIST_MAX];
 281         uint32_t                ep_mulcst_addr_count;
 282 #if EFSYS_OPT_LOOPBACK
 283         efx_loopback_type_t     ep_loopback_type;
 284         efx_link_mode_t         ep_loopback_link_mode;
 285 #endif  /* EFSYS_OPT_LOOPBACK */
 286 #if EFSYS_OPT_PHY_FLAGS
 287         uint32_t                ep_phy_flags;
 288 #endif  /* EFSYS_OPT_PHY_FLAGS */
 289 #if EFSYS_OPT_PHY_LED_CONTROL
 290         efx_phy_led_mode_t      ep_phy_led_mode;
 291 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 292         efx_phy_media_type_t    ep_fixed_port_type;
 293         efx_phy_media_type_t    ep_module_type;
 294         uint32_t                ep_adv_cap_mask;
 295         uint32_t                ep_lp_cap_mask;
 296         uint32_t                ep_default_adv_cap_mask;
 297         uint32_t                ep_phy_cap_mask;
 298         boolean_t               ep_mac_drain;
 299 #if EFSYS_OPT_BIST
 300         efx_bist_type_t         ep_current_bist;
 301 #endif
 302         const efx_mac_ops_t     *ep_emop;
 303         const efx_phy_ops_t     *ep_epop;
 304 } efx_port_t;
 305
 306 typedef struct efx_mon_ops_s {
 307 #if EFSYS_OPT_MON_STATS
 308         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 309                                             efx_mon_stat_value_t *);
 310 #endif  /* EFSYS_OPT_MON_STATS */
 311 } efx_mon_ops_t;
 312
 313 typedef struct efx_mon_s {
 314         efx_mon_type_t          em_type;
 315         const efx_mon_ops_t     *em_emop;
 316 } efx_mon_t;
 317
 318 typedef struct efx_intr_ops_s {
 319         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 320         void            (*eio_enable)(efx_nic_t *);
 321         void            (*eio_disable)(efx_nic_t *);
 322         void            (*eio_disable_unlocked)(efx_nic_t *);
 323         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 324         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 325         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 326                                  boolean_t *);
 327         void            (*eio_fatal)(efx_nic_t *);
 328         void            (*eio_fini)(efx_nic_t *);
 329 } efx_intr_ops_t;
 330
 331 typedef struct efx_intr_s {
 332         const efx_intr_ops_t    *ei_eiop;
 333         efsys_mem_t             *ei_esmp;
 334         efx_intr_type_t         ei_type;
 335         unsigned int            ei_level;
 336 } efx_intr_t;
 337
 338 typedef struct efx_nic_ops_s {
 339         efx_rc_t        (*eno_probe)(efx_nic_t *);
 340         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 341         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 342         efx_rc_t        (*eno_reset)(efx_nic_t *);
 343         efx_rc_t        (*eno_init)(efx_nic_t *);
 344         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 345         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 346                                         uint32_t *, size_t *);
 347 #if EFSYS_OPT_DIAG
 348         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 349 #endif  /* EFSYS_OPT_DIAG */
 350         void            (*eno_fini)(efx_nic_t *);
 351         void            (*eno_unprobe)(efx_nic_t *);
 352 } efx_nic_ops_t;
 353
 354 #ifndef EFX_TXQ_LIMIT_TARGET
 355 #define EFX_TXQ_LIMIT_TARGET 259
 356 #endif
 357 #ifndef EFX_RXQ_LIMIT_TARGET
 358 #define EFX_RXQ_LIMIT_TARGET 512
 359 #endif
 360 #ifndef EFX_TXQ_DC_SIZE
 361 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 362 #endif
 363 #ifndef EFX_RXQ_DC_SIZE
 364 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 365 #endif
 366
 367 #if EFSYS_OPT_FILTER
 368
 369 #if EFSYS_OPT_SIENA
 370
 371 typedef struct siena_filter_spec_s {
 372         uint8_t         sfs_type;
 373         uint32_t        sfs_flags;
 374         uint32_t        sfs_dmaq_id;
 375         uint32_t        sfs_dword[3];
 376 } siena_filter_spec_t;
 377
 378 typedef enum siena_filter_type_e {
 379         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 380         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 381         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 382         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 383         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 384         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 385
 386         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 387         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 388         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 389         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 390         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 391         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 392
 393         EFX_SIENA_FILTER_NTYPES
 394 } siena_filter_type_t;
 395
 396 typedef enum siena_filter_tbl_id_e {
 397         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 398         EFX_SIENA_FILTER_TBL_RX_MAC,
 399         EFX_SIENA_FILTER_TBL_TX_IP,
 400         EFX_SIENA_FILTER_TBL_TX_MAC,
 401         EFX_SIENA_FILTER_NTBLS
 402 } siena_filter_tbl_id_t;
 403
 404 typedef struct siena_filter_tbl_s {
 405         int                     sft_size;       /* number of entries */
 406         int                     sft_used;       /* active count */
 407         uint32_t                *sft_bitmap;    /* active bitmap */
 408         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 409 } siena_filter_tbl_t;
 410
 411 typedef struct siena_filter_s {
 412         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 413         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 414 } siena_filter_t;
 415
 416 #endif  /* EFSYS_OPT_SIENA */
 417
 418 typedef struct efx_filter_s {
 419 #if EFSYS_OPT_SIENA
 420         siena_filter_t          *ef_siena_filter;
 421 #endif /* EFSYS_OPT_SIENA */
 422 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 423         ef10_filter_table_t     *ef_ef10_filter_table;
 424 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 425 } efx_filter_t;
 426
 427 #if EFSYS_OPT_SIENA
 428
 429 extern                  void
 430 siena_filter_tbl_clear(
 431         __in            efx_nic_t *enp,
 432         __in            siena_filter_tbl_id_t tbl);
 433
 434 #endif  /* EFSYS_OPT_SIENA */
 435
 436 #endif  /* EFSYS_OPT_FILTER */
 437
 438 #if EFSYS_OPT_MCDI
 439
 440 typedef struct efx_mcdi_ops_s {
 441         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 442         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 443                                         void *, size_t);
 444         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 445         boolean_t       (*emco_poll_response)(efx_nic_t *);
 446         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 447         void            (*emco_fini)(efx_nic_t *);
 448         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 449                                             efx_mcdi_feature_id_t, boolean_t *);
 450         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 451                                             uint32_t *);
 452 } efx_mcdi_ops_t;
 453
 454 typedef struct efx_mcdi_s {
 455         const efx_mcdi_ops_t            *em_emcop;
 456         const efx_mcdi_transport_t      *em_emtp;
 457         efx_mcdi_iface_t                em_emip;
 458 } efx_mcdi_t;
 459
 460 #endif /* EFSYS_OPT_MCDI */
 461
 462 #if EFSYS_OPT_NVRAM
 463 typedef struct efx_nvram_ops_s {
 464 #if EFSYS_OPT_DIAG
 465         efx_rc_t        (*envo_test)(efx_nic_t *);
 466 #endif  /* EFSYS_OPT_DIAG */
 467         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 468                                             uint32_t *);
 469         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 470         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 471         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 472                                             unsigned int, caddr_t, size_t);
 473         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 474                                             unsigned int, size_t);
 475         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 476                                             unsigned int, caddr_t, size_t);
 477         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 478         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 479                                             uint32_t *, uint16_t *);
 480         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 481                                             uint16_t *);
 482         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 483                                             caddr_t, size_t);
 484 } efx_nvram_ops_t;
 485 #endif /* EFSYS_OPT_NVRAM */
 486
 487 #if EFSYS_OPT_VPD
 488 typedef struct efx_vpd_ops_s {
 489         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 490         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 491         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 492         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 493         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 494         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 495                                         efx_vpd_value_t *);
 496         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 497                                         efx_vpd_value_t *);
 498         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 499                                         efx_vpd_value_t *, unsigned int *);
 500         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 501         void            (*evpdo_fini)(efx_nic_t *);
 502 } efx_vpd_ops_t;
 503 #endif  /* EFSYS_OPT_VPD */
 504
 505 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 506
 507         __checkReturn           efx_rc_t
 508 efx_mcdi_nvram_partitions(
 509         __in                    efx_nic_t *enp,
 510         __out_bcount(size)      caddr_t data,
 511         __in                    size_t size,
 512         __out                   unsigned int *npartnp);
 513
 514         __checkReturn           efx_rc_t
 515 efx_mcdi_nvram_metadata(
 516         __in                    efx_nic_t *enp,
 517         __in                    uint32_t partn,
 518         __out                   uint32_t *subtypep,
 519         __out_ecount(4)         uint16_t version[4],
 520         __out_bcount_opt(size)  char *descp,
 521         __in                    size_t size);
 522
 523         __checkReturn           efx_rc_t
 524 efx_mcdi_nvram_info(
 525         __in                    efx_nic_t *enp,
 526         __in                    uint32_t partn,
 527         __out_opt               size_t *sizep,
 528         __out_opt               uint32_t *addressp,
 529         __out_opt               uint32_t *erase_sizep,
 530         __out_opt               uint32_t *write_sizep);
 531
 532         __checkReturn           efx_rc_t
 533 efx_mcdi_nvram_update_start(
 534         __in                    efx_nic_t *enp,
 535         __in                    uint32_t partn);
 536
 537         __checkReturn           efx_rc_t
 538 efx_mcdi_nvram_read(
 539         __in                    efx_nic_t *enp,
 540         __in                    uint32_t partn,
 541         __in                    uint32_t offset,
 542         __out_bcount(size)      caddr_t data,
 543         __in                    size_t size,
 544         __in                    uint32_t mode);
 545
 546         __checkReturn           efx_rc_t
 547 efx_mcdi_nvram_erase(
 548         __in                    efx_nic_t *enp,
 549         __in                    uint32_t partn,
 550         __in                    uint32_t offset,
 551         __in                    size_t size);
 552
 553         __checkReturn           efx_rc_t
 554 efx_mcdi_nvram_write(
 555         __in                    efx_nic_t *enp,
 556         __in                    uint32_t partn,
 557         __in                    uint32_t offset,
 558         __in_bcount(size)       caddr_t data,
 559         __in                    size_t size);
 560
 561         __checkReturn           efx_rc_t
 562 efx_mcdi_nvram_update_finish(
 563         __in                    efx_nic_t *enp,
 564         __in                    uint32_t partn,
 565         __in                    boolean_t reboot,
 566         __out_opt               uint32_t *resultp);
 567
 568 #if EFSYS_OPT_DIAG
 569
 570         __checkReturn           efx_rc_t
 571 efx_mcdi_nvram_test(
 572         __in                    efx_nic_t *enp,
 573         __in                    uint32_t partn);
 574
 575 #endif  /* EFSYS_OPT_DIAG */
 576
 577 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 578
 579 #if EFSYS_OPT_LICENSING
 580
 581 typedef struct efx_lic_ops_s {
 582         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 583         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 584         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 585         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 586                                       size_t *, uint8_t *);
 587         efx_rc_t        (*elo_find_start)
 588                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 589         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 590                                 uint32_t, uint32_t *);
 591         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 592                                 uint32_t, uint32_t *, uint32_t *);
 593         boolean_t       (*elo_validate_key)(efx_nic_t *,
 594                                 caddr_t, uint32_t);
 595         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 596                                 caddr_t, size_t, uint32_t, uint32_t,
 597                                 caddr_t, size_t, uint32_t *);
 598         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 599                                 caddr_t, size_t, uint32_t,
 600                                 caddr_t, uint32_t, uint32_t *);
 601         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 602                                 caddr_t, size_t, uint32_t,
 603                                 uint32_t, uint32_t, uint32_t *);
 604         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 605                                 caddr_t, size_t);
 606         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 607                                 caddr_t, size_t);
 608 } efx_lic_ops_t;
 609
 610 #endif
 611
 612 typedef struct efx_drv_cfg_s {
 613         uint32_t                edc_min_vi_count;
 614         uint32_t                edc_max_vi_count;
 615
 616         uint32_t                edc_max_piobuf_count;
 617         uint32_t                edc_pio_alloc_size;
 618 } efx_drv_cfg_t;
 619
 620 struct efx_nic_s {
 621         uint32_t                en_magic;
 622         efx_family_t            en_family;
 623         uint32_t                en_features;
 624         efsys_identifier_t      *en_esip;
 625         efsys_lock_t            *en_eslp;
 626         efsys_bar_t             *en_esbp;
 627         unsigned int            en_mod_flags;
 628         unsigned int            en_reset_flags;
 629         efx_nic_cfg_t           en_nic_cfg;
 630         efx_drv_cfg_t           en_drv_cfg;
 631         efx_port_t              en_port;
 632         efx_mon_t               en_mon;
 633         efx_intr_t              en_intr;
 634         uint32_t                en_ev_qcount;
 635         uint32_t                en_rx_qcount;
 636         uint32_t                en_tx_qcount;
 637         const efx_nic_ops_t     *en_enop;
 638         const efx_ev_ops_t      *en_eevop;
 639         const efx_tx_ops_t      *en_etxop;
 640         const efx_rx_ops_t      *en_erxop;
 641 #if EFSYS_OPT_FILTER
 642         efx_filter_t            en_filter;
 643         const efx_filter_ops_t  *en_efop;
 644 #endif  /* EFSYS_OPT_FILTER */
 645 #if EFSYS_OPT_MCDI
 646         efx_mcdi_t              en_mcdi;
 647 #endif  /* EFSYS_OPT_MCDI */
 648 #if EFSYS_OPT_NVRAM
 649         efx_nvram_type_t        en_nvram_locked;
 650         const efx_nvram_ops_t   *en_envop;
 651 #endif  /* EFSYS_OPT_NVRAM */
 652 #if EFSYS_OPT_VPD
 653         const efx_vpd_ops_t     *en_evpdop;
 654 #endif  /* EFSYS_OPT_VPD */
 655 #if EFSYS_OPT_RX_SCALE
 656         efx_rx_hash_support_t           en_hash_support;
 657         efx_rx_scale_context_type_t     en_rss_context_type;
 658         uint32_t                        en_rss_context;
 659 #endif  /* EFSYS_OPT_RX_SCALE */
 660         uint32_t                en_vport_id;
 661 #if EFSYS_OPT_LICENSING
 662         const efx_lic_ops_t     *en_elop;
 663         boolean_t               en_licensing_supported;
 664 #endif
 665         union {
 666 #if EFSYS_OPT_SIENA
 667                 struct {
 668 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 669                         unsigned int            enu_partn_mask;
 670 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 671 #if EFSYS_OPT_VPD
 672                         caddr_t                 enu_svpd;
 673                         size_t                  enu_svpd_length;
 674 #endif  /* EFSYS_OPT_VPD */
 675                         int                     enu_unused;
 676                 } siena;
 677 #endif  /* EFSYS_OPT_SIENA */
 678                 int     enu_unused;
 679         } en_u;
 680 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 681         union en_arch {
 682                 struct {
 683                         int                     ena_vi_base;
 684                         int                     ena_vi_count;
 685                         int                     ena_vi_shift;
 686 #if EFSYS_OPT_VPD
 687                         caddr_t                 ena_svpd;
 688                         size_t                  ena_svpd_length;
 689 #endif  /* EFSYS_OPT_VPD */
 690                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 691                         uint32_t                ena_piobuf_count;
 692                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 693                         uint32_t                ena_pio_write_vi_base;
 694                         /* Memory BAR mapping regions */
 695                         uint32_t                ena_uc_mem_map_offset;
 696                         size_t                  ena_uc_mem_map_size;
 697                         uint32_t                ena_wc_mem_map_offset;
 698                         size_t                  ena_wc_mem_map_size;
 699                 } ef10;
 700         } en_arch;
 701 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 702 };
 703
 704
 705 #define EFX_NIC_MAGIC   0x02121996
 706
 707 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 708     const efx_ev_callbacks_t *, void *);
 709
 710 typedef struct efx_evq_rxq_state_s {
 711         unsigned int                    eers_rx_read_ptr;
 712         unsigned int                    eers_rx_mask;
 713 #if EFSYS_OPT_RX_PACKED_STREAM
 714         unsigned int                    eers_rx_stream_npackets;
 715         boolean_t                       eers_rx_packed_stream;
 716         unsigned int                    eers_rx_packed_stream_credits;
 717 #endif
 718 } efx_evq_rxq_state_t;
 719
 720 struct efx_evq_s {
 721         uint32_t                        ee_magic;
 722         efx_nic_t                       *ee_enp;
 723         unsigned int                    ee_index;
 724         unsigned int                    ee_mask;
 725         efsys_mem_t                     *ee_esmp;
 726 #if EFSYS_OPT_QSTATS
 727         uint32_t                        ee_stat[EV_NQSTATS];
 728 #endif  /* EFSYS_OPT_QSTATS */
 729
 730         efx_ev_handler_t                ee_rx;
 731         efx_ev_handler_t                ee_tx;
 732         efx_ev_handler_t                ee_driver;
 733         efx_ev_handler_t                ee_global;
 734         efx_ev_handler_t                ee_drv_gen;
 735 #if EFSYS_OPT_MCDI
 736         efx_ev_handler_t                ee_mcdi;
 737 #endif  /* EFSYS_OPT_MCDI */
 738
 739         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 740
 741         uint32_t                        ee_flags;
 742 };
 743
 744 #define EFX_EVQ_MAGIC   0x08081997
 745
 746 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 747
 748 struct efx_rxq_s {
 749         uint32_t                        er_magic;
 750         efx_nic_t                       *er_enp;
 751         efx_evq_t                       *er_eep;
 752         unsigned int                    er_index;
 753         unsigned int                    er_label;
 754         unsigned int                    er_mask;
 755         efsys_mem_t                     *er_esmp;
 756 };
 757
 758 #define EFX_RXQ_MAGIC   0x15022005
 759
 760 struct efx_txq_s {
 761         uint32_t                        et_magic;
 762         efx_nic_t                       *et_enp;
 763         unsigned int                    et_index;
 764         unsigned int                    et_mask;
 765         efsys_mem_t                     *et_esmp;
 766 #if EFSYS_OPT_HUNTINGTON
 767         uint32_t                        et_pio_bufnum;
 768         uint32_t                        et_pio_blknum;
 769         uint32_t                        et_pio_write_offset;
 770         uint32_t                        et_pio_offset;
 771         size_t                          et_pio_size;
 772 #endif
 773 #if EFSYS_OPT_QSTATS
 774         uint32_t                        et_stat[TX_NQSTATS];
 775 #endif  /* EFSYS_OPT_QSTATS */
 776 };
 777
 778 #define EFX_TXQ_MAGIC   0x05092005
 779
 780 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 781         do {                                                            \
 782                 (_dst)[0] = (_src)[0];                                  \
 783                 (_dst)[1] = (_src)[1];                                  \
 784                 (_dst)[2] = (_src)[2];                                  \
 785                 (_dst)[3] = (_src)[3];                                  \
 786                 (_dst)[4] = (_src)[4];                                  \
 787                 (_dst)[5] = (_src)[5];                                  \
 788         _NOTE(CONSTANTCONDITION)                                        \
 789         } while (B_FALSE)
 790
 791 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 792         do {                                                            \
 793                 uint16_t *_d = (uint16_t *)(_dst);                      \
 794                 _d[0] = 0xffff;                                         \
 795                 _d[1] = 0xffff;                                         \
 796                 _d[2] = 0xffff;                                         \
 797         _NOTE(CONSTANTCONDITION)                                        \
 798         } while (B_FALSE)
 799
 800 #if EFSYS_OPT_CHECK_REG
 801 #define EFX_CHECK_REG(_enp, _reg)                                       \
 802         do {                                                            \
 803                 const char *name = #_reg;                               \
 804                 char min = name[4];                                     \
 805                 char max = name[5];                                     \
 806                 char rev;                                               \
 807                                                                         \
 808                 switch ((_enp)->en_family) {                            \
 809                 case EFX_FAMILY_SIENA:                                  \
 810                         rev = 'C';                                      \
 811                         break;                                          \
 812                                                                         \
 813                 case EFX_FAMILY_HUNTINGTON:                             \
 814                         rev = 'D';                                      \
 815                         break;                                          \
 816                                                                         \
 817                 case EFX_FAMILY_MEDFORD:                                \
 818                         rev = 'E';                                      \
 819                         break;                                          \
 820                                                                         \
 821                 default:                                                \
 822                         rev = '?';                                      \
 823                         break;                                          \
 824                 }                                                       \
 825                                                                         \
 826                 EFSYS_ASSERT3S(rev, >=, min);                           \
 827                 EFSYS_ASSERT3S(rev, <=, max);                           \
 828                                                                         \
 829         _NOTE(CONSTANTCONDITION)                                        \
 830         } while (B_FALSE)
 831 #else
 832 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 833         _NOTE(CONSTANTCONDITION)                                        \
 834         } while (B_FALSE)
 835 #endif
 836
 837 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 838         do {                                                            \
 839                 EFX_CHECK_REG((_enp), (_reg));                          \
 840                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 841                     (_edp), (_lock));                                   \
 842                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 843                     uint32_t, _reg ## _OFST,                            \
 844                     uint32_t, (_edp)->ed_u32[0]);                       \
 845         _NOTE(CONSTANTCONDITION)                                        \
 846         } while (B_FALSE)
 847
 848 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 849         do {                                                            \
 850                 EFX_CHECK_REG((_enp), (_reg));                          \
 851                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 852                     uint32_t, _reg ## _OFST,                            \
 853                     uint32_t, (_edp)->ed_u32[0]);                       \
 854                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 855                     (_edp), (_lock));                                   \
 856         _NOTE(CONSTANTCONDITION)                                        \
 857         } while (B_FALSE)
 858
 859 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 860         do {                                                            \
 861                 EFX_CHECK_REG((_enp), (_reg));                          \
 862                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 863                     (_eqp));                                            \
 864                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 865                     uint32_t, _reg ## _OFST,                            \
 866                     uint32_t, (_eqp)->eq_u32[1],                        \
 867                     uint32_t, (_eqp)->eq_u32[0]);                       \
 868         _NOTE(CONSTANTCONDITION)                                        \
 869         } while (B_FALSE)
 870
 871 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 872         do {                                                            \
 873                 EFX_CHECK_REG((_enp), (_reg));                          \
 874                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 875                     uint32_t, _reg ## _OFST,                            \
 876                     uint32_t, (_eqp)->eq_u32[1],                        \
 877                     uint32_t, (_eqp)->eq_u32[0]);                       \
 878                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 879                     (_eqp));                                            \
 880         _NOTE(CONSTANTCONDITION)                                        \
 881         } while (B_FALSE)
 882
 883 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 884         do {                                                            \
 885                 EFX_CHECK_REG((_enp), (_reg));                          \
 886                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 887                     (_eop), B_TRUE);                                    \
 888                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 889                     uint32_t, _reg ## _OFST,                            \
 890                     uint32_t, (_eop)->eo_u32[3],                        \
 891                     uint32_t, (_eop)->eo_u32[2],                        \
 892                     uint32_t, (_eop)->eo_u32[1],                        \
 893                     uint32_t, (_eop)->eo_u32[0]);                       \
 894         _NOTE(CONSTANTCONDITION)                                        \
 895         } while (B_FALSE)
 896
 897 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 898         do {                                                            \
 899                 EFX_CHECK_REG((_enp), (_reg));                          \
 900                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 901                     uint32_t, _reg ## _OFST,                            \
 902                     uint32_t, (_eop)->eo_u32[3],                        \
 903                     uint32_t, (_eop)->eo_u32[2],                        \
 904                     uint32_t, (_eop)->eo_u32[1],                        \
 905                     uint32_t, (_eop)->eo_u32[0]);                       \
 906                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 907                     (_eop), B_TRUE);                                    \
 908         _NOTE(CONSTANTCONDITION)                                        \
 909         } while (B_FALSE)
 910
 911 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 912         do {                                                            \
 913                 EFX_CHECK_REG((_enp), (_reg));                          \
 914                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 915                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 916                     (_edp), (_lock));                                   \
 917                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 918                     uint32_t, (_index),                                 \
 919                     uint32_t, _reg ## _OFST,                            \
 920                     uint32_t, (_edp)->ed_u32[0]);                       \
 921         _NOTE(CONSTANTCONDITION)                                        \
 922         } while (B_FALSE)
 923
 924 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 925         do {                                                            \
 926                 EFX_CHECK_REG((_enp), (_reg));                          \
 927                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 928                     uint32_t, (_index),                                 \
 929                     uint32_t, _reg ## _OFST,                            \
 930                     uint32_t, (_edp)->ed_u32[0]);                       \
 931                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 932                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 933                     (_edp), (_lock));                                   \
 934         _NOTE(CONSTANTCONDITION)                                        \
 935         } while (B_FALSE)
 936
 937 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 938         do {                                                            \
 939                 EFX_CHECK_REG((_enp), (_reg));                          \
 940                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 941                     uint32_t, (_index),                                 \
 942                     uint32_t, _reg ## _OFST,                            \
 943                     uint32_t, (_edp)->ed_u32[0]);                       \
 944                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 945                     (_reg ## _OFST +                                    \
 946                     (2 * sizeof (efx_dword_t)) +                        \
 947                     ((_index) * _reg ## _STEP)),                        \
 948                     (_edp), (_lock));                                   \
 949         _NOTE(CONSTANTCONDITION)                                        \
 950         } while (B_FALSE)
 951
 952 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 953         do {                                                            \
 954                 EFX_CHECK_REG((_enp), (_reg));                          \
 955                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 956                     uint32_t, (_index),                                 \
 957                     uint32_t, _reg ## _OFST,                            \
 958                     uint32_t, (_edp)->ed_u32[0]);                       \
 959                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 960                     (_reg ## _OFST +                                    \
 961                     (3 * sizeof (efx_dword_t)) +                        \
 962                     ((_index) * _reg ## _STEP)),                        \
 963                     (_edp), (_lock));                                   \
 964         _NOTE(CONSTANTCONDITION)                                        \
 965         } while (B_FALSE)
 966
 967 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 968         do {                                                            \
 969                 EFX_CHECK_REG((_enp), (_reg));                          \
 970                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 971                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 972                     (_eqp));                                            \
 973                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 974                     uint32_t, (_index),                                 \
 975                     uint32_t, _reg ## _OFST,                            \
 976                     uint32_t, (_eqp)->eq_u32[1],                        \
 977                     uint32_t, (_eqp)->eq_u32[0]);                       \
 978         _NOTE(CONSTANTCONDITION)                                        \
 979         } while (B_FALSE)
 980
 981 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 982         do {                                                            \
 983                 EFX_CHECK_REG((_enp), (_reg));                          \
 984                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 985                     uint32_t, (_index),                                 \
 986                     uint32_t, _reg ## _OFST,                            \
 987                     uint32_t, (_eqp)->eq_u32[1],                        \
 988                     uint32_t, (_eqp)->eq_u32[0]);                       \
 989                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 990                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 991                     (_eqp));                                            \
 992         _NOTE(CONSTANTCONDITION)                                        \
 993         } while (B_FALSE)
 994
 995 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 996         do {                                                            \
 997                 EFX_CHECK_REG((_enp), (_reg));                          \
 998                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 999                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1000                     (_eop), (_lock));                                   \
1001                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1002                     uint32_t, (_index),                                 \
1003                     uint32_t, _reg ## _OFST,                            \
1004                     uint32_t, (_eop)->eo_u32[3],                        \
1005                     uint32_t, (_eop)->eo_u32[2],                        \
1006                     uint32_t, (_eop)->eo_u32[1],                        \
1007                     uint32_t, (_eop)->eo_u32[0]);                       \
1008         _NOTE(CONSTANTCONDITION)                                        \
1009         } while (B_FALSE)
1010
1011 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1012         do {                                                            \
1013                 EFX_CHECK_REG((_enp), (_reg));                          \
1014                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1015                     uint32_t, (_index),                                 \
1016                     uint32_t, _reg ## _OFST,                            \
1017                     uint32_t, (_eop)->eo_u32[3],                        \
1018                     uint32_t, (_eop)->eo_u32[2],                        \
1019                     uint32_t, (_eop)->eo_u32[1],                        \
1020                     uint32_t, (_eop)->eo_u32[0]);                       \
1021                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1022                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1023                     (_eop), (_lock));                                   \
1024         _NOTE(CONSTANTCONDITION)                                        \
1025         } while (B_FALSE)
1026
1027 /*
1028  * Allow drivers to perform optimised 128-bit doorbell writes.
1029  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1030  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1031  * the need for locking in the host, and are the only ones known to be safe to
1032  * use 128-bites write with.
1033  */
1034 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1035         do {                                                            \
1036                 EFX_CHECK_REG((_enp), (_reg));                          \
1037                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1038                     const char *,                                       \
1039                     #_reg,                                              \
1040                     uint32_t, (_index),                                 \
1041                     uint32_t, _reg ## _OFST,                            \
1042                     uint32_t, (_eop)->eo_u32[3],                        \
1043                     uint32_t, (_eop)->eo_u32[2],                        \
1044                     uint32_t, (_eop)->eo_u32[1],                        \
1045                     uint32_t, (_eop)->eo_u32[0]);                       \
1046                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1047                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1048                     (_eop));                                            \
1049         _NOTE(CONSTANTCONDITION)                                        \
1050         } while (B_FALSE)
1051
1052 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1053         do {                                                            \
1054                 unsigned int _new = (_wptr);                            \
1055                 unsigned int _old = (_owptr);                           \
1056                                                                         \
1057                 if ((_new) >= (_old))                                   \
1058                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1059                             (_old) * sizeof (efx_desc_t),               \
1060                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1061                 else                                                    \
1062                         /*                                              \
1063                          * It is cheaper to sync entire map than sync   \
1064                          * two parts especially when offset/size are    \
1065                          * ignored and entire map is synced in any case.\
1066                          */                                             \
1067                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1068                             0,                                          \
1069                             (_entries) * sizeof (efx_desc_t));          \
1070         _NOTE(CONSTANTCONDITION)                                        \
1071         } while (B_FALSE)
1072
1073 extern  __checkReturn   efx_rc_t
1074 efx_nic_biu_test(
1075         __in            efx_nic_t *enp);
1076
1077 extern  __checkReturn   efx_rc_t
1078 efx_mac_select(
1079         __in            efx_nic_t *enp);
1080
1081 extern  void
1082 efx_mac_multicast_hash_compute(
1083         __in_ecount(6*count)            uint8_t const *addrs,
1084         __in                            int count,
1085         __out                           efx_oword_t *hash_low,
1086         __out                           efx_oword_t *hash_high);
1087
1088 extern  __checkReturn   efx_rc_t
1089 efx_phy_probe(
1090         __in            efx_nic_t *enp);
1091
1092 extern                  void
1093 efx_phy_unprobe(
1094         __in            efx_nic_t *enp);
1095
1096 #if EFSYS_OPT_VPD
1097
1098 /* VPD utility functions */
1099
1100 extern  __checkReturn           efx_rc_t
1101 efx_vpd_hunk_length(
1102         __in_bcount(size)       caddr_t data,
1103         __in                    size_t size,
1104         __out                   size_t *lengthp);
1105
1106 extern  __checkReturn           efx_rc_t
1107 efx_vpd_hunk_verify(
1108         __in_bcount(size)       caddr_t data,
1109         __in                    size_t size,
1110         __out_opt               boolean_t *cksummedp);
1111
1112 extern  __checkReturn           efx_rc_t
1113 efx_vpd_hunk_reinit(
1114         __in_bcount(size)       caddr_t data,
1115         __in                    size_t size,
1116         __in                    boolean_t wantpid);
1117
1118 extern  __checkReturn           efx_rc_t
1119 efx_vpd_hunk_get(
1120         __in_bcount(size)       caddr_t data,
1121         __in                    size_t size,
1122         __in                    efx_vpd_tag_t tag,
1123         __in                    efx_vpd_keyword_t keyword,
1124         __out                   unsigned int *payloadp,
1125         __out                   uint8_t *paylenp);
1126
1127 extern  __checkReturn                   efx_rc_t
1128 efx_vpd_hunk_next(
1129         __in_bcount(size)               caddr_t data,
1130         __in                            size_t size,
1131         __out                           efx_vpd_tag_t *tagp,
1132         __out                           efx_vpd_keyword_t *keyword,
1133         __out_opt                       unsigned int *payloadp,
1134         __out_opt                       uint8_t *paylenp,
1135         __inout                         unsigned int *contp);
1136
1137 extern  __checkReturn           efx_rc_t
1138 efx_vpd_hunk_set(
1139         __in_bcount(size)       caddr_t data,
1140         __in                    size_t size,
1141         __in                    efx_vpd_value_t *evvp);
1142
1143 #endif  /* EFSYS_OPT_VPD */
1144
1145 #if EFSYS_OPT_DIAG
1146
1147 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1148
1149 typedef struct efx_register_set_s {
1150         unsigned int            address;
1151         unsigned int            step;
1152         unsigned int            rows;
1153         efx_oword_t             mask;
1154 } efx_register_set_t;
1155
1156 extern  __checkReturn   efx_rc_t
1157 efx_nic_test_registers(
1158         __in            efx_nic_t *enp,
1159         __in            efx_register_set_t *rsp,
1160         __in            size_t count);
1161
1162 extern  __checkReturn   efx_rc_t
1163 efx_nic_test_tables(
1164         __in            efx_nic_t *enp,
1165         __in            efx_register_set_t *rsp,
1166         __in            efx_pattern_type_t pattern,
1167         __in            size_t count);
1168
1169 #endif  /* EFSYS_OPT_DIAG */
1170
1171 #if EFSYS_OPT_MCDI
1172
1173 extern  __checkReturn           efx_rc_t
1174 efx_mcdi_set_workaround(
1175         __in                    efx_nic_t *enp,
1176         __in                    uint32_t type,
1177         __in                    boolean_t enabled,
1178         __out_opt               uint32_t *flagsp);
1179
1180 extern  __checkReturn           efx_rc_t
1181 efx_mcdi_get_workarounds(
1182         __in                    efx_nic_t *enp,
1183         __out_opt               uint32_t *implementedp,
1184         __out_opt               uint32_t *enabledp);
1185
1186 #endif /* EFSYS_OPT_MCDI */
1187
1188 #if EFSYS_OPT_MAC_STATS
1189
1190 /*
1191  * Closed range of stats (i.e. the first and the last are included).
1192  * The last must be greater or equal (if the range is one item only) to
1193  * the first.
1194  */
1195 struct efx_mac_stats_range {
1196         efx_mac_stat_t          first;
1197         efx_mac_stat_t          last;
1198 };
1199
1200 extern                                  efx_rc_t
1201 efx_mac_stats_mask_add_ranges(
1202         __inout_bcount(mask_size)       uint32_t *maskp,
1203         __in                            size_t mask_size,
1204         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1205         __in                            unsigned int rng_count);
1206
1207 #endif  /* EFSYS_OPT_MAC_STATS */
1208
1209 #ifdef  __cplusplus
1210 }
1211 #endif
1212
1213 #endif  /* _SYS_EFX_IMPL_H */