drivers/net/sfc/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11         __checkReturn   efx_rc_t
  12 efx_family(
  13         __in            uint16_t venid,
  14         __in            uint16_t devid,
  15         __out           efx_family_t *efp,
  16         __out           unsigned int *membarp)
  17 {
  18         if (venid == EFX_PCI_VENID_SFC) {
  19                 switch (devid) {
  20 #if EFSYS_OPT_SIENA
  21                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  22                         /*
  23                          * Hardware default for PF0 of uninitialised Siena.
  24                          * manftest must be able to cope with this device id.
  25                          */
  26                 case EFX_PCI_DEVID_BETHPAGE:
  27                 case EFX_PCI_DEVID_SIENA:
  28                         *efp = EFX_FAMILY_SIENA;
  29                         *membarp = EFX_MEM_BAR_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                 case EFX_PCI_DEVID_FARMINGDALE:
  40                 case EFX_PCI_DEVID_GREENPORT:
  41                         *efp = EFX_FAMILY_HUNTINGTON;
  42                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  43                         return (0);
  44
  45                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  46                 case EFX_PCI_DEVID_GREENPORT_VF:
  47                         *efp = EFX_FAMILY_HUNTINGTON;
  48                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  49                         return (0);
  50 #endif /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  54                         /*
  55                          * Hardware default for PF0 of uninitialised Medford.
  56                          * manftest must be able to cope with this device id.
  57                          */
  58                 case EFX_PCI_DEVID_MEDFORD:
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  61                         return (0);
  62
  63                 case EFX_PCI_DEVID_MEDFORD_VF:
  64                         *efp = EFX_FAMILY_MEDFORD;
  65                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  66                         return (0);
  67 #endif /* EFSYS_OPT_MEDFORD */
  68
  69 #if EFSYS_OPT_MEDFORD2
  70                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  71                         /*
  72                          * Hardware default for PF0 of uninitialised Medford2.
  73                          * manftest must be able to cope with this device id.
  74                          */
  75                 case EFX_PCI_DEVID_MEDFORD2:
  76                 case EFX_PCI_DEVID_MEDFORD2_VF:
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         *membarp = EFX_MEM_BAR_MEDFORD2;
  79                         return (0);
  80 #endif /* EFSYS_OPT_MEDFORD2 */
  81
  82                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  83                 default:
  84                         break;
  85                 }
  86         }
  87
  88         *efp = EFX_FAMILY_INVALID;
  89         return (ENOTSUP);
  90 }
  91
  92
  93 #if EFSYS_OPT_SIENA
  94
  95 static const efx_nic_ops_t      __efx_nic_siena_ops = {
  96         siena_nic_probe,                /* eno_probe */
  97         NULL,                           /* eno_board_cfg */
  98         NULL,                           /* eno_set_drv_limits */
  99         siena_nic_reset,                /* eno_reset */
 100         siena_nic_init,                 /* eno_init */
 101         NULL,                           /* eno_get_vi_pool */
 102         NULL,                           /* eno_get_bar_region */
 103         NULL,                           /* eno_hw_unavailable */
 104         NULL,                           /* eno_set_hw_unavailable */
 105 #if EFSYS_OPT_DIAG
 106         siena_nic_register_test,        /* eno_register_test */
 107 #endif  /* EFSYS_OPT_DIAG */
 108         siena_nic_fini,                 /* eno_fini */
 109         siena_nic_unprobe,              /* eno_unprobe */
 110 };
 111
 112 #endif  /* EFSYS_OPT_SIENA */
 113
 114 #if EFSYS_OPT_HUNTINGTON
 115
 116 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 117         ef10_nic_probe,                 /* eno_probe */
 118         hunt_board_cfg,                 /* eno_board_cfg */
 119         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 120         ef10_nic_reset,                 /* eno_reset */
 121         ef10_nic_init,                  /* eno_init */
 122         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 123         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 124         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 125         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 126 #if EFSYS_OPT_DIAG
 127         ef10_nic_register_test,         /* eno_register_test */
 128 #endif  /* EFSYS_OPT_DIAG */
 129         ef10_nic_fini,                  /* eno_fini */
 130         ef10_nic_unprobe,               /* eno_unprobe */
 131 };
 132
 133 #endif  /* EFSYS_OPT_HUNTINGTON */
 134
 135 #if EFSYS_OPT_MEDFORD
 136
 137 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 138         ef10_nic_probe,                 /* eno_probe */
 139         medford_board_cfg,              /* eno_board_cfg */
 140         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 141         ef10_nic_reset,                 /* eno_reset */
 142         ef10_nic_init,                  /* eno_init */
 143         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 144         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 145         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 146         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 147 #if EFSYS_OPT_DIAG
 148         ef10_nic_register_test,         /* eno_register_test */
 149 #endif  /* EFSYS_OPT_DIAG */
 150         ef10_nic_fini,                  /* eno_fini */
 151         ef10_nic_unprobe,               /* eno_unprobe */
 152 };
 153
 154 #endif  /* EFSYS_OPT_MEDFORD */
 155
 156 #if EFSYS_OPT_MEDFORD2
 157
 158 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 159         ef10_nic_probe,                 /* eno_probe */
 160         medford2_board_cfg,             /* eno_board_cfg */
 161         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 162         ef10_nic_reset,                 /* eno_reset */
 163         ef10_nic_init,                  /* eno_init */
 164         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 165         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 166         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 167         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 168 #if EFSYS_OPT_DIAG
 169         ef10_nic_register_test,         /* eno_register_test */
 170 #endif  /* EFSYS_OPT_DIAG */
 171         ef10_nic_fini,                  /* eno_fini */
 172         ef10_nic_unprobe,               /* eno_unprobe */
 173 };
 174
 175 #endif  /* EFSYS_OPT_MEDFORD2 */
 176
 177
 178         __checkReturn   efx_rc_t
 179 efx_nic_create(
 180         __in            efx_family_t family,
 181         __in            efsys_identifier_t *esip,
 182         __in            efsys_bar_t *esbp,
 183         __in            efsys_lock_t *eslp,
 184         __deref_out     efx_nic_t **enpp)
 185 {
 186         efx_nic_t *enp;
 187         efx_rc_t rc;
 188
 189         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 190         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 191
 192         /* Allocate a NIC object */
 193         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 194
 195         if (enp == NULL) {
 196                 rc = ENOMEM;
 197                 goto fail1;
 198         }
 199
 200         enp->en_magic = EFX_NIC_MAGIC;
 201
 202         switch (family) {
 203 #if EFSYS_OPT_SIENA
 204         case EFX_FAMILY_SIENA:
 205                 enp->en_enop = &__efx_nic_siena_ops;
 206                 enp->en_features =
 207                     EFX_FEATURE_IPV6 |
 208                     EFX_FEATURE_LFSR_HASH_INSERT |
 209                     EFX_FEATURE_LINK_EVENTS |
 210                     EFX_FEATURE_PERIODIC_MAC_STATS |
 211                     EFX_FEATURE_MCDI |
 212                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 213                     EFX_FEATURE_MAC_HEADER_FILTERS |
 214                     EFX_FEATURE_TX_SRC_FILTERS;
 215                 break;
 216 #endif  /* EFSYS_OPT_SIENA */
 217
 218 #if EFSYS_OPT_HUNTINGTON
 219         case EFX_FAMILY_HUNTINGTON:
 220                 enp->en_enop = &__efx_nic_hunt_ops;
 221                 enp->en_features =
 222                     EFX_FEATURE_IPV6 |
 223                     EFX_FEATURE_LINK_EVENTS |
 224                     EFX_FEATURE_PERIODIC_MAC_STATS |
 225                     EFX_FEATURE_MCDI |
 226                     EFX_FEATURE_MAC_HEADER_FILTERS |
 227                     EFX_FEATURE_MCDI_DMA |
 228                     EFX_FEATURE_PIO_BUFFERS |
 229                     EFX_FEATURE_FW_ASSISTED_TSO |
 230                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 231                     EFX_FEATURE_PACKED_STREAM;
 232                 break;
 233 #endif  /* EFSYS_OPT_HUNTINGTON */
 234
 235 #if EFSYS_OPT_MEDFORD
 236         case EFX_FAMILY_MEDFORD:
 237                 enp->en_enop = &__efx_nic_medford_ops;
 238                 /*
 239                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 240                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 241                  */
 242                 enp->en_features =
 243                     EFX_FEATURE_IPV6 |
 244                     EFX_FEATURE_LINK_EVENTS |
 245                     EFX_FEATURE_PERIODIC_MAC_STATS |
 246                     EFX_FEATURE_MCDI |
 247                     EFX_FEATURE_MAC_HEADER_FILTERS |
 248                     EFX_FEATURE_MCDI_DMA |
 249                     EFX_FEATURE_PIO_BUFFERS |
 250                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 251                     EFX_FEATURE_PACKED_STREAM;
 252                 break;
 253 #endif  /* EFSYS_OPT_MEDFORD */
 254
 255 #if EFSYS_OPT_MEDFORD2
 256         case EFX_FAMILY_MEDFORD2:
 257                 enp->en_enop = &__efx_nic_medford2_ops;
 258                 enp->en_features =
 259                     EFX_FEATURE_IPV6 |
 260                     EFX_FEATURE_LINK_EVENTS |
 261                     EFX_FEATURE_PERIODIC_MAC_STATS |
 262                     EFX_FEATURE_MCDI |
 263                     EFX_FEATURE_MAC_HEADER_FILTERS |
 264                     EFX_FEATURE_MCDI_DMA |
 265                     EFX_FEATURE_PIO_BUFFERS |
 266                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 267                     EFX_FEATURE_PACKED_STREAM;
 268                 break;
 269 #endif  /* EFSYS_OPT_MEDFORD2 */
 270
 271         default:
 272                 rc = ENOTSUP;
 273                 goto fail2;
 274         }
 275
 276         enp->en_family = family;
 277         enp->en_esip = esip;
 278         enp->en_esbp = esbp;
 279         enp->en_eslp = eslp;
 280
 281         *enpp = enp;
 282
 283         return (0);
 284
 285 fail2:
 286         EFSYS_PROBE(fail2);
 287
 288         enp->en_magic = 0;
 289
 290         /* Free the NIC object */
 291         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 292
 293 fail1:
 294         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 295
 296         return (rc);
 297 }
 298
 299         __checkReturn   efx_rc_t
 300 efx_nic_probe(
 301         __in            efx_nic_t *enp,
 302         __in            efx_fw_variant_t efv)
 303 {
 304         const efx_nic_ops_t *enop;
 305         efx_rc_t rc;
 306
 307         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 308 #if EFSYS_OPT_MCDI
 309         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 310 #endif  /* EFSYS_OPT_MCDI */
 311         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 312
 313         /* Ensure FW variant codes match with MC_CMD_FW codes */
 314         EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
 315             MC_CMD_FW_FULL_FEATURED);
 316         EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
 317             MC_CMD_FW_LOW_LATENCY);
 318         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
 319             MC_CMD_FW_PACKED_STREAM);
 320         EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
 321             MC_CMD_FW_HIGH_TX_RATE);
 322         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
 323             MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
 324         EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
 325             MC_CMD_FW_RULES_ENGINE);
 326         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
 327             MC_CMD_FW_DPDK);
 328         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
 329             (int)MC_CMD_FW_DONT_CARE);
 330
 331         enop = enp->en_enop;
 332         enp->efv = efv;
 333
 334         if ((rc = enop->eno_probe(enp)) != 0)
 335                 goto fail1;
 336
 337         if ((rc = efx_phy_probe(enp)) != 0)
 338                 goto fail2;
 339
 340         enp->en_mod_flags |= EFX_MOD_PROBE;
 341
 342         return (0);
 343
 344 fail2:
 345         EFSYS_PROBE(fail2);
 346
 347         enop->eno_unprobe(enp);
 348
 349 fail1:
 350         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 351
 352         return (rc);
 353 }
 354
 355         __checkReturn   efx_rc_t
 356 efx_nic_set_drv_limits(
 357         __inout         efx_nic_t *enp,
 358         __in            efx_drv_limits_t *edlp)
 359 {
 360         const efx_nic_ops_t *enop = enp->en_enop;
 361         efx_rc_t rc;
 362
 363         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 364         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 365
 366         if (enop->eno_set_drv_limits != NULL) {
 367                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 368                         goto fail1;
 369         }
 370
 371         return (0);
 372
 373 fail1:
 374         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 375
 376         return (rc);
 377 }
 378
 379         __checkReturn   efx_rc_t
 380 efx_nic_get_bar_region(
 381         __in            efx_nic_t *enp,
 382         __in            efx_nic_region_t region,
 383         __out           uint32_t *offsetp,
 384         __out           size_t *sizep)
 385 {
 386         const efx_nic_ops_t *enop = enp->en_enop;
 387         efx_rc_t rc;
 388
 389         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 390         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 391         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 392
 393         if (enop->eno_get_bar_region == NULL) {
 394                 rc = ENOTSUP;
 395                 goto fail1;
 396         }
 397         if ((rc = (enop->eno_get_bar_region)(enp,
 398                     region, offsetp, sizep)) != 0) {
 399                 goto fail2;
 400         }
 401
 402         return (0);
 403
 404 fail2:
 405         EFSYS_PROBE(fail2);
 406
 407 fail1:
 408         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 409
 410         return (rc);
 411 }
 412
 413
 414         __checkReturn   efx_rc_t
 415 efx_nic_get_vi_pool(
 416         __in            efx_nic_t *enp,
 417         __out           uint32_t *evq_countp,
 418         __out           uint32_t *rxq_countp,
 419         __out           uint32_t *txq_countp)
 420 {
 421         const efx_nic_ops_t *enop = enp->en_enop;
 422         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 423         efx_rc_t rc;
 424
 425         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 426         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 427         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 428
 429         if (enop->eno_get_vi_pool != NULL) {
 430                 uint32_t vi_count = 0;
 431
 432                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 433                         goto fail1;
 434
 435                 *evq_countp = vi_count;
 436                 *rxq_countp = vi_count;
 437                 *txq_countp = vi_count;
 438         } else {
 439                 /* Use NIC limits as default value */
 440                 *evq_countp = encp->enc_evq_limit;
 441                 *rxq_countp = encp->enc_rxq_limit;
 442                 *txq_countp = encp->enc_txq_limit;
 443         }
 444
 445         return (0);
 446
 447 fail1:
 448         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 449
 450         return (rc);
 451 }
 452
 453
 454         __checkReturn   efx_rc_t
 455 efx_nic_init(
 456         __in            efx_nic_t *enp)
 457 {
 458         const efx_nic_ops_t *enop = enp->en_enop;
 459         efx_rc_t rc;
 460
 461         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 462         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 463
 464         if (enp->en_mod_flags & EFX_MOD_NIC) {
 465                 rc = EINVAL;
 466                 goto fail1;
 467         }
 468
 469         if ((rc = enop->eno_init(enp)) != 0)
 470                 goto fail2;
 471
 472         enp->en_mod_flags |= EFX_MOD_NIC;
 473
 474         return (0);
 475
 476 fail2:
 477         EFSYS_PROBE(fail2);
 478 fail1:
 479         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 480
 481         return (rc);
 482 }
 483
 484                         void
 485 efx_nic_fini(
 486         __in            efx_nic_t *enp)
 487 {
 488         const efx_nic_ops_t *enop = enp->en_enop;
 489
 490         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 491         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 492         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 493         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 494         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 495         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 496         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 497
 498         enop->eno_fini(enp);
 499
 500         enp->en_mod_flags &= ~EFX_MOD_NIC;
 501 }
 502
 503                         void
 504 efx_nic_unprobe(
 505         __in            efx_nic_t *enp)
 506 {
 507         const efx_nic_ops_t *enop = enp->en_enop;
 508
 509         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 510 #if EFSYS_OPT_MCDI
 511         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 512 #endif  /* EFSYS_OPT_MCDI */
 513         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 514         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 515         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 516         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 517         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 518         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 519
 520         efx_phy_unprobe(enp);
 521
 522         enop->eno_unprobe(enp);
 523
 524         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 525 }
 526
 527                         void
 528 efx_nic_destroy(
 529         __in    efx_nic_t *enp)
 530 {
 531         efsys_identifier_t *esip = enp->en_esip;
 532
 533         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 534         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 535
 536         enp->en_family = EFX_FAMILY_INVALID;
 537         enp->en_esip = NULL;
 538         enp->en_esbp = NULL;
 539         enp->en_eslp = NULL;
 540
 541         enp->en_enop = NULL;
 542
 543         enp->en_magic = 0;
 544
 545         /* Free the NIC object */
 546         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 547 }
 548
 549         __checkReturn   efx_rc_t
 550 efx_nic_reset(
 551         __in            efx_nic_t *enp)
 552 {
 553         const efx_nic_ops_t *enop = enp->en_enop;
 554         unsigned int mod_flags;
 555         efx_rc_t rc;
 556
 557         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 558         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 559         /*
 560          * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
 561          * (which we do not reset here) must have been shut down or never
 562          * initialized.
 563          *
 564          * A rule of thumb here is: If the controller or MC reboots, is *any*
 565          * state lost. If it's lost and needs reapplying, then the module
 566          * *must* not be initialised during the reset.
 567          */
 568         mod_flags = enp->en_mod_flags;
 569         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 570             EFX_MOD_VPD | EFX_MOD_MON);
 571 #if EFSYS_OPT_TUNNEL
 572         mod_flags &= ~EFX_MOD_TUNNEL;
 573 #endif /* EFSYS_OPT_TUNNEL */
 574         EFSYS_ASSERT3U(mod_flags, ==, 0);
 575         if (mod_flags != 0) {
 576                 rc = EINVAL;
 577                 goto fail1;
 578         }
 579
 580         if ((rc = enop->eno_reset(enp)) != 0)
 581                 goto fail2;
 582
 583         return (0);
 584
 585 fail2:
 586         EFSYS_PROBE(fail2);
 587 fail1:
 588         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 589
 590         return (rc);
 591 }
 592
 593                         const efx_nic_cfg_t *
 594 efx_nic_cfg_get(
 595         __in            efx_nic_t *enp)
 596 {
 597         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 598         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 599
 600         return (&(enp->en_nic_cfg));
 601 }
 602
 603         __checkReturn           efx_rc_t
 604 efx_nic_get_fw_version(
 605         __in                    efx_nic_t *enp,
 606         __out                   efx_nic_fw_info_t *enfip)
 607 {
 608         uint16_t mc_fw_version[4];
 609         efx_rc_t rc;
 610
 611         if (enfip == NULL) {
 612                 rc = EINVAL;
 613                 goto fail1;
 614         }
 615
 616         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 617         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 618
 619         /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
 620         EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
 621             MC_CMD_GET_CAPABILITIES_OUT_RXDP);
 622         EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
 623             MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
 624         EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
 625             MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
 626         EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
 627             MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
 628         EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
 629             MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
 630
 631         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 632         if (rc != 0)
 633                 goto fail2;
 634
 635         rc = efx_mcdi_get_capabilities(enp, NULL,
 636             &enfip->enfi_rx_dpcpu_fw_id,
 637             &enfip->enfi_tx_dpcpu_fw_id,
 638             NULL, NULL);
 639         if (rc == 0) {
 640                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 641         } else if (rc == ENOTSUP) {
 642                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 643                 enfip->enfi_rx_dpcpu_fw_id = 0;
 644                 enfip->enfi_tx_dpcpu_fw_id = 0;
 645         } else {
 646                 goto fail3;
 647         }
 648
 649         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 650             sizeof (mc_fw_version));
 651
 652         return (0);
 653
 654 fail3:
 655         EFSYS_PROBE(fail3);
 656 fail2:
 657         EFSYS_PROBE(fail2);
 658 fail1:
 659         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 660
 661         return (rc);
 662 }
 663
 664         __checkReturn   boolean_t
 665 efx_nic_hw_unavailable(
 666         __in            efx_nic_t *enp)
 667 {
 668         const efx_nic_ops_t *enop = enp->en_enop;
 669
 670         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 671         /* NOTE: can be used by MCDI before NIC probe */
 672
 673         if (enop->eno_hw_unavailable != NULL) {
 674                 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
 675                         goto unavail;
 676         }
 677
 678         return (B_FALSE);
 679
 680 unavail:
 681         return (B_TRUE);
 682 }
 683
 684                         void
 685 efx_nic_set_hw_unavailable(
 686         __in            efx_nic_t *enp)
 687 {
 688         const efx_nic_ops_t *enop = enp->en_enop;
 689
 690         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 691
 692         if (enop->eno_set_hw_unavailable != NULL)
 693                 enop->eno_set_hw_unavailable(enp);
 694 }
 695
 696
 697 #if EFSYS_OPT_DIAG
 698
 699         __checkReturn   efx_rc_t
 700 efx_nic_register_test(
 701         __in            efx_nic_t *enp)
 702 {
 703         const efx_nic_ops_t *enop = enp->en_enop;
 704         efx_rc_t rc;
 705
 706         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 707         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 708         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 709
 710         if ((rc = enop->eno_register_test(enp)) != 0)
 711                 goto fail1;
 712
 713         return (0);
 714
 715 fail1:
 716         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 717
 718         return (rc);
 719 }
 720
 721 #endif  /* EFSYS_OPT_DIAG */
 722
 723 #if EFSYS_OPT_LOOPBACK
 724
 725 extern                  void
 726 efx_loopback_mask(
 727         __in    efx_loopback_kind_t loopback_kind,
 728         __out   efx_qword_t *maskp)
 729 {
 730         efx_qword_t mask;
 731
 732         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 733         EFSYS_ASSERT(maskp != NULL);
 734
 735         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
 736 #define LOOPBACK_CHECK(_mcdi, _efx) \
 737         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
 738
 739         LOOPBACK_CHECK(NONE, OFF);
 740         LOOPBACK_CHECK(DATA, DATA);
 741         LOOPBACK_CHECK(GMAC, GMAC);
 742         LOOPBACK_CHECK(XGMII, XGMII);
 743         LOOPBACK_CHECK(XGXS, XGXS);
 744         LOOPBACK_CHECK(XAUI, XAUI);
 745         LOOPBACK_CHECK(GMII, GMII);
 746         LOOPBACK_CHECK(SGMII, SGMII);
 747         LOOPBACK_CHECK(XGBR, XGBR);
 748         LOOPBACK_CHECK(XFI, XFI);
 749         LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
 750         LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
 751         LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
 752         LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
 753         LOOPBACK_CHECK(GPHY, GPHY);
 754         LOOPBACK_CHECK(PHYXS, PHY_XS);
 755         LOOPBACK_CHECK(PCS, PCS);
 756         LOOPBACK_CHECK(PMAPMD, PMA_PMD);
 757         LOOPBACK_CHECK(XPORT, XPORT);
 758         LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
 759         LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
 760         LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
 761         LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
 762         LOOPBACK_CHECK(GMII_WS, GMII_WS);
 763         LOOPBACK_CHECK(XFI_WS, XFI_WS);
 764         LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
 765         LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
 766         LOOPBACK_CHECK(PMA_INT, PMA_INT);
 767         LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
 768         LOOPBACK_CHECK(SD_FAR, SD_FAR);
 769         LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
 770         LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
 771         LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
 772         LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
 773         LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
 774         LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
 775         LOOPBACK_CHECK(DATA_WS, DATA_WS);
 776         LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
 777 #undef LOOPBACK_CHECK
 778
 779         /* Build bitmask of possible loopback types */
 780         EFX_ZERO_QWORD(mask);
 781
 782         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 783             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 784                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 785         }
 786
 787         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 788             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 789                 /*
 790                  * The "MAC" grouping has historically been used by drivers to
 791                  * mean loopbacks supported by on-chip hardware. Keep that
 792                  * meaning here, and include on-chip PHY layer loopbacks.
 793                  */
 794                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 795                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 796                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 797                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 798                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 799                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 800                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 801                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 802                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 803                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 804                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 805                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 806                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 807                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 808                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 809                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 810         }
 811
 812         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 813             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 814                 /*
 815                  * The "PHY" grouping has historically been used by drivers to
 816                  * mean loopbacks supported by off-chip hardware. Keep that
 817                  * meaning here.
 818                  */
 819                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 820                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 821                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 822                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 823         }
 824
 825         *maskp = mask;
 826 }
 827
 828         __checkReturn   efx_rc_t
 829 efx_mcdi_get_loopback_modes(
 830         __in            efx_nic_t *enp)
 831 {
 832         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 833         efx_mcdi_req_t req;
 834         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 835                 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
 836         efx_qword_t mask;
 837         efx_qword_t modes;
 838         efx_rc_t rc;
 839
 840         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 841         req.emr_in_buf = payload;
 842         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 843         req.emr_out_buf = payload;
 844         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
 845
 846         efx_mcdi_execute(enp, &req);
 847
 848         if (req.emr_rc != 0) {
 849                 rc = req.emr_rc;
 850                 goto fail1;
 851         }
 852
 853         if (req.emr_out_length_used <
 854             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 855             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 856                 rc = EMSGSIZE;
 857                 goto fail2;
 858         }
 859
 860         /*
 861          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 862          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 863          */
 864         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 865
 866         EFX_AND_QWORD(mask,
 867             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 868
 869         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 870         EFX_AND_QWORD(modes, mask);
 871         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 872
 873         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 874         EFX_AND_QWORD(modes, mask);
 875         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 876
 877         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 878         EFX_AND_QWORD(modes, mask);
 879         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 880
 881         if (req.emr_out_length_used >=
 882             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 883             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 884                 /* Response includes 40G loopback modes */
 885                 modes = *MCDI_OUT2(req, efx_qword_t,
 886                     GET_LOOPBACK_MODES_OUT_40G);
 887                 EFX_AND_QWORD(modes, mask);
 888                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 889         }
 890
 891         if (req.emr_out_length_used >=
 892             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
 893             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
 894                 /* Response includes 25G loopback modes */
 895                 modes = *MCDI_OUT2(req, efx_qword_t,
 896                     GET_LOOPBACK_MODES_OUT_V2_25G);
 897                 EFX_AND_QWORD(modes, mask);
 898                 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
 899         }
 900
 901         if (req.emr_out_length_used >=
 902             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
 903             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
 904                 /* Response includes 50G loopback modes */
 905                 modes = *MCDI_OUT2(req, efx_qword_t,
 906                     GET_LOOPBACK_MODES_OUT_V2_50G);
 907                 EFX_AND_QWORD(modes, mask);
 908                 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
 909         }
 910
 911         if (req.emr_out_length_used >=
 912             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
 913             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
 914                 /* Response includes 100G loopback modes */
 915                 modes = *MCDI_OUT2(req, efx_qword_t,
 916                     GET_LOOPBACK_MODES_OUT_V2_100G);
 917                 EFX_AND_QWORD(modes, mask);
 918                 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
 919         }
 920
 921         EFX_ZERO_QWORD(modes);
 922         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
 923         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
 924         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
 925         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
 926         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
 927         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
 928         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
 929         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
 930         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
 931
 932         return (0);
 933
 934 fail2:
 935         EFSYS_PROBE(fail2);
 936 fail1:
 937         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 938
 939         return (rc);
 940 }
 941
 942 #endif /* EFSYS_OPT_LOOPBACK */
 943
 944         __checkReturn   efx_rc_t
 945 efx_nic_calculate_pcie_link_bandwidth(
 946         __in            uint32_t pcie_link_width,
 947         __in            uint32_t pcie_link_gen,
 948         __out           uint32_t *bandwidth_mbpsp)
 949 {
 950         uint32_t lane_bandwidth;
 951         uint32_t total_bandwidth;
 952         efx_rc_t rc;
 953
 954         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
 955             !ISP2(pcie_link_width)) {
 956                 rc = EINVAL;
 957                 goto fail1;
 958         }
 959
 960         switch (pcie_link_gen) {
 961         case EFX_PCIE_LINK_SPEED_GEN1:
 962                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
 963                 lane_bandwidth = 2000;
 964                 break;
 965         case EFX_PCIE_LINK_SPEED_GEN2:
 966                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
 967                 lane_bandwidth = 4000;
 968                 break;
 969         case EFX_PCIE_LINK_SPEED_GEN3:
 970                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
 971                 lane_bandwidth = 7877;
 972                 break;
 973         default:
 974                 rc = EINVAL;
 975                 goto fail2;
 976         }
 977
 978         total_bandwidth = lane_bandwidth * pcie_link_width;
 979         *bandwidth_mbpsp = total_bandwidth;
 980
 981         return (0);
 982
 983 fail2:
 984         EFSYS_PROBE(fail2);
 985 fail1:
 986         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 987
 988         return (rc);
 989 }
 990
 991 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
 992
 993         __checkReturn   efx_rc_t
 994 efx_nic_get_fw_subvariant(
 995         __in            efx_nic_t *enp,
 996         __out           efx_nic_fw_subvariant_t *subvariantp)
 997 {
 998         efx_rc_t rc;
 999         uint32_t value;
1000
1001         rc = efx_mcdi_get_nic_global(enp,
1002             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1003         if (rc != 0)
1004                 goto fail1;
1005
1006         /* Mapping is not required since values match MCDI */
1007         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1008             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1009         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1010             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1011
1012         switch (value) {
1013         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1014         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1015                 *subvariantp = value;
1016                 break;
1017         default:
1018                 rc = EINVAL;
1019                 goto fail2;
1020         }
1021
1022         return (0);
1023
1024 fail2:
1025         EFSYS_PROBE(fail2);
1026
1027 fail1:
1028         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1029
1030         return (rc);
1031 }
1032
1033         __checkReturn   efx_rc_t
1034 efx_nic_set_fw_subvariant(
1035         __in            efx_nic_t *enp,
1036         __in            efx_nic_fw_subvariant_t subvariant)
1037 {
1038         efx_rc_t rc;
1039
1040         switch (subvariant) {
1041         case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1042         case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1043                 /* Mapping is not required since values match MCDI */
1044                 break;
1045         default:
1046                 rc = EINVAL;
1047                 goto fail1;
1048         }
1049
1050         rc = efx_mcdi_set_nic_global(enp,
1051             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1052         if (rc != 0)
1053                 goto fail2;
1054
1055         return (0);
1056
1057 fail2:
1058         EFSYS_PROBE(fail2);
1059
1060 fail1:
1061         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1062
1063         return (rc);
1064 }
1065
1066 #endif  /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1067
1068         __checkReturn   efx_rc_t
1069 efx_nic_check_pcie_link_speed(
1070         __in            efx_nic_t *enp,
1071         __in            uint32_t pcie_link_width,
1072         __in            uint32_t pcie_link_gen,
1073         __out           efx_pcie_link_performance_t *resultp)
1074 {
1075         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1076         uint32_t bandwidth;
1077         efx_pcie_link_performance_t result;
1078         efx_rc_t rc;
1079
1080         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1081             (pcie_link_width == 0) || (pcie_link_width == 32) ||
1082             (pcie_link_gen == 0)) {
1083                 /*
1084                  * No usable info on what is required and/or in use. In virtual
1085                  * machines, sometimes the PCIe link width is reported as 0 or
1086                  * 32, or the speed as 0.
1087                  */
1088                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1089                 goto out;
1090         }
1091
1092         /* Calculate the available bandwidth in megabits per second */
1093         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1094                                             pcie_link_gen, &bandwidth);
1095         if (rc != 0)
1096                 goto fail1;
1097
1098         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1099                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1100         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1101                 /* The link provides enough bandwidth but not optimal latency */
1102                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1103         } else {
1104                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1105         }
1106
1107 out:
1108         *resultp = result;
1109
1110         return (0);
1111
1112 fail1:
1113         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1114
1115         return (rc);
1116 }