drivers/net/sfc/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10         __checkReturn   efx_rc_t
  11 efx_family(
  12         __in            uint16_t venid,
  13         __in            uint16_t devid,
  14         __out           efx_family_t *efp)
  15 {
  16         if (venid == EFX_PCI_VENID_SFC) {
  17                 switch (devid) {
  18 #if EFSYS_OPT_SIENA
  19                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  20                         /*
  21                          * Hardware default for PF0 of uninitialised Siena.
  22                          * manftest must be able to cope with this device id.
  23                          */
  24                         *efp = EFX_FAMILY_SIENA;
  25                         return (0);
  26
  27                 case EFX_PCI_DEVID_BETHPAGE:
  28                 case EFX_PCI_DEVID_SIENA:
  29                         *efp = EFX_FAMILY_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                         *efp = EFX_FAMILY_HUNTINGTON;
  40                         return (0);
  41
  42                 case EFX_PCI_DEVID_FARMINGDALE:
  43                 case EFX_PCI_DEVID_GREENPORT:
  44                         *efp = EFX_FAMILY_HUNTINGTON;
  45                         return (0);
  46
  47                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  48                 case EFX_PCI_DEVID_GREENPORT_VF:
  49                         *efp = EFX_FAMILY_HUNTINGTON;
  50                         return (0);
  51 #endif /* EFSYS_OPT_HUNTINGTON */
  52
  53 #if EFSYS_OPT_MEDFORD
  54                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  55                         /*
  56                          * Hardware default for PF0 of uninitialised Medford.
  57                          * manftest must be able to cope with this device id.
  58                          */
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         return (0);
  61
  62                 case EFX_PCI_DEVID_MEDFORD:
  63                         *efp = EFX_FAMILY_MEDFORD;
  64                         return (0);
  65
  66                 case EFX_PCI_DEVID_MEDFORD_VF:
  67                         *efp = EFX_FAMILY_MEDFORD;
  68                         return (0);
  69 #endif /* EFSYS_OPT_MEDFORD */
  70
  71                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  72                 default:
  73                         break;
  74                 }
  75         }
  76
  77         *efp = EFX_FAMILY_INVALID;
  78         return (ENOTSUP);
  79 }
  80
  81 #if EFSYS_OPT_SIENA
  82
  83 static const efx_nic_ops_t      __efx_nic_siena_ops = {
  84         siena_nic_probe,                /* eno_probe */
  85         NULL,                           /* eno_board_cfg */
  86         NULL,                           /* eno_set_drv_limits */
  87         siena_nic_reset,                /* eno_reset */
  88         siena_nic_init,                 /* eno_init */
  89         NULL,                           /* eno_get_vi_pool */
  90         NULL,                           /* eno_get_bar_region */
  91 #if EFSYS_OPT_DIAG
  92         siena_nic_register_test,        /* eno_register_test */
  93 #endif  /* EFSYS_OPT_DIAG */
  94         siena_nic_fini,                 /* eno_fini */
  95         siena_nic_unprobe,              /* eno_unprobe */
  96 };
  97
  98 #endif  /* EFSYS_OPT_SIENA */
  99
 100 #if EFSYS_OPT_HUNTINGTON
 101
 102 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 103         ef10_nic_probe,                 /* eno_probe */
 104         hunt_board_cfg,                 /* eno_board_cfg */
 105         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 106         ef10_nic_reset,                 /* eno_reset */
 107         ef10_nic_init,                  /* eno_init */
 108         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 109         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 110 #if EFSYS_OPT_DIAG
 111         ef10_nic_register_test,         /* eno_register_test */
 112 #endif  /* EFSYS_OPT_DIAG */
 113         ef10_nic_fini,                  /* eno_fini */
 114         ef10_nic_unprobe,               /* eno_unprobe */
 115 };
 116
 117 #endif  /* EFSYS_OPT_HUNTINGTON */
 118
 119 #if EFSYS_OPT_MEDFORD
 120
 121 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 122         ef10_nic_probe,                 /* eno_probe */
 123         medford_board_cfg,              /* eno_board_cfg */
 124         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 125         ef10_nic_reset,                 /* eno_reset */
 126         ef10_nic_init,                  /* eno_init */
 127         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 128         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 129 #if EFSYS_OPT_DIAG
 130         ef10_nic_register_test,         /* eno_register_test */
 131 #endif  /* EFSYS_OPT_DIAG */
 132         ef10_nic_fini,                  /* eno_fini */
 133         ef10_nic_unprobe,               /* eno_unprobe */
 134 };
 135
 136 #endif  /* EFSYS_OPT_MEDFORD */
 137
 138
 139         __checkReturn   efx_rc_t
 140 efx_nic_create(
 141         __in            efx_family_t family,
 142         __in            efsys_identifier_t *esip,
 143         __in            efsys_bar_t *esbp,
 144         __in            efsys_lock_t *eslp,
 145         __deref_out     efx_nic_t **enpp)
 146 {
 147         efx_nic_t *enp;
 148         efx_rc_t rc;
 149
 150         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 151         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 152
 153         /* Allocate a NIC object */
 154         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 155
 156         if (enp == NULL) {
 157                 rc = ENOMEM;
 158                 goto fail1;
 159         }
 160
 161         enp->en_magic = EFX_NIC_MAGIC;
 162
 163         switch (family) {
 164 #if EFSYS_OPT_SIENA
 165         case EFX_FAMILY_SIENA:
 166                 enp->en_enop = &__efx_nic_siena_ops;
 167                 enp->en_features =
 168                     EFX_FEATURE_IPV6 |
 169                     EFX_FEATURE_LFSR_HASH_INSERT |
 170                     EFX_FEATURE_LINK_EVENTS |
 171                     EFX_FEATURE_PERIODIC_MAC_STATS |
 172                     EFX_FEATURE_MCDI |
 173                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 174                     EFX_FEATURE_MAC_HEADER_FILTERS |
 175                     EFX_FEATURE_TX_SRC_FILTERS;
 176                 break;
 177 #endif  /* EFSYS_OPT_SIENA */
 178
 179 #if EFSYS_OPT_HUNTINGTON
 180         case EFX_FAMILY_HUNTINGTON:
 181                 enp->en_enop = &__efx_nic_hunt_ops;
 182                 enp->en_features =
 183                     EFX_FEATURE_IPV6 |
 184                     EFX_FEATURE_LINK_EVENTS |
 185                     EFX_FEATURE_PERIODIC_MAC_STATS |
 186                     EFX_FEATURE_MCDI |
 187                     EFX_FEATURE_MAC_HEADER_FILTERS |
 188                     EFX_FEATURE_MCDI_DMA |
 189                     EFX_FEATURE_PIO_BUFFERS |
 190                     EFX_FEATURE_FW_ASSISTED_TSO |
 191                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 192                     EFX_FEATURE_PACKED_STREAM;
 193                 break;
 194 #endif  /* EFSYS_OPT_HUNTINGTON */
 195
 196 #if EFSYS_OPT_MEDFORD
 197         case EFX_FAMILY_MEDFORD:
 198                 enp->en_enop = &__efx_nic_medford_ops;
 199                 /*
 200                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 201                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 202                  */
 203                 enp->en_features =
 204                     EFX_FEATURE_IPV6 |
 205                     EFX_FEATURE_LINK_EVENTS |
 206                     EFX_FEATURE_PERIODIC_MAC_STATS |
 207                     EFX_FEATURE_MCDI |
 208                     EFX_FEATURE_MAC_HEADER_FILTERS |
 209                     EFX_FEATURE_MCDI_DMA |
 210                     EFX_FEATURE_PIO_BUFFERS |
 211                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 212                     EFX_FEATURE_PACKED_STREAM;
 213                 break;
 214 #endif  /* EFSYS_OPT_MEDFORD */
 215
 216         default:
 217                 rc = ENOTSUP;
 218                 goto fail2;
 219         }
 220
 221         enp->en_family = family;
 222         enp->en_esip = esip;
 223         enp->en_esbp = esbp;
 224         enp->en_eslp = eslp;
 225
 226         *enpp = enp;
 227
 228         return (0);
 229
 230 fail2:
 231         EFSYS_PROBE(fail2);
 232
 233         enp->en_magic = 0;
 234
 235         /* Free the NIC object */
 236         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 237
 238 fail1:
 239         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 240
 241         return (rc);
 242 }
 243
 244         __checkReturn   efx_rc_t
 245 efx_nic_probe(
 246         __in            efx_nic_t *enp)
 247 {
 248         const efx_nic_ops_t *enop;
 249         efx_rc_t rc;
 250
 251         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 252 #if EFSYS_OPT_MCDI
 253         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 254 #endif  /* EFSYS_OPT_MCDI */
 255         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 256
 257         enop = enp->en_enop;
 258         if ((rc = enop->eno_probe(enp)) != 0)
 259                 goto fail1;
 260
 261         if ((rc = efx_phy_probe(enp)) != 0)
 262                 goto fail2;
 263
 264         enp->en_mod_flags |= EFX_MOD_PROBE;
 265
 266         return (0);
 267
 268 fail2:
 269         EFSYS_PROBE(fail2);
 270
 271         enop->eno_unprobe(enp);
 272
 273 fail1:
 274         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 275
 276         return (rc);
 277 }
 278
 279         __checkReturn   efx_rc_t
 280 efx_nic_set_drv_limits(
 281         __inout         efx_nic_t *enp,
 282         __in            efx_drv_limits_t *edlp)
 283 {
 284         const efx_nic_ops_t *enop = enp->en_enop;
 285         efx_rc_t rc;
 286
 287         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 288         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 289
 290         if (enop->eno_set_drv_limits != NULL) {
 291                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 292                         goto fail1;
 293         }
 294
 295         return (0);
 296
 297 fail1:
 298         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 299
 300         return (rc);
 301 }
 302
 303         __checkReturn   efx_rc_t
 304 efx_nic_get_bar_region(
 305         __in            efx_nic_t *enp,
 306         __in            efx_nic_region_t region,
 307         __out           uint32_t *offsetp,
 308         __out           size_t *sizep)
 309 {
 310         const efx_nic_ops_t *enop = enp->en_enop;
 311         efx_rc_t rc;
 312
 313         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 314         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 315         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 316
 317         if (enop->eno_get_bar_region == NULL) {
 318                 rc = ENOTSUP;
 319                 goto fail1;
 320         }
 321         if ((rc = (enop->eno_get_bar_region)(enp,
 322                     region, offsetp, sizep)) != 0) {
 323                 goto fail2;
 324         }
 325
 326         return (0);
 327
 328 fail2:
 329         EFSYS_PROBE(fail2);
 330
 331 fail1:
 332         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 333
 334         return (rc);
 335 }
 336
 337
 338         __checkReturn   efx_rc_t
 339 efx_nic_get_vi_pool(
 340         __in            efx_nic_t *enp,
 341         __out           uint32_t *evq_countp,
 342         __out           uint32_t *rxq_countp,
 343         __out           uint32_t *txq_countp)
 344 {
 345         const efx_nic_ops_t *enop = enp->en_enop;
 346         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 347         efx_rc_t rc;
 348
 349         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 350         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 351         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 352
 353         if (enop->eno_get_vi_pool != NULL) {
 354                 uint32_t vi_count = 0;
 355
 356                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 357                         goto fail1;
 358
 359                 *evq_countp = vi_count;
 360                 *rxq_countp = vi_count;
 361                 *txq_countp = vi_count;
 362         } else {
 363                 /* Use NIC limits as default value */
 364                 *evq_countp = encp->enc_evq_limit;
 365                 *rxq_countp = encp->enc_rxq_limit;
 366                 *txq_countp = encp->enc_txq_limit;
 367         }
 368
 369         return (0);
 370
 371 fail1:
 372         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 373
 374         return (rc);
 375 }
 376
 377
 378         __checkReturn   efx_rc_t
 379 efx_nic_init(
 380         __in            efx_nic_t *enp)
 381 {
 382         const efx_nic_ops_t *enop = enp->en_enop;
 383         efx_rc_t rc;
 384
 385         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 386         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 387
 388         if (enp->en_mod_flags & EFX_MOD_NIC) {
 389                 rc = EINVAL;
 390                 goto fail1;
 391         }
 392
 393         if ((rc = enop->eno_init(enp)) != 0)
 394                 goto fail2;
 395
 396         enp->en_mod_flags |= EFX_MOD_NIC;
 397
 398         return (0);
 399
 400 fail2:
 401         EFSYS_PROBE(fail2);
 402 fail1:
 403         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 404
 405         return (rc);
 406 }
 407
 408                         void
 409 efx_nic_fini(
 410         __in            efx_nic_t *enp)
 411 {
 412         const efx_nic_ops_t *enop = enp->en_enop;
 413
 414         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 415         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 416         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 417         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 418         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 419         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 420         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 421
 422         enop->eno_fini(enp);
 423
 424         enp->en_mod_flags &= ~EFX_MOD_NIC;
 425 }
 426
 427                         void
 428 efx_nic_unprobe(
 429         __in            efx_nic_t *enp)
 430 {
 431         const efx_nic_ops_t *enop = enp->en_enop;
 432
 433         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 434 #if EFSYS_OPT_MCDI
 435         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 436 #endif  /* EFSYS_OPT_MCDI */
 437         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 438         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 439         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 440         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 441         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 442         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 443
 444         efx_phy_unprobe(enp);
 445
 446         enop->eno_unprobe(enp);
 447
 448         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 449 }
 450
 451                         void
 452 efx_nic_destroy(
 453         __in    efx_nic_t *enp)
 454 {
 455         efsys_identifier_t *esip = enp->en_esip;
 456
 457         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 458         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 459
 460         enp->en_family = EFX_FAMILY_INVALID;
 461         enp->en_esip = NULL;
 462         enp->en_esbp = NULL;
 463         enp->en_eslp = NULL;
 464
 465         enp->en_enop = NULL;
 466
 467         enp->en_magic = 0;
 468
 469         /* Free the NIC object */
 470         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 471 }
 472
 473         __checkReturn   efx_rc_t
 474 efx_nic_reset(
 475         __in            efx_nic_t *enp)
 476 {
 477         const efx_nic_ops_t *enop = enp->en_enop;
 478         unsigned int mod_flags;
 479         efx_rc_t rc;
 480
 481         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 482         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 483         /*
 484          * All modules except the MCDI, PROBE, NVRAM, VPD, MON
 485          * (which we do not reset here) must have been shut down or never
 486          * initialized.
 487          *
 488          * A rule of thumb here is: If the controller or MC reboots, is *any*
 489          * state lost. If it's lost and needs reapplying, then the module
 490          * *must* not be initialised during the reset.
 491          */
 492         mod_flags = enp->en_mod_flags;
 493         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 494                     EFX_MOD_VPD | EFX_MOD_MON);
 495         EFSYS_ASSERT3U(mod_flags, ==, 0);
 496         if (mod_flags != 0) {
 497                 rc = EINVAL;
 498                 goto fail1;
 499         }
 500
 501         if ((rc = enop->eno_reset(enp)) != 0)
 502                 goto fail2;
 503
 504         return (0);
 505
 506 fail2:
 507         EFSYS_PROBE(fail2);
 508 fail1:
 509         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 510
 511         return (rc);
 512 }
 513
 514                         const efx_nic_cfg_t *
 515 efx_nic_cfg_get(
 516         __in            efx_nic_t *enp)
 517 {
 518         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 519
 520         return (&(enp->en_nic_cfg));
 521 }
 522
 523         __checkReturn           efx_rc_t
 524 efx_nic_get_fw_version(
 525         __in                    efx_nic_t *enp,
 526         __out                   efx_nic_fw_info_t *enfip)
 527 {
 528         uint16_t mc_fw_version[4];
 529         efx_rc_t rc;
 530
 531         if (enfip == NULL) {
 532                 rc = EINVAL;
 533                 goto fail1;
 534         }
 535
 536         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 537         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 538
 539         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 540         if (rc != 0)
 541                 goto fail2;
 542
 543         rc = efx_mcdi_get_capabilities(enp, NULL,
 544             &enfip->enfi_rx_dpcpu_fw_id,
 545             &enfip->enfi_tx_dpcpu_fw_id,
 546             NULL, NULL);
 547         if (rc == 0) {
 548                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 549         } else if (rc == ENOTSUP) {
 550                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 551                 enfip->enfi_rx_dpcpu_fw_id = 0;
 552                 enfip->enfi_tx_dpcpu_fw_id = 0;
 553         } else {
 554                 goto fail3;
 555         }
 556
 557         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 558             sizeof (mc_fw_version));
 559
 560         return (0);
 561
 562 fail3:
 563         EFSYS_PROBE(fail3);
 564 fail2:
 565         EFSYS_PROBE(fail2);
 566 fail1:
 567         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 568
 569         return (rc);
 570 }
 571
 572 #if EFSYS_OPT_DIAG
 573
 574         __checkReturn   efx_rc_t
 575 efx_nic_register_test(
 576         __in            efx_nic_t *enp)
 577 {
 578         const efx_nic_ops_t *enop = enp->en_enop;
 579         efx_rc_t rc;
 580
 581         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 582         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 583         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 584
 585         if ((rc = enop->eno_register_test(enp)) != 0)
 586                 goto fail1;
 587
 588         return (0);
 589
 590 fail1:
 591         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 592
 593         return (rc);
 594 }
 595
 596 #endif  /* EFSYS_OPT_DIAG */
 597
 598 #if EFSYS_OPT_LOOPBACK
 599
 600 extern                  void
 601 efx_loopback_mask(
 602         __in    efx_loopback_kind_t loopback_kind,
 603         __out   efx_qword_t *maskp)
 604 {
 605         efx_qword_t mask;
 606
 607         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 608         EFSYS_ASSERT(maskp != NULL);
 609
 610         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */
 611         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
 612         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
 613         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
 614         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
 615         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
 616         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
 617         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
 618         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
 619         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
 620         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
 621         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
 622         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
 623         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
 624         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
 625         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
 626         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
 627         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
 628         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
 629         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XPORT == EFX_LOOPBACK_XPORT);
 630         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII_WS == EFX_LOOPBACK_XGMII_WS);
 631         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS == EFX_LOOPBACK_XAUI_WS);
 632         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_FAR ==
 633             EFX_LOOPBACK_XAUI_WS_FAR);
 634         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_NEAR ==
 635             EFX_LOOPBACK_XAUI_WS_NEAR);
 636         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_WS == EFX_LOOPBACK_GMII_WS);
 637         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS == EFX_LOOPBACK_XFI_WS);
 638         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS_FAR ==
 639             EFX_LOOPBACK_XFI_WS_FAR);
 640         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS_WS == EFX_LOOPBACK_PHYXS_WS);
 641         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT == EFX_LOOPBACK_PMA_INT);
 642         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_NEAR == EFX_LOOPBACK_SD_NEAR);
 643         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FAR == EFX_LOOPBACK_SD_FAR);
 644         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT_WS ==
 645             EFX_LOOPBACK_PMA_INT_WS);
 646         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP2_WS ==
 647             EFX_LOOPBACK_SD_FEP2_WS);
 648         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP1_5_WS ==
 649             EFX_LOOPBACK_SD_FEP1_5_WS);
 650         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP_WS == EFX_LOOPBACK_SD_FEP_WS);
 651         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FES_WS == EFX_LOOPBACK_SD_FES_WS);
 652
 653         /* Build bitmask of possible loopback types */
 654         EFX_ZERO_QWORD(mask);
 655
 656         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 657             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 658                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 659         }
 660
 661         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 662             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 663                 /*
 664                  * The "MAC" grouping has historically been used by drivers to
 665                  * mean loopbacks supported by on-chip hardware. Keep that
 666                  * meaning here, and include on-chip PHY layer loopbacks.
 667                  */
 668                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 669                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 670                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 671                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 672                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 673                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 674                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 675                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 676                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 677                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 678                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 679                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 680                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 681                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 682                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 683                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 684         }
 685
 686         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 687             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 688                 /*
 689                  * The "PHY" grouping has historically been used by drivers to
 690                  * mean loopbacks supported by off-chip hardware. Keep that
 691                  * meaning here.
 692                  */
 693                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 694                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 695                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 696                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 697         }
 698
 699         *maskp = mask;
 700 }
 701
 702         __checkReturn   efx_rc_t
 703 efx_mcdi_get_loopback_modes(
 704         __in            efx_nic_t *enp)
 705 {
 706         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 707         efx_mcdi_req_t req;
 708         uint8_t payload[MAX(MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 709                             MC_CMD_GET_LOOPBACK_MODES_OUT_LEN)];
 710         efx_qword_t mask;
 711         efx_qword_t modes;
 712         efx_rc_t rc;
 713
 714         (void) memset(payload, 0, sizeof (payload));
 715         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 716         req.emr_in_buf = payload;
 717         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 718         req.emr_out_buf = payload;
 719         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_LEN;
 720
 721         efx_mcdi_execute(enp, &req);
 722
 723         if (req.emr_rc != 0) {
 724                 rc = req.emr_rc;
 725                 goto fail1;
 726         }
 727
 728         if (req.emr_out_length_used <
 729             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 730             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 731                 rc = EMSGSIZE;
 732                 goto fail2;
 733         }
 734
 735         /*
 736          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 737          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 738          */
 739         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 740
 741         EFX_AND_QWORD(mask,
 742             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 743
 744         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 745         EFX_AND_QWORD(modes, mask);
 746         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 747
 748         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 749         EFX_AND_QWORD(modes, mask);
 750         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 751
 752         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 753         EFX_AND_QWORD(modes, mask);
 754         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 755
 756         if (req.emr_out_length_used >=
 757             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 758             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 759                 /* Response includes 40G loopback modes */
 760                 modes =
 761                     *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_40G);
 762                 EFX_AND_QWORD(modes, mask);
 763                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 764         }
 765
 766         EFX_ZERO_QWORD(modes);
 767         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
 768         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
 769         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
 770         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
 771         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
 772         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
 773
 774         return (0);
 775
 776 fail2:
 777         EFSYS_PROBE(fail2);
 778 fail1:
 779         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 780
 781         return (rc);
 782 }
 783
 784 #endif /* EFSYS_OPT_LOOPBACK */
 785
 786         __checkReturn   efx_rc_t
 787 efx_nic_calculate_pcie_link_bandwidth(
 788         __in            uint32_t pcie_link_width,
 789         __in            uint32_t pcie_link_gen,
 790         __out           uint32_t *bandwidth_mbpsp)
 791 {
 792         uint32_t lane_bandwidth;
 793         uint32_t total_bandwidth;
 794         efx_rc_t rc;
 795
 796         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
 797             !ISP2(pcie_link_width)) {
 798                 rc = EINVAL;
 799                 goto fail1;
 800         }
 801
 802         switch (pcie_link_gen) {
 803         case EFX_PCIE_LINK_SPEED_GEN1:
 804                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
 805                 lane_bandwidth = 2000;
 806                 break;
 807         case EFX_PCIE_LINK_SPEED_GEN2:
 808                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
 809                 lane_bandwidth = 4000;
 810                 break;
 811         case EFX_PCIE_LINK_SPEED_GEN3:
 812                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
 813                 lane_bandwidth = 7877;
 814                 break;
 815         default:
 816                 rc = EINVAL;
 817                 goto fail2;
 818         }
 819
 820         total_bandwidth = lane_bandwidth * pcie_link_width;
 821         *bandwidth_mbpsp = total_bandwidth;
 822
 823         return (0);
 824
 825 fail2:
 826         EFSYS_PROBE(fail2);
 827 fail1:
 828         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 829
 830         return (rc);
 831 }
 832
 833
 834         __checkReturn   efx_rc_t
 835 efx_nic_check_pcie_link_speed(
 836         __in            efx_nic_t *enp,
 837         __in            uint32_t pcie_link_width,
 838         __in            uint32_t pcie_link_gen,
 839         __out           efx_pcie_link_performance_t *resultp)
 840 {
 841         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 842         uint32_t bandwidth;
 843         efx_pcie_link_performance_t result;
 844         efx_rc_t rc;
 845
 846         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
 847             (pcie_link_width == 0) || (pcie_link_width == 32) ||
 848             (pcie_link_gen == 0)) {
 849                 /*
 850                  * No usable info on what is required and/or in use. In virtual
 851                  * machines, sometimes the PCIe link width is reported as 0 or
 852                  * 32, or the speed as 0.
 853                  */
 854                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
 855                 goto out;
 856         }
 857
 858         /* Calculate the available bandwidth in megabits per second */
 859         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
 860                                             pcie_link_gen, &bandwidth);
 861         if (rc != 0)
 862                 goto fail1;
 863
 864         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
 865                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
 866         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
 867                 /* The link provides enough bandwidth but not optimal latency */
 868                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
 869         } else {
 870                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
 871         }
 872
 873 out:
 874         *resultp = result;
 875
 876         return (0);
 877
 878 fail1:
 879         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 880
 881         return (rc);
 882 }