drivers/net/sfc/base/efx_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_SIENA
  12
  13 static  __checkReturn   efx_rc_t
  14 siena_rx_init(
  15         __in            efx_nic_t *enp);
  16
  17 static                  void
  18 siena_rx_fini(
  19         __in            efx_nic_t *enp);
  20
  21 #if EFSYS_OPT_RX_SCATTER
  22 static  __checkReturn   efx_rc_t
  23 siena_rx_scatter_enable(
  24         __in            efx_nic_t *enp,
  25         __in            unsigned int buf_size);
  26 #endif /* EFSYS_OPT_RX_SCATTER */
  27
  28 #if EFSYS_OPT_RX_SCALE
  29 static  __checkReturn   efx_rc_t
  30 siena_rx_scale_mode_set(
  31         __in            efx_nic_t *enp,
  32         __in            uint32_t rss_context,
  33         __in            efx_rx_hash_alg_t alg,
  34         __in            efx_rx_hash_type_t type,
  35         __in            boolean_t insert);
  36
  37 static  __checkReturn   efx_rc_t
  38 siena_rx_scale_key_set(
  39         __in            efx_nic_t *enp,
  40         __in            uint32_t rss_context,
  41         __in_ecount(n)  uint8_t *key,
  42         __in            size_t n);
  43
  44 static  __checkReturn   efx_rc_t
  45 siena_rx_scale_tbl_set(
  46         __in            efx_nic_t *enp,
  47         __in            uint32_t rss_context,
  48         __in_ecount(n)  unsigned int *table,
  49         __in            size_t n);
  50
  51 static  __checkReturn   uint32_t
  52 siena_rx_prefix_hash(
  53         __in            efx_nic_t *enp,
  54         __in            efx_rx_hash_alg_t func,
  55         __in            uint8_t *buffer);
  56
  57 #endif /* EFSYS_OPT_RX_SCALE */
  58
  59 static  __checkReturn   efx_rc_t
  60 siena_rx_prefix_pktlen(
  61         __in            efx_nic_t *enp,
  62         __in            uint8_t *buffer,
  63         __out           uint16_t *lengthp);
  64
  65 static                          void
  66 siena_rx_qpost(
  67         __in                    efx_rxq_t *erp,
  68         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
  69         __in                    size_t size,
  70         __in                    unsigned int ndescs,
  71         __in                    unsigned int completed,
  72         __in                    unsigned int added);
  73
  74 static                  void
  75 siena_rx_qpush(
  76         __in            efx_rxq_t *erp,
  77         __in            unsigned int added,
  78         __inout         unsigned int *pushedp);
  79
  80 #if EFSYS_OPT_RX_PACKED_STREAM
  81 static          void
  82 siena_rx_qpush_ps_credits(
  83         __in            efx_rxq_t *erp);
  84
  85 static  __checkReturn   uint8_t *
  86 siena_rx_qps_packet_info(
  87         __in            efx_rxq_t *erp,
  88         __in            uint8_t *buffer,
  89         __in            uint32_t buffer_length,
  90         __in            uint32_t current_offset,
  91         __out           uint16_t *lengthp,
  92         __out           uint32_t *next_offsetp,
  93         __out           uint32_t *timestamp);
  94 #endif
  95
  96 static  __checkReturn   efx_rc_t
  97 siena_rx_qflush(
  98         __in            efx_rxq_t *erp);
  99
 100 static                  void
 101 siena_rx_qenable(
 102         __in            efx_rxq_t *erp);
 103
 104 static  __checkReturn   efx_rc_t
 105 siena_rx_qcreate(
 106         __in            efx_nic_t *enp,
 107         __in            unsigned int index,
 108         __in            unsigned int label,
 109         __in            efx_rxq_type_t type,
 110         __in            const efx_rxq_type_data_t *type_data,
 111         __in            efsys_mem_t *esmp,
 112         __in            size_t ndescs,
 113         __in            uint32_t id,
 114         __in            unsigned int flags,
 115         __in            efx_evq_t *eep,
 116         __in            efx_rxq_t *erp);
 117
 118 static                  void
 119 siena_rx_qdestroy(
 120         __in            efx_rxq_t *erp);
 121
 122 #endif /* EFSYS_OPT_SIENA */
 123
 124
 125 #if EFSYS_OPT_SIENA
 126 static const efx_rx_ops_t __efx_rx_siena_ops = {
 127         siena_rx_init,                          /* erxo_init */
 128         siena_rx_fini,                          /* erxo_fini */
 129 #if EFSYS_OPT_RX_SCATTER
 130         siena_rx_scatter_enable,                /* erxo_scatter_enable */
 131 #endif
 132 #if EFSYS_OPT_RX_SCALE
 133         NULL,                                   /* erxo_scale_context_alloc */
 134         NULL,                                   /* erxo_scale_context_free */
 135         siena_rx_scale_mode_set,                /* erxo_scale_mode_set */
 136         siena_rx_scale_key_set,                 /* erxo_scale_key_set */
 137         siena_rx_scale_tbl_set,                 /* erxo_scale_tbl_set */
 138         siena_rx_prefix_hash,                   /* erxo_prefix_hash */
 139 #endif
 140         siena_rx_prefix_pktlen,                 /* erxo_prefix_pktlen */
 141         siena_rx_qpost,                         /* erxo_qpost */
 142         siena_rx_qpush,                         /* erxo_qpush */
 143 #if EFSYS_OPT_RX_PACKED_STREAM
 144         siena_rx_qpush_ps_credits,              /* erxo_qpush_ps_credits */
 145         siena_rx_qps_packet_info,               /* erxo_qps_packet_info */
 146 #endif
 147         siena_rx_qflush,                        /* erxo_qflush */
 148         siena_rx_qenable,                       /* erxo_qenable */
 149         siena_rx_qcreate,                       /* erxo_qcreate */
 150         siena_rx_qdestroy,                      /* erxo_qdestroy */
 151 };
 152 #endif  /* EFSYS_OPT_SIENA */
 153
 154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
 156         ef10_rx_init,                           /* erxo_init */
 157         ef10_rx_fini,                           /* erxo_fini */
 158 #if EFSYS_OPT_RX_SCATTER
 159         ef10_rx_scatter_enable,                 /* erxo_scatter_enable */
 160 #endif
 161 #if EFSYS_OPT_RX_SCALE
 162         ef10_rx_scale_context_alloc,            /* erxo_scale_context_alloc */
 163         ef10_rx_scale_context_free,             /* erxo_scale_context_free */
 164         ef10_rx_scale_mode_set,                 /* erxo_scale_mode_set */
 165         ef10_rx_scale_key_set,                  /* erxo_scale_key_set */
 166         ef10_rx_scale_tbl_set,                  /* erxo_scale_tbl_set */
 167         ef10_rx_prefix_hash,                    /* erxo_prefix_hash */
 168 #endif
 169         ef10_rx_prefix_pktlen,                  /* erxo_prefix_pktlen */
 170         ef10_rx_qpost,                          /* erxo_qpost */
 171         ef10_rx_qpush,                          /* erxo_qpush */
 172 #if EFSYS_OPT_RX_PACKED_STREAM
 173         ef10_rx_qpush_ps_credits,               /* erxo_qpush_ps_credits */
 174         ef10_rx_qps_packet_info,                /* erxo_qps_packet_info */
 175 #endif
 176         ef10_rx_qflush,                         /* erxo_qflush */
 177         ef10_rx_qenable,                        /* erxo_qenable */
 178         ef10_rx_qcreate,                        /* erxo_qcreate */
 179         ef10_rx_qdestroy,                       /* erxo_qdestroy */
 180 };
 181 #endif  /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 182
 183
 184         __checkReturn   efx_rc_t
 185 efx_rx_init(
 186         __inout         efx_nic_t *enp)
 187 {
 188         const efx_rx_ops_t *erxop;
 189         efx_rc_t rc;
 190
 191         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 192         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 193
 194         if (!(enp->en_mod_flags & EFX_MOD_EV)) {
 195                 rc = EINVAL;
 196                 goto fail1;
 197         }
 198
 199         if (enp->en_mod_flags & EFX_MOD_RX) {
 200                 rc = EINVAL;
 201                 goto fail2;
 202         }
 203
 204         switch (enp->en_family) {
 205 #if EFSYS_OPT_SIENA
 206         case EFX_FAMILY_SIENA:
 207                 erxop = &__efx_rx_siena_ops;
 208                 break;
 209 #endif /* EFSYS_OPT_SIENA */
 210
 211 #if EFSYS_OPT_HUNTINGTON
 212         case EFX_FAMILY_HUNTINGTON:
 213                 erxop = &__efx_rx_ef10_ops;
 214                 break;
 215 #endif /* EFSYS_OPT_HUNTINGTON */
 216
 217 #if EFSYS_OPT_MEDFORD
 218         case EFX_FAMILY_MEDFORD:
 219                 erxop = &__efx_rx_ef10_ops;
 220                 break;
 221 #endif /* EFSYS_OPT_MEDFORD */
 222
 223 #if EFSYS_OPT_MEDFORD2
 224         case EFX_FAMILY_MEDFORD2:
 225                 erxop = &__efx_rx_ef10_ops;
 226                 break;
 227 #endif /* EFSYS_OPT_MEDFORD2 */
 228
 229         default:
 230                 EFSYS_ASSERT(0);
 231                 rc = ENOTSUP;
 232                 goto fail3;
 233         }
 234
 235         if ((rc = erxop->erxo_init(enp)) != 0)
 236                 goto fail4;
 237
 238         enp->en_erxop = erxop;
 239         enp->en_mod_flags |= EFX_MOD_RX;
 240         return (0);
 241
 242 fail4:
 243         EFSYS_PROBE(fail4);
 244 fail3:
 245         EFSYS_PROBE(fail3);
 246 fail2:
 247         EFSYS_PROBE(fail2);
 248 fail1:
 249         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 250
 251         enp->en_erxop = NULL;
 252         enp->en_mod_flags &= ~EFX_MOD_RX;
 253         return (rc);
 254 }
 255
 256                         void
 257 efx_rx_fini(
 258         __in            efx_nic_t *enp)
 259 {
 260         const efx_rx_ops_t *erxop = enp->en_erxop;
 261
 262         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 263         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 264         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 265         EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
 266
 267         erxop->erxo_fini(enp);
 268
 269         enp->en_erxop = NULL;
 270         enp->en_mod_flags &= ~EFX_MOD_RX;
 271 }
 272
 273 #if EFSYS_OPT_RX_SCATTER
 274         __checkReturn   efx_rc_t
 275 efx_rx_scatter_enable(
 276         __in            efx_nic_t *enp,
 277         __in            unsigned int buf_size)
 278 {
 279         const efx_rx_ops_t *erxop = enp->en_erxop;
 280         efx_rc_t rc;
 281
 282         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 283         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 284
 285         if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
 286                 goto fail1;
 287
 288         return (0);
 289
 290 fail1:
 291         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 292         return (rc);
 293 }
 294 #endif  /* EFSYS_OPT_RX_SCATTER */
 295
 296 #if EFSYS_OPT_RX_SCALE
 297         __checkReturn                           efx_rc_t
 298 efx_rx_scale_hash_flags_get(
 299         __in                                    efx_nic_t *enp,
 300         __in                                    efx_rx_hash_alg_t hash_alg,
 301         __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
 302         __in                                    unsigned int max_nflags,
 303         __out                                   unsigned int *nflagsp)
 304 {
 305         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 306         unsigned int nflags = 0;
 307         efx_rc_t rc;
 308
 309         if (flagsp == NULL || nflagsp == NULL) {
 310                 rc = EINVAL;
 311                 goto fail1;
 312         }
 313
 314         if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0) {
 315                 nflags = 0;
 316                 goto done;
 317         }
 318
 319         /* Helper to add flags word to flags array without buffer overflow */
 320 #define INSERT_FLAGS(_flags)                    \
 321         do {                                    \
 322                 if (nflags >= max_nflags) {     \
 323                         rc = E2BIG;             \
 324                         goto fail2;             \
 325                 }                               \
 326                 *(flagsp + nflags) = (_flags);  \
 327                 nflags++;                       \
 328                                                 \
 329                 _NOTE(CONSTANTCONDITION)        \
 330         } while (B_FALSE)
 331
 332         if (encp->enc_rx_scale_l4_hash_supported != B_FALSE) {
 333                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 4TUPLE));
 334                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 4TUPLE));
 335         }
 336
 337         if ((encp->enc_rx_scale_l4_hash_supported != B_FALSE) &&
 338             (encp->enc_rx_scale_additional_modes_supported != B_FALSE)) {
 339                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_DST));
 340                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_SRC));
 341
 342                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_DST));
 343                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_SRC));
 344
 345                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 4TUPLE));
 346                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_DST));
 347                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_SRC));
 348
 349                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 4TUPLE));
 350                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_DST));
 351                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_SRC));
 352         }
 353
 354         INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE));
 355         INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE));
 356
 357         INSERT_FLAGS(EFX_RX_HASH(IPV4, 2TUPLE));
 358         INSERT_FLAGS(EFX_RX_HASH(IPV6, 2TUPLE));
 359
 360         if (encp->enc_rx_scale_additional_modes_supported != B_FALSE) {
 361                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_DST));
 362                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_SRC));
 363
 364                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_DST));
 365                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_SRC));
 366
 367                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE));
 368                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_DST));
 369                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_SRC));
 370
 371                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE));
 372                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_DST));
 373                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_SRC));
 374
 375                 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_DST));
 376                 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_SRC));
 377
 378                 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_DST));
 379                 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_SRC));
 380         }
 381
 382         INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, DISABLE));
 383         INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, DISABLE));
 384
 385         INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, DISABLE));
 386         INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, DISABLE));
 387
 388         INSERT_FLAGS(EFX_RX_HASH(IPV4, DISABLE));
 389         INSERT_FLAGS(EFX_RX_HASH(IPV6, DISABLE));
 390
 391 #undef INSERT_FLAGS
 392
 393 done:
 394         *nflagsp = nflags;
 395         return (0);
 396
 397 fail2:
 398         EFSYS_PROBE(fail2);
 399 fail1:
 400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 401
 402         return (rc);
 403 }
 404
 405         __checkReturn   efx_rc_t
 406 efx_rx_hash_default_support_get(
 407         __in            efx_nic_t *enp,
 408         __out           efx_rx_hash_support_t *supportp)
 409 {
 410         efx_rc_t rc;
 411
 412         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 413         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 414
 415         if (supportp == NULL) {
 416                 rc = EINVAL;
 417                 goto fail1;
 418         }
 419
 420         /*
 421          * Report the hashing support the client gets by default if it
 422          * does not allocate an RSS context itself.
 423          */
 424         *supportp = enp->en_hash_support;
 425
 426         return (0);
 427
 428 fail1:
 429         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 430
 431         return (rc);
 432 }
 433
 434         __checkReturn   efx_rc_t
 435 efx_rx_scale_default_support_get(
 436         __in            efx_nic_t *enp,
 437         __out           efx_rx_scale_context_type_t *typep)
 438 {
 439         efx_rc_t rc;
 440
 441         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 442         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 443
 444         if (typep == NULL) {
 445                 rc = EINVAL;
 446                 goto fail1;
 447         }
 448
 449         /*
 450          * Report the RSS support the client gets by default if it
 451          * does not allocate an RSS context itself.
 452          */
 453         *typep = enp->en_rss_context_type;
 454
 455         return (0);
 456
 457 fail1:
 458         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 459
 460         return (rc);
 461 }
 462 #endif  /* EFSYS_OPT_RX_SCALE */
 463
 464 #if EFSYS_OPT_RX_SCALE
 465         __checkReturn   efx_rc_t
 466 efx_rx_scale_context_alloc(
 467         __in            efx_nic_t *enp,
 468         __in            efx_rx_scale_context_type_t type,
 469         __in            uint32_t num_queues,
 470         __out           uint32_t *rss_contextp)
 471 {
 472         const efx_rx_ops_t *erxop = enp->en_erxop;
 473         efx_rc_t rc;
 474
 475         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 476         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 477
 478         if (erxop->erxo_scale_context_alloc == NULL) {
 479                 rc = ENOTSUP;
 480                 goto fail1;
 481         }
 482         if ((rc = erxop->erxo_scale_context_alloc(enp, type,
 483                             num_queues, rss_contextp)) != 0) {
 484                 goto fail2;
 485         }
 486
 487         return (0);
 488
 489 fail2:
 490         EFSYS_PROBE(fail2);
 491 fail1:
 492         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 493         return (rc);
 494 }
 495 #endif  /* EFSYS_OPT_RX_SCALE */
 496
 497 #if EFSYS_OPT_RX_SCALE
 498         __checkReturn   efx_rc_t
 499 efx_rx_scale_context_free(
 500         __in            efx_nic_t *enp,
 501         __in            uint32_t rss_context)
 502 {
 503         const efx_rx_ops_t *erxop = enp->en_erxop;
 504         efx_rc_t rc;
 505
 506         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 507         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 508
 509         if (erxop->erxo_scale_context_free == NULL) {
 510                 rc = ENOTSUP;
 511                 goto fail1;
 512         }
 513         if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
 514                 goto fail2;
 515
 516         return (0);
 517
 518 fail2:
 519         EFSYS_PROBE(fail2);
 520 fail1:
 521         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 522         return (rc);
 523 }
 524 #endif  /* EFSYS_OPT_RX_SCALE */
 525
 526 #if EFSYS_OPT_RX_SCALE
 527         __checkReturn   efx_rc_t
 528 efx_rx_scale_mode_set(
 529         __in            efx_nic_t *enp,
 530         __in            uint32_t rss_context,
 531         __in            efx_rx_hash_alg_t alg,
 532         __in            efx_rx_hash_type_t type,
 533         __in            boolean_t insert)
 534 {
 535         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 536         const efx_rx_ops_t *erxop = enp->en_erxop;
 537         efx_rx_hash_type_t type_check;
 538         unsigned int i;
 539         efx_rc_t rc;
 540
 541         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 542         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 543
 544         /*
 545          * Legacy flags and modern bits cannot be
 546          * used at the same time in the hash type.
 547          */
 548         if ((type & EFX_RX_HASH_LEGACY_MASK) &&
 549             (type & ~EFX_RX_HASH_LEGACY_MASK)) {
 550                 rc = EINVAL;
 551                 goto fail1;
 552         }
 553
 554         /*
 555          * If RSS hash type is represented by additional bits
 556          * in the value, the latter need to be verified since
 557          * not all bit combinations are valid RSS modes. Also,
 558          * depending on the firmware, some valid combinations
 559          * may be unsupported. Discern additional bits in the
 560          * type value and try to recognise valid combinations.
 561          * If some bits remain unrecognised, report the error.
 562          */
 563         type_check = type & ~EFX_RX_HASH_LEGACY_MASK;
 564         if (type_check != 0) {
 565                 unsigned int type_flags[EFX_RX_HASH_NFLAGS];
 566                 unsigned int type_nflags;
 567
 568                 rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags,
 569                                     EFX_ARRAY_SIZE(type_flags), &type_nflags);
 570                 if (rc != 0)
 571                         goto fail2;
 572
 573                 for (i = 0; i < type_nflags; ++i) {
 574                         if ((type_check & type_flags[i]) == type_flags[i])
 575                                 type_check &= ~(type_flags[i]);
 576                 }
 577
 578                 if (type_check != 0) {
 579                         rc = EINVAL;
 580                         goto fail3;
 581                 }
 582         }
 583
 584         /*
 585          * Translate EFX_RX_HASH() flags to their legacy counterparts
 586          * provided that the FW claims no support for additional modes.
 587          */
 588         if (encp->enc_rx_scale_additional_modes_supported == B_FALSE) {
 589                 efx_rx_hash_type_t t_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE) |
 590                                             EFX_RX_HASH(IPV4_TCP, 2TUPLE);
 591                 efx_rx_hash_type_t t_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE) |
 592                                             EFX_RX_HASH(IPV6_TCP, 2TUPLE);
 593                 efx_rx_hash_type_t t_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
 594                 efx_rx_hash_type_t t_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
 595
 596                 if ((type & t_ipv4) == t_ipv4)
 597                         type |= EFX_RX_HASH_IPV4;
 598                 if ((type & t_ipv6) == t_ipv6)
 599                         type |= EFX_RX_HASH_IPV6;
 600
 601                 if (encp->enc_rx_scale_l4_hash_supported == B_TRUE) {
 602                         if ((type & t_ipv4_tcp) == t_ipv4_tcp)
 603                                 type |= EFX_RX_HASH_TCPIPV4;
 604                         if ((type & t_ipv6_tcp) == t_ipv6_tcp)
 605                                 type |= EFX_RX_HASH_TCPIPV6;
 606                 }
 607
 608                 type &= EFX_RX_HASH_LEGACY_MASK;
 609         }
 610
 611         if (erxop->erxo_scale_mode_set != NULL) {
 612                 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
 613                             type, insert)) != 0)
 614                         goto fail4;
 615         }
 616
 617         return (0);
 618
 619 fail4:
 620         EFSYS_PROBE(fail4);
 621 fail3:
 622         EFSYS_PROBE(fail3);
 623 fail2:
 624         EFSYS_PROBE(fail2);
 625 fail1:
 626         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 627         return (rc);
 628 }
 629 #endif  /* EFSYS_OPT_RX_SCALE */
 630
 631 #if EFSYS_OPT_RX_SCALE
 632         __checkReturn   efx_rc_t
 633 efx_rx_scale_key_set(
 634         __in            efx_nic_t *enp,
 635         __in            uint32_t rss_context,
 636         __in_ecount(n)  uint8_t *key,
 637         __in            size_t n)
 638 {
 639         const efx_rx_ops_t *erxop = enp->en_erxop;
 640         efx_rc_t rc;
 641
 642         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 643         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 644
 645         if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
 646                 goto fail1;
 647
 648         return (0);
 649
 650 fail1:
 651         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 652
 653         return (rc);
 654 }
 655 #endif  /* EFSYS_OPT_RX_SCALE */
 656
 657 #if EFSYS_OPT_RX_SCALE
 658         __checkReturn   efx_rc_t
 659 efx_rx_scale_tbl_set(
 660         __in            efx_nic_t *enp,
 661         __in            uint32_t rss_context,
 662         __in_ecount(n)  unsigned int *table,
 663         __in            size_t n)
 664 {
 665         const efx_rx_ops_t *erxop = enp->en_erxop;
 666         efx_rc_t rc;
 667
 668         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 669         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 670
 671         if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
 672                 goto fail1;
 673
 674         return (0);
 675
 676 fail1:
 677         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 678
 679         return (rc);
 680 }
 681 #endif  /* EFSYS_OPT_RX_SCALE */
 682
 683                                 void
 684 efx_rx_qpost(
 685         __in                    efx_rxq_t *erp,
 686         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
 687         __in                    size_t size,
 688         __in                    unsigned int ndescs,
 689         __in                    unsigned int completed,
 690         __in                    unsigned int added)
 691 {
 692         efx_nic_t *enp = erp->er_enp;
 693         const efx_rx_ops_t *erxop = enp->en_erxop;
 694
 695         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 696
 697         erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
 698 }
 699
 700 #if EFSYS_OPT_RX_PACKED_STREAM
 701
 702                         void
 703 efx_rx_qpush_ps_credits(
 704         __in            efx_rxq_t *erp)
 705 {
 706         efx_nic_t *enp = erp->er_enp;
 707         const efx_rx_ops_t *erxop = enp->en_erxop;
 708
 709         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 710
 711         erxop->erxo_qpush_ps_credits(erp);
 712 }
 713
 714         __checkReturn   uint8_t *
 715 efx_rx_qps_packet_info(
 716         __in            efx_rxq_t *erp,
 717         __in            uint8_t *buffer,
 718         __in            uint32_t buffer_length,
 719         __in            uint32_t current_offset,
 720         __out           uint16_t *lengthp,
 721         __out           uint32_t *next_offsetp,
 722         __out           uint32_t *timestamp)
 723 {
 724         efx_nic_t *enp = erp->er_enp;
 725         const efx_rx_ops_t *erxop = enp->en_erxop;
 726
 727         return (erxop->erxo_qps_packet_info(erp, buffer,
 728                 buffer_length, current_offset, lengthp,
 729                 next_offsetp, timestamp));
 730 }
 731
 732 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
 733
 734                         void
 735 efx_rx_qpush(
 736         __in            efx_rxq_t *erp,
 737         __in            unsigned int added,
 738         __inout         unsigned int *pushedp)
 739 {
 740         efx_nic_t *enp = erp->er_enp;
 741         const efx_rx_ops_t *erxop = enp->en_erxop;
 742
 743         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 744
 745         erxop->erxo_qpush(erp, added, pushedp);
 746 }
 747
 748         __checkReturn   efx_rc_t
 749 efx_rx_qflush(
 750         __in            efx_rxq_t *erp)
 751 {
 752         efx_nic_t *enp = erp->er_enp;
 753         const efx_rx_ops_t *erxop = enp->en_erxop;
 754         efx_rc_t rc;
 755
 756         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 757
 758         if ((rc = erxop->erxo_qflush(erp)) != 0)
 759                 goto fail1;
 760
 761         return (0);
 762
 763 fail1:
 764         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 765
 766         return (rc);
 767 }
 768
 769                         void
 770 efx_rx_qenable(
 771         __in            efx_rxq_t *erp)
 772 {
 773         efx_nic_t *enp = erp->er_enp;
 774         const efx_rx_ops_t *erxop = enp->en_erxop;
 775
 776         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 777
 778         erxop->erxo_qenable(erp);
 779 }
 780
 781 static  __checkReturn   efx_rc_t
 782 efx_rx_qcreate_internal(
 783         __in            efx_nic_t *enp,
 784         __in            unsigned int index,
 785         __in            unsigned int label,
 786         __in            efx_rxq_type_t type,
 787         __in            const efx_rxq_type_data_t *type_data,
 788         __in            efsys_mem_t *esmp,
 789         __in            size_t ndescs,
 790         __in            uint32_t id,
 791         __in            unsigned int flags,
 792         __in            efx_evq_t *eep,
 793         __deref_out     efx_rxq_t **erpp)
 794 {
 795         const efx_rx_ops_t *erxop = enp->en_erxop;
 796         efx_rxq_t *erp;
 797         efx_rc_t rc;
 798
 799         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 800         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 801
 802         /* Allocate an RXQ object */
 803         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
 804
 805         if (erp == NULL) {
 806                 rc = ENOMEM;
 807                 goto fail1;
 808         }
 809
 810         erp->er_magic = EFX_RXQ_MAGIC;
 811         erp->er_enp = enp;
 812         erp->er_index = index;
 813         erp->er_mask = ndescs - 1;
 814         erp->er_esmp = esmp;
 815
 816         if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
 817             ndescs, id, flags, eep, erp)) != 0)
 818                 goto fail2;
 819
 820         enp->en_rx_qcount++;
 821         *erpp = erp;
 822
 823         return (0);
 824
 825 fail2:
 826         EFSYS_PROBE(fail2);
 827
 828         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
 829 fail1:
 830         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 831
 832         return (rc);
 833 }
 834
 835         __checkReturn   efx_rc_t
 836 efx_rx_qcreate(
 837         __in            efx_nic_t *enp,
 838         __in            unsigned int index,
 839         __in            unsigned int label,
 840         __in            efx_rxq_type_t type,
 841         __in            efsys_mem_t *esmp,
 842         __in            size_t ndescs,
 843         __in            uint32_t id,
 844         __in            unsigned int flags,
 845         __in            efx_evq_t *eep,
 846         __deref_out     efx_rxq_t **erpp)
 847 {
 848         return efx_rx_qcreate_internal(enp, index, label, type, NULL,
 849             esmp, ndescs, id, flags, eep, erpp);
 850 }
 851
 852 #if EFSYS_OPT_RX_PACKED_STREAM
 853
 854         __checkReturn   efx_rc_t
 855 efx_rx_qcreate_packed_stream(
 856         __in            efx_nic_t *enp,
 857         __in            unsigned int index,
 858         __in            unsigned int label,
 859         __in            uint32_t ps_buf_size,
 860         __in            efsys_mem_t *esmp,
 861         __in            size_t ndescs,
 862         __in            efx_evq_t *eep,
 863         __deref_out     efx_rxq_t **erpp)
 864 {
 865         efx_rxq_type_data_t type_data;
 866
 867         memset(&type_data, 0, sizeof (type_data));
 868
 869         type_data.ertd_packed_stream.eps_buf_size = ps_buf_size;
 870
 871         return efx_rx_qcreate_internal(enp, index, label,
 872             EFX_RXQ_TYPE_PACKED_STREAM, &type_data, esmp, ndescs,
 873             0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
 874 }
 875
 876 #endif
 877
 878 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 879
 880         __checkReturn   efx_rc_t
 881 efx_rx_qcreate_es_super_buffer(
 882         __in            efx_nic_t *enp,
 883         __in            unsigned int index,
 884         __in            unsigned int label,
 885         __in            uint32_t n_bufs_per_desc,
 886         __in            uint32_t max_dma_len,
 887         __in            uint32_t buf_stride,
 888         __in            uint32_t hol_block_timeout,
 889         __in            efsys_mem_t *esmp,
 890         __in            size_t ndescs,
 891         __in            unsigned int flags,
 892         __in            efx_evq_t *eep,
 893         __deref_out     efx_rxq_t **erpp)
 894 {
 895         efx_rc_t rc;
 896         efx_rxq_type_data_t type_data;
 897
 898         if (hol_block_timeout > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) {
 899                 rc = EINVAL;
 900                 goto fail1;
 901         }
 902
 903         memset(&type_data, 0, sizeof (type_data));
 904
 905         type_data.ertd_es_super_buffer.eessb_bufs_per_desc = n_bufs_per_desc;
 906         type_data.ertd_es_super_buffer.eessb_max_dma_len = max_dma_len;
 907         type_data.ertd_es_super_buffer.eessb_buf_stride = buf_stride;
 908         type_data.ertd_es_super_buffer.eessb_hol_block_timeout =
 909             hol_block_timeout;
 910
 911         rc = efx_rx_qcreate_internal(enp, index, label,
 912             EFX_RXQ_TYPE_ES_SUPER_BUFFER, &type_data, esmp, ndescs,
 913             0 /* id unused on EF10 */, flags, eep, erpp);
 914         if (rc != 0)
 915                 goto fail2;
 916
 917         return (0);
 918
 919 fail2:
 920         EFSYS_PROBE(fail2);
 921 fail1:
 922         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 923
 924         return (rc);
 925 }
 926
 927 #endif
 928
 929
 930                         void
 931 efx_rx_qdestroy(
 932         __in            efx_rxq_t *erp)
 933 {
 934         efx_nic_t *enp = erp->er_enp;
 935         const efx_rx_ops_t *erxop = enp->en_erxop;
 936
 937         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 938
 939         erxop->erxo_qdestroy(erp);
 940 }
 941
 942         __checkReturn   efx_rc_t
 943 efx_pseudo_hdr_pkt_length_get(
 944         __in            efx_rxq_t *erp,
 945         __in            uint8_t *buffer,
 946         __out           uint16_t *lengthp)
 947 {
 948         efx_nic_t *enp = erp->er_enp;
 949         const efx_rx_ops_t *erxop = enp->en_erxop;
 950
 951         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 952
 953         return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
 954 }
 955
 956 #if EFSYS_OPT_RX_SCALE
 957         __checkReturn   uint32_t
 958 efx_pseudo_hdr_hash_get(
 959         __in            efx_rxq_t *erp,
 960         __in            efx_rx_hash_alg_t func,
 961         __in            uint8_t *buffer)
 962 {
 963         efx_nic_t *enp = erp->er_enp;
 964         const efx_rx_ops_t *erxop = enp->en_erxop;
 965
 966         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 967
 968         EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
 969         return (erxop->erxo_prefix_hash(enp, func, buffer));
 970 }
 971 #endif  /* EFSYS_OPT_RX_SCALE */
 972
 973 #if EFSYS_OPT_SIENA
 974
 975 static  __checkReturn   efx_rc_t
 976 siena_rx_init(
 977         __in            efx_nic_t *enp)
 978 {
 979         efx_oword_t oword;
 980         unsigned int index;
 981
 982         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
 983
 984         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
 985         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
 986         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
 987         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
 988         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
 989         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
 990         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
 991
 992         /* Zero the RSS table */
 993         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
 994             index++) {
 995                 EFX_ZERO_OWORD(oword);
 996                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
 997                                     index, &oword, B_TRUE);
 998         }
 999
1000 #if EFSYS_OPT_RX_SCALE
1001         /* The RSS key and indirection table are writable. */
1002         enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
1003
1004         /* Hardware can insert RX hash with/without RSS */
1005         enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
1006 #endif  /* EFSYS_OPT_RX_SCALE */
1007
1008         return (0);
1009 }
1010
1011 #if EFSYS_OPT_RX_SCATTER
1012 static  __checkReturn   efx_rc_t
1013 siena_rx_scatter_enable(
1014         __in            efx_nic_t *enp,
1015         __in            unsigned int buf_size)
1016 {
1017         unsigned int nbuf32;
1018         efx_oword_t oword;
1019         efx_rc_t rc;
1020
1021         nbuf32 = buf_size / 32;
1022         if ((nbuf32 == 0) ||
1023             (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
1024             ((buf_size % 32) != 0)) {
1025                 rc = EINVAL;
1026                 goto fail1;
1027         }
1028
1029         if (enp->en_rx_qcount > 0) {
1030                 rc = EBUSY;
1031                 goto fail2;
1032         }
1033
1034         /* Set scatter buffer size */
1035         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1036         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
1037         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1038
1039         /* Enable scatter for packets not matching a filter */
1040         EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1041         EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
1042         EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1043
1044         return (0);
1045
1046 fail2:
1047         EFSYS_PROBE(fail2);
1048 fail1:
1049         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1050
1051         return (rc);
1052 }
1053 #endif  /* EFSYS_OPT_RX_SCATTER */
1054
1055
1056 #define EFX_RX_LFSR_HASH(_enp, _insert)                                 \
1057         do {                                                            \
1058                 efx_oword_t oword;                                      \
1059                                                                         \
1060                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
1061                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);      \
1062                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);       \
1063                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);       \
1064                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
1065                     (_insert) ? 1 : 0);                                 \
1066                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
1067                                                                         \
1068                 if ((_enp)->en_family == EFX_FAMILY_SIENA) {            \
1069                         EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3,   \
1070                             &oword);                                    \
1071                         EFX_SET_OWORD_FIELD(oword,                      \
1072                             FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0);        \
1073                         EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3,  \
1074                             &oword);                                    \
1075                 }                                                       \
1076                                                                         \
1077                 _NOTE(CONSTANTCONDITION)                                \
1078         } while (B_FALSE)
1079
1080 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp)             \
1081         do {                                                            \
1082                 efx_oword_t oword;                                      \
1083                                                                         \
1084                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
1085                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1);      \
1086                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH,           \
1087                     (_ip) ? 1 : 0);                                     \
1088                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP,           \
1089                     (_tcp) ? 0 : 1);                                    \
1090                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
1091                     (_insert) ? 1 : 0);                                 \
1092                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
1093                                                                         \
1094                 _NOTE(CONSTANTCONDITION)                                \
1095         } while (B_FALSE)
1096
1097 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc)                 \
1098         do {                                                            \
1099                 efx_oword_t oword;                                      \
1100                                                                         \
1101                 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword);  \
1102                 EFX_SET_OWORD_FIELD(oword,                              \
1103                     FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1);                \
1104                 EFX_SET_OWORD_FIELD(oword,                              \
1105                     FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1106                 EFX_SET_OWORD_FIELD(oword,                              \
1107                     FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1);   \
1108                 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1109                                                                         \
1110                 (_rc) = 0;                                              \
1111                                                                         \
1112                 _NOTE(CONSTANTCONDITION)                                \
1113         } while (B_FALSE)
1114
1115
1116 #if EFSYS_OPT_RX_SCALE
1117
1118 static  __checkReturn   efx_rc_t
1119 siena_rx_scale_mode_set(
1120         __in            efx_nic_t *enp,
1121         __in            uint32_t rss_context,
1122         __in            efx_rx_hash_alg_t alg,
1123         __in            efx_rx_hash_type_t type,
1124         __in            boolean_t insert)
1125 {
1126         efx_rc_t rc;
1127
1128         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1129                 rc = EINVAL;
1130                 goto fail1;
1131         }
1132
1133         switch (alg) {
1134         case EFX_RX_HASHALG_LFSR:
1135                 EFX_RX_LFSR_HASH(enp, insert);
1136                 break;
1137
1138         case EFX_RX_HASHALG_TOEPLITZ:
1139                 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1140                     (type & EFX_RX_HASH_IPV4) ? B_TRUE : B_FALSE,
1141                     (type & EFX_RX_HASH_TCPIPV4) ? B_TRUE : B_FALSE);
1142
1143                 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1144                     (type & EFX_RX_HASH_IPV6) ? B_TRUE : B_FALSE,
1145                     (type & EFX_RX_HASH_TCPIPV6) ? B_TRUE : B_FALSE,
1146                     rc);
1147                 if (rc != 0)
1148                         goto fail2;
1149
1150                 break;
1151
1152         default:
1153                 rc = EINVAL;
1154                 goto fail3;
1155         }
1156
1157         return (0);
1158
1159 fail3:
1160         EFSYS_PROBE(fail3);
1161 fail2:
1162         EFSYS_PROBE(fail2);
1163 fail1:
1164         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1165
1166         EFX_RX_LFSR_HASH(enp, B_FALSE);
1167
1168         return (rc);
1169 }
1170 #endif
1171
1172 #if EFSYS_OPT_RX_SCALE
1173 static  __checkReturn   efx_rc_t
1174 siena_rx_scale_key_set(
1175         __in            efx_nic_t *enp,
1176         __in            uint32_t rss_context,
1177         __in_ecount(n)  uint8_t *key,
1178         __in            size_t n)
1179 {
1180         efx_oword_t oword;
1181         unsigned int byte;
1182         unsigned int offset;
1183         efx_rc_t rc;
1184
1185         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1186                 rc = EINVAL;
1187                 goto fail1;
1188         }
1189
1190         byte = 0;
1191
1192         /* Write Toeplitz IPv4 hash key */
1193         EFX_ZERO_OWORD(oword);
1194         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1195             offset > 0 && byte < n;
1196             --offset)
1197                 oword.eo_u8[offset - 1] = key[byte++];
1198
1199         EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1200
1201         byte = 0;
1202
1203         /* Verify Toeplitz IPv4 hash key */
1204         EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1205         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1206             offset > 0 && byte < n;
1207             --offset) {
1208                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1209                         rc = EFAULT;
1210                         goto fail2;
1211                 }
1212         }
1213
1214         if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1215                 goto done;
1216
1217         byte = 0;
1218
1219         /* Write Toeplitz IPv6 hash key 3 */
1220         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1221         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1222             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1223             offset > 0 && byte < n;
1224             --offset)
1225                 oword.eo_u8[offset - 1] = key[byte++];
1226
1227         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1228
1229         /* Write Toeplitz IPv6 hash key 2 */
1230         EFX_ZERO_OWORD(oword);
1231         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1232             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1233             offset > 0 && byte < n;
1234             --offset)
1235                 oword.eo_u8[offset - 1] = key[byte++];
1236
1237         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1238
1239         /* Write Toeplitz IPv6 hash key 1 */
1240         EFX_ZERO_OWORD(oword);
1241         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1242             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1243             offset > 0 && byte < n;
1244             --offset)
1245                 oword.eo_u8[offset - 1] = key[byte++];
1246
1247         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1248
1249         byte = 0;
1250
1251         /* Verify Toeplitz IPv6 hash key 3 */
1252         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1253         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1254             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1255             offset > 0 && byte < n;
1256             --offset) {
1257                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1258                         rc = EFAULT;
1259                         goto fail3;
1260                 }
1261         }
1262
1263         /* Verify Toeplitz IPv6 hash key 2 */
1264         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1265         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1266             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1267             offset > 0 && byte < n;
1268             --offset) {
1269                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1270                         rc = EFAULT;
1271                         goto fail4;
1272                 }
1273         }
1274
1275         /* Verify Toeplitz IPv6 hash key 1 */
1276         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1277         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1278             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1279             offset > 0 && byte < n;
1280             --offset) {
1281                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1282                         rc = EFAULT;
1283                         goto fail5;
1284                 }
1285         }
1286
1287 done:
1288         return (0);
1289
1290 fail5:
1291         EFSYS_PROBE(fail5);
1292 fail4:
1293         EFSYS_PROBE(fail4);
1294 fail3:
1295         EFSYS_PROBE(fail3);
1296 fail2:
1297         EFSYS_PROBE(fail2);
1298 fail1:
1299         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1300
1301         return (rc);
1302 }
1303 #endif
1304
1305 #if EFSYS_OPT_RX_SCALE
1306 static  __checkReturn   efx_rc_t
1307 siena_rx_scale_tbl_set(
1308         __in            efx_nic_t *enp,
1309         __in            uint32_t rss_context,
1310         __in_ecount(n)  unsigned int *table,
1311         __in            size_t n)
1312 {
1313         efx_oword_t oword;
1314         int index;
1315         efx_rc_t rc;
1316
1317         EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1318         EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1319
1320         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1321                 rc = EINVAL;
1322                 goto fail1;
1323         }
1324
1325         if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1326                 rc = EINVAL;
1327                 goto fail2;
1328         }
1329
1330         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1331                 uint32_t byte;
1332
1333                 /* Calculate the entry to place in the table */
1334                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1335
1336                 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1337
1338                 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1339
1340                 /* Write the table */
1341                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1342                                     index, &oword, B_TRUE);
1343         }
1344
1345         for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1346                 uint32_t byte;
1347
1348                 /* Determine if we're starting a new batch */
1349                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1350
1351                 /* Read the table */
1352                 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1353                                     index, &oword, B_TRUE);
1354
1355                 /* Verify the entry */
1356                 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1357                         rc = EFAULT;
1358                         goto fail3;
1359                 }
1360         }
1361
1362         return (0);
1363
1364 fail3:
1365         EFSYS_PROBE(fail3);
1366 fail2:
1367         EFSYS_PROBE(fail2);
1368 fail1:
1369         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1370
1371         return (rc);
1372 }
1373 #endif
1374
1375 /*
1376  * Falcon/Siena pseudo-header
1377  * --------------------------
1378  *
1379  * Receive packets are prefixed by an optional 16 byte pseudo-header.
1380  * The pseudo-header is a byte array of one of the forms:
1381  *
1382  *  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
1383  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1384  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1385  *
1386  * where:
1387  *   TT.TT.TT.TT   Toeplitz hash (32-bit big-endian)
1388  *   LL.LL         LFSR hash     (16-bit big-endian)
1389  */
1390
1391 #if EFSYS_OPT_RX_SCALE
1392 static  __checkReturn   uint32_t
1393 siena_rx_prefix_hash(
1394         __in            efx_nic_t *enp,
1395         __in            efx_rx_hash_alg_t func,
1396         __in            uint8_t *buffer)
1397 {
1398         _NOTE(ARGUNUSED(enp))
1399
1400         switch (func) {
1401         case EFX_RX_HASHALG_TOEPLITZ:
1402                 return ((buffer[12] << 24) |
1403                     (buffer[13] << 16) |
1404                     (buffer[14] <<  8) |
1405                     buffer[15]);
1406
1407         case EFX_RX_HASHALG_LFSR:
1408                 return ((buffer[14] << 8) | buffer[15]);
1409
1410         default:
1411                 EFSYS_ASSERT(0);
1412                 return (0);
1413         }
1414 }
1415 #endif /* EFSYS_OPT_RX_SCALE */
1416
1417 static  __checkReturn   efx_rc_t
1418 siena_rx_prefix_pktlen(
1419         __in            efx_nic_t *enp,
1420         __in            uint8_t *buffer,
1421         __out           uint16_t *lengthp)
1422 {
1423         _NOTE(ARGUNUSED(enp, buffer, lengthp))
1424
1425         /* Not supported by Falcon/Siena hardware */
1426         EFSYS_ASSERT(0);
1427         return (ENOTSUP);
1428 }
1429
1430
1431 static                          void
1432 siena_rx_qpost(
1433         __in                    efx_rxq_t *erp,
1434         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
1435         __in                    size_t size,
1436         __in                    unsigned int ndescs,
1437         __in                    unsigned int completed,
1438         __in                    unsigned int added)
1439 {
1440         efx_qword_t qword;
1441         unsigned int i;
1442         unsigned int offset;
1443         unsigned int id;
1444
1445         /* The client driver must not overfill the queue */
1446         EFSYS_ASSERT3U(added - completed + ndescs, <=,
1447             EFX_RXQ_LIMIT(erp->er_mask + 1));
1448
1449         id = added & (erp->er_mask);
1450         for (i = 0; i < ndescs; i++) {
1451                 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1452                     unsigned int, id, efsys_dma_addr_t, addrp[i],
1453                     size_t, size);
1454
1455                 EFX_POPULATE_QWORD_3(qword,
1456                     FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1457                     FSF_AZ_RX_KER_BUF_ADDR_DW0,
1458                     (uint32_t)(addrp[i] & 0xffffffff),
1459                     FSF_AZ_RX_KER_BUF_ADDR_DW1,
1460                     (uint32_t)(addrp[i] >> 32));
1461
1462                 offset = id * sizeof (efx_qword_t);
1463                 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1464
1465                 id = (id + 1) & (erp->er_mask);
1466         }
1467 }
1468
1469 static                  void
1470 siena_rx_qpush(
1471         __in    efx_rxq_t *erp,
1472         __in    unsigned int added,
1473         __inout unsigned int *pushedp)
1474 {
1475         efx_nic_t *enp = erp->er_enp;
1476         unsigned int pushed = *pushedp;
1477         uint32_t wptr;
1478         efx_oword_t oword;
1479         efx_dword_t dword;
1480
1481         /* All descriptors are pushed */
1482         *pushedp = added;
1483
1484         /* Push the populated descriptors out */
1485         wptr = added & erp->er_mask;
1486
1487         EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1488
1489         /* Only write the third DWORD */
1490         EFX_POPULATE_DWORD_1(dword,
1491             EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1492
1493         /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1494         EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1495             wptr, pushed & erp->er_mask);
1496         EFSYS_PIO_WRITE_BARRIER();
1497         EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1498                             erp->er_index, &dword, B_FALSE);
1499 }
1500
1501 #if EFSYS_OPT_RX_PACKED_STREAM
1502 static          void
1503 siena_rx_qpush_ps_credits(
1504         __in            efx_rxq_t *erp)
1505 {
1506         /* Not supported by Siena hardware */
1507         EFSYS_ASSERT(0);
1508 }
1509
1510 static          uint8_t *
1511 siena_rx_qps_packet_info(
1512         __in            efx_rxq_t *erp,
1513         __in            uint8_t *buffer,
1514         __in            uint32_t buffer_length,
1515         __in            uint32_t current_offset,
1516         __out           uint16_t *lengthp,
1517         __out           uint32_t *next_offsetp,
1518         __out           uint32_t *timestamp)
1519 {
1520         /* Not supported by Siena hardware */
1521         EFSYS_ASSERT(0);
1522
1523         return (NULL);
1524 }
1525 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1526
1527 static  __checkReturn   efx_rc_t
1528 siena_rx_qflush(
1529         __in    efx_rxq_t *erp)
1530 {
1531         efx_nic_t *enp = erp->er_enp;
1532         efx_oword_t oword;
1533         uint32_t label;
1534
1535         label = erp->er_index;
1536
1537         /* Flush the queue */
1538         EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1539             FRF_AZ_RX_FLUSH_DESCQ, label);
1540         EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1541
1542         return (0);
1543 }
1544
1545 static          void
1546 siena_rx_qenable(
1547         __in    efx_rxq_t *erp)
1548 {
1549         efx_nic_t *enp = erp->er_enp;
1550         efx_oword_t oword;
1551
1552         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1553
1554         EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1555                             erp->er_index, &oword, B_TRUE);
1556
1557         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1558         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1559         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1560
1561         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1562                             erp->er_index, &oword, B_TRUE);
1563 }
1564
1565 static  __checkReturn   efx_rc_t
1566 siena_rx_qcreate(
1567         __in            efx_nic_t *enp,
1568         __in            unsigned int index,
1569         __in            unsigned int label,
1570         __in            efx_rxq_type_t type,
1571         __in            const efx_rxq_type_data_t *type_data,
1572         __in            efsys_mem_t *esmp,
1573         __in            size_t ndescs,
1574         __in            uint32_t id,
1575         __in            unsigned int flags,
1576         __in            efx_evq_t *eep,
1577         __in            efx_rxq_t *erp)
1578 {
1579         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1580         efx_oword_t oword;
1581         uint32_t size;
1582         boolean_t jumbo = B_FALSE;
1583         efx_rc_t rc;
1584
1585         _NOTE(ARGUNUSED(esmp))
1586         _NOTE(ARGUNUSED(type_data))
1587
1588         EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1589             (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1590         EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1591         EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1592
1593         EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
1594         EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
1595
1596         if (!ISP2(ndescs) ||
1597             (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
1598                 rc = EINVAL;
1599                 goto fail1;
1600         }
1601         if (index >= encp->enc_rxq_limit) {
1602                 rc = EINVAL;
1603                 goto fail2;
1604         }
1605         for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
1606             size++)
1607                 if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
1608                         break;
1609         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1610                 rc = EINVAL;
1611                 goto fail3;
1612         }
1613
1614         switch (type) {
1615         case EFX_RXQ_TYPE_DEFAULT:
1616                 break;
1617
1618         default:
1619                 rc = EINVAL;
1620                 goto fail4;
1621         }
1622
1623         if (flags & EFX_RXQ_FLAG_SCATTER) {
1624 #if EFSYS_OPT_RX_SCATTER
1625                 jumbo = B_TRUE;
1626 #else
1627                 rc = EINVAL;
1628                 goto fail5;
1629 #endif  /* EFSYS_OPT_RX_SCATTER */
1630         }
1631
1632         /* Set up the new descriptor queue */
1633         EFX_POPULATE_OWORD_7(oword,
1634             FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1635             FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1636             FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1637             FRF_AZ_RX_DESCQ_LABEL, label,
1638             FRF_AZ_RX_DESCQ_SIZE, size,
1639             FRF_AZ_RX_DESCQ_TYPE, 0,
1640             FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1641
1642         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1643                             erp->er_index, &oword, B_TRUE);
1644
1645         return (0);
1646
1647 #if !EFSYS_OPT_RX_SCATTER
1648 fail5:
1649         EFSYS_PROBE(fail5);
1650 #endif
1651 fail4:
1652         EFSYS_PROBE(fail4);
1653 fail3:
1654         EFSYS_PROBE(fail3);
1655 fail2:
1656         EFSYS_PROBE(fail2);
1657 fail1:
1658         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1659
1660         return (rc);
1661 }
1662
1663 static          void
1664 siena_rx_qdestroy(
1665         __in    efx_rxq_t *erp)
1666 {
1667         efx_nic_t *enp = erp->er_enp;
1668         efx_oword_t oword;
1669
1670         EFSYS_ASSERT(enp->en_rx_qcount != 0);
1671         --enp->en_rx_qcount;
1672
1673         /* Purge descriptor queue */
1674         EFX_ZERO_OWORD(oword);
1675
1676         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1677                             erp->er_index, &oword, B_TRUE);
1678
1679         /* Free the RXQ object */
1680         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1681 }
1682
1683 static          void
1684 siena_rx_fini(
1685         __in    efx_nic_t *enp)
1686 {
1687         _NOTE(ARGUNUSED(enp))
1688 }
1689
1690 #endif /* EFSYS_OPT_SIENA */