2 * Copyright (c) 2009-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
38 __in uint32_t mcdi_cap,
39 __out uint32_t *maskp)
44 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN))
45 mask |= (1 << EFX_PHY_CAP_10HDX);
46 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN))
47 mask |= (1 << EFX_PHY_CAP_10FDX);
48 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN))
49 mask |= (1 << EFX_PHY_CAP_100HDX);
50 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN))
51 mask |= (1 << EFX_PHY_CAP_100FDX);
52 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN))
53 mask |= (1 << EFX_PHY_CAP_1000HDX);
54 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN))
55 mask |= (1 << EFX_PHY_CAP_1000FDX);
56 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN))
57 mask |= (1 << EFX_PHY_CAP_10000FDX);
58 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN))
59 mask |= (1 << EFX_PHY_CAP_PAUSE);
60 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN))
61 mask |= (1 << EFX_PHY_CAP_ASYM);
62 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
63 mask |= (1 << EFX_PHY_CAP_AN);
69 siena_phy_decode_link_mode(
71 __in uint32_t link_flags,
72 __in unsigned int speed,
73 __in unsigned int fcntl,
74 __out efx_link_mode_t *link_modep,
75 __out unsigned int *fcntlp)
77 boolean_t fd = !!(link_flags &
78 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
79 boolean_t up = !!(link_flags &
80 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
85 *link_modep = EFX_LINK_DOWN;
86 else if (speed == 10000 && fd)
87 *link_modep = EFX_LINK_10000FDX;
88 else if (speed == 1000)
89 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX;
90 else if (speed == 100)
91 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX;
93 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX;
95 *link_modep = EFX_LINK_UNKNOWN;
97 if (fcntl == MC_CMD_FCNTL_OFF)
99 else if (fcntl == MC_CMD_FCNTL_RESPOND)
100 *fcntlp = EFX_FCNTL_RESPOND;
101 else if (fcntl == MC_CMD_FCNTL_BIDIR)
102 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
104 EFSYS_PROBE1(mc_pcol_error, int, fcntl);
112 __in efx_qword_t *eqp,
113 __out efx_link_mode_t *link_modep)
115 efx_port_t *epp = &(enp->en_port);
116 unsigned int link_flags;
119 efx_link_mode_t link_mode;
120 uint32_t lp_cap_mask;
123 * Convert the LINKCHANGE speed enumeration into mbit/s, in the
124 * same way as GET_LINK encodes the speed
126 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) {
127 case MCDI_EVENT_LINKCHANGE_SPEED_100M:
130 case MCDI_EVENT_LINKCHANGE_SPEED_1G:
133 case MCDI_EVENT_LINKCHANGE_SPEED_10G:
141 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS);
142 siena_phy_decode_link_mode(enp, link_flags, speed,
143 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL),
145 siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP),
149 * It's safe to update ep_lp_cap_mask without the driver's port lock
150 * because presumably any concurrently running efx_port_poll() is
151 * only going to arrive at the same value.
153 * ep_fcntl has two meanings. It's either the link common fcntl
154 * (if the PHY supports AN), or it's the forced link state. If
155 * the former, it's safe to update the value for the same reason as
156 * for ep_lp_cap_mask. If the latter, then just ignore the value,
157 * because we can race with efx_mac_fcntl_set().
159 epp->ep_lp_cap_mask = lp_cap_mask;
160 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))
161 epp->ep_fcntl = fcntl;
163 *link_modep = link_mode;
166 __checkReturn efx_rc_t
169 __in boolean_t power)
176 /* Check if the PHY is a zombie */
177 if ((rc = siena_phy_verify(enp)) != 0)
180 enp->en_reset_flags |= EFX_RESET_PHY;
185 EFSYS_PROBE1(fail1, efx_rc_t, rc);
190 __checkReturn efx_rc_t
193 __out siena_link_state_t *slsp)
196 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LINK_IN_LEN,
197 MC_CMD_GET_LINK_OUT_LEN);
200 req.emr_cmd = MC_CMD_GET_LINK;
201 req.emr_in_buf = payload;
202 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN;
203 req.emr_out_buf = payload;
204 req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN;
206 efx_mcdi_execute(enp, &req);
208 if (req.emr_rc != 0) {
213 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) {
218 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP),
219 &slsp->sls_adv_cap_mask);
220 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP),
221 &slsp->sls_lp_cap_mask);
223 siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
224 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),
225 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),
226 &slsp->sls_link_mode, &slsp->sls_fcntl);
228 #if EFSYS_OPT_LOOPBACK
229 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */
230 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
231 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
232 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
233 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
234 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
235 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
243 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
244 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
245 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
246 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
247 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
249 slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE);
250 #endif /* EFSYS_OPT_LOOPBACK */
252 slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0;
259 EFSYS_PROBE1(fail1, efx_rc_t, rc);
264 __checkReturn efx_rc_t
265 siena_phy_reconfigure(
268 efx_port_t *epp = &(enp->en_port);
270 EFX_MCDI_DECLARE_BUF(payload,
271 MAX(MC_CMD_SET_ID_LED_IN_LEN, MC_CMD_SET_LINK_IN_LEN),
272 MAX(MC_CMD_SET_ID_LED_OUT_LEN, MC_CMD_SET_LINK_OUT_LEN));
274 unsigned int led_mode;
278 req.emr_cmd = MC_CMD_SET_LINK;
279 req.emr_in_buf = payload;
280 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN;
281 req.emr_out_buf = payload;
282 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN;
284 cap_mask = epp->ep_adv_cap_mask;
285 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP,
286 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1,
287 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1,
288 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1,
289 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1,
290 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1,
291 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1,
292 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1,
293 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1,
294 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1,
295 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1);
297 #if EFSYS_OPT_LOOPBACK
298 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE,
299 epp->ep_loopback_type);
300 switch (epp->ep_loopback_link_mode) {
301 case EFX_LINK_100FDX:
304 case EFX_LINK_1000FDX:
307 case EFX_LINK_10000FDX:
314 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE);
316 #endif /* EFSYS_OPT_LOOPBACK */
317 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed);
319 #if EFSYS_OPT_PHY_FLAGS
320 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags);
322 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0);
323 #endif /* EFSYS_OPT_PHY_FLAGS */
325 efx_mcdi_execute(enp, &req);
327 if (req.emr_rc != 0) {
332 /* And set the blink mode */
333 (void) memset(payload, 0, sizeof (payload));
334 req.emr_cmd = MC_CMD_SET_ID_LED;
335 req.emr_in_buf = payload;
336 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN;
337 req.emr_out_buf = payload;
338 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN;
340 #if EFSYS_OPT_PHY_LED_CONTROL
341 switch (epp->ep_phy_led_mode) {
342 case EFX_PHY_LED_DEFAULT:
343 led_mode = MC_CMD_LED_DEFAULT;
345 case EFX_PHY_LED_OFF:
346 led_mode = MC_CMD_LED_OFF;
349 led_mode = MC_CMD_LED_ON;
353 led_mode = MC_CMD_LED_DEFAULT;
356 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode);
358 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT);
359 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
361 efx_mcdi_execute(enp, &req);
363 if (req.emr_rc != 0) {
373 EFSYS_PROBE1(fail1, efx_rc_t, rc);
378 __checkReturn efx_rc_t
383 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PHY_STATE_IN_LEN,
384 MC_CMD_GET_PHY_STATE_OUT_LEN);
388 req.emr_cmd = MC_CMD_GET_PHY_STATE;
389 req.emr_in_buf = payload;
390 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN;
391 req.emr_out_buf = payload;
392 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN;
394 efx_mcdi_execute(enp, &req);
396 if (req.emr_rc != 0) {
401 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) {
406 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE);
407 if (state != MC_CMD_PHY_STATE_OK) {
408 if (state != MC_CMD_PHY_STATE_ZOMBIE)
409 EFSYS_PROBE1(mc_pcol_error, int, state);
421 EFSYS_PROBE1(fail1, efx_rc_t, rc);
426 __checkReturn efx_rc_t
429 __out uint32_t *ouip)
431 _NOTE(ARGUNUSED(enp, ouip))
436 #if EFSYS_OPT_PHY_STATS
438 #define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
439 _mc_record, _efx_record) \
440 if ((_vmask) & (1ULL << (_mc_record))) { \
441 (_smask) |= (1ULL << (_efx_record)); \
442 if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \
444 EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\
445 (_stat)[_efx_record] = \
446 EFX_DWORD_FIELD(dword, EFX_DWORD_0); \
450 #define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \
451 SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
452 MC_CMD_ ## _record, \
453 EFX_PHY_STAT_ ## _record)
456 siena_phy_decode_stats(
459 __in_opt efsys_mem_t *esmp,
460 __out_opt uint64_t *smaskp,
461 __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat)
465 _NOTE(ARGUNUSED(enp))
467 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI);
468 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP);
469 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT);
470 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT);
472 if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) {
473 smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) |
474 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) |
475 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) |
476 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D));
477 if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
480 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL,
482 sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
483 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1;
484 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1;
485 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1;
486 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1;
490 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A,
492 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B,
494 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C,
496 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D,
499 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP);
500 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT);
501 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT);
502 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER);
503 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS);
505 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP,
506 EFX_PHY_STAT_PHY_XS_LINK_UP);
507 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT,
508 EFX_PHY_STAT_PHY_XS_RX_FAULT);
509 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT,
510 EFX_PHY_STAT_PHY_XS_TX_FAULT);
511 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN,
512 EFX_PHY_STAT_PHY_XS_ALIGN);
514 if (vmask & (1 << MC_CMD_PHYXS_SYNC)) {
515 smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) |
516 (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) |
517 (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) |
518 (1 << EFX_PHY_STAT_PHY_XS_SYNC_D));
519 if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
522 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword);
523 sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
524 stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1;
525 stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1;
526 stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1;
527 stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1;
531 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP);
532 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE);
534 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP,
535 EFX_PHY_STAT_CL22EXT_LINK_UP);
541 __checkReturn efx_rc_t
542 siena_phy_stats_update(
544 __in efsys_mem_t *esmp,
545 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
547 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
548 uint32_t vmask = encp->enc_mcdi_phy_stat_mask;
551 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_PHY_STATS_IN_LEN,
552 MC_CMD_PHY_STATS_OUT_DMA_LEN);
555 req.emr_cmd = MC_CMD_PHY_STATS;
556 req.emr_in_buf = payload;
557 req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN;
558 req.emr_out_buf = payload;
559 req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN;
561 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO,
562 EFSYS_MEM_ADDR(esmp) & 0xffffffff);
563 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI,
564 EFSYS_MEM_ADDR(esmp) >> 32);
566 efx_mcdi_execute(enp, &req);
568 if (req.emr_rc != 0) {
572 EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN);
574 siena_phy_decode_stats(enp, vmask, esmp, &smask, stat);
575 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask);
580 EFSYS_PROBE1(fail1, efx_rc_t, rc);
585 #endif /* EFSYS_OPT_PHY_STATS */
589 __checkReturn efx_rc_t
590 siena_phy_bist_start(
592 __in efx_bist_type_t type)
596 if ((rc = efx_mcdi_bist_start(enp, type)) != 0)
602 EFSYS_PROBE1(fail1, efx_rc_t, rc);
607 static __checkReturn unsigned long
608 siena_phy_sft9001_bist_status(
612 case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY:
613 return (EFX_PHY_CABLE_STATUS_BUSY);
614 case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT:
615 return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT);
616 case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT:
617 return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT);
618 case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN:
619 return (EFX_PHY_CABLE_STATUS_OPEN);
620 case MC_CMD_POLL_BIST_SFT9001_PAIR_OK:
621 return (EFX_PHY_CABLE_STATUS_OK);
623 return (EFX_PHY_CABLE_STATUS_INVALID);
627 __checkReturn efx_rc_t
630 __in efx_bist_type_t type,
631 __out efx_bist_result_t *resultp,
632 __out_opt __drv_when(count > 0, __notnull)
633 uint32_t *value_maskp,
634 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
635 unsigned long *valuesp,
638 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
639 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_POLL_BIST_IN_LEN,
640 MCDI_CTL_SDU_LEN_MAX);
641 uint32_t value_mask = 0;
646 req.emr_cmd = MC_CMD_POLL_BIST;
647 req.emr_in_buf = payload;
648 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN;
649 req.emr_out_buf = payload;
650 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX;
652 efx_mcdi_execute(enp, &req);
654 if (req.emr_rc != 0) {
659 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) {
665 (void) memset(valuesp, '\0', count * sizeof (unsigned long));
667 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT);
669 /* Extract PHY specific results */
670 if (result == MC_CMD_POLL_BIST_PASSED &&
671 encp->enc_phy_type == EFX_PHY_SFT9001B &&
672 req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN &&
673 (type == EFX_BIST_TYPE_PHY_CABLE_SHORT ||
674 type == EFX_BIST_TYPE_PHY_CABLE_LONG)) {
677 if (count > EFX_BIST_PHY_CABLE_LENGTH_A) {
679 valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] =
681 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A);
682 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A);
685 if (count > EFX_BIST_PHY_CABLE_LENGTH_B) {
687 valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] =
689 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B);
690 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B);
693 if (count > EFX_BIST_PHY_CABLE_LENGTH_C) {
695 valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] =
697 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C);
698 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C);
701 if (count > EFX_BIST_PHY_CABLE_LENGTH_D) {
703 valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] =
705 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D);
706 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D);
709 if (count > EFX_BIST_PHY_CABLE_STATUS_A) {
710 if (valuesp != NULL) {
711 word = MCDI_OUT_WORD(req,
712 POLL_BIST_OUT_SFT9001_CABLE_STATUS_A);
713 valuesp[EFX_BIST_PHY_CABLE_STATUS_A] =
714 siena_phy_sft9001_bist_status(word);
716 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A);
719 if (count > EFX_BIST_PHY_CABLE_STATUS_B) {
720 if (valuesp != NULL) {
721 word = MCDI_OUT_WORD(req,
722 POLL_BIST_OUT_SFT9001_CABLE_STATUS_B);
723 valuesp[EFX_BIST_PHY_CABLE_STATUS_B] =
724 siena_phy_sft9001_bist_status(word);
726 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B);
729 if (count > EFX_BIST_PHY_CABLE_STATUS_C) {
730 if (valuesp != NULL) {
731 word = MCDI_OUT_WORD(req,
732 POLL_BIST_OUT_SFT9001_CABLE_STATUS_C);
733 valuesp[EFX_BIST_PHY_CABLE_STATUS_C] =
734 siena_phy_sft9001_bist_status(word);
736 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C);
739 if (count > EFX_BIST_PHY_CABLE_STATUS_D) {
740 if (valuesp != NULL) {
741 word = MCDI_OUT_WORD(req,
742 POLL_BIST_OUT_SFT9001_CABLE_STATUS_D);
743 valuesp[EFX_BIST_PHY_CABLE_STATUS_D] =
744 siena_phy_sft9001_bist_status(word);
746 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D);
749 } else if (result == MC_CMD_POLL_BIST_FAILED &&
750 encp->enc_phy_type == EFX_PHY_QLX111V &&
751 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN &&
752 count > EFX_BIST_FAULT_CODE) {
754 valuesp[EFX_BIST_FAULT_CODE] =
755 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST);
756 value_mask |= 1 << EFX_BIST_FAULT_CODE;
759 if (value_maskp != NULL)
760 *value_maskp = value_mask;
762 EFSYS_ASSERT(resultp != NULL);
763 if (result == MC_CMD_POLL_BIST_RUNNING)
764 *resultp = EFX_BIST_RESULT_RUNNING;
765 else if (result == MC_CMD_POLL_BIST_PASSED)
766 *resultp = EFX_BIST_RESULT_PASSED;
768 *resultp = EFX_BIST_RESULT_FAILED;
775 EFSYS_PROBE1(fail1, efx_rc_t, rc);
783 __in efx_bist_type_t type)
785 /* There is no way to stop BIST on Siena */
786 _NOTE(ARGUNUSED(enp, type))
789 #endif /* EFSYS_OPT_BIST */
791 #endif /* EFSYS_OPT_SIENA */