drivers/net/thunderx/base/nicvf_hw_defs.h

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium networks Ltd. 2016.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium networks nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef _THUNDERX_NICVF_HW_DEFS_H
  34 #define _THUNDERX_NICVF_HW_DEFS_H
  35
  36 #include <stdint.h>
  37 #include <stdbool.h>
  38
  39 /* Virtual function register offsets */
  40
  41 #define NIC_VF_CFG                      (0x000020)
  42 #define NIC_VF_PF_MAILBOX_0_1           (0x000130)
  43 #define NIC_VF_INT                      (0x000200)
  44 #define NIC_VF_INT_W1S                  (0x000220)
  45 #define NIC_VF_ENA_W1C                  (0x000240)
  46 #define NIC_VF_ENA_W1S                  (0x000260)
  47
  48 #define NIC_VNIC_RSS_CFG                (0x0020E0)
  49 #define NIC_VNIC_RSS_KEY_0_4            (0x002200)
  50 #define NIC_VNIC_TX_STAT_0_4            (0x004000)
  51 #define NIC_VNIC_RX_STAT_0_13           (0x004100)
  52 #define NIC_VNIC_RQ_GEN_CFG             (0x010010)
  53
  54 #define NIC_QSET_CQ_0_7_CFG             (0x010400)
  55 #define NIC_QSET_CQ_0_7_CFG2            (0x010408)
  56 #define NIC_QSET_CQ_0_7_THRESH          (0x010410)
  57 #define NIC_QSET_CQ_0_7_BASE            (0x010420)
  58 #define NIC_QSET_CQ_0_7_HEAD            (0x010428)
  59 #define NIC_QSET_CQ_0_7_TAIL            (0x010430)
  60 #define NIC_QSET_CQ_0_7_DOOR            (0x010438)
  61 #define NIC_QSET_CQ_0_7_STATUS          (0x010440)
  62 #define NIC_QSET_CQ_0_7_STATUS2         (0x010448)
  63 #define NIC_QSET_CQ_0_7_DEBUG           (0x010450)
  64
  65 #define NIC_QSET_RQ_0_7_CFG             (0x010600)
  66 #define NIC_QSET_RQ_0_7_STATUS0         (0x010700)
  67 #define NIC_QSET_RQ_0_7_STATUS1         (0x010708)
  68
  69 #define NIC_QSET_SQ_0_7_CFG             (0x010800)
  70 #define NIC_QSET_SQ_0_7_THRESH          (0x010810)
  71 #define NIC_QSET_SQ_0_7_BASE            (0x010820)
  72 #define NIC_QSET_SQ_0_7_HEAD            (0x010828)
  73 #define NIC_QSET_SQ_0_7_TAIL            (0x010830)
  74 #define NIC_QSET_SQ_0_7_DOOR            (0x010838)
  75 #define NIC_QSET_SQ_0_7_STATUS          (0x010840)
  76 #define NIC_QSET_SQ_0_7_DEBUG           (0x010848)
  77 #define NIC_QSET_SQ_0_7_STATUS0         (0x010900)
  78 #define NIC_QSET_SQ_0_7_STATUS1         (0x010908)
  79
  80 #define NIC_QSET_RBDR_0_1_CFG           (0x010C00)
  81 #define NIC_QSET_RBDR_0_1_THRESH        (0x010C10)
  82 #define NIC_QSET_RBDR_0_1_BASE          (0x010C20)
  83 #define NIC_QSET_RBDR_0_1_HEAD          (0x010C28)
  84 #define NIC_QSET_RBDR_0_1_TAIL          (0x010C30)
  85 #define NIC_QSET_RBDR_0_1_DOOR          (0x010C38)
  86 #define NIC_QSET_RBDR_0_1_STATUS0       (0x010C40)
  87 #define NIC_QSET_RBDR_0_1_STATUS1       (0x010C48)
  88 #define NIC_QSET_RBDR_0_1_PRFCH_STATUS  (0x010C50)
  89
  90 /* vNIC HW Constants */
  91
  92 #define NIC_Q_NUM_SHIFT                 18
  93
  94 #define MAX_QUEUE_SET                   128
  95 #define MAX_RCV_QUEUES_PER_QS           8
  96 #define MAX_RCV_BUF_DESC_RINGS_PER_QS   2
  97 #define MAX_SND_QUEUES_PER_QS           8
  98 #define MAX_CMP_QUEUES_PER_QS           8
  99
 100 #define NICVF_INTR_CQ_SHIFT             0
 101 #define NICVF_INTR_SQ_SHIFT             8
 102 #define NICVF_INTR_RBDR_SHIFT           16
 103 #define NICVF_INTR_PKT_DROP_SHIFT       20
 104 #define NICVF_INTR_TCP_TIMER_SHIFT      21
 105 #define NICVF_INTR_MBOX_SHIFT           22
 106 #define NICVF_INTR_QS_ERR_SHIFT         23
 107
 108 #define NICVF_INTR_CQ_MASK              (0xFF << NICVF_INTR_CQ_SHIFT)
 109 #define NICVF_INTR_SQ_MASK              (0xFF << NICVF_INTR_SQ_SHIFT)
 110 #define NICVF_INTR_RBDR_MASK            (0x03 << NICVF_INTR_RBDR_SHIFT)
 111 #define NICVF_INTR_PKT_DROP_MASK        (1 << NICVF_INTR_PKT_DROP_SHIFT)
 112 #define NICVF_INTR_TCP_TIMER_MASK       (1 << NICVF_INTR_TCP_TIMER_SHIFT)
 113 #define NICVF_INTR_MBOX_MASK            (1 << NICVF_INTR_MBOX_SHIFT)
 114 #define NICVF_INTR_QS_ERR_MASK          (1 << NICVF_INTR_QS_ERR_SHIFT)
 115 #define NICVF_INTR_ALL_MASK             (0x7FFFFF)
 116
 117 #define NICVF_CQ_WR_FULL                (1ULL << 26)
 118 #define NICVF_CQ_WR_DISABLE             (1ULL << 25)
 119 #define NICVF_CQ_WR_FAULT               (1ULL << 24)
 120 #define NICVF_CQ_ERR_MASK               (NICVF_CQ_WR_FULL |\
 121                                          NICVF_CQ_WR_DISABLE |\
 122                                          NICVF_CQ_WR_FAULT)
 123 #define NICVF_CQ_CQE_COUNT_MASK         (0xFFFF)
 124
 125 #define NICVF_SQ_ERR_STOPPED            (1ULL << 21)
 126 #define NICVF_SQ_ERR_SEND               (1ULL << 20)
 127 #define NICVF_SQ_ERR_DPE                (1ULL << 19)
 128 #define NICVF_SQ_ERR_MASK               (NICVF_SQ_ERR_STOPPED |\
 129                                          NICVF_SQ_ERR_SEND |\
 130                                          NICVF_SQ_ERR_DPE)
 131 #define NICVF_SQ_STATUS_STOPPED_BIT     (21)
 132
 133 #define NICVF_RBDR_FIFO_STATE_SHIFT     (62)
 134 #define NICVF_RBDR_FIFO_STATE_MASK      (3ULL << NICVF_RBDR_FIFO_STATE_SHIFT)
 135 #define NICVF_RBDR_COUNT_MASK           (0x7FFFF)
 136
 137 /* Queue reset */
 138 #define NICVF_CQ_RESET                  (1ULL << 41)
 139 #define NICVF_SQ_RESET                  (1ULL << 17)
 140 #define NICVF_RBDR_RESET                (1ULL << 43)
 141
 142 /* RSS constants */
 143 #define NIC_MAX_RSS_HASH_BITS           (8)
 144 #define NIC_MAX_RSS_IDR_TBL_SIZE        (1 << NIC_MAX_RSS_HASH_BITS)
 145 #define RSS_HASH_KEY_SIZE               (5) /* 320 bit key */
 146 #define RSS_HASH_KEY_BYTE_SIZE          (40) /* 320 bit key */
 147
 148 #define RSS_L2_EXTENDED_HASH_ENA        (1 << 0)
 149 #define RSS_IP_ENA                      (1 << 1)
 150 #define RSS_TCP_ENA                     (1 << 2)
 151 #define RSS_TCP_SYN_ENA                 (1 << 3)
 152 #define RSS_UDP_ENA                     (1 << 4)
 153 #define RSS_L4_EXTENDED_ENA             (1 << 5)
 154 #define RSS_L3_BI_DIRECTION_ENA         (1 << 7)
 155 #define RSS_L4_BI_DIRECTION_ENA         (1 << 8)
 156 #define RSS_TUN_VXLAN_ENA               (1 << 9)
 157 #define RSS_TUN_GENEVE_ENA              (1 << 10)
 158 #define RSS_TUN_NVGRE_ENA               (1 << 11)
 159
 160 #define RBDR_QUEUE_SZ_8K                (8 * 1024)
 161 #define RBDR_QUEUE_SZ_16K               (16 * 1024)
 162 #define RBDR_QUEUE_SZ_32K               (32 * 1024)
 163 #define RBDR_QUEUE_SZ_64K               (64 * 1024)
 164 #define RBDR_QUEUE_SZ_128K              (128 * 1024)
 165 #define RBDR_QUEUE_SZ_256K              (256 * 1024)
 166 #define RBDR_QUEUE_SZ_512K              (512 * 1024)
 167 #define RBDR_QUEUE_SZ_MAX               RBDR_QUEUE_SZ_512K
 168
 169 #define RBDR_SIZE_SHIFT                 (13) /* 8k */
 170
 171 #define SND_QUEUE_SZ_1K                 (1 * 1024)
 172 #define SND_QUEUE_SZ_2K                 (2 * 1024)
 173 #define SND_QUEUE_SZ_4K                 (4 * 1024)
 174 #define SND_QUEUE_SZ_8K                 (8 * 1024)
 175 #define SND_QUEUE_SZ_16K                (16 * 1024)
 176 #define SND_QUEUE_SZ_32K                (32 * 1024)
 177 #define SND_QUEUE_SZ_64K                (64 * 1024)
 178 #define SND_QUEUE_SZ_MAX                SND_QUEUE_SZ_64K
 179
 180 #define SND_QSIZE_SHIFT                 (10) /* 1k */
 181
 182 #define CMP_QUEUE_SZ_1K                 (1 * 1024)
 183 #define CMP_QUEUE_SZ_2K                 (2 * 1024)
 184 #define CMP_QUEUE_SZ_4K                 (4 * 1024)
 185 #define CMP_QUEUE_SZ_8K                 (8 * 1024)
 186 #define CMP_QUEUE_SZ_16K                (16 * 1024)
 187 #define CMP_QUEUE_SZ_32K                (32 * 1024)
 188 #define CMP_QUEUE_SZ_64K                (64 * 1024)
 189 #define CMP_QUEUE_SZ_MAX                CMP_QUEUE_SZ_64K
 190
 191 #define CMP_QSIZE_SHIFT                 (10) /* 1k */
 192
 193 #define NICVF_QSIZE_MIN_VAL             (0)
 194 #define NICVF_QSIZE_MAX_VAL             (6)
 195
 196 /* Min/Max packet size */
 197 #define NIC_HW_MIN_FRS                  (64)
 198 #define NIC_HW_MAX_FRS                  (9200) /* 9216 max pkt including FCS */
 199 #define NIC_HW_MAX_SEGS                 (12)
 200
 201 /* Descriptor alignments */
 202 #define NICVF_RBDR_BASE_ALIGN_BYTES     (128) /* 7 bits */
 203 #define NICVF_CQ_BASE_ALIGN_BYTES       (512) /* 9 bits */
 204 #define NICVF_SQ_BASE_ALIGN_BYTES       (128) /* 7 bits */
 205
 206 #define NICVF_CQE_RBPTR_WORD            (6)
 207 #define NICVF_CQE_RX2_RBPTR_WORD        (7)
 208
 209 #define NICVF_STATIC_ASSERT(s) _Static_assert(s, #s)
 210
 211 typedef uint64_t nicvf_phys_addr_t;
 212
 213 #ifndef __BYTE_ORDER__
 214 #error __BYTE_ORDER__ not defined
 215 #endif
 216
 217 /* vNIC HW Enumerations */
 218
 219 enum nic_send_ld_type_e {
 220         NIC_SEND_LD_TYPE_E_LDD,
 221         NIC_SEND_LD_TYPE_E_LDT,
 222         NIC_SEND_LD_TYPE_E_LDWB,
 223         NIC_SEND_LD_TYPE_E_ENUM_LAST,
 224 };
 225
 226 enum ether_type_algorithm {
 227         ETYPE_ALG_NONE,
 228         ETYPE_ALG_SKIP,
 229         ETYPE_ALG_ENDPARSE,
 230         ETYPE_ALG_VLAN,
 231         ETYPE_ALG_VLAN_STRIP,
 232 };
 233
 234 enum layer3_type {
 235         L3TYPE_NONE,
 236         L3TYPE_GRH,
 237         L3TYPE_IPV4 = 0x4,
 238         L3TYPE_IPV4_OPTIONS = 0x5,
 239         L3TYPE_IPV6 = 0x6,
 240         L3TYPE_IPV6_OPTIONS = 0x7,
 241         L3TYPE_ET_STOP = 0xD,
 242         L3TYPE_OTHER = 0xE,
 243 };
 244
 245 #define NICVF_L3TYPE_OPTIONS_MASK       ((uint8_t)1)
 246 #define NICVF_L3TYPE_IPVX_MASK          ((uint8_t)0x06)
 247
 248 enum layer4_type {
 249         L4TYPE_NONE,
 250         L4TYPE_IPSEC_ESP,
 251         L4TYPE_IPFRAG,
 252         L4TYPE_IPCOMP,
 253         L4TYPE_TCP,
 254         L4TYPE_UDP,
 255         L4TYPE_SCTP,
 256         L4TYPE_GRE,
 257         L4TYPE_ROCE_BTH,
 258         L4TYPE_OTHER = 0xE,
 259 };
 260
 261 /* CPI and RSSI configuration */
 262 enum cpi_algorithm_type {
 263         CPI_ALG_NONE,
 264         CPI_ALG_VLAN,
 265         CPI_ALG_VLAN16,
 266         CPI_ALG_DIFF,
 267 };
 268
 269 enum rss_algorithm_type {
 270         RSS_ALG_NONE,
 271         RSS_ALG_PORT,
 272         RSS_ALG_IP,
 273         RSS_ALG_TCP_IP,
 274         RSS_ALG_UDP_IP,
 275         RSS_ALG_SCTP_IP,
 276         RSS_ALG_GRE_IP,
 277         RSS_ALG_ROCE,
 278 };
 279
 280 enum rss_hash_cfg {
 281         RSS_HASH_L2ETC,
 282         RSS_HASH_IP,
 283         RSS_HASH_TCP,
 284         RSS_HASH_TCP_SYN_DIS,
 285         RSS_HASH_UDP,
 286         RSS_HASH_L4ETC,
 287         RSS_HASH_ROCE,
 288         RSS_L3_BIDI,
 289         RSS_L4_BIDI,
 290 };
 291
 292 /* Completion queue entry types */
 293 enum cqe_type {
 294         CQE_TYPE_INVALID,
 295         CQE_TYPE_RX = 0x2,
 296         CQE_TYPE_RX_SPLIT = 0x3,
 297         CQE_TYPE_RX_TCP = 0x4,
 298         CQE_TYPE_SEND = 0x8,
 299         CQE_TYPE_SEND_PTP = 0x9,
 300 };
 301
 302 enum cqe_rx_tcp_status {
 303         CQE_RX_STATUS_VALID_TCP_CNXT,
 304         CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F,
 305 };
 306
 307 enum cqe_send_status {
 308         CQE_SEND_STATUS_GOOD,
 309         CQE_SEND_STATUS_DESC_FAULT = 0x01,
 310         CQE_SEND_STATUS_HDR_CONS_ERR = 0x11,
 311         CQE_SEND_STATUS_SUBDESC_ERR = 0x12,
 312         CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80,
 313         CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81,
 314         CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82,
 315         CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83,
 316         CQE_SEND_STATUS_LOCK_VIOL = 0x84,
 317         CQE_SEND_STATUS_LOCK_UFLOW = 0x85,
 318         CQE_SEND_STATUS_DATA_FAULT = 0x86,
 319         CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87,
 320         CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88,
 321         CQE_SEND_STATUS_MEM_FAULT = 0x89,
 322         CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A,
 323         CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B,
 324 };
 325
 326 enum cqe_rx_tcp_end_reason {
 327         CQE_RX_TCP_END_FIN_FLAG_DET,
 328         CQE_RX_TCP_END_INVALID_FLAG,
 329         CQE_RX_TCP_END_TIMEOUT,
 330         CQE_RX_TCP_END_OUT_OF_SEQ,
 331         CQE_RX_TCP_END_PKT_ERR,
 332         CQE_RX_TCP_END_QS_DISABLED = 0x0F,
 333 };
 334
 335 /* Packet protocol level error enumeration */
 336 enum cqe_rx_err_level {
 337         CQE_RX_ERRLVL_RE,
 338         CQE_RX_ERRLVL_L2,
 339         CQE_RX_ERRLVL_L3,
 340         CQE_RX_ERRLVL_L4,
 341 };
 342
 343 /* Packet protocol level error type enumeration */
 344 enum cqe_rx_err_opcode {
 345         CQE_RX_ERR_RE_NONE,
 346         CQE_RX_ERR_RE_PARTIAL,
 347         CQE_RX_ERR_RE_JABBER,
 348         CQE_RX_ERR_RE_FCS = 0x7,
 349         CQE_RX_ERR_RE_TERMINATE = 0x9,
 350         CQE_RX_ERR_RE_RX_CTL = 0xb,
 351         CQE_RX_ERR_PREL2_ERR = 0x1f,
 352         CQE_RX_ERR_L2_FRAGMENT = 0x20,
 353         CQE_RX_ERR_L2_OVERRUN = 0x21,
 354         CQE_RX_ERR_L2_PFCS = 0x22,
 355         CQE_RX_ERR_L2_PUNY = 0x23,
 356         CQE_RX_ERR_L2_MAL = 0x24,
 357         CQE_RX_ERR_L2_OVERSIZE = 0x25,
 358         CQE_RX_ERR_L2_UNDERSIZE = 0x26,
 359         CQE_RX_ERR_L2_LENMISM = 0x27,
 360         CQE_RX_ERR_L2_PCLP = 0x28,
 361         CQE_RX_ERR_IP_NOT = 0x41,
 362         CQE_RX_ERR_IP_CHK = 0x42,
 363         CQE_RX_ERR_IP_MAL = 0x43,
 364         CQE_RX_ERR_IP_MALD = 0x44,
 365         CQE_RX_ERR_IP_HOP = 0x45,
 366         CQE_RX_ERR_L3_ICRC = 0x46,
 367         CQE_RX_ERR_L3_PCLP = 0x47,
 368         CQE_RX_ERR_L4_MAL = 0x61,
 369         CQE_RX_ERR_L4_CHK = 0x62,
 370         CQE_RX_ERR_UDP_LEN = 0x63,
 371         CQE_RX_ERR_L4_PORT = 0x64,
 372         CQE_RX_ERR_TCP_FLAG = 0x65,
 373         CQE_RX_ERR_TCP_OFFSET = 0x66,
 374         CQE_RX_ERR_L4_PCLP = 0x67,
 375         CQE_RX_ERR_RBDR_TRUNC = 0x70,
 376 };
 377
 378 enum send_l4_csum_type {
 379         SEND_L4_CSUM_DISABLE,
 380         SEND_L4_CSUM_UDP,
 381         SEND_L4_CSUM_TCP,
 382 };
 383
 384 enum send_crc_alg {
 385         SEND_CRCALG_CRC32,
 386         SEND_CRCALG_CRC32C,
 387         SEND_CRCALG_ICRC,
 388 };
 389
 390 enum send_load_type {
 391         SEND_LD_TYPE_LDD,
 392         SEND_LD_TYPE_LDT,
 393         SEND_LD_TYPE_LDWB,
 394 };
 395
 396 enum send_mem_alg_type {
 397         SEND_MEMALG_SET,
 398         SEND_MEMALG_ADD = 0x08,
 399         SEND_MEMALG_SUB = 0x09,
 400         SEND_MEMALG_ADDLEN = 0x0A,
 401         SEND_MEMALG_SUBLEN = 0x0B,
 402 };
 403
 404 enum send_mem_dsz_type {
 405         SEND_MEMDSZ_B64,
 406         SEND_MEMDSZ_B32,
 407         SEND_MEMDSZ_B8 = 0x03,
 408 };
 409
 410 enum sq_subdesc_type {
 411         SQ_DESC_TYPE_INVALID,
 412         SQ_DESC_TYPE_HEADER,
 413         SQ_DESC_TYPE_CRC,
 414         SQ_DESC_TYPE_IMMEDIATE,
 415         SQ_DESC_TYPE_GATHER,
 416         SQ_DESC_TYPE_MEMORY,
 417 };
 418
 419 enum l3_type_t {
 420         L3_NONE,
 421         L3_IPV4         = 0x04,
 422         L3_IPV4_OPT     = 0x05,
 423         L3_IPV6         = 0x06,
 424         L3_IPV6_OPT     = 0x07,
 425         L3_ET_STOP      = 0x0D,
 426         L3_OTHER        = 0x0E
 427 };
 428
 429 enum l4_type_t {
 430         L4_NONE,
 431         L4_IPSEC_ESP    = 0x01,
 432         L4_IPFRAG       = 0x02,
 433         L4_IPCOMP       = 0x03,
 434         L4_TCP          = 0x04,
 435         L4_UDP_PASS1    = 0x05,
 436         L4_GRE          = 0x07,
 437         L4_UDP_PASS2    = 0x08,
 438         L4_UDP_GENEVE   = 0x09,
 439         L4_UDP_VXLAN    = 0x0A,
 440         L4_NVGRE        = 0x0C,
 441         L4_OTHER        = 0x0E
 442 };
 443
 444 enum vlan_strip {
 445         NO_STRIP,
 446         STRIP_FIRST_VLAN,
 447         STRIP_SECOND_VLAN,
 448         STRIP_RESERV,
 449 };
 450
 451 enum rbdr_state {
 452         RBDR_FIFO_STATE_INACTIVE,
 453         RBDR_FIFO_STATE_ACTIVE,
 454         RBDR_FIFO_STATE_RESET,
 455         RBDR_FIFO_STATE_FAIL,
 456 };
 457
 458 enum rq_cache_allocation {
 459         RQ_CACHE_ALLOC_OFF,
 460         RQ_CACHE_ALLOC_ALL,
 461         RQ_CACHE_ALLOC_FIRST,
 462         RQ_CACHE_ALLOC_TWO,
 463 };
 464
 465 enum cq_rx_errlvl_e {
 466         CQ_ERRLVL_MAC,
 467         CQ_ERRLVL_L2,
 468         CQ_ERRLVL_L3,
 469         CQ_ERRLVL_L4,
 470 };
 471
 472 enum cq_rx_errop_e {
 473         CQ_RX_ERROP_RE_NONE,
 474         CQ_RX_ERROP_RE_PARTIAL = 0x1,
 475         CQ_RX_ERROP_RE_JABBER = 0x2,
 476         CQ_RX_ERROP_RE_FCS = 0x7,
 477         CQ_RX_ERROP_RE_TERMINATE = 0x9,
 478         CQ_RX_ERROP_RE_RX_CTL = 0xb,
 479         CQ_RX_ERROP_PREL2_ERR = 0x1f,
 480         CQ_RX_ERROP_L2_FRAGMENT = 0x20,
 481         CQ_RX_ERROP_L2_OVERRUN = 0x21,
 482         CQ_RX_ERROP_L2_PFCS = 0x22,
 483         CQ_RX_ERROP_L2_PUNY = 0x23,
 484         CQ_RX_ERROP_L2_MAL = 0x24,
 485         CQ_RX_ERROP_L2_OVERSIZE = 0x25,
 486         CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
 487         CQ_RX_ERROP_L2_LENMISM = 0x27,
 488         CQ_RX_ERROP_L2_PCLP = 0x28,
 489         CQ_RX_ERROP_IP_NOT = 0x41,
 490         CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
 491         CQ_RX_ERROP_IP_MAL = 0x43,
 492         CQ_RX_ERROP_IP_MALD = 0x44,
 493         CQ_RX_ERROP_IP_HOP = 0x45,
 494         CQ_RX_ERROP_L3_ICRC = 0x46,
 495         CQ_RX_ERROP_L3_PCLP = 0x47,
 496         CQ_RX_ERROP_L4_MAL = 0x61,
 497         CQ_RX_ERROP_L4_CHK = 0x62,
 498         CQ_RX_ERROP_UDP_LEN = 0x63,
 499         CQ_RX_ERROP_L4_PORT = 0x64,
 500         CQ_RX_ERROP_TCP_FLAG = 0x65,
 501         CQ_RX_ERROP_TCP_OFFSET = 0x66,
 502         CQ_RX_ERROP_L4_PCLP = 0x67,
 503         CQ_RX_ERROP_RBDR_TRUNC = 0x70,
 504 };
 505
 506 enum cq_tx_errop_e {
 507         CQ_TX_ERROP_GOOD,
 508         CQ_TX_ERROP_DESC_FAULT = 0x10,
 509         CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
 510         CQ_TX_ERROP_SUBDC_ERR = 0x12,
 511         CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
 512         CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
 513         CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
 514         CQ_TX_ERROP_LOCK_VIOL = 0x83,
 515         CQ_TX_ERROP_DATA_FAULT = 0x84,
 516         CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
 517         CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
 518         CQ_TX_ERROP_MEM_FAULT = 0x87,
 519         CQ_TX_ERROP_CK_OVERLAP = 0x88,
 520         CQ_TX_ERROP_CK_OFLOW = 0x89,
 521         CQ_TX_ERROP_ENUM_LAST = 0x8a,
 522 };
 523
 524 enum rq_sq_stats_reg_offset {
 525         RQ_SQ_STATS_OCTS,
 526         RQ_SQ_STATS_PKTS,
 527 };
 528
 529 enum nic_stat_vnic_rx_e {
 530         RX_OCTS,
 531         RX_UCAST,
 532         RX_BCAST,
 533         RX_MCAST,
 534         RX_RED,
 535         RX_RED_OCTS,
 536         RX_ORUN,
 537         RX_ORUN_OCTS,
 538         RX_FCS,
 539         RX_L2ERR,
 540         RX_DRP_BCAST,
 541         RX_DRP_MCAST,
 542         RX_DRP_L3BCAST,
 543         RX_DRP_L3MCAST,
 544 };
 545
 546 enum nic_stat_vnic_tx_e {
 547         TX_OCTS,
 548         TX_UCAST,
 549         TX_BCAST,
 550         TX_MCAST,
 551         TX_DROP,
 552 };
 553
 554 /* vNIC HW Register structures */
 555
 556 typedef union {
 557         uint64_t u64;
 558         struct {
 559 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 560                 uint64_t cqe_type:4;
 561                 uint64_t stdn_fault:1;
 562                 uint64_t rsvd0:1;
 563                 uint64_t rq_qs:7;
 564                 uint64_t rq_idx:3;
 565                 uint64_t rsvd1:12;
 566                 uint64_t rss_alg:4;
 567                 uint64_t rsvd2:4;
 568                 uint64_t rb_cnt:4;
 569                 uint64_t vlan_found:1;
 570                 uint64_t vlan_stripped:1;
 571                 uint64_t vlan2_found:1;
 572                 uint64_t vlan2_stripped:1;
 573                 uint64_t l4_type:4;
 574                 uint64_t l3_type:4;
 575                 uint64_t l2_present:1;
 576                 uint64_t err_level:3;
 577                 uint64_t err_opcode:8;
 578 #else
 579                 uint64_t err_opcode:8;
 580                 uint64_t err_level:3;
 581                 uint64_t l2_present:1;
 582                 uint64_t l3_type:4;
 583                 uint64_t l4_type:4;
 584                 uint64_t vlan2_stripped:1;
 585                 uint64_t vlan2_found:1;
 586                 uint64_t vlan_stripped:1;
 587                 uint64_t vlan_found:1;
 588                 uint64_t rb_cnt:4;
 589                 uint64_t rsvd2:4;
 590                 uint64_t rss_alg:4;
 591                 uint64_t rsvd1:12;
 592                 uint64_t rq_idx:3;
 593                 uint64_t rq_qs:7;
 594                 uint64_t rsvd0:1;
 595                 uint64_t stdn_fault:1;
 596                 uint64_t cqe_type:4;
 597 #endif
 598         };
 599 } cqe_rx_word0_t;
 600
 601 typedef union {
 602         uint64_t u64;
 603         struct {
 604 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 605                 uint64_t pkt_len:16;
 606                 uint64_t l2_ptr:8;
 607                 uint64_t l3_ptr:8;
 608                 uint64_t l4_ptr:8;
 609                 uint64_t cq_pkt_len:8;
 610                 uint64_t align_pad:3;
 611                 uint64_t rsvd3:1;
 612                 uint64_t chan:12;
 613 #else
 614                 uint64_t chan:12;
 615                 uint64_t rsvd3:1;
 616                 uint64_t align_pad:3;
 617                 uint64_t cq_pkt_len:8;
 618                 uint64_t l4_ptr:8;
 619                 uint64_t l3_ptr:8;
 620                 uint64_t l2_ptr:8;
 621                 uint64_t pkt_len:16;
 622 #endif
 623         };
 624 } cqe_rx_word1_t;
 625
 626 typedef union {
 627         uint64_t u64;
 628         struct {
 629 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 630                 uint64_t rss_tag:32;
 631                 uint64_t vlan_tci:16;
 632                 uint64_t vlan_ptr:8;
 633                 uint64_t vlan2_ptr:8;
 634 #else
 635                 uint64_t vlan2_ptr:8;
 636                 uint64_t vlan_ptr:8;
 637                 uint64_t vlan_tci:16;
 638                 uint64_t rss_tag:32;
 639 #endif
 640         };
 641 } cqe_rx_word2_t;
 642
 643 typedef union {
 644         uint64_t u64;
 645         struct {
 646 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 647                 uint16_t rb3_sz;
 648                 uint16_t rb2_sz;
 649                 uint16_t rb1_sz;
 650                 uint16_t rb0_sz;
 651 #else
 652                 uint16_t rb0_sz;
 653                 uint16_t rb1_sz;
 654                 uint16_t rb2_sz;
 655                 uint16_t rb3_sz;
 656 #endif
 657         };
 658 } cqe_rx_word3_t;
 659
 660 typedef union {
 661         uint64_t u64;
 662         struct {
 663 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 664                 uint16_t rb7_sz;
 665                 uint16_t rb6_sz;
 666                 uint16_t rb5_sz;
 667                 uint16_t rb4_sz;
 668 #else
 669                 uint16_t rb4_sz;
 670                 uint16_t rb5_sz;
 671                 uint16_t rb6_sz;
 672                 uint16_t rb7_sz;
 673 #endif
 674         };
 675 } cqe_rx_word4_t;
 676
 677 typedef union {
 678         uint64_t u64;
 679         struct {
 680 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 681                 uint16_t rb11_sz;
 682                 uint16_t rb10_sz;
 683                 uint16_t rb9_sz;
 684                 uint16_t rb8_sz;
 685 #else
 686                 uint16_t rb8_sz;
 687                 uint16_t rb9_sz;
 688                 uint16_t rb10_sz;
 689                 uint16_t rb11_sz;
 690 #endif
 691         };
 692 } cqe_rx_word5_t;
 693
 694 typedef union {
 695         uint64_t u64;
 696         struct {
 697 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 698                 uint64_t vlan_found:1;
 699                 uint64_t vlan_stripped:1;
 700                 uint64_t vlan2_found:1;
 701                 uint64_t vlan2_stripped:1;
 702                 uint64_t rsvd2:3;
 703                 uint64_t inner_l2:1;
 704                 uint64_t inner_l4type:4;
 705                 uint64_t inner_l3type:4;
 706                 uint64_t vlan_ptr:8;
 707                 uint64_t vlan2_ptr:8;
 708                 uint64_t rsvd1:8;
 709                 uint64_t rsvd0:8;
 710                 uint64_t inner_l3ptr:8;
 711                 uint64_t inner_l4ptr:8;
 712 #else
 713                 uint64_t inner_l4ptr:8;
 714                 uint64_t inner_l3ptr:8;
 715                 uint64_t rsvd0:8;
 716                 uint64_t rsvd1:8;
 717                 uint64_t vlan2_ptr:8;
 718                 uint64_t vlan_ptr:8;
 719                 uint64_t inner_l3type:4;
 720                 uint64_t inner_l4type:4;
 721                 uint64_t inner_l2:1;
 722                 uint64_t rsvd2:3;
 723                 uint64_t vlan2_stripped:1;
 724                 uint64_t vlan2_found:1;
 725                 uint64_t vlan_stripped:1;
 726                 uint64_t vlan_found:1;
 727 #endif
 728         };
 729 } cqe_rx2_word6_t;
 730
 731 struct cqe_rx_t {
 732         cqe_rx_word0_t word0;
 733         cqe_rx_word1_t word1;
 734         cqe_rx_word2_t word2;
 735         cqe_rx_word3_t word3;
 736         cqe_rx_word4_t word4;
 737         cqe_rx_word5_t word5;
 738         cqe_rx2_word6_t word6; /* if NIC_PF_RX_CFG[CQE_RX2_ENA] set */
 739 };
 740
 741 struct cqe_rx_tcp_err_t {
 742 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 743         uint64_t   cqe_type:4; /* W0 */
 744         uint64_t   rsvd0:60;
 745
 746         uint64_t   rsvd1:4; /* W1 */
 747         uint64_t   partial_first:1;
 748         uint64_t   rsvd2:27;
 749         uint64_t   rbdr_bytes:8;
 750         uint64_t   rsvd3:24;
 751 #else
 752         uint64_t   rsvd0:60;
 753         uint64_t   cqe_type:4;
 754
 755         uint64_t   rsvd3:24;
 756         uint64_t   rbdr_bytes:8;
 757         uint64_t   rsvd2:27;
 758         uint64_t   partial_first:1;
 759         uint64_t   rsvd1:4;
 760 #endif
 761 };
 762
 763 struct cqe_rx_tcp_t {
 764 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 765         uint64_t   cqe_type:4; /* W0 */
 766         uint64_t   rsvd0:52;
 767         uint64_t   cq_tcp_status:8;
 768
 769         uint64_t   rsvd1:32; /* W1 */
 770         uint64_t   tcp_cntx_bytes:8;
 771         uint64_t   rsvd2:8;
 772         uint64_t   tcp_err_bytes:16;
 773 #else
 774         uint64_t   cq_tcp_status:8;
 775         uint64_t   rsvd0:52;
 776         uint64_t   cqe_type:4; /* W0 */
 777
 778         uint64_t   tcp_err_bytes:16;
 779         uint64_t   rsvd2:8;
 780         uint64_t   tcp_cntx_bytes:8;
 781         uint64_t   rsvd1:32; /* W1 */
 782 #endif
 783 };
 784
 785 struct cqe_send_t {
 786 #if defined(__BIG_ENDIAN_BITFIELD)
 787         uint64_t   cqe_type:4; /* W0 */
 788         uint64_t   rsvd0:4;
 789         uint64_t   sqe_ptr:16;
 790         uint64_t   rsvd1:4;
 791         uint64_t   rsvd2:10;
 792         uint64_t   sq_qs:7;
 793         uint64_t   sq_idx:3;
 794         uint64_t   rsvd3:8;
 795         uint64_t   send_status:8;
 796
 797         uint64_t   ptp_timestamp:64; /* W1 */
 798 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 799         uint64_t   send_status:8;
 800         uint64_t   rsvd3:8;
 801         uint64_t   sq_idx:3;
 802         uint64_t   sq_qs:7;
 803         uint64_t   rsvd2:10;
 804         uint64_t   rsvd1:4;
 805         uint64_t   sqe_ptr:16;
 806         uint64_t   rsvd0:4;
 807         uint64_t   cqe_type:4; /* W0 */
 808
 809         uint64_t   ptp_timestamp:64;
 810 #endif
 811 };
 812
 813 struct cq_entry_type_t {
 814 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 815         uint64_t cqe_type:4;
 816         uint64_t __pad:60;
 817 #else
 818         uint64_t __pad:60;
 819         uint64_t cqe_type:4;
 820 #endif
 821 };
 822
 823 union cq_entry_t {
 824         uint64_t u[64];
 825         struct cq_entry_type_t type;
 826         struct cqe_rx_t rx_hdr;
 827         struct cqe_rx_tcp_t rx_tcp_hdr;
 828         struct cqe_rx_tcp_err_t rx_tcp_err_hdr;
 829         struct cqe_send_t cqe_send;
 830 };
 831
 832 NICVF_STATIC_ASSERT(sizeof(union cq_entry_t) == 512);
 833
 834 struct rbdr_entry_t {
 835 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 836         union {
 837                 struct {
 838                         uint64_t   rsvd0:15;
 839                         uint64_t   buf_addr:42;
 840                         uint64_t   cache_align:7;
 841                 };
 842                 nicvf_phys_addr_t full_addr;
 843         };
 844 #else
 845         union {
 846                 struct {
 847                         uint64_t   cache_align:7;
 848                         uint64_t   buf_addr:42;
 849                         uint64_t   rsvd0:15;
 850                 };
 851                 nicvf_phys_addr_t full_addr;
 852         };
 853 #endif
 854 };
 855
 856 NICVF_STATIC_ASSERT(sizeof(struct rbdr_entry_t) == sizeof(uint64_t));
 857
 858 /* TCP reassembly context */
 859 struct rbe_tcp_cnxt_t {
 860 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 861         uint64_t   tcp_pkt_cnt:12;
 862         uint64_t   rsvd1:4;
 863         uint64_t   align_hdr_bytes:4;
 864         uint64_t   align_ptr_bytes:4;
 865         uint64_t   ptr_bytes:16;
 866         uint64_t   rsvd2:24;
 867         uint64_t   cqe_type:4;
 868         uint64_t   rsvd0:54;
 869         uint64_t   tcp_end_reason:2;
 870         uint64_t   tcp_status:4;
 871 #else
 872         uint64_t   tcp_status:4;
 873         uint64_t   tcp_end_reason:2;
 874         uint64_t   rsvd0:54;
 875         uint64_t   cqe_type:4;
 876         uint64_t   rsvd2:24;
 877         uint64_t   ptr_bytes:16;
 878         uint64_t   align_ptr_bytes:4;
 879         uint64_t   align_hdr_bytes:4;
 880         uint64_t   rsvd1:4;
 881         uint64_t   tcp_pkt_cnt:12;
 882 #endif
 883 };
 884
 885 /* Always Big endian */
 886 struct rx_hdr_t {
 887         uint64_t   opaque:32;
 888         uint64_t   rss_flow:8;
 889         uint64_t   skip_length:6;
 890         uint64_t   disable_rss:1;
 891         uint64_t   disable_tcp_reassembly:1;
 892         uint64_t   nodrop:1;
 893         uint64_t   dest_alg:2;
 894         uint64_t   rsvd0:2;
 895         uint64_t   dest_rq:11;
 896 };
 897
 898 struct sq_crc_subdesc {
 899 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 900         uint64_t    rsvd1:32;
 901         uint64_t    crc_ival:32;
 902         uint64_t    subdesc_type:4;
 903         uint64_t    crc_alg:2;
 904         uint64_t    rsvd0:10;
 905         uint64_t    crc_insert_pos:16;
 906         uint64_t    hdr_start:16;
 907         uint64_t    crc_len:16;
 908 #else
 909         uint64_t    crc_len:16;
 910         uint64_t    hdr_start:16;
 911         uint64_t    crc_insert_pos:16;
 912         uint64_t    rsvd0:10;
 913         uint64_t    crc_alg:2;
 914         uint64_t    subdesc_type:4;
 915         uint64_t    crc_ival:32;
 916         uint64_t    rsvd1:32;
 917 #endif
 918 };
 919
 920 struct sq_gather_subdesc {
 921 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 922         uint64_t    subdesc_type:4; /* W0 */
 923         uint64_t    ld_type:2;
 924         uint64_t    rsvd0:42;
 925         uint64_t    size:16;
 926
 927         uint64_t    rsvd1:15; /* W1 */
 928         uint64_t    addr:49;
 929 #else
 930         uint64_t    size:16;
 931         uint64_t    rsvd0:42;
 932         uint64_t    ld_type:2;
 933         uint64_t    subdesc_type:4; /* W0 */
 934
 935         uint64_t    addr:49;
 936         uint64_t    rsvd1:15; /* W1 */
 937 #endif
 938 };
 939
 940 /* SQ immediate subdescriptor */
 941 struct sq_imm_subdesc {
 942 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 943         uint64_t    subdesc_type:4; /* W0 */
 944         uint64_t    rsvd0:46;
 945         uint64_t    len:14;
 946
 947         uint64_t    data:64; /* W1 */
 948 #else
 949         uint64_t    len:14;
 950         uint64_t    rsvd0:46;
 951         uint64_t    subdesc_type:4; /* W0 */
 952
 953         uint64_t    data:64; /* W1 */
 954 #endif
 955 };
 956
 957 struct sq_mem_subdesc {
 958 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 959         uint64_t    subdesc_type:4; /* W0 */
 960         uint64_t    mem_alg:4;
 961         uint64_t    mem_dsz:2;
 962         uint64_t    wmem:1;
 963         uint64_t    rsvd0:21;
 964         uint64_t    offset:32;
 965
 966         uint64_t    rsvd1:15; /* W1 */
 967         uint64_t    addr:49;
 968 #else
 969         uint64_t    offset:32;
 970         uint64_t    rsvd0:21;
 971         uint64_t    wmem:1;
 972         uint64_t    mem_dsz:2;
 973         uint64_t    mem_alg:4;
 974         uint64_t    subdesc_type:4; /* W0 */
 975
 976         uint64_t    addr:49;
 977         uint64_t    rsvd1:15; /* W1 */
 978 #endif
 979 };
 980
 981 struct sq_hdr_subdesc {
 982 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
 983         uint64_t    subdesc_type:4;
 984         uint64_t    tso:1;
 985         uint64_t    post_cqe:1; /* Post CQE on no error also */
 986         uint64_t    dont_send:1;
 987         uint64_t    tstmp:1;
 988         uint64_t    subdesc_cnt:8;
 989         uint64_t    csum_l4:2;
 990         uint64_t    csum_l3:1;
 991         uint64_t    csum_inner_l4:2;
 992         uint64_t    csum_inner_l3:1;
 993         uint64_t    rsvd0:2;
 994         uint64_t    l4_offset:8;
 995         uint64_t    l3_offset:8;
 996         uint64_t    rsvd1:4;
 997         uint64_t    tot_len:20; /* W0 */
 998
 999         uint64_t    rsvd2:24;
1000         uint64_t    inner_l4_offset:8;
1001         uint64_t    inner_l3_offset:8;
1002         uint64_t    tso_start:8;
1003         uint64_t    rsvd3:2;
1004         uint64_t    tso_max_paysize:14; /* W1 */
1005 #else
1006         uint64_t    tot_len:20;
1007         uint64_t    rsvd1:4;
1008         uint64_t    l3_offset:8;
1009         uint64_t    l4_offset:8;
1010         uint64_t    rsvd0:2;
1011         uint64_t    csum_inner_l3:1;
1012         uint64_t    csum_inner_l4:2;
1013         uint64_t    csum_l3:1;
1014         uint64_t    csum_l4:2;
1015         uint64_t    subdesc_cnt:8;
1016         uint64_t    tstmp:1;
1017         uint64_t    dont_send:1;
1018         uint64_t    post_cqe:1; /* Post CQE on no error also */
1019         uint64_t    tso:1;
1020         uint64_t    subdesc_type:4; /* W0 */
1021
1022         uint64_t    tso_max_paysize:14;
1023         uint64_t    rsvd3:2;
1024         uint64_t    tso_start:8;
1025         uint64_t    inner_l3_offset:8;
1026         uint64_t    inner_l4_offset:8;
1027         uint64_t    rsvd2:24; /* W1 */
1028 #endif
1029 };
1030
1031 /* Each sq entry is 128 bits wide */
1032 union sq_entry_t {
1033         uint64_t buff[2];
1034         struct sq_hdr_subdesc hdr;
1035         struct sq_imm_subdesc imm;
1036         struct sq_gather_subdesc gather;
1037         struct sq_crc_subdesc crc;
1038         struct sq_mem_subdesc mem;
1039 };
1040
1041 NICVF_STATIC_ASSERT(sizeof(union sq_entry_t) == 16);
1042
1043 /* Queue config register formats */
1044 struct rq_cfg { union { struct {
1045 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1046         uint64_t reserved_2_63:62;
1047         uint64_t ena:1;
1048         uint64_t reserved_0:1;
1049 #else
1050         uint64_t reserved_0:1;
1051         uint64_t ena:1;
1052         uint64_t reserved_2_63:62;
1053 #endif
1054         };
1055         uint64_t value;
1056 }; };
1057
1058 struct cq_cfg { union { struct {
1059 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1060         uint64_t reserved_43_63:21;
1061         uint64_t ena:1;
1062         uint64_t reset:1;
1063         uint64_t caching:1;
1064         uint64_t reserved_35_39:5;
1065         uint64_t qsize:3;
1066         uint64_t reserved_25_31:7;
1067         uint64_t avg_con:9;
1068         uint64_t reserved_0_15:16;
1069 #else
1070         uint64_t reserved_0_15:16;
1071         uint64_t avg_con:9;
1072         uint64_t reserved_25_31:7;
1073         uint64_t qsize:3;
1074         uint64_t reserved_35_39:5;
1075         uint64_t caching:1;
1076         uint64_t reset:1;
1077         uint64_t ena:1;
1078         uint64_t reserved_43_63:21;
1079 #endif
1080         };
1081         uint64_t value;
1082 }; };
1083
1084 struct sq_cfg { union { struct {
1085 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1086         uint64_t reserved_20_63:44;
1087         uint64_t ena:1;
1088         uint64_t reserved_18_18:1;
1089         uint64_t reset:1;
1090         uint64_t ldwb:1;
1091         uint64_t reserved_11_15:5;
1092         uint64_t qsize:3;
1093         uint64_t reserved_3_7:5;
1094         uint64_t tstmp_bgx_intf:3;
1095 #else
1096         uint64_t tstmp_bgx_intf:3;
1097         uint64_t reserved_3_7:5;
1098         uint64_t qsize:3;
1099         uint64_t reserved_11_15:5;
1100         uint64_t ldwb:1;
1101         uint64_t reset:1;
1102         uint64_t reserved_18_18:1;
1103         uint64_t ena:1;
1104         uint64_t reserved_20_63:44;
1105 #endif
1106         };
1107         uint64_t value;
1108 }; };
1109
1110 struct rbdr_cfg { union { struct {
1111 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1112         uint64_t reserved_45_63:19;
1113         uint64_t ena:1;
1114         uint64_t reset:1;
1115         uint64_t ldwb:1;
1116         uint64_t reserved_36_41:6;
1117         uint64_t qsize:4;
1118         uint64_t reserved_25_31:7;
1119         uint64_t avg_con:9;
1120         uint64_t reserved_12_15:4;
1121         uint64_t lines:12;
1122 #else
1123         uint64_t lines:12;
1124         uint64_t reserved_12_15:4;
1125         uint64_t avg_con:9;
1126         uint64_t reserved_25_31:7;
1127         uint64_t qsize:4;
1128         uint64_t reserved_36_41:6;
1129         uint64_t ldwb:1;
1130         uint64_t reset:1;
1131         uint64_t ena: 1;
1132         uint64_t reserved_45_63:19;
1133 #endif
1134         };
1135         uint64_t value;
1136 }; };
1137
1138 struct pf_qs_cfg { union { struct {
1139 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1140         uint64_t reserved_32_63:32;
1141         uint64_t ena:1;
1142         uint64_t reserved_27_30:4;
1143         uint64_t sq_ins_ena:1;
1144         uint64_t sq_ins_pos:6;
1145         uint64_t lock_ena:1;
1146         uint64_t lock_viol_cqe_ena:1;
1147         uint64_t send_tstmp_ena:1;
1148         uint64_t be:1;
1149         uint64_t reserved_7_15:9;
1150         uint64_t vnic:7;
1151 #else
1152         uint64_t vnic:7;
1153         uint64_t reserved_7_15:9;
1154         uint64_t be:1;
1155         uint64_t send_tstmp_ena:1;
1156         uint64_t lock_viol_cqe_ena:1;
1157         uint64_t lock_ena:1;
1158         uint64_t sq_ins_pos:6;
1159         uint64_t sq_ins_ena:1;
1160         uint64_t reserved_27_30:4;
1161         uint64_t ena:1;
1162         uint64_t reserved_32_63:32;
1163 #endif
1164         };
1165         uint64_t value;
1166 }; };
1167
1168 struct pf_rq_cfg { union { struct {
1169 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1170         uint64_t reserved1:1;
1171         uint64_t reserved0:34;
1172         uint64_t strip_pre_l2:1;
1173         uint64_t caching:2;
1174         uint64_t cq_qs:7;
1175         uint64_t cq_idx:3;
1176         uint64_t rbdr_cont_qs:7;
1177         uint64_t rbdr_cont_idx:1;
1178         uint64_t rbdr_strt_qs:7;
1179         uint64_t rbdr_strt_idx:1;
1180 #else
1181         uint64_t rbdr_strt_idx:1;
1182         uint64_t rbdr_strt_qs:7;
1183         uint64_t rbdr_cont_idx:1;
1184         uint64_t rbdr_cont_qs:7;
1185         uint64_t cq_idx:3;
1186         uint64_t cq_qs:7;
1187         uint64_t caching:2;
1188         uint64_t strip_pre_l2:1;
1189         uint64_t reserved0:34;
1190         uint64_t reserved1:1;
1191 #endif
1192         };
1193         uint64_t value;
1194 }; };
1195
1196 struct pf_rq_drop_cfg { union { struct {
1197 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1198         uint64_t rbdr_red:1;
1199         uint64_t cq_red:1;
1200         uint64_t reserved3:14;
1201         uint64_t rbdr_pass:8;
1202         uint64_t rbdr_drop:8;
1203         uint64_t reserved2:8;
1204         uint64_t cq_pass:8;
1205         uint64_t cq_drop:8;
1206         uint64_t reserved1:8;
1207 #else
1208         uint64_t reserved1:8;
1209         uint64_t cq_drop:8;
1210         uint64_t cq_pass:8;
1211         uint64_t reserved2:8;
1212         uint64_t rbdr_drop:8;
1213         uint64_t rbdr_pass:8;
1214         uint64_t reserved3:14;
1215         uint64_t cq_red:1;
1216         uint64_t rbdr_red:1;
1217 #endif
1218         };
1219         uint64_t value;
1220 }; };
1221
1222 #endif /* _THUNDERX_NICVF_HW_DEFS_H */