drivers/net/thunderx/nicvf_ethdev.c

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium networks Ltd. 2016.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium networks nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <assert.h>
  34 #include <stdio.h>
  35 #include <stdbool.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <sys/queue.h>
  44
  45 #include <rte_alarm.h>
  46 #include <rte_atomic.h>
  47 #include <rte_branch_prediction.h>
  48 #include <rte_byteorder.h>
  49 #include <rte_common.h>
  50 #include <rte_cycles.h>
  51 #include <rte_debug.h>
  52 #include <rte_dev.h>
  53 #include <rte_eal.h>
  54 #include <rte_ether.h>
  55 #include <rte_ethdev.h>
  56 #include <rte_interrupts.h>
  57 #include <rte_log.h>
  58 #include <rte_memory.h>
  59 #include <rte_memzone.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_pci.h>
  63 #include <rte_tailq.h>
  64
  65 #include "base/nicvf_plat.h"
  66
  67 #include "nicvf_ethdev.h"
  68 #include "nicvf_rxtx.h"
  69 #include "nicvf_svf.h"
  70 #include "nicvf_logs.h"
  71
  72 static void nicvf_dev_stop(struct rte_eth_dev *dev);
  73 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
  74 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
  75                           bool cleanup);
  76
  77 static inline int
  78 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
  79                                struct rte_eth_link *link)
  80 {
  81         struct rte_eth_link *dst = &dev->data->dev_link;
  82         struct rte_eth_link *src = link;
  83
  84         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
  85                 *(uint64_t *)src) == 0)
  86                 return -1;
  87
  88         return 0;
  89 }
  90
  91 static inline void
  92 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
  93 {
  94         link->link_status = nic->link_up;
  95         link->link_duplex = ETH_LINK_AUTONEG;
  96         if (nic->duplex == NICVF_HALF_DUPLEX)
  97                 link->link_duplex = ETH_LINK_HALF_DUPLEX;
  98         else if (nic->duplex == NICVF_FULL_DUPLEX)
  99                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
 100         link->link_speed = nic->speed;
 101         link->link_autoneg = ETH_LINK_AUTONEG;
 102 }
 103
 104 static void
 105 nicvf_interrupt(void *arg)
 106 {
 107         struct rte_eth_dev *dev = arg;
 108         struct nicvf *nic = nicvf_pmd_priv(dev);
 109
 110         if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
 111                 if (dev->data->dev_conf.intr_conf.lsc)
 112                         nicvf_set_eth_link_status(nic, &dev->data->dev_link);
 113                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 114         }
 115
 116         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 117                                 nicvf_interrupt, dev);
 118 }
 119
 120 static void
 121 nicvf_vf_interrupt(void *arg)
 122 {
 123         struct nicvf *nic = arg;
 124
 125         nicvf_reg_poll_interrupts(nic);
 126
 127         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 128                                 nicvf_vf_interrupt, nic);
 129 }
 130
 131 static int
 132 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
 133 {
 134         return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
 135 }
 136
 137 static int
 138 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
 139 {
 140         return rte_eal_alarm_cancel(fn, arg);
 141 }
 142
 143 /*
 144  * Return 0 means link status changed, -1 means not changed
 145  */
 146 static int
 147 nicvf_dev_link_update(struct rte_eth_dev *dev,
 148                       int wait_to_complete __rte_unused)
 149 {
 150         struct rte_eth_link link;
 151         struct nicvf *nic = nicvf_pmd_priv(dev);
 152
 153         PMD_INIT_FUNC_TRACE();
 154
 155         memset(&link, 0, sizeof(link));
 156         nicvf_set_eth_link_status(nic, &link);
 157         return nicvf_atomic_write_link_status(dev, &link);
 158 }
 159
 160 static int
 161 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 162 {
 163         struct nicvf *nic = nicvf_pmd_priv(dev);
 164         uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD;
 165         size_t i;
 166
 167         PMD_INIT_FUNC_TRACE();
 168
 169         if (frame_size > NIC_HW_MAX_FRS)
 170                 return -EINVAL;
 171
 172         if (frame_size < NIC_HW_MIN_FRS)
 173                 return -EINVAL;
 174
 175         buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 176
 177         /*
 178          * Refuse mtu that requires the support of scattered packets
 179          * when this feature has not been enabled before.
 180          */
 181         if (dev->data->dev_started && !dev->data->scattered_rx &&
 182                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
 183                 return -EINVAL;
 184
 185         /* check <seg size> * <max_seg>  >= max_frame */
 186         if (dev->data->scattered_rx &&
 187                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
 188                 return -EINVAL;
 189
 190         if (frame_size > ETHER_MAX_LEN)
 191                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
 192         else
 193                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
 194
 195         if (nicvf_mbox_update_hw_max_frs(nic, mtu))
 196                 return -EINVAL;
 197
 198         /* Update max_rx_pkt_len */
 199         dev->data->dev_conf.rxmode.max_rx_pkt_len = mtu + ETHER_HDR_LEN;
 200         nic->mtu = mtu;
 201
 202         for (i = 0; i < nic->sqs_count; i++)
 203                 nic->snicvf[i]->mtu = mtu;
 204
 205         return 0;
 206 }
 207
 208 static int
 209 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 210 {
 211         uint64_t *data = regs->data;
 212         struct nicvf *nic = nicvf_pmd_priv(dev);
 213
 214         if (data == NULL) {
 215                 regs->length = nicvf_reg_get_count();
 216                 regs->width = THUNDERX_REG_BYTES;
 217                 return 0;
 218         }
 219
 220         /* Support only full register dump */
 221         if ((regs->length == 0) ||
 222                 (regs->length == (uint32_t)nicvf_reg_get_count())) {
 223                 regs->version = nic->vendor_id << 16 | nic->device_id;
 224                 nicvf_reg_dump(nic, data);
 225                 return 0;
 226         }
 227         return -ENOTSUP;
 228 }
 229
 230 static void
 231 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 232 {
 233         uint16_t qidx;
 234         struct nicvf_hw_rx_qstats rx_qstats;
 235         struct nicvf_hw_tx_qstats tx_qstats;
 236         struct nicvf_hw_stats port_stats;
 237         struct nicvf *nic = nicvf_pmd_priv(dev);
 238         uint16_t rx_start, rx_end;
 239         uint16_t tx_start, tx_end;
 240         size_t i;
 241
 242         /* RX queue indices for the first VF */
 243         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 244
 245         /* Reading per RX ring stats */
 246         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 247                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 248                         break;
 249
 250                 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
 251                 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 252                 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 253         }
 254
 255         /* TX queue indices for the first VF */
 256         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 257
 258         /* Reading per TX ring stats */
 259         for (qidx = tx_start; qidx <= tx_end; qidx++) {
 260                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 261                         break;
 262
 263                 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
 264                 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 265                 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 266         }
 267
 268         for (i = 0; i < nic->sqs_count; i++) {
 269                 struct nicvf *snic = nic->snicvf[i];
 270
 271                 if (snic == NULL)
 272                         break;
 273
 274                 /* RX queue indices for a secondary VF */
 275                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 276
 277                 /* Reading per RX ring stats */
 278                 for (qidx = rx_start; qidx <= rx_end; qidx++) {
 279                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 280                                 break;
 281
 282                         nicvf_hw_get_rx_qstats(snic, &rx_qstats,
 283                                                qidx % MAX_RCV_QUEUES_PER_QS);
 284                         stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 285                         stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 286                 }
 287
 288                 /* TX queue indices for a secondary VF */
 289                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 290                 /* Reading per TX ring stats */
 291                 for (qidx = tx_start; qidx <= tx_end; qidx++) {
 292                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 293                                 break;
 294
 295                         nicvf_hw_get_tx_qstats(snic, &tx_qstats,
 296                                                qidx % MAX_SND_QUEUES_PER_QS);
 297                         stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 298                         stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 299                 }
 300         }
 301
 302         nicvf_hw_get_stats(nic, &port_stats);
 303         stats->ibytes = port_stats.rx_bytes;
 304         stats->ipackets = port_stats.rx_ucast_frames;
 305         stats->ipackets += port_stats.rx_bcast_frames;
 306         stats->ipackets += port_stats.rx_mcast_frames;
 307         stats->ierrors = port_stats.rx_l2_errors;
 308         stats->imissed = port_stats.rx_drop_red;
 309         stats->imissed += port_stats.rx_drop_overrun;
 310         stats->imissed += port_stats.rx_drop_bcast;
 311         stats->imissed += port_stats.rx_drop_mcast;
 312         stats->imissed += port_stats.rx_drop_l3_bcast;
 313         stats->imissed += port_stats.rx_drop_l3_mcast;
 314
 315         stats->obytes = port_stats.tx_bytes_ok;
 316         stats->opackets = port_stats.tx_ucast_frames_ok;
 317         stats->opackets += port_stats.tx_bcast_frames_ok;
 318         stats->opackets += port_stats.tx_mcast_frames_ok;
 319         stats->oerrors = port_stats.tx_drops;
 320 }
 321
 322 static const uint32_t *
 323 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 324 {
 325         size_t copied;
 326         static uint32_t ptypes[32];
 327         struct nicvf *nic = nicvf_pmd_priv(dev);
 328         static const uint32_t ptypes_common[] = {
 329                 RTE_PTYPE_L3_IPV4,
 330                 RTE_PTYPE_L3_IPV4_EXT,
 331                 RTE_PTYPE_L3_IPV6,
 332                 RTE_PTYPE_L3_IPV6_EXT,
 333                 RTE_PTYPE_L4_TCP,
 334                 RTE_PTYPE_L4_UDP,
 335                 RTE_PTYPE_L4_FRAG,
 336         };
 337         static const uint32_t ptypes_tunnel[] = {
 338                 RTE_PTYPE_TUNNEL_GRE,
 339                 RTE_PTYPE_TUNNEL_GENEVE,
 340                 RTE_PTYPE_TUNNEL_VXLAN,
 341                 RTE_PTYPE_TUNNEL_NVGRE,
 342         };
 343         static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
 344
 345         copied = sizeof(ptypes_common);
 346         memcpy(ptypes, ptypes_common, copied);
 347         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 348                 memcpy((char *)ptypes + copied, ptypes_tunnel,
 349                         sizeof(ptypes_tunnel));
 350                 copied += sizeof(ptypes_tunnel);
 351         }
 352
 353         memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
 354         if (dev->rx_pkt_burst == nicvf_recv_pkts ||
 355                 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
 356                 return ptypes;
 357
 358         return NULL;
 359 }
 360
 361 static void
 362 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
 363 {
 364         int i;
 365         uint16_t rxqs = 0, txqs = 0;
 366         struct nicvf *nic = nicvf_pmd_priv(dev);
 367         uint16_t rx_start, rx_end;
 368         uint16_t tx_start, tx_end;
 369
 370         /* Reset all primary nic counters */
 371         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 372         for (i = rx_start; i <= rx_end; i++)
 373                 rxqs |= (0x3 << (i * 2));
 374
 375         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 376         for (i = tx_start; i <= tx_end; i++)
 377                 txqs |= (0x3 << (i * 2));
 378
 379         nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
 380
 381         /* Reset secondary nic queue counters */
 382         for (i = 0; i < nic->sqs_count; i++) {
 383                 struct nicvf *snic = nic->snicvf[i];
 384                 if (snic == NULL)
 385                         break;
 386
 387                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 388                 for (i = rx_start; i <= rx_end; i++)
 389                         rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
 390
 391                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 392                 for (i = tx_start; i <= tx_end; i++)
 393                         txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
 394
 395                 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
 396         }
 397 }
 398
 399 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
 400 static void
 401 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
 402 {
 403 }
 404
 405 static inline uint64_t
 406 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
 407 {
 408         uint64_t nic_rss = 0;
 409
 410         if (ethdev_rss & ETH_RSS_IPV4)
 411                 nic_rss |= RSS_IP_ENA;
 412
 413         if (ethdev_rss & ETH_RSS_IPV6)
 414                 nic_rss |= RSS_IP_ENA;
 415
 416         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
 417                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 418
 419         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
 420                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 421
 422         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
 423                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 424
 425         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
 426                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 427
 428         if (ethdev_rss & ETH_RSS_PORT)
 429                 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
 430
 431         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 432                 if (ethdev_rss & ETH_RSS_VXLAN)
 433                         nic_rss |= RSS_TUN_VXLAN_ENA;
 434
 435                 if (ethdev_rss & ETH_RSS_GENEVE)
 436                         nic_rss |= RSS_TUN_GENEVE_ENA;
 437
 438                 if (ethdev_rss & ETH_RSS_NVGRE)
 439                         nic_rss |= RSS_TUN_NVGRE_ENA;
 440         }
 441
 442         return nic_rss;
 443 }
 444
 445 static inline uint64_t
 446 nicvf_rss_nic_to_ethdev(struct nicvf *nic,  uint64_t nic_rss)
 447 {
 448         uint64_t ethdev_rss = 0;
 449
 450         if (nic_rss & RSS_IP_ENA)
 451                 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
 452
 453         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
 454                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
 455                                 ETH_RSS_NONFRAG_IPV6_TCP);
 456
 457         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
 458                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
 459                                 ETH_RSS_NONFRAG_IPV6_UDP);
 460
 461         if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
 462                 ethdev_rss |= ETH_RSS_PORT;
 463
 464         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 465                 if (nic_rss & RSS_TUN_VXLAN_ENA)
 466                         ethdev_rss |= ETH_RSS_VXLAN;
 467
 468                 if (nic_rss & RSS_TUN_GENEVE_ENA)
 469                         ethdev_rss |= ETH_RSS_GENEVE;
 470
 471                 if (nic_rss & RSS_TUN_NVGRE_ENA)
 472                         ethdev_rss |= ETH_RSS_NVGRE;
 473         }
 474         return ethdev_rss;
 475 }
 476
 477 static int
 478 nicvf_dev_reta_query(struct rte_eth_dev *dev,
 479                      struct rte_eth_rss_reta_entry64 *reta_conf,
 480                      uint16_t reta_size)
 481 {
 482         struct nicvf *nic = nicvf_pmd_priv(dev);
 483         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 484         int ret, i, j;
 485
 486         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 487                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 488                         "(%d) doesn't match the number hardware can supported "
 489                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 490                 return -EINVAL;
 491         }
 492
 493         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 494         if (ret)
 495                 return ret;
 496
 497         /* Copy RETA table */
 498         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 499                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 500                         if ((reta_conf[i].mask >> j) & 0x01)
 501                                 reta_conf[i].reta[j] = tbl[j];
 502         }
 503
 504         return 0;
 505 }
 506
 507 static int
 508 nicvf_dev_reta_update(struct rte_eth_dev *dev,
 509                       struct rte_eth_rss_reta_entry64 *reta_conf,
 510                       uint16_t reta_size)
 511 {
 512         struct nicvf *nic = nicvf_pmd_priv(dev);
 513         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 514         int ret, i, j;
 515
 516         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 517                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 518                         "(%d) doesn't match the number hardware can supported "
 519                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 520                 return -EINVAL;
 521         }
 522
 523         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 524         if (ret)
 525                 return ret;
 526
 527         /* Copy RETA table */
 528         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 529                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 530                         if ((reta_conf[i].mask >> j) & 0x01)
 531                                 tbl[j] = reta_conf[i].reta[j];
 532         }
 533
 534         return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 535 }
 536
 537 static int
 538 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 539                             struct rte_eth_rss_conf *rss_conf)
 540 {
 541         struct nicvf *nic = nicvf_pmd_priv(dev);
 542
 543         if (rss_conf->rss_key)
 544                 nicvf_rss_get_key(nic, rss_conf->rss_key);
 545
 546         rss_conf->rss_key_len =  RSS_HASH_KEY_BYTE_SIZE;
 547         rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
 548         return 0;
 549 }
 550
 551 static int
 552 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
 553                           struct rte_eth_rss_conf *rss_conf)
 554 {
 555         struct nicvf *nic = nicvf_pmd_priv(dev);
 556         uint64_t nic_rss;
 557
 558         if (rss_conf->rss_key &&
 559                 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
 560                 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
 561                                 rss_conf->rss_key_len);
 562                 return -EINVAL;
 563         }
 564
 565         if (rss_conf->rss_key)
 566                 nicvf_rss_set_key(nic, rss_conf->rss_key);
 567
 568         nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
 569         nicvf_rss_set_cfg(nic, nic_rss);
 570         return 0;
 571 }
 572
 573 static int
 574 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 575                     struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
 576 {
 577         const struct rte_memzone *rz;
 578         uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
 579
 580         rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
 581                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 582                                       NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
 583         if (rz == NULL) {
 584                 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
 585                 return -ENOMEM;
 586         }
 587
 588         memset(rz->addr, 0, ring_size);
 589
 590         rxq->phys = rz->phys_addr;
 591         rxq->desc = rz->addr;
 592         rxq->qlen_mask = desc_cnt - 1;
 593
 594         return 0;
 595 }
 596
 597 static int
 598 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 599                     struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
 600 {
 601         const struct rte_memzone *rz;
 602         uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
 603
 604         rz = rte_eth_dma_zone_reserve(dev, "sq",
 605                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 606                                       NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
 607         if (rz == NULL) {
 608                 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
 609                 return -ENOMEM;
 610         }
 611
 612         memset(rz->addr, 0, ring_size);
 613
 614         sq->phys = rz->phys_addr;
 615         sq->desc = rz->addr;
 616         sq->qlen_mask = desc_cnt - 1;
 617
 618         return 0;
 619 }
 620
 621 static int
 622 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 623                       uint32_t desc_cnt, uint32_t buffsz)
 624 {
 625         struct nicvf_rbdr *rbdr;
 626         const struct rte_memzone *rz;
 627         uint32_t ring_size;
 628
 629         assert(nic->rbdr == NULL);
 630         rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
 631                                   RTE_CACHE_LINE_SIZE, nic->node);
 632         if (rbdr == NULL) {
 633                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
 634                 return -ENOMEM;
 635         }
 636
 637         ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
 638         rz = rte_eth_dma_zone_reserve(dev, "rbdr",
 639                                       nicvf_netdev_qidx(nic, 0), ring_size,
 640                                       NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
 641         if (rz == NULL) {
 642                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
 643                 return -ENOMEM;
 644         }
 645
 646         memset(rz->addr, 0, ring_size);
 647
 648         rbdr->phys = rz->phys_addr;
 649         rbdr->tail = 0;
 650         rbdr->next_tail = 0;
 651         rbdr->desc = rz->addr;
 652         rbdr->buffsz = buffsz;
 653         rbdr->qlen_mask = desc_cnt - 1;
 654         rbdr->rbdr_status =
 655                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
 656         rbdr->rbdr_door =
 657                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
 658
 659         nic->rbdr = rbdr;
 660         return 0;
 661 }
 662
 663 static void
 664 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
 665                         nicvf_phys_addr_t phy)
 666 {
 667         uint16_t qidx;
 668         void *obj;
 669         struct nicvf_rxq *rxq;
 670         uint16_t rx_start, rx_end;
 671
 672         /* Get queue ranges for this VF */
 673         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 674
 675         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 676                 rxq = dev->data->rx_queues[qidx];
 677                 if (rxq->precharge_cnt) {
 678                         obj = (void *)nicvf_mbuff_phy2virt(phy,
 679                                                            rxq->mbuf_phys_off);
 680                         rte_mempool_put(rxq->pool, obj);
 681                         rxq->precharge_cnt--;
 682                         break;
 683                 }
 684         }
 685 }
 686
 687 static inline void
 688 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
 689 {
 690         uint32_t qlen_mask, head;
 691         struct rbdr_entry_t *entry;
 692         struct nicvf_rbdr *rbdr = nic->rbdr;
 693
 694         qlen_mask = rbdr->qlen_mask;
 695         head = rbdr->head;
 696         while (head != rbdr->tail) {
 697                 entry = rbdr->desc + head;
 698                 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
 699                 head++;
 700                 head = head & qlen_mask;
 701         }
 702 }
 703
 704 static inline void
 705 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
 706 {
 707         uint32_t head;
 708
 709         head = txq->head;
 710         while (head != txq->tail) {
 711                 if (txq->txbuffs[head]) {
 712                         rte_pktmbuf_free_seg(txq->txbuffs[head]);
 713                         txq->txbuffs[head] = NULL;
 714                 }
 715                 head++;
 716                 head = head & txq->qlen_mask;
 717         }
 718 }
 719
 720 static void
 721 nicvf_tx_queue_reset(struct nicvf_txq *txq)
 722 {
 723         uint32_t txq_desc_cnt = txq->qlen_mask + 1;
 724
 725         memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
 726         memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
 727         txq->tail = 0;
 728         txq->head = 0;
 729         txq->xmit_bufs = 0;
 730 }
 731
 732 static inline int
 733 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 734                         uint16_t qidx)
 735 {
 736         struct nicvf_txq *txq;
 737         int ret;
 738
 739         assert(qidx < MAX_SND_QUEUES_PER_QS);
 740
 741         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 742                 RTE_ETH_QUEUE_STATE_STARTED)
 743                 return 0;
 744
 745         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 746         txq->pool = NULL;
 747         ret = nicvf_qset_sq_config(nic, qidx, txq);
 748         if (ret) {
 749                 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
 750                              nic->vf_id, qidx, ret);
 751                 goto config_sq_error;
 752         }
 753
 754         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 755                 RTE_ETH_QUEUE_STATE_STARTED;
 756         return ret;
 757
 758 config_sq_error:
 759         nicvf_qset_sq_reclaim(nic, qidx);
 760         return ret;
 761 }
 762
 763 static inline int
 764 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 765                        uint16_t qidx)
 766 {
 767         struct nicvf_txq *txq;
 768         int ret;
 769
 770         assert(qidx < MAX_SND_QUEUES_PER_QS);
 771
 772         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 773                 RTE_ETH_QUEUE_STATE_STOPPED)
 774                 return 0;
 775
 776         ret = nicvf_qset_sq_reclaim(nic, qidx);
 777         if (ret)
 778                 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
 779                              nic->vf_id, qidx, ret);
 780
 781         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 782         nicvf_tx_queue_release_mbufs(txq);
 783         nicvf_tx_queue_reset(txq);
 784
 785         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 786                 RTE_ETH_QUEUE_STATE_STOPPED;
 787         return ret;
 788 }
 789
 790 static inline int
 791 nicvf_configure_cpi(struct rte_eth_dev *dev)
 792 {
 793         struct nicvf *nic = nicvf_pmd_priv(dev);
 794         uint16_t qidx, qcnt;
 795         int ret;
 796
 797         /* Count started rx queues */
 798         for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
 799                 if (dev->data->rx_queue_state[qidx] ==
 800                     RTE_ETH_QUEUE_STATE_STARTED)
 801                         qcnt++;
 802
 803         nic->cpi_alg = CPI_ALG_NONE;
 804         ret = nicvf_mbox_config_cpi(nic, qcnt);
 805         if (ret)
 806                 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
 807
 808         return ret;
 809 }
 810
 811 static inline int
 812 nicvf_configure_rss(struct rte_eth_dev *dev)
 813 {
 814         struct nicvf *nic = nicvf_pmd_priv(dev);
 815         uint64_t rsshf;
 816         int ret = -EINVAL;
 817
 818         rsshf = nicvf_rss_ethdev_to_nic(nic,
 819                         dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
 820         PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
 821                     dev->data->dev_conf.rxmode.mq_mode,
 822                     dev->data->nb_rx_queues,
 823                     dev->data->dev_conf.lpbk_mode, rsshf);
 824
 825         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
 826                 ret = nicvf_rss_term(nic);
 827         else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
 828                 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
 829         if (ret)
 830                 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
 831
 832         return ret;
 833 }
 834
 835 static int
 836 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
 837 {
 838         struct nicvf *nic = nicvf_pmd_priv(dev);
 839         unsigned int idx, qmap_size;
 840         uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
 841         uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
 842
 843         if (nic->cpi_alg != CPI_ALG_NONE)
 844                 return -EINVAL;
 845
 846         /* Prepare queue map */
 847         for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
 848                 if (dev->data->rx_queue_state[idx] ==
 849                                 RTE_ETH_QUEUE_STATE_STARTED)
 850                         qmap[qmap_size++] = idx;
 851         }
 852
 853         /* Update default RSS RETA */
 854         for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
 855                 default_reta[idx] = qmap[idx % qmap_size];
 856
 857         return nicvf_rss_reta_update(nic, default_reta,
 858                                      NIC_MAX_RSS_IDR_TBL_SIZE);
 859 }
 860
 861 static void
 862 nicvf_dev_tx_queue_release(void *sq)
 863 {
 864         struct nicvf_txq *txq;
 865
 866         PMD_INIT_FUNC_TRACE();
 867
 868         txq = (struct nicvf_txq *)sq;
 869         if (txq) {
 870                 if (txq->txbuffs != NULL) {
 871                         nicvf_tx_queue_release_mbufs(txq);
 872                         rte_free(txq->txbuffs);
 873                         txq->txbuffs = NULL;
 874                 }
 875                 rte_free(txq);
 876         }
 877 }
 878
 879 static void
 880 nicvf_set_tx_function(struct rte_eth_dev *dev)
 881 {
 882         struct nicvf_txq *txq = NULL;
 883         size_t i;
 884         bool multiseg = false;
 885
 886         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 887                 txq = dev->data->tx_queues[i];
 888                 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) {
 889                         multiseg = true;
 890                         break;
 891                 }
 892         }
 893
 894         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 895         if (multiseg) {
 896                 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
 897                 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
 898         } else {
 899                 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
 900                 dev->tx_pkt_burst = nicvf_xmit_pkts;
 901         }
 902
 903         if (!txq)
 904                 return;
 905
 906         if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
 907                 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
 908         else
 909                 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
 910 }
 911
 912 static void
 913 nicvf_set_rx_function(struct rte_eth_dev *dev)
 914 {
 915         if (dev->data->scattered_rx) {
 916                 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
 917                 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
 918         } else {
 919                 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
 920                 dev->rx_pkt_burst = nicvf_recv_pkts;
 921         }
 922 }
 923
 924 static int
 925 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 926                          uint16_t nb_desc, unsigned int socket_id,
 927                          const struct rte_eth_txconf *tx_conf)
 928 {
 929         uint16_t tx_free_thresh;
 930         uint8_t is_single_pool;
 931         struct nicvf_txq *txq;
 932         struct nicvf *nic = nicvf_pmd_priv(dev);
 933
 934         PMD_INIT_FUNC_TRACE();
 935
 936         if (qidx >= MAX_SND_QUEUES_PER_QS)
 937                 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
 938
 939         qidx = qidx % MAX_SND_QUEUES_PER_QS;
 940
 941         /* Socket id check */
 942         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 943                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 944                 socket_id, nic->node);
 945
 946         /* Tx deferred start is not supported */
 947         if (tx_conf->tx_deferred_start) {
 948                 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
 949                 return -EINVAL;
 950         }
 951
 952         /* Roundup nb_desc to available qsize and validate max number of desc */
 953         nb_desc = nicvf_qsize_sq_roundup(nb_desc);
 954         if (nb_desc == 0) {
 955                 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
 956                 return -EINVAL;
 957         }
 958
 959         /* Validate tx_free_thresh */
 960         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 961                                 tx_conf->tx_free_thresh :
 962                                 NICVF_DEFAULT_TX_FREE_THRESH);
 963
 964         if (tx_free_thresh > (nb_desc) ||
 965                 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
 966                 PMD_INIT_LOG(ERR,
 967                         "tx_free_thresh must be less than the number of TX "
 968                         "descriptors. (tx_free_thresh=%u port=%d "
 969                         "queue=%d)", (unsigned int)tx_free_thresh,
 970                         (int)dev->data->port_id, (int)qidx);
 971                 return -EINVAL;
 972         }
 973
 974         /* Free memory prior to re-allocation if needed. */
 975         if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
 976                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 977                                 nicvf_netdev_qidx(nic, qidx));
 978                 nicvf_dev_tx_queue_release(
 979                         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
 980                 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
 981         }
 982
 983         /* Allocating tx queue data structure */
 984         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
 985                                         RTE_CACHE_LINE_SIZE, nic->node);
 986         if (txq == NULL) {
 987                 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
 988                              nicvf_netdev_qidx(nic, qidx));
 989                 return -ENOMEM;
 990         }
 991
 992         txq->nic = nic;
 993         txq->queue_id = qidx;
 994         txq->tx_free_thresh = tx_free_thresh;
 995         txq->txq_flags = tx_conf->txq_flags;
 996         txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
 997         txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
 998         is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
 999                                 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
1000
1001         /* Choose optimum free threshold value for multipool case */
1002         if (!is_single_pool) {
1003                 txq->tx_free_thresh = (uint16_t)
1004                 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1005                                 NICVF_TX_FREE_MPOOL_THRESH :
1006                                 tx_conf->tx_free_thresh);
1007                 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1008         } else {
1009                 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1010         }
1011
1012         /* Allocate software ring */
1013         txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1014                                 nb_desc * sizeof(struct rte_mbuf *),
1015                                 RTE_CACHE_LINE_SIZE, nic->node);
1016
1017         if (txq->txbuffs == NULL) {
1018                 nicvf_dev_tx_queue_release(txq);
1019                 return -ENOMEM;
1020         }
1021
1022         if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1023                 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1024                 nicvf_dev_tx_queue_release(txq);
1025                 return -ENOMEM;
1026         }
1027
1028         nicvf_tx_queue_reset(txq);
1029
1030         PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
1031                         nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1032                         txq->phys);
1033
1034         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1035         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1036                 RTE_ETH_QUEUE_STATE_STOPPED;
1037         return 0;
1038 }
1039
1040 static inline void
1041 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1042 {
1043         uint32_t rxq_cnt;
1044         uint32_t nb_pkts, released_pkts = 0;
1045         uint32_t refill_cnt = 0;
1046         struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1047
1048         if (dev->rx_pkt_burst == NULL)
1049                 return;
1050
1051         while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1052                                 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1053                 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1054                                         NICVF_MAX_RX_FREE_THRESH);
1055                 PMD_DRV_LOG(INFO, "nb_pkts=%d  rxq_cnt=%d", nb_pkts, rxq_cnt);
1056                 while (nb_pkts) {
1057                         rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1058                         released_pkts++;
1059                 }
1060         }
1061
1062
1063         refill_cnt += nicvf_dev_rbdr_refill(dev,
1064                         nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1065
1066         PMD_DRV_LOG(INFO, "free_cnt=%d  refill_cnt=%d",
1067                     released_pkts, refill_cnt);
1068 }
1069
1070 static void
1071 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1072 {
1073         rxq->head = 0;
1074         rxq->available_space = 0;
1075         rxq->recv_buffers = 0;
1076 }
1077
1078 static inline int
1079 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1080                         uint16_t qidx)
1081 {
1082         struct nicvf_rxq *rxq;
1083         int ret;
1084
1085         assert(qidx < MAX_RCV_QUEUES_PER_QS);
1086
1087         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1088                 RTE_ETH_QUEUE_STATE_STARTED)
1089                 return 0;
1090
1091         /* Update rbdr pointer to all rxq */
1092         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1093         rxq->shared_rbdr = nic->rbdr;
1094
1095         ret = nicvf_qset_rq_config(nic, qidx, rxq);
1096         if (ret) {
1097                 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1098                              nic->vf_id, qidx, ret);
1099                 goto config_rq_error;
1100         }
1101         ret = nicvf_qset_cq_config(nic, qidx, rxq);
1102         if (ret) {
1103                 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1104                              nic->vf_id, qidx, ret);
1105                 goto config_cq_error;
1106         }
1107
1108         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1109                 RTE_ETH_QUEUE_STATE_STARTED;
1110         return 0;
1111
1112 config_cq_error:
1113         nicvf_qset_cq_reclaim(nic, qidx);
1114 config_rq_error:
1115         nicvf_qset_rq_reclaim(nic, qidx);
1116         return ret;
1117 }
1118
1119 static inline int
1120 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1121                        uint16_t qidx)
1122 {
1123         struct nicvf_rxq *rxq;
1124         int ret, other_error;
1125
1126         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1127                 RTE_ETH_QUEUE_STATE_STOPPED)
1128                 return 0;
1129
1130         ret = nicvf_qset_rq_reclaim(nic, qidx);
1131         if (ret)
1132                 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1133                              nic->vf_id, qidx, ret);
1134
1135         other_error = ret;
1136         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1137         nicvf_rx_queue_release_mbufs(dev, rxq);
1138         nicvf_rx_queue_reset(rxq);
1139
1140         ret = nicvf_qset_cq_reclaim(nic, qidx);
1141         if (ret)
1142                 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1143                              nic->vf_id, qidx, ret);
1144
1145         other_error |= ret;
1146         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1147                 RTE_ETH_QUEUE_STATE_STOPPED;
1148         return other_error;
1149 }
1150
1151 static void
1152 nicvf_dev_rx_queue_release(void *rx_queue)
1153 {
1154         PMD_INIT_FUNC_TRACE();
1155
1156         rte_free(rx_queue);
1157 }
1158
1159 static int
1160 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1161 {
1162         struct nicvf *nic = nicvf_pmd_priv(dev);
1163         int ret;
1164
1165         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1166                 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1167
1168         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1169
1170         ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1171         if (ret)
1172                 return ret;
1173
1174         ret = nicvf_configure_cpi(dev);
1175         if (ret)
1176                 return ret;
1177
1178         return nicvf_configure_rss_reta(dev);
1179 }
1180
1181 static int
1182 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1183 {
1184         int ret;
1185         struct nicvf *nic = nicvf_pmd_priv(dev);
1186
1187         if (qidx >= MAX_SND_QUEUES_PER_QS)
1188                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1189
1190         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1191
1192         ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1193         ret |= nicvf_configure_cpi(dev);
1194         ret |= nicvf_configure_rss_reta(dev);
1195         return ret;
1196 }
1197
1198 static int
1199 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1200 {
1201         struct nicvf *nic = nicvf_pmd_priv(dev);
1202
1203         if (qidx >= MAX_SND_QUEUES_PER_QS)
1204                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1205
1206         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1207
1208         return nicvf_vf_start_tx_queue(dev, nic, qidx);
1209 }
1210
1211 static int
1212 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1213 {
1214         struct nicvf *nic = nicvf_pmd_priv(dev);
1215
1216         if (qidx >= MAX_SND_QUEUES_PER_QS)
1217                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1218
1219         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1220
1221         return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1222 }
1223
1224
1225 static int
1226 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1227                          uint16_t nb_desc, unsigned int socket_id,
1228                          const struct rte_eth_rxconf *rx_conf,
1229                          struct rte_mempool *mp)
1230 {
1231         uint16_t rx_free_thresh;
1232         struct nicvf_rxq *rxq;
1233         struct nicvf *nic = nicvf_pmd_priv(dev);
1234
1235         PMD_INIT_FUNC_TRACE();
1236
1237         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1238                 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1239
1240         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1241
1242         /* Socket id check */
1243         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1244                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1245                 socket_id, nic->node);
1246
1247         /* Mempool memory must be contiguous, so must be one memory segment*/
1248         if (mp->nb_mem_chunks != 1) {
1249                 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1250                 return -EINVAL;
1251         }
1252
1253         /* Mempool memory must be physically contiguous */
1254         if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) {
1255                 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1256                 return -EINVAL;
1257         }
1258
1259         /* Rx deferred start is not supported */
1260         if (rx_conf->rx_deferred_start) {
1261                 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1262                 return -EINVAL;
1263         }
1264
1265         /* Roundup nb_desc to available qsize and validate max number of desc */
1266         nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1267         if (nb_desc == 0) {
1268                 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1269                 return -EINVAL;
1270         }
1271
1272         /* Check rx_free_thresh upper bound */
1273         rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1274                                 rx_conf->rx_free_thresh :
1275                                 NICVF_DEFAULT_RX_FREE_THRESH);
1276         if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1277                 rx_free_thresh >= nb_desc * .75) {
1278                 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1279                                 rx_free_thresh);
1280                 return -EINVAL;
1281         }
1282
1283         /* Free memory prior to re-allocation if needed */
1284         if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1285                 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1286                                 nicvf_netdev_qidx(nic, qidx));
1287                 nicvf_dev_rx_queue_release(
1288                         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1289                 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1290         }
1291
1292         /* Allocate rxq memory */
1293         rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1294                                         RTE_CACHE_LINE_SIZE, nic->node);
1295         if (rxq == NULL) {
1296                 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1297                              nicvf_netdev_qidx(nic, qidx));
1298                 return -ENOMEM;
1299         }
1300
1301         rxq->nic = nic;
1302         rxq->pool = mp;
1303         rxq->queue_id = qidx;
1304         rxq->port_id = dev->data->port_id;
1305         rxq->rx_free_thresh = rx_free_thresh;
1306         rxq->rx_drop_en = rx_conf->rx_drop_en;
1307         rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1308         rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1309         rxq->precharge_cnt = 0;
1310
1311         if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1312                 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1313         else
1314                 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1315
1316
1317         /* Alloc completion queue */
1318         if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1319                 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1320                 nicvf_dev_rx_queue_release(rxq);
1321                 return -ENOMEM;
1322         }
1323
1324         nicvf_rx_queue_reset(rxq);
1325
1326         PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
1327                         nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1328                         rte_mempool_avail_count(mp), rxq->phys);
1329
1330         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1331         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1332                 RTE_ETH_QUEUE_STATE_STOPPED;
1333         return 0;
1334 }
1335
1336 static void
1337 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1338 {
1339         struct nicvf *nic = nicvf_pmd_priv(dev);
1340
1341         PMD_INIT_FUNC_TRACE();
1342
1343         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1344         dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + ETHER_HDR_LEN;
1345         dev_info->max_rx_queues =
1346                         (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1347         dev_info->max_tx_queues =
1348                         (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1349         dev_info->max_mac_addrs = 1;
1350         dev_info->max_vfs = dev->pci_dev->max_vfs;
1351
1352         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1353         dev_info->tx_offload_capa =
1354                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1355                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1356                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1357                 DEV_TX_OFFLOAD_TCP_TSO     |
1358                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1359
1360         dev_info->reta_size = nic->rss_info.rss_size;
1361         dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1362         dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1363         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1364                 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1365
1366         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1367                 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1368                 .rx_drop_en = 0,
1369         };
1370
1371         dev_info->default_txconf = (struct rte_eth_txconf) {
1372                 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1373                 .txq_flags =
1374                         ETH_TXQ_FLAGS_NOMULTSEGS  |
1375                         ETH_TXQ_FLAGS_NOREFCOUNT  |
1376                         ETH_TXQ_FLAGS_NOMULTMEMP  |
1377                         ETH_TXQ_FLAGS_NOVLANOFFL  |
1378                         ETH_TXQ_FLAGS_NOXSUMSCTP,
1379         };
1380 }
1381
1382 static nicvf_phys_addr_t
1383 rbdr_rte_mempool_get(void *dev, void *opaque)
1384 {
1385         uint16_t qidx;
1386         uintptr_t mbuf;
1387         struct nicvf_rxq *rxq;
1388         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1389         struct nicvf *nic = (struct nicvf *)opaque;
1390         uint16_t rx_start, rx_end;
1391
1392         /* Get queue ranges for this VF */
1393         nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1394
1395         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1396                 rxq = eth_dev->data->rx_queues[qidx];
1397                 /* Maintain equal buffer count across all pools */
1398                 if (rxq->precharge_cnt >= rxq->qlen_mask)
1399                         continue;
1400                 rxq->precharge_cnt++;
1401                 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1402                 if (mbuf)
1403                         return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1404         }
1405         return 0;
1406 }
1407
1408 static int
1409 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1410 {
1411         int ret;
1412         uint16_t qidx;
1413         uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1414         uint64_t mbuf_phys_off = 0;
1415         struct nicvf_rxq *rxq;
1416         struct rte_mbuf *mbuf;
1417         uint16_t rx_start, rx_end;
1418         uint16_t tx_start, tx_end;
1419
1420         PMD_INIT_FUNC_TRACE();
1421
1422         /* Userspace process exited without proper shutdown in last run */
1423         if (nicvf_qset_rbdr_active(nic, 0))
1424                 nicvf_vf_stop(dev, nic, false);
1425
1426         /* Get queue ranges for this VF */
1427         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1428
1429         /*
1430          * Thunderx nicvf PMD can support more than one pool per port only when
1431          * 1) Data payload size is same across all the pools in given port
1432          * AND
1433          * 2) All mbuffs in the pools are from the same hugepage
1434          * AND
1435          * 3) Mbuff metadata size is same across all the pools in given port
1436          *
1437          * This is to support existing application that uses multiple pool/port.
1438          * But, the purpose of using multipool for QoS will not be addressed.
1439          *
1440          */
1441
1442         /* Validate mempool attributes */
1443         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1444                 rxq = dev->data->rx_queues[qidx];
1445                 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1446                 mbuf = rte_pktmbuf_alloc(rxq->pool);
1447                 if (mbuf == NULL) {
1448                         PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1449                                      "pool=%s",
1450                                      nic->vf_id, qidx, rxq->pool->name);
1451                         return -ENOMEM;
1452                 }
1453                 rxq->mbuf_phys_off -= nicvf_mbuff_meta_length(mbuf);
1454                 rxq->mbuf_phys_off -= RTE_PKTMBUF_HEADROOM;
1455                 rte_pktmbuf_free(mbuf);
1456
1457                 if (mbuf_phys_off == 0)
1458                         mbuf_phys_off = rxq->mbuf_phys_off;
1459                 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1460                         PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1461                                      PRIx64, rxq->pool->name, nic->vf_id,
1462                                      mbuf_phys_off);
1463                         return -EINVAL;
1464                 }
1465         }
1466
1467         /* Check the level of buffers in the pool */
1468         total_rxq_desc = 0;
1469         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1470                 rxq = dev->data->rx_queues[qidx];
1471                 /* Count total numbers of rxq descs */
1472                 total_rxq_desc += rxq->qlen_mask + 1;
1473                 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1474                 exp_buffs *= dev->data->nb_rx_queues;
1475                 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1476                         PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1477                                      rxq->pool->name,
1478                                      rte_mempool_avail_count(rxq->pool),
1479                                      exp_buffs);
1480                         return -ENOENT;
1481                 }
1482         }
1483
1484         /* Check RBDR desc overflow */
1485         ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1486         if (ret == 0) {
1487                 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1488                              "VF%d", nic->vf_id);
1489                 return -ENOMEM;
1490         }
1491
1492         /* Enable qset */
1493         ret = nicvf_qset_config(nic);
1494         if (ret) {
1495                 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1496                              nic->vf_id);
1497                 return ret;
1498         }
1499
1500         /* Allocate RBDR and RBDR ring desc */
1501         nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1502         ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1503         if (ret) {
1504                 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1505                              "VF%d", nic->vf_id);
1506                 goto qset_reclaim;
1507         }
1508
1509         /* Enable and configure RBDR registers */
1510         ret = nicvf_qset_rbdr_config(nic, 0);
1511         if (ret) {
1512                 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1513                              nic->vf_id);
1514                 goto qset_rbdr_free;
1515         }
1516
1517         /* Fill rte_mempool buffers in RBDR pool and precharge it */
1518         ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1519                                         total_rxq_desc);
1520         if (ret) {
1521                 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1522                              nic->vf_id);
1523                 goto qset_rbdr_reclaim;
1524         }
1525
1526         PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1527                      nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1528
1529         /* Configure VLAN Strip */
1530         nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
1531
1532         /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1533          * to the 64bit memory address.
1534          * The alignment creates a hole in mbuf(between the end of headroom and
1535          * packet data start). The new revision of the HW provides an option to
1536          * disable the L3 alignment feature and make mbuf layout looks
1537          * more like other NICs. For better application compatibility, disabling
1538          * l3 alignment feature on the hardware revisions it supports
1539          */
1540         nicvf_apad_config(nic, false);
1541
1542         /* Get queue ranges for this VF */
1543         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1544
1545         /* Configure TX queues */
1546         for (qidx = tx_start; qidx <= tx_end; qidx++) {
1547                 ret = nicvf_vf_start_tx_queue(dev, nic,
1548                         qidx % MAX_SND_QUEUES_PER_QS);
1549                 if (ret)
1550                         goto start_txq_error;
1551         }
1552
1553         /* Configure RX queues */
1554         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1555                 ret = nicvf_vf_start_rx_queue(dev, nic,
1556                         qidx % MAX_RCV_QUEUES_PER_QS);
1557                 if (ret)
1558                         goto start_rxq_error;
1559         }
1560
1561         if (!nic->sqs_mode) {
1562                 /* Configure CPI algorithm */
1563                 ret = nicvf_configure_cpi(dev);
1564                 if (ret)
1565                         goto start_txq_error;
1566
1567                 ret = nicvf_mbox_get_rss_size(nic);
1568                 if (ret) {
1569                         PMD_INIT_LOG(ERR, "Failed to get rss table size");
1570                         goto qset_rss_error;
1571                 }
1572
1573                 /* Configure RSS */
1574                 ret = nicvf_configure_rss(dev);
1575                 if (ret)
1576                         goto qset_rss_error;
1577         }
1578
1579         /* Done; Let PF make the BGX's RX and TX switches to ON position */
1580         nicvf_mbox_cfg_done(nic);
1581         return 0;
1582
1583 qset_rss_error:
1584         nicvf_rss_term(nic);
1585 start_rxq_error:
1586         for (qidx = rx_start; qidx <= rx_end; qidx++)
1587                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1588 start_txq_error:
1589         for (qidx = tx_start; qidx <= tx_end; qidx++)
1590                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1591 qset_rbdr_reclaim:
1592         nicvf_qset_rbdr_reclaim(nic, 0);
1593         nicvf_rbdr_release_mbufs(dev, nic);
1594 qset_rbdr_free:
1595         if (nic->rbdr) {
1596                 rte_free(nic->rbdr);
1597                 nic->rbdr = NULL;
1598         }
1599 qset_reclaim:
1600         nicvf_qset_reclaim(nic);
1601         return ret;
1602 }
1603
1604 static int
1605 nicvf_dev_start(struct rte_eth_dev *dev)
1606 {
1607         uint16_t qidx;
1608         int ret;
1609         size_t i;
1610         struct nicvf *nic = nicvf_pmd_priv(dev);
1611         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1612         uint16_t mtu;
1613         uint32_t buffsz = 0, rbdrsz = 0;
1614         struct rte_pktmbuf_pool_private *mbp_priv;
1615         struct nicvf_rxq *rxq;
1616
1617         PMD_INIT_FUNC_TRACE();
1618
1619         /* This function must be called for a primary device */
1620         assert_primary(nic);
1621
1622         /* Validate RBDR buff size */
1623         for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1624                 rxq = dev->data->rx_queues[qidx];
1625                 mbp_priv = rte_mempool_get_priv(rxq->pool);
1626                 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1627                 if (buffsz % 128) {
1628                         PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1629                         return -EINVAL;
1630                 }
1631                 if (rbdrsz == 0)
1632                         rbdrsz = buffsz;
1633                 if (rbdrsz != buffsz) {
1634                         PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1635                                      qidx, rbdrsz, buffsz);
1636                         return -EINVAL;
1637                 }
1638         }
1639
1640         /* Configure loopback */
1641         ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1642         if (ret) {
1643                 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1644                 return ret;
1645         }
1646
1647         /* Reset all statistics counters attached to this port */
1648         ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1649         if (ret) {
1650                 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1651                 return ret;
1652         }
1653
1654         /* Setup scatter mode if needed by jumbo */
1655         if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1656                                             2 * VLAN_TAG_SIZE > buffsz)
1657                 dev->data->scattered_rx = 1;
1658         if (rx_conf->enable_scatter)
1659                 dev->data->scattered_rx = 1;
1660
1661         /* Setup MTU based on max_rx_pkt_len or default */
1662         mtu = dev->data->dev_conf.rxmode.jumbo_frame ?
1663                 dev->data->dev_conf.rxmode.max_rx_pkt_len
1664                         -  ETHER_HDR_LEN : ETHER_MTU;
1665
1666         if (nicvf_dev_set_mtu(dev, mtu)) {
1667                 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1668                 return -EBUSY;
1669         }
1670
1671         ret = nicvf_vf_start(dev, nic, rbdrsz);
1672         if (ret != 0)
1673                 return ret;
1674
1675         for (i = 0; i < nic->sqs_count; i++) {
1676                 assert(nic->snicvf[i]);
1677
1678                 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1679                 if (ret != 0)
1680                         return ret;
1681         }
1682
1683         /* Configure callbacks based on scatter mode */
1684         nicvf_set_tx_function(dev);
1685         nicvf_set_rx_function(dev);
1686
1687         return 0;
1688 }
1689
1690 static void
1691 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1692 {
1693         size_t i;
1694         int ret;
1695         struct nicvf *nic = nicvf_pmd_priv(dev);
1696
1697         PMD_INIT_FUNC_TRACE();
1698
1699         /* Teardown secondary vf first */
1700         for (i = 0; i < nic->sqs_count; i++) {
1701                 if (!nic->snicvf[i])
1702                         continue;
1703
1704                 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1705         }
1706
1707         /* Stop the primary VF now */
1708         nicvf_vf_stop(dev, nic, cleanup);
1709
1710         /* Disable loopback */
1711         ret = nicvf_loopback_config(nic, 0);
1712         if (ret)
1713                 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1714
1715         /* Reclaim CPI configuration */
1716         ret = nicvf_mbox_config_cpi(nic, 0);
1717         if (ret)
1718                 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1719 }
1720
1721 static void
1722 nicvf_dev_stop(struct rte_eth_dev *dev)
1723 {
1724         PMD_INIT_FUNC_TRACE();
1725
1726         nicvf_dev_stop_cleanup(dev, false);
1727 }
1728
1729 static void
1730 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1731 {
1732         int ret;
1733         uint16_t qidx;
1734         uint16_t tx_start, tx_end;
1735         uint16_t rx_start, rx_end;
1736
1737         PMD_INIT_FUNC_TRACE();
1738
1739         if (cleanup) {
1740                 /* Let PF make the BGX's RX and TX switches to OFF position */
1741                 nicvf_mbox_shutdown(nic);
1742         }
1743
1744         /* Disable VLAN Strip */
1745         nicvf_vlan_hw_strip(nic, 0);
1746
1747         /* Get queue ranges for this VF */
1748         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1749
1750         for (qidx = tx_start; qidx <= tx_end; qidx++)
1751                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1752
1753         /* Get queue ranges for this VF */
1754         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1755
1756         /* Reclaim rq */
1757         for (qidx = rx_start; qidx <= rx_end; qidx++)
1758                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1759
1760         /* Reclaim RBDR */
1761         ret = nicvf_qset_rbdr_reclaim(nic, 0);
1762         if (ret)
1763                 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1764
1765         /* Move all charged buffers in RBDR back to pool */
1766         if (nic->rbdr != NULL)
1767                 nicvf_rbdr_release_mbufs(dev, nic);
1768
1769         /* Disable qset */
1770         ret = nicvf_qset_reclaim(nic);
1771         if (ret)
1772                 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1773
1774         /* Disable all interrupts */
1775         nicvf_disable_all_interrupts(nic);
1776
1777         /* Free RBDR SW structure */
1778         if (nic->rbdr) {
1779                 rte_free(nic->rbdr);
1780                 nic->rbdr = NULL;
1781         }
1782 }
1783
1784 static void
1785 nicvf_dev_close(struct rte_eth_dev *dev)
1786 {
1787         size_t i;
1788         struct nicvf *nic = nicvf_pmd_priv(dev);
1789
1790         PMD_INIT_FUNC_TRACE();
1791
1792         nicvf_dev_stop_cleanup(dev, true);
1793         nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1794
1795         for (i = 0; i < nic->sqs_count; i++) {
1796                 if (!nic->snicvf[i])
1797                         continue;
1798
1799                 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1800         }
1801 }
1802
1803 static int
1804 nicvf_request_sqs(struct nicvf *nic)
1805 {
1806         size_t i;
1807
1808         assert_primary(nic);
1809         assert(nic->sqs_count > 0);
1810         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1811
1812         /* Set no of Rx/Tx queues in each of the SQsets */
1813         for (i = 0; i < nic->sqs_count; i++) {
1814                 if (nicvf_svf_empty())
1815                         rte_panic("Cannot assign sufficient number of "
1816                                   "secondary queues to primary VF%" PRIu8 "\n",
1817                                   nic->vf_id);
1818
1819                 nic->snicvf[i] = nicvf_svf_pop();
1820                 nic->snicvf[i]->sqs_id = i;
1821         }
1822
1823         return nicvf_mbox_request_sqs(nic);
1824 }
1825
1826 static int
1827 nicvf_dev_configure(struct rte_eth_dev *dev)
1828 {
1829         struct rte_eth_dev_data *data = dev->data;
1830         struct rte_eth_conf *conf = &data->dev_conf;
1831         struct rte_eth_rxmode *rxmode = &conf->rxmode;
1832         struct rte_eth_txmode *txmode = &conf->txmode;
1833         struct nicvf *nic = nicvf_pmd_priv(dev);
1834         uint8_t cqcount;
1835
1836         PMD_INIT_FUNC_TRACE();
1837
1838         if (!rte_eal_has_hugepages()) {
1839                 PMD_INIT_LOG(INFO, "Huge page is not configured");
1840                 return -EINVAL;
1841         }
1842
1843         if (txmode->mq_mode) {
1844                 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1845                 return -EINVAL;
1846         }
1847
1848         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1849                 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1850                 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1851                 return -EINVAL;
1852         }
1853
1854         if (!rxmode->hw_strip_crc) {
1855                 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1856                 rxmode->hw_strip_crc = 1;
1857         }
1858
1859         if (rxmode->hw_ip_checksum) {
1860                 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
1861                 rxmode->hw_ip_checksum = 0;
1862         }
1863
1864         if (rxmode->split_hdr_size) {
1865                 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1866                 return -EINVAL;
1867         }
1868
1869         if (rxmode->hw_vlan_filter) {
1870                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
1871                 return -EINVAL;
1872         }
1873
1874         if (rxmode->hw_vlan_extend) {
1875                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
1876                 return -EINVAL;
1877         }
1878
1879         if (rxmode->enable_lro) {
1880                 PMD_INIT_LOG(INFO, "LRO not supported");
1881                 return -EINVAL;
1882         }
1883
1884         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1885                 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1886                 return -EINVAL;
1887         }
1888
1889         if (conf->dcb_capability_en) {
1890                 PMD_INIT_LOG(INFO, "DCB enable not supported");
1891                 return -EINVAL;
1892         }
1893
1894         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1895                 PMD_INIT_LOG(INFO, "Flow director not supported");
1896                 return -EINVAL;
1897         }
1898
1899         assert_primary(nic);
1900         NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1901         cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1902         if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1903                 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1904                 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1905         } else {
1906                 nic->sqs_count = 0;
1907         }
1908
1909         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1910
1911         if (nic->sqs_count > 0) {
1912                 if (nicvf_request_sqs(nic)) {
1913                         rte_panic("Cannot assign sufficient number of "
1914                                   "secondary queues to PORT%d VF%" PRIu8 "\n",
1915                                   dev->data->port_id, nic->vf_id);
1916                 }
1917         }
1918
1919         PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1920                 dev->data->port_id, nicvf_hw_cap(nic));
1921
1922         return 0;
1923 }
1924
1925 /* Initialize and register driver with DPDK Application */
1926 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1927         .dev_configure            = nicvf_dev_configure,
1928         .dev_start                = nicvf_dev_start,
1929         .dev_stop                 = nicvf_dev_stop,
1930         .link_update              = nicvf_dev_link_update,
1931         .dev_close                = nicvf_dev_close,
1932         .stats_get                = nicvf_dev_stats_get,
1933         .stats_reset              = nicvf_dev_stats_reset,
1934         .promiscuous_enable       = nicvf_dev_promisc_enable,
1935         .dev_infos_get            = nicvf_dev_info_get,
1936         .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1937         .mtu_set                  = nicvf_dev_set_mtu,
1938         .reta_update              = nicvf_dev_reta_update,
1939         .reta_query               = nicvf_dev_reta_query,
1940         .rss_hash_update          = nicvf_dev_rss_hash_update,
1941         .rss_hash_conf_get        = nicvf_dev_rss_hash_conf_get,
1942         .rx_queue_start           = nicvf_dev_rx_queue_start,
1943         .rx_queue_stop            = nicvf_dev_rx_queue_stop,
1944         .tx_queue_start           = nicvf_dev_tx_queue_start,
1945         .tx_queue_stop            = nicvf_dev_tx_queue_stop,
1946         .rx_queue_setup           = nicvf_dev_rx_queue_setup,
1947         .rx_queue_release         = nicvf_dev_rx_queue_release,
1948         .rx_queue_count           = nicvf_dev_rx_queue_count,
1949         .tx_queue_setup           = nicvf_dev_tx_queue_setup,
1950         .tx_queue_release         = nicvf_dev_tx_queue_release,
1951         .get_reg                  = nicvf_dev_get_regs,
1952 };
1953
1954 static int
1955 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
1956 {
1957         int ret;
1958         struct rte_pci_device *pci_dev;
1959         struct nicvf *nic = nicvf_pmd_priv(eth_dev);
1960
1961         PMD_INIT_FUNC_TRACE();
1962
1963         eth_dev->dev_ops = &nicvf_eth_dev_ops;
1964
1965         /* For secondary processes, the primary has done all the work */
1966         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1967                 if (nic) {
1968                         /* Setup callbacks for secondary process */
1969                         nicvf_set_tx_function(eth_dev);
1970                         nicvf_set_rx_function(eth_dev);
1971                         return 0;
1972                 } else {
1973                         /* If nic == NULL than it is secondary function
1974                          * so ethdev need to be released by caller */
1975                         return ENOTSUP;
1976                 }
1977         }
1978
1979         pci_dev = eth_dev->pci_dev;
1980         rte_eth_copy_pci_info(eth_dev, pci_dev);
1981
1982         nic->device_id = pci_dev->id.device_id;
1983         nic->vendor_id = pci_dev->id.vendor_id;
1984         nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
1985         nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1986
1987         PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
1988                         pci_dev->id.vendor_id, pci_dev->id.device_id,
1989                         pci_dev->addr.domain, pci_dev->addr.bus,
1990                         pci_dev->addr.devid, pci_dev->addr.function);
1991
1992         nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
1993         if (!nic->reg_base) {
1994                 PMD_INIT_LOG(ERR, "Failed to map BAR0");
1995                 ret = -ENODEV;
1996                 goto fail;
1997         }
1998
1999         nicvf_disable_all_interrupts(nic);
2000
2001         ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2002         if (ret) {
2003                 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2004                 goto fail;
2005         }
2006
2007         ret = nicvf_mbox_check_pf_ready(nic);
2008         if (ret) {
2009                 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2010                 goto alarm_fail;
2011         } else {
2012                 PMD_INIT_LOG(INFO,
2013                         "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2014                         nic->node, nic->vf_id,
2015                         nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2016                         nic->sqs_mode ? "true" : "false",
2017                         nic->loopback_supported ? "true" : "false"
2018                         );
2019         }
2020
2021         ret = nicvf_base_init(nic);
2022         if (ret) {
2023                 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2024                 goto malloc_fail;
2025         }
2026
2027         if (nic->sqs_mode) {
2028                 /* Push nic to stack of secondary vfs */
2029                 nicvf_svf_push(nic);
2030
2031                 /* Steal nic pointer from the device for further reuse */
2032                 eth_dev->data->dev_private = NULL;
2033
2034                 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2035                 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2036                 if (ret) {
2037                         PMD_INIT_LOG(ERR, "Failed to start period alarm");
2038                         goto fail;
2039                 }
2040
2041                 /* Detach port by returning postive error number */
2042                 return ENOTSUP;
2043         }
2044
2045         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2046         if (eth_dev->data->mac_addrs == NULL) {
2047                 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2048                 ret = -ENOMEM;
2049                 goto alarm_fail;
2050         }
2051         if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2052                 eth_random_addr(&nic->mac_addr[0]);
2053
2054         ether_addr_copy((struct ether_addr *)nic->mac_addr,
2055                         &eth_dev->data->mac_addrs[0]);
2056
2057         ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2058         if (ret) {
2059                 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2060                 goto malloc_fail;
2061         }
2062
2063         PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2064                 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2065                 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2066                 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2067
2068         return 0;
2069
2070 malloc_fail:
2071         rte_free(eth_dev->data->mac_addrs);
2072 alarm_fail:
2073         nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2074 fail:
2075         return ret;
2076 }
2077
2078 static const struct rte_pci_id pci_id_nicvf_map[] = {
2079         {
2080                 .class_id = RTE_CLASS_ANY_ID,
2081                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2082                 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2083                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2084                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2085         },
2086         {
2087                 .class_id = RTE_CLASS_ANY_ID,
2088                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2089                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2090                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2091                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2092         },
2093         {
2094                 .class_id = RTE_CLASS_ANY_ID,
2095                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2096                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2097                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2098                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2099         },
2100         {
2101                 .class_id = RTE_CLASS_ANY_ID,
2102                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2103                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2104                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2105                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2106         },
2107         {
2108                 .vendor_id = 0,
2109         },
2110 };
2111
2112 static struct eth_driver rte_nicvf_pmd = {
2113         .pci_drv = {
2114                 .id_table = pci_id_nicvf_map,
2115                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2116                 .probe = rte_eth_dev_pci_probe,
2117                 .remove = rte_eth_dev_pci_remove,
2118         },
2119         .eth_dev_init = nicvf_eth_dev_init,
2120         .dev_private_size = sizeof(struct nicvf),
2121 };
2122
2123 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd.pci_drv);
2124 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);