drivers/net/thunderx/nicvf_ethdev.c

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium, Inc. 2016.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium, Inc nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <assert.h>
  34 #include <stdio.h>
  35 #include <stdbool.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <sys/queue.h>
  44
  45 #include <rte_alarm.h>
  46 #include <rte_atomic.h>
  47 #include <rte_branch_prediction.h>
  48 #include <rte_byteorder.h>
  49 #include <rte_common.h>
  50 #include <rte_cycles.h>
  51 #include <rte_debug.h>
  52 #include <rte_dev.h>
  53 #include <rte_eal.h>
  54 #include <rte_ether.h>
  55 #include <rte_ethdev.h>
  56 #include <rte_ethdev_pci.h>
  57 #include <rte_interrupts.h>
  58 #include <rte_log.h>
  59 #include <rte_memory.h>
  60 #include <rte_memzone.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_pci.h>
  64 #include <rte_tailq.h>
  65
  66 #include "base/nicvf_plat.h"
  67
  68 #include "nicvf_ethdev.h"
  69 #include "nicvf_rxtx.h"
  70 #include "nicvf_svf.h"
  71 #include "nicvf_logs.h"
  72
  73 static void nicvf_dev_stop(struct rte_eth_dev *dev);
  74 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
  75 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
  76                           bool cleanup);
  77
  78 static inline int
  79 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
  80                                struct rte_eth_link *link)
  81 {
  82         struct rte_eth_link *dst = &dev->data->dev_link;
  83         struct rte_eth_link *src = link;
  84
  85         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
  86                 *(uint64_t *)src) == 0)
  87                 return -1;
  88
  89         return 0;
  90 }
  91
  92 static inline void
  93 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
  94 {
  95         link->link_status = nic->link_up;
  96         link->link_duplex = ETH_LINK_AUTONEG;
  97         if (nic->duplex == NICVF_HALF_DUPLEX)
  98                 link->link_duplex = ETH_LINK_HALF_DUPLEX;
  99         else if (nic->duplex == NICVF_FULL_DUPLEX)
 100                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
 101         link->link_speed = nic->speed;
 102         link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
 103 }
 104
 105 static void
 106 nicvf_interrupt(void *arg)
 107 {
 108         struct rte_eth_dev *dev = arg;
 109         struct nicvf *nic = nicvf_pmd_priv(dev);
 110
 111         if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
 112                 if (dev->data->dev_conf.intr_conf.lsc)
 113                         nicvf_set_eth_link_status(nic, &dev->data->dev_link);
 114                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
 115                                               NULL, NULL);
 116         }
 117
 118         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 119                                 nicvf_interrupt, dev);
 120 }
 121
 122 static void
 123 nicvf_vf_interrupt(void *arg)
 124 {
 125         struct nicvf *nic = arg;
 126
 127         nicvf_reg_poll_interrupts(nic);
 128
 129         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 130                                 nicvf_vf_interrupt, nic);
 131 }
 132
 133 static int
 134 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
 135 {
 136         return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
 137 }
 138
 139 static int
 140 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
 141 {
 142         return rte_eal_alarm_cancel(fn, arg);
 143 }
 144
 145 /*
 146  * Return 0 means link status changed, -1 means not changed
 147  */
 148 static int
 149 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 150 {
 151 #define CHECK_INTERVAL 100  /* 100ms */
 152 #define MAX_CHECK_TIME 90   /* 9s (90 * 100ms) in total */
 153         struct rte_eth_link link;
 154         struct nicvf *nic = nicvf_pmd_priv(dev);
 155         int i;
 156
 157         PMD_INIT_FUNC_TRACE();
 158
 159         if (wait_to_complete) {
 160                 /* rte_eth_link_get() might need to wait up to 9 seconds */
 161                 for (i = 0; i < MAX_CHECK_TIME; i++) {
 162                         memset(&link, 0, sizeof(link));
 163                         nicvf_set_eth_link_status(nic, &link);
 164                         if (link.link_status)
 165                                 break;
 166                         rte_delay_ms(CHECK_INTERVAL);
 167                 }
 168         } else {
 169                 memset(&link, 0, sizeof(link));
 170                 nicvf_set_eth_link_status(nic, &link);
 171         }
 172         return nicvf_atomic_write_link_status(dev, &link);
 173 }
 174
 175 static int
 176 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 177 {
 178         struct nicvf *nic = nicvf_pmd_priv(dev);
 179         uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 180         size_t i;
 181
 182         PMD_INIT_FUNC_TRACE();
 183
 184         if (frame_size > NIC_HW_MAX_FRS)
 185                 return -EINVAL;
 186
 187         if (frame_size < NIC_HW_MIN_FRS)
 188                 return -EINVAL;
 189
 190         buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 191
 192         /*
 193          * Refuse mtu that requires the support of scattered packets
 194          * when this feature has not been enabled before.
 195          */
 196         if (!dev->data->scattered_rx &&
 197                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
 198                 return -EINVAL;
 199
 200         /* check <seg size> * <max_seg>  >= max_frame */
 201         if (dev->data->scattered_rx &&
 202                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
 203                 return -EINVAL;
 204
 205         if (frame_size > ETHER_MAX_LEN)
 206                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
 207         else
 208                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
 209
 210         if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
 211                 return -EINVAL;
 212
 213         /* Update max frame size */
 214         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
 215         nic->mtu = mtu;
 216
 217         for (i = 0; i < nic->sqs_count; i++)
 218                 nic->snicvf[i]->mtu = mtu;
 219
 220         return 0;
 221 }
 222
 223 static int
 224 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 225 {
 226         uint64_t *data = regs->data;
 227         struct nicvf *nic = nicvf_pmd_priv(dev);
 228
 229         if (data == NULL) {
 230                 regs->length = nicvf_reg_get_count();
 231                 regs->width = THUNDERX_REG_BYTES;
 232                 return 0;
 233         }
 234
 235         /* Support only full register dump */
 236         if ((regs->length == 0) ||
 237                 (regs->length == (uint32_t)nicvf_reg_get_count())) {
 238                 regs->version = nic->vendor_id << 16 | nic->device_id;
 239                 nicvf_reg_dump(nic, data);
 240                 return 0;
 241         }
 242         return -ENOTSUP;
 243 }
 244
 245 static void
 246 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 247 {
 248         uint16_t qidx;
 249         struct nicvf_hw_rx_qstats rx_qstats;
 250         struct nicvf_hw_tx_qstats tx_qstats;
 251         struct nicvf_hw_stats port_stats;
 252         struct nicvf *nic = nicvf_pmd_priv(dev);
 253         uint16_t rx_start, rx_end;
 254         uint16_t tx_start, tx_end;
 255         size_t i;
 256
 257         /* RX queue indices for the first VF */
 258         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 259
 260         /* Reading per RX ring stats */
 261         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 262                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 263                         break;
 264
 265                 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
 266                 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 267                 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 268         }
 269
 270         /* TX queue indices for the first VF */
 271         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 272
 273         /* Reading per TX ring stats */
 274         for (qidx = tx_start; qidx <= tx_end; qidx++) {
 275                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 276                         break;
 277
 278                 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
 279                 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 280                 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 281         }
 282
 283         for (i = 0; i < nic->sqs_count; i++) {
 284                 struct nicvf *snic = nic->snicvf[i];
 285
 286                 if (snic == NULL)
 287                         break;
 288
 289                 /* RX queue indices for a secondary VF */
 290                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 291
 292                 /* Reading per RX ring stats */
 293                 for (qidx = rx_start; qidx <= rx_end; qidx++) {
 294                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 295                                 break;
 296
 297                         nicvf_hw_get_rx_qstats(snic, &rx_qstats,
 298                                                qidx % MAX_RCV_QUEUES_PER_QS);
 299                         stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 300                         stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 301                 }
 302
 303                 /* TX queue indices for a secondary VF */
 304                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 305                 /* Reading per TX ring stats */
 306                 for (qidx = tx_start; qidx <= tx_end; qidx++) {
 307                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 308                                 break;
 309
 310                         nicvf_hw_get_tx_qstats(snic, &tx_qstats,
 311                                                qidx % MAX_SND_QUEUES_PER_QS);
 312                         stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 313                         stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 314                 }
 315         }
 316
 317         nicvf_hw_get_stats(nic, &port_stats);
 318         stats->ibytes = port_stats.rx_bytes;
 319         stats->ipackets = port_stats.rx_ucast_frames;
 320         stats->ipackets += port_stats.rx_bcast_frames;
 321         stats->ipackets += port_stats.rx_mcast_frames;
 322         stats->ierrors = port_stats.rx_l2_errors;
 323         stats->imissed = port_stats.rx_drop_red;
 324         stats->imissed += port_stats.rx_drop_overrun;
 325         stats->imissed += port_stats.rx_drop_bcast;
 326         stats->imissed += port_stats.rx_drop_mcast;
 327         stats->imissed += port_stats.rx_drop_l3_bcast;
 328         stats->imissed += port_stats.rx_drop_l3_mcast;
 329
 330         stats->obytes = port_stats.tx_bytes_ok;
 331         stats->opackets = port_stats.tx_ucast_frames_ok;
 332         stats->opackets += port_stats.tx_bcast_frames_ok;
 333         stats->opackets += port_stats.tx_mcast_frames_ok;
 334         stats->oerrors = port_stats.tx_drops;
 335 }
 336
 337 static const uint32_t *
 338 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 339 {
 340         size_t copied;
 341         static uint32_t ptypes[32];
 342         struct nicvf *nic = nicvf_pmd_priv(dev);
 343         static const uint32_t ptypes_common[] = {
 344                 RTE_PTYPE_L3_IPV4,
 345                 RTE_PTYPE_L3_IPV4_EXT,
 346                 RTE_PTYPE_L3_IPV6,
 347                 RTE_PTYPE_L3_IPV6_EXT,
 348                 RTE_PTYPE_L4_TCP,
 349                 RTE_PTYPE_L4_UDP,
 350                 RTE_PTYPE_L4_FRAG,
 351         };
 352         static const uint32_t ptypes_tunnel[] = {
 353                 RTE_PTYPE_TUNNEL_GRE,
 354                 RTE_PTYPE_TUNNEL_GENEVE,
 355                 RTE_PTYPE_TUNNEL_VXLAN,
 356                 RTE_PTYPE_TUNNEL_NVGRE,
 357         };
 358         static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
 359
 360         copied = sizeof(ptypes_common);
 361         memcpy(ptypes, ptypes_common, copied);
 362         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 363                 memcpy((char *)ptypes + copied, ptypes_tunnel,
 364                         sizeof(ptypes_tunnel));
 365                 copied += sizeof(ptypes_tunnel);
 366         }
 367
 368         memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
 369         if (dev->rx_pkt_burst == nicvf_recv_pkts ||
 370                 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
 371                 return ptypes;
 372
 373         return NULL;
 374 }
 375
 376 static void
 377 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
 378 {
 379         int i;
 380         uint16_t rxqs = 0, txqs = 0;
 381         struct nicvf *nic = nicvf_pmd_priv(dev);
 382         uint16_t rx_start, rx_end;
 383         uint16_t tx_start, tx_end;
 384
 385         /* Reset all primary nic counters */
 386         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 387         for (i = rx_start; i <= rx_end; i++)
 388                 rxqs |= (0x3 << (i * 2));
 389
 390         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 391         for (i = tx_start; i <= tx_end; i++)
 392                 txqs |= (0x3 << (i * 2));
 393
 394         nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
 395
 396         /* Reset secondary nic queue counters */
 397         for (i = 0; i < nic->sqs_count; i++) {
 398                 struct nicvf *snic = nic->snicvf[i];
 399                 if (snic == NULL)
 400                         break;
 401
 402                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 403                 for (i = rx_start; i <= rx_end; i++)
 404                         rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
 405
 406                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 407                 for (i = tx_start; i <= tx_end; i++)
 408                         txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
 409
 410                 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
 411         }
 412 }
 413
 414 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
 415 static void
 416 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
 417 {
 418 }
 419
 420 static inline uint64_t
 421 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
 422 {
 423         uint64_t nic_rss = 0;
 424
 425         if (ethdev_rss & ETH_RSS_IPV4)
 426                 nic_rss |= RSS_IP_ENA;
 427
 428         if (ethdev_rss & ETH_RSS_IPV6)
 429                 nic_rss |= RSS_IP_ENA;
 430
 431         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
 432                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 433
 434         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
 435                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 436
 437         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
 438                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 439
 440         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
 441                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 442
 443         if (ethdev_rss & ETH_RSS_PORT)
 444                 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
 445
 446         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 447                 if (ethdev_rss & ETH_RSS_VXLAN)
 448                         nic_rss |= RSS_TUN_VXLAN_ENA;
 449
 450                 if (ethdev_rss & ETH_RSS_GENEVE)
 451                         nic_rss |= RSS_TUN_GENEVE_ENA;
 452
 453                 if (ethdev_rss & ETH_RSS_NVGRE)
 454                         nic_rss |= RSS_TUN_NVGRE_ENA;
 455         }
 456
 457         return nic_rss;
 458 }
 459
 460 static inline uint64_t
 461 nicvf_rss_nic_to_ethdev(struct nicvf *nic,  uint64_t nic_rss)
 462 {
 463         uint64_t ethdev_rss = 0;
 464
 465         if (nic_rss & RSS_IP_ENA)
 466                 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
 467
 468         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
 469                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
 470                                 ETH_RSS_NONFRAG_IPV6_TCP);
 471
 472         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
 473                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
 474                                 ETH_RSS_NONFRAG_IPV6_UDP);
 475
 476         if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
 477                 ethdev_rss |= ETH_RSS_PORT;
 478
 479         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 480                 if (nic_rss & RSS_TUN_VXLAN_ENA)
 481                         ethdev_rss |= ETH_RSS_VXLAN;
 482
 483                 if (nic_rss & RSS_TUN_GENEVE_ENA)
 484                         ethdev_rss |= ETH_RSS_GENEVE;
 485
 486                 if (nic_rss & RSS_TUN_NVGRE_ENA)
 487                         ethdev_rss |= ETH_RSS_NVGRE;
 488         }
 489         return ethdev_rss;
 490 }
 491
 492 static int
 493 nicvf_dev_reta_query(struct rte_eth_dev *dev,
 494                      struct rte_eth_rss_reta_entry64 *reta_conf,
 495                      uint16_t reta_size)
 496 {
 497         struct nicvf *nic = nicvf_pmd_priv(dev);
 498         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 499         int ret, i, j;
 500
 501         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 502                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 503                         "(%d) doesn't match the number hardware can supported "
 504                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 505                 return -EINVAL;
 506         }
 507
 508         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 509         if (ret)
 510                 return ret;
 511
 512         /* Copy RETA table */
 513         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 514                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 515                         if ((reta_conf[i].mask >> j) & 0x01)
 516                                 reta_conf[i].reta[j] = tbl[j];
 517         }
 518
 519         return 0;
 520 }
 521
 522 static int
 523 nicvf_dev_reta_update(struct rte_eth_dev *dev,
 524                       struct rte_eth_rss_reta_entry64 *reta_conf,
 525                       uint16_t reta_size)
 526 {
 527         struct nicvf *nic = nicvf_pmd_priv(dev);
 528         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 529         int ret, i, j;
 530
 531         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 532                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 533                         "(%d) doesn't match the number hardware can supported "
 534                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 535                 return -EINVAL;
 536         }
 537
 538         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 539         if (ret)
 540                 return ret;
 541
 542         /* Copy RETA table */
 543         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 544                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 545                         if ((reta_conf[i].mask >> j) & 0x01)
 546                                 tbl[j] = reta_conf[i].reta[j];
 547         }
 548
 549         return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 550 }
 551
 552 static int
 553 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 554                             struct rte_eth_rss_conf *rss_conf)
 555 {
 556         struct nicvf *nic = nicvf_pmd_priv(dev);
 557
 558         if (rss_conf->rss_key)
 559                 nicvf_rss_get_key(nic, rss_conf->rss_key);
 560
 561         rss_conf->rss_key_len =  RSS_HASH_KEY_BYTE_SIZE;
 562         rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
 563         return 0;
 564 }
 565
 566 static int
 567 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
 568                           struct rte_eth_rss_conf *rss_conf)
 569 {
 570         struct nicvf *nic = nicvf_pmd_priv(dev);
 571         uint64_t nic_rss;
 572
 573         if (rss_conf->rss_key &&
 574                 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
 575                 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
 576                                 rss_conf->rss_key_len);
 577                 return -EINVAL;
 578         }
 579
 580         if (rss_conf->rss_key)
 581                 nicvf_rss_set_key(nic, rss_conf->rss_key);
 582
 583         nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
 584         nicvf_rss_set_cfg(nic, nic_rss);
 585         return 0;
 586 }
 587
 588 static int
 589 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 590                     struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
 591 {
 592         const struct rte_memzone *rz;
 593         uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
 594
 595         rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
 596                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 597                                       NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
 598         if (rz == NULL) {
 599                 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
 600                 return -ENOMEM;
 601         }
 602
 603         memset(rz->addr, 0, ring_size);
 604
 605         rxq->phys = rz->phys_addr;
 606         rxq->desc = rz->addr;
 607         rxq->qlen_mask = desc_cnt - 1;
 608
 609         return 0;
 610 }
 611
 612 static int
 613 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 614                     struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
 615 {
 616         const struct rte_memzone *rz;
 617         uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
 618
 619         rz = rte_eth_dma_zone_reserve(dev, "sq",
 620                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 621                                       NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
 622         if (rz == NULL) {
 623                 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
 624                 return -ENOMEM;
 625         }
 626
 627         memset(rz->addr, 0, ring_size);
 628
 629         sq->phys = rz->phys_addr;
 630         sq->desc = rz->addr;
 631         sq->qlen_mask = desc_cnt - 1;
 632
 633         return 0;
 634 }
 635
 636 static int
 637 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 638                       uint32_t desc_cnt, uint32_t buffsz)
 639 {
 640         struct nicvf_rbdr *rbdr;
 641         const struct rte_memzone *rz;
 642         uint32_t ring_size;
 643
 644         assert(nic->rbdr == NULL);
 645         rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
 646                                   RTE_CACHE_LINE_SIZE, nic->node);
 647         if (rbdr == NULL) {
 648                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
 649                 return -ENOMEM;
 650         }
 651
 652         ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
 653         rz = rte_eth_dma_zone_reserve(dev, "rbdr",
 654                                       nicvf_netdev_qidx(nic, 0), ring_size,
 655                                       NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
 656         if (rz == NULL) {
 657                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
 658                 return -ENOMEM;
 659         }
 660
 661         memset(rz->addr, 0, ring_size);
 662
 663         rbdr->phys = rz->phys_addr;
 664         rbdr->tail = 0;
 665         rbdr->next_tail = 0;
 666         rbdr->desc = rz->addr;
 667         rbdr->buffsz = buffsz;
 668         rbdr->qlen_mask = desc_cnt - 1;
 669         rbdr->rbdr_status =
 670                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
 671         rbdr->rbdr_door =
 672                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
 673
 674         nic->rbdr = rbdr;
 675         return 0;
 676 }
 677
 678 static void
 679 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
 680                         nicvf_phys_addr_t phy)
 681 {
 682         uint16_t qidx;
 683         void *obj;
 684         struct nicvf_rxq *rxq;
 685         uint16_t rx_start, rx_end;
 686
 687         /* Get queue ranges for this VF */
 688         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 689
 690         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 691                 rxq = dev->data->rx_queues[qidx];
 692                 if (rxq->precharge_cnt) {
 693                         obj = (void *)nicvf_mbuff_phy2virt(phy,
 694                                                            rxq->mbuf_phys_off);
 695                         rte_mempool_put(rxq->pool, obj);
 696                         rxq->precharge_cnt--;
 697                         break;
 698                 }
 699         }
 700 }
 701
 702 static inline void
 703 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
 704 {
 705         uint32_t qlen_mask, head;
 706         struct rbdr_entry_t *entry;
 707         struct nicvf_rbdr *rbdr = nic->rbdr;
 708
 709         qlen_mask = rbdr->qlen_mask;
 710         head = rbdr->head;
 711         while (head != rbdr->tail) {
 712                 entry = rbdr->desc + head;
 713                 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
 714                 head++;
 715                 head = head & qlen_mask;
 716         }
 717 }
 718
 719 static inline void
 720 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
 721 {
 722         uint32_t head;
 723
 724         head = txq->head;
 725         while (head != txq->tail) {
 726                 if (txq->txbuffs[head]) {
 727                         rte_pktmbuf_free_seg(txq->txbuffs[head]);
 728                         txq->txbuffs[head] = NULL;
 729                 }
 730                 head++;
 731                 head = head & txq->qlen_mask;
 732         }
 733 }
 734
 735 static void
 736 nicvf_tx_queue_reset(struct nicvf_txq *txq)
 737 {
 738         uint32_t txq_desc_cnt = txq->qlen_mask + 1;
 739
 740         memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
 741         memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
 742         txq->tail = 0;
 743         txq->head = 0;
 744         txq->xmit_bufs = 0;
 745 }
 746
 747 static inline int
 748 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 749                         uint16_t qidx)
 750 {
 751         struct nicvf_txq *txq;
 752         int ret;
 753
 754         assert(qidx < MAX_SND_QUEUES_PER_QS);
 755
 756         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 757                 RTE_ETH_QUEUE_STATE_STARTED)
 758                 return 0;
 759
 760         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 761         txq->pool = NULL;
 762         ret = nicvf_qset_sq_config(nic, qidx, txq);
 763         if (ret) {
 764                 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
 765                              nic->vf_id, qidx, ret);
 766                 goto config_sq_error;
 767         }
 768
 769         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 770                 RTE_ETH_QUEUE_STATE_STARTED;
 771         return ret;
 772
 773 config_sq_error:
 774         nicvf_qset_sq_reclaim(nic, qidx);
 775         return ret;
 776 }
 777
 778 static inline int
 779 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 780                        uint16_t qidx)
 781 {
 782         struct nicvf_txq *txq;
 783         int ret;
 784
 785         assert(qidx < MAX_SND_QUEUES_PER_QS);
 786
 787         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 788                 RTE_ETH_QUEUE_STATE_STOPPED)
 789                 return 0;
 790
 791         ret = nicvf_qset_sq_reclaim(nic, qidx);
 792         if (ret)
 793                 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
 794                              nic->vf_id, qidx, ret);
 795
 796         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 797         nicvf_tx_queue_release_mbufs(txq);
 798         nicvf_tx_queue_reset(txq);
 799
 800         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 801                 RTE_ETH_QUEUE_STATE_STOPPED;
 802         return ret;
 803 }
 804
 805 static inline int
 806 nicvf_configure_cpi(struct rte_eth_dev *dev)
 807 {
 808         struct nicvf *nic = nicvf_pmd_priv(dev);
 809         uint16_t qidx, qcnt;
 810         int ret;
 811
 812         /* Count started rx queues */
 813         for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
 814                 if (dev->data->rx_queue_state[qidx] ==
 815                     RTE_ETH_QUEUE_STATE_STARTED)
 816                         qcnt++;
 817
 818         nic->cpi_alg = CPI_ALG_NONE;
 819         ret = nicvf_mbox_config_cpi(nic, qcnt);
 820         if (ret)
 821                 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
 822
 823         return ret;
 824 }
 825
 826 static inline int
 827 nicvf_configure_rss(struct rte_eth_dev *dev)
 828 {
 829         struct nicvf *nic = nicvf_pmd_priv(dev);
 830         uint64_t rsshf;
 831         int ret = -EINVAL;
 832
 833         rsshf = nicvf_rss_ethdev_to_nic(nic,
 834                         dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
 835         PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
 836                     dev->data->dev_conf.rxmode.mq_mode,
 837                     dev->data->nb_rx_queues,
 838                     dev->data->dev_conf.lpbk_mode, rsshf);
 839
 840         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
 841                 ret = nicvf_rss_term(nic);
 842         else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
 843                 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
 844         if (ret)
 845                 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
 846
 847         return ret;
 848 }
 849
 850 static int
 851 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
 852 {
 853         struct nicvf *nic = nicvf_pmd_priv(dev);
 854         unsigned int idx, qmap_size;
 855         uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
 856         uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
 857
 858         if (nic->cpi_alg != CPI_ALG_NONE)
 859                 return -EINVAL;
 860
 861         /* Prepare queue map */
 862         for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
 863                 if (dev->data->rx_queue_state[idx] ==
 864                                 RTE_ETH_QUEUE_STATE_STARTED)
 865                         qmap[qmap_size++] = idx;
 866         }
 867
 868         /* Update default RSS RETA */
 869         for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
 870                 default_reta[idx] = qmap[idx % qmap_size];
 871
 872         return nicvf_rss_reta_update(nic, default_reta,
 873                                      NIC_MAX_RSS_IDR_TBL_SIZE);
 874 }
 875
 876 static void
 877 nicvf_dev_tx_queue_release(void *sq)
 878 {
 879         struct nicvf_txq *txq;
 880
 881         PMD_INIT_FUNC_TRACE();
 882
 883         txq = (struct nicvf_txq *)sq;
 884         if (txq) {
 885                 if (txq->txbuffs != NULL) {
 886                         nicvf_tx_queue_release_mbufs(txq);
 887                         rte_free(txq->txbuffs);
 888                         txq->txbuffs = NULL;
 889                 }
 890                 rte_free(txq);
 891         }
 892 }
 893
 894 static void
 895 nicvf_set_tx_function(struct rte_eth_dev *dev)
 896 {
 897         struct nicvf_txq *txq;
 898         size_t i;
 899         bool multiseg = false;
 900
 901         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 902                 txq = dev->data->tx_queues[i];
 903                 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) {
 904                         multiseg = true;
 905                         break;
 906                 }
 907         }
 908
 909         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 910         if (multiseg) {
 911                 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
 912                 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
 913         } else {
 914                 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
 915                 dev->tx_pkt_burst = nicvf_xmit_pkts;
 916         }
 917
 918         if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
 919                 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
 920         else
 921                 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
 922 }
 923
 924 static void
 925 nicvf_set_rx_function(struct rte_eth_dev *dev)
 926 {
 927         if (dev->data->scattered_rx) {
 928                 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
 929                 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
 930         } else {
 931                 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
 932                 dev->rx_pkt_burst = nicvf_recv_pkts;
 933         }
 934 }
 935
 936 static int
 937 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 938                          uint16_t nb_desc, unsigned int socket_id,
 939                          const struct rte_eth_txconf *tx_conf)
 940 {
 941         uint16_t tx_free_thresh;
 942         uint8_t is_single_pool;
 943         struct nicvf_txq *txq;
 944         struct nicvf *nic = nicvf_pmd_priv(dev);
 945
 946         PMD_INIT_FUNC_TRACE();
 947
 948         if (qidx >= MAX_SND_QUEUES_PER_QS)
 949                 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
 950
 951         qidx = qidx % MAX_SND_QUEUES_PER_QS;
 952
 953         /* Socket id check */
 954         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 955                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 956                 socket_id, nic->node);
 957
 958         /* Tx deferred start is not supported */
 959         if (tx_conf->tx_deferred_start) {
 960                 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
 961                 return -EINVAL;
 962         }
 963
 964         /* Roundup nb_desc to available qsize and validate max number of desc */
 965         nb_desc = nicvf_qsize_sq_roundup(nb_desc);
 966         if (nb_desc == 0) {
 967                 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
 968                 return -EINVAL;
 969         }
 970
 971         /* Validate tx_free_thresh */
 972         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 973                                 tx_conf->tx_free_thresh :
 974                                 NICVF_DEFAULT_TX_FREE_THRESH);
 975
 976         if (tx_free_thresh > (nb_desc) ||
 977                 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
 978                 PMD_INIT_LOG(ERR,
 979                         "tx_free_thresh must be less than the number of TX "
 980                         "descriptors. (tx_free_thresh=%u port=%d "
 981                         "queue=%d)", (unsigned int)tx_free_thresh,
 982                         (int)dev->data->port_id, (int)qidx);
 983                 return -EINVAL;
 984         }
 985
 986         /* Free memory prior to re-allocation if needed. */
 987         if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
 988                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 989                                 nicvf_netdev_qidx(nic, qidx));
 990                 nicvf_dev_tx_queue_release(
 991                         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
 992                 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
 993         }
 994
 995         /* Allocating tx queue data structure */
 996         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
 997                                         RTE_CACHE_LINE_SIZE, nic->node);
 998         if (txq == NULL) {
 999                 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
1000                              nicvf_netdev_qidx(nic, qidx));
1001                 return -ENOMEM;
1002         }
1003
1004         txq->nic = nic;
1005         txq->queue_id = qidx;
1006         txq->tx_free_thresh = tx_free_thresh;
1007         txq->txq_flags = tx_conf->txq_flags;
1008         txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
1009         txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
1010         is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
1011                                 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
1012
1013         /* Choose optimum free threshold value for multipool case */
1014         if (!is_single_pool) {
1015                 txq->tx_free_thresh = (uint16_t)
1016                 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1017                                 NICVF_TX_FREE_MPOOL_THRESH :
1018                                 tx_conf->tx_free_thresh);
1019                 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1020         } else {
1021                 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1022         }
1023
1024         /* Allocate software ring */
1025         txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1026                                 nb_desc * sizeof(struct rte_mbuf *),
1027                                 RTE_CACHE_LINE_SIZE, nic->node);
1028
1029         if (txq->txbuffs == NULL) {
1030                 nicvf_dev_tx_queue_release(txq);
1031                 return -ENOMEM;
1032         }
1033
1034         if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1035                 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1036                 nicvf_dev_tx_queue_release(txq);
1037                 return -ENOMEM;
1038         }
1039
1040         nicvf_tx_queue_reset(txq);
1041
1042         PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
1043                         nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1044                         txq->phys);
1045
1046         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1047         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1048                 RTE_ETH_QUEUE_STATE_STOPPED;
1049         return 0;
1050 }
1051
1052 static inline void
1053 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1054 {
1055         uint32_t rxq_cnt;
1056         uint32_t nb_pkts, released_pkts = 0;
1057         uint32_t refill_cnt = 0;
1058         struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1059
1060         if (dev->rx_pkt_burst == NULL)
1061                 return;
1062
1063         while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1064                                 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1065                 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1066                                         NICVF_MAX_RX_FREE_THRESH);
1067                 PMD_DRV_LOG(INFO, "nb_pkts=%d  rxq_cnt=%d", nb_pkts, rxq_cnt);
1068                 while (nb_pkts) {
1069                         rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1070                         released_pkts++;
1071                 }
1072         }
1073
1074
1075         refill_cnt += nicvf_dev_rbdr_refill(dev,
1076                         nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1077
1078         PMD_DRV_LOG(INFO, "free_cnt=%d  refill_cnt=%d",
1079                     released_pkts, refill_cnt);
1080 }
1081
1082 static void
1083 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1084 {
1085         rxq->head = 0;
1086         rxq->available_space = 0;
1087         rxq->recv_buffers = 0;
1088 }
1089
1090 static inline int
1091 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1092                         uint16_t qidx)
1093 {
1094         struct nicvf_rxq *rxq;
1095         int ret;
1096
1097         assert(qidx < MAX_RCV_QUEUES_PER_QS);
1098
1099         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1100                 RTE_ETH_QUEUE_STATE_STARTED)
1101                 return 0;
1102
1103         /* Update rbdr pointer to all rxq */
1104         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1105         rxq->shared_rbdr = nic->rbdr;
1106
1107         ret = nicvf_qset_rq_config(nic, qidx, rxq);
1108         if (ret) {
1109                 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1110                              nic->vf_id, qidx, ret);
1111                 goto config_rq_error;
1112         }
1113         ret = nicvf_qset_cq_config(nic, qidx, rxq);
1114         if (ret) {
1115                 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1116                              nic->vf_id, qidx, ret);
1117                 goto config_cq_error;
1118         }
1119
1120         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1121                 RTE_ETH_QUEUE_STATE_STARTED;
1122         return 0;
1123
1124 config_cq_error:
1125         nicvf_qset_cq_reclaim(nic, qidx);
1126 config_rq_error:
1127         nicvf_qset_rq_reclaim(nic, qidx);
1128         return ret;
1129 }
1130
1131 static inline int
1132 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1133                        uint16_t qidx)
1134 {
1135         struct nicvf_rxq *rxq;
1136         int ret, other_error;
1137
1138         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1139                 RTE_ETH_QUEUE_STATE_STOPPED)
1140                 return 0;
1141
1142         ret = nicvf_qset_rq_reclaim(nic, qidx);
1143         if (ret)
1144                 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1145                              nic->vf_id, qidx, ret);
1146
1147         other_error = ret;
1148         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1149         nicvf_rx_queue_release_mbufs(dev, rxq);
1150         nicvf_rx_queue_reset(rxq);
1151
1152         ret = nicvf_qset_cq_reclaim(nic, qidx);
1153         if (ret)
1154                 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1155                              nic->vf_id, qidx, ret);
1156
1157         other_error |= ret;
1158         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1159                 RTE_ETH_QUEUE_STATE_STOPPED;
1160         return other_error;
1161 }
1162
1163 static void
1164 nicvf_dev_rx_queue_release(void *rx_queue)
1165 {
1166         PMD_INIT_FUNC_TRACE();
1167
1168         rte_free(rx_queue);
1169 }
1170
1171 static int
1172 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1173 {
1174         struct nicvf *nic = nicvf_pmd_priv(dev);
1175         int ret;
1176
1177         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1178                 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1179
1180         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1181
1182         ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1183         if (ret)
1184                 return ret;
1185
1186         ret = nicvf_configure_cpi(dev);
1187         if (ret)
1188                 return ret;
1189
1190         return nicvf_configure_rss_reta(dev);
1191 }
1192
1193 static int
1194 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1195 {
1196         int ret;
1197         struct nicvf *nic = nicvf_pmd_priv(dev);
1198
1199         if (qidx >= MAX_SND_QUEUES_PER_QS)
1200                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1201
1202         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1203
1204         ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1205         ret |= nicvf_configure_cpi(dev);
1206         ret |= nicvf_configure_rss_reta(dev);
1207         return ret;
1208 }
1209
1210 static int
1211 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1212 {
1213         struct nicvf *nic = nicvf_pmd_priv(dev);
1214
1215         if (qidx >= MAX_SND_QUEUES_PER_QS)
1216                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1217
1218         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1219
1220         return nicvf_vf_start_tx_queue(dev, nic, qidx);
1221 }
1222
1223 static int
1224 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1225 {
1226         struct nicvf *nic = nicvf_pmd_priv(dev);
1227
1228         if (qidx >= MAX_SND_QUEUES_PER_QS)
1229                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1230
1231         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1232
1233         return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1234 }
1235
1236 static inline void
1237 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq)
1238 {
1239         uintptr_t p;
1240         struct rte_mbuf mb_def;
1241
1242         RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8);
1243         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
1244         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
1245                                 offsetof(struct rte_mbuf, data_off) != 2);
1246         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
1247                                 offsetof(struct rte_mbuf, data_off) != 4);
1248         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
1249                                 offsetof(struct rte_mbuf, data_off) != 6);
1250         mb_def.nb_segs = 1;
1251         mb_def.data_off = RTE_PKTMBUF_HEADROOM;
1252         mb_def.port = rxq->port_id;
1253         rte_mbuf_refcnt_set(&mb_def, 1);
1254
1255         /* Prevent compiler reordering: rearm_data covers previous fields */
1256         rte_compiler_barrier();
1257         p = (uintptr_t)&mb_def.rearm_data;
1258         rxq->mbuf_initializer.value = *(uint64_t *)p;
1259 }
1260
1261 static int
1262 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1263                          uint16_t nb_desc, unsigned int socket_id,
1264                          const struct rte_eth_rxconf *rx_conf,
1265                          struct rte_mempool *mp)
1266 {
1267         uint16_t rx_free_thresh;
1268         struct nicvf_rxq *rxq;
1269         struct nicvf *nic = nicvf_pmd_priv(dev);
1270
1271         PMD_INIT_FUNC_TRACE();
1272
1273         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1274                 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1275
1276         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1277
1278         /* Socket id check */
1279         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1280                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1281                 socket_id, nic->node);
1282
1283         /* Mempool memory must be contiguous, so must be one memory segment*/
1284         if (mp->nb_mem_chunks != 1) {
1285                 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1286                 return -EINVAL;
1287         }
1288
1289         /* Mempool memory must be physically contiguous */
1290         if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) {
1291                 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1292                 return -EINVAL;
1293         }
1294
1295         /* Rx deferred start is not supported */
1296         if (rx_conf->rx_deferred_start) {
1297                 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1298                 return -EINVAL;
1299         }
1300
1301         /* Roundup nb_desc to available qsize and validate max number of desc */
1302         nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1303         if (nb_desc == 0) {
1304                 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1305                 return -EINVAL;
1306         }
1307
1308         /* Check rx_free_thresh upper bound */
1309         rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1310                                 rx_conf->rx_free_thresh :
1311                                 NICVF_DEFAULT_RX_FREE_THRESH);
1312         if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1313                 rx_free_thresh >= nb_desc * .75) {
1314                 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1315                                 rx_free_thresh);
1316                 return -EINVAL;
1317         }
1318
1319         /* Free memory prior to re-allocation if needed */
1320         if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1321                 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1322                                 nicvf_netdev_qidx(nic, qidx));
1323                 nicvf_dev_rx_queue_release(
1324                         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1325                 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1326         }
1327
1328         /* Allocate rxq memory */
1329         rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1330                                         RTE_CACHE_LINE_SIZE, nic->node);
1331         if (rxq == NULL) {
1332                 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1333                              nicvf_netdev_qidx(nic, qidx));
1334                 return -ENOMEM;
1335         }
1336
1337         rxq->nic = nic;
1338         rxq->pool = mp;
1339         rxq->queue_id = qidx;
1340         rxq->port_id = dev->data->port_id;
1341         rxq->rx_free_thresh = rx_free_thresh;
1342         rxq->rx_drop_en = rx_conf->rx_drop_en;
1343         rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1344         rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1345         rxq->precharge_cnt = 0;
1346
1347         if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1348                 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1349         else
1350                 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1351
1352         nicvf_rxq_mbuf_setup(rxq);
1353
1354         /* Alloc completion queue */
1355         if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1356                 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1357                 nicvf_dev_rx_queue_release(rxq);
1358                 return -ENOMEM;
1359         }
1360
1361         nicvf_rx_queue_reset(rxq);
1362
1363         PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
1364                         nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1365                         rte_mempool_avail_count(mp), rxq->phys);
1366
1367         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1368         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1369                 RTE_ETH_QUEUE_STATE_STOPPED;
1370         return 0;
1371 }
1372
1373 static void
1374 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1375 {
1376         struct nicvf *nic = nicvf_pmd_priv(dev);
1377         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1378
1379         PMD_INIT_FUNC_TRACE();
1380
1381         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1382
1383         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1384         dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
1385         dev_info->max_rx_queues =
1386                         (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1387         dev_info->max_tx_queues =
1388                         (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1389         dev_info->max_mac_addrs = 1;
1390         dev_info->max_vfs = pci_dev->max_vfs;
1391
1392         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1393         dev_info->tx_offload_capa =
1394                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1395                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1396                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1397                 DEV_TX_OFFLOAD_TCP_TSO     |
1398                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1399
1400         dev_info->reta_size = nic->rss_info.rss_size;
1401         dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1402         dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1403         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1404                 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1405
1406         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1407                 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1408                 .rx_drop_en = 0,
1409         };
1410
1411         dev_info->default_txconf = (struct rte_eth_txconf) {
1412                 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1413                 .txq_flags =
1414                         ETH_TXQ_FLAGS_NOMULTSEGS  |
1415                         ETH_TXQ_FLAGS_NOREFCOUNT  |
1416                         ETH_TXQ_FLAGS_NOMULTMEMP  |
1417                         ETH_TXQ_FLAGS_NOVLANOFFL  |
1418                         ETH_TXQ_FLAGS_NOXSUMSCTP,
1419         };
1420 }
1421
1422 static nicvf_phys_addr_t
1423 rbdr_rte_mempool_get(void *dev, void *opaque)
1424 {
1425         uint16_t qidx;
1426         uintptr_t mbuf;
1427         struct nicvf_rxq *rxq;
1428         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1429         struct nicvf *nic = (struct nicvf *)opaque;
1430         uint16_t rx_start, rx_end;
1431
1432         /* Get queue ranges for this VF */
1433         nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1434
1435         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1436                 rxq = eth_dev->data->rx_queues[qidx];
1437                 /* Maintain equal buffer count across all pools */
1438                 if (rxq->precharge_cnt >= rxq->qlen_mask)
1439                         continue;
1440                 rxq->precharge_cnt++;
1441                 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1442                 if (mbuf)
1443                         return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1444         }
1445         return 0;
1446 }
1447
1448 static int
1449 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1450 {
1451         int ret;
1452         uint16_t qidx, data_off;
1453         uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1454         uint64_t mbuf_phys_off = 0;
1455         struct nicvf_rxq *rxq;
1456         struct rte_mbuf *mbuf;
1457         uint16_t rx_start, rx_end;
1458         uint16_t tx_start, tx_end;
1459
1460         PMD_INIT_FUNC_TRACE();
1461
1462         /* Userspace process exited without proper shutdown in last run */
1463         if (nicvf_qset_rbdr_active(nic, 0))
1464                 nicvf_vf_stop(dev, nic, false);
1465
1466         /* Get queue ranges for this VF */
1467         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1468
1469         /*
1470          * Thunderx nicvf PMD can support more than one pool per port only when
1471          * 1) Data payload size is same across all the pools in given port
1472          * AND
1473          * 2) All mbuffs in the pools are from the same hugepage
1474          * AND
1475          * 3) Mbuff metadata size is same across all the pools in given port
1476          *
1477          * This is to support existing application that uses multiple pool/port.
1478          * But, the purpose of using multipool for QoS will not be addressed.
1479          *
1480          */
1481
1482         /* Validate mempool attributes */
1483         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1484                 rxq = dev->data->rx_queues[qidx];
1485                 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1486                 mbuf = rte_pktmbuf_alloc(rxq->pool);
1487                 if (mbuf == NULL) {
1488                         PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1489                                      "pool=%s",
1490                                      nic->vf_id, qidx, rxq->pool->name);
1491                         return -ENOMEM;
1492                 }
1493                 data_off = nicvf_mbuff_meta_length(mbuf);
1494                 data_off += RTE_PKTMBUF_HEADROOM;
1495                 rte_pktmbuf_free(mbuf);
1496
1497                 if (data_off % RTE_CACHE_LINE_SIZE) {
1498                         PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1499                                 rxq->pool->name, data_off,
1500                                 data_off % RTE_CACHE_LINE_SIZE);
1501                         return -EINVAL;
1502                 }
1503                 rxq->mbuf_phys_off -= data_off;
1504
1505                 if (mbuf_phys_off == 0)
1506                         mbuf_phys_off = rxq->mbuf_phys_off;
1507                 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1508                         PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1509                                      PRIx64, rxq->pool->name, nic->vf_id,
1510                                      mbuf_phys_off);
1511                         return -EINVAL;
1512                 }
1513         }
1514
1515         /* Check the level of buffers in the pool */
1516         total_rxq_desc = 0;
1517         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1518                 rxq = dev->data->rx_queues[qidx];
1519                 /* Count total numbers of rxq descs */
1520                 total_rxq_desc += rxq->qlen_mask + 1;
1521                 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1522                 exp_buffs *= dev->data->nb_rx_queues;
1523                 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1524                         PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1525                                      rxq->pool->name,
1526                                      rte_mempool_avail_count(rxq->pool),
1527                                      exp_buffs);
1528                         return -ENOENT;
1529                 }
1530         }
1531
1532         /* Check RBDR desc overflow */
1533         ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1534         if (ret == 0) {
1535                 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1536                              "VF%d", nic->vf_id);
1537                 return -ENOMEM;
1538         }
1539
1540         /* Enable qset */
1541         ret = nicvf_qset_config(nic);
1542         if (ret) {
1543                 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1544                              nic->vf_id);
1545                 return ret;
1546         }
1547
1548         /* Allocate RBDR and RBDR ring desc */
1549         nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1550         ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1551         if (ret) {
1552                 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1553                              "VF%d", nic->vf_id);
1554                 goto qset_reclaim;
1555         }
1556
1557         /* Enable and configure RBDR registers */
1558         ret = nicvf_qset_rbdr_config(nic, 0);
1559         if (ret) {
1560                 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1561                              nic->vf_id);
1562                 goto qset_rbdr_free;
1563         }
1564
1565         /* Fill rte_mempool buffers in RBDR pool and precharge it */
1566         ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1567                                         total_rxq_desc);
1568         if (ret) {
1569                 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1570                              nic->vf_id);
1571                 goto qset_rbdr_reclaim;
1572         }
1573
1574         PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1575                      nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1576
1577         /* Configure VLAN Strip */
1578         nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
1579
1580         /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1581          * to the 64bit memory address.
1582          * The alignment creates a hole in mbuf(between the end of headroom and
1583          * packet data start). The new revision of the HW provides an option to
1584          * disable the L3 alignment feature and make mbuf layout looks
1585          * more like other NICs. For better application compatibility, disabling
1586          * l3 alignment feature on the hardware revisions it supports
1587          */
1588         nicvf_apad_config(nic, false);
1589
1590         /* Get queue ranges for this VF */
1591         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1592
1593         /* Configure TX queues */
1594         for (qidx = tx_start; qidx <= tx_end; qidx++) {
1595                 ret = nicvf_vf_start_tx_queue(dev, nic,
1596                         qidx % MAX_SND_QUEUES_PER_QS);
1597                 if (ret)
1598                         goto start_txq_error;
1599         }
1600
1601         /* Configure RX queues */
1602         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1603                 ret = nicvf_vf_start_rx_queue(dev, nic,
1604                         qidx % MAX_RCV_QUEUES_PER_QS);
1605                 if (ret)
1606                         goto start_rxq_error;
1607         }
1608
1609         if (!nic->sqs_mode) {
1610                 /* Configure CPI algorithm */
1611                 ret = nicvf_configure_cpi(dev);
1612                 if (ret)
1613                         goto start_txq_error;
1614
1615                 ret = nicvf_mbox_get_rss_size(nic);
1616                 if (ret) {
1617                         PMD_INIT_LOG(ERR, "Failed to get rss table size");
1618                         goto qset_rss_error;
1619                 }
1620
1621                 /* Configure RSS */
1622                 ret = nicvf_configure_rss(dev);
1623                 if (ret)
1624                         goto qset_rss_error;
1625         }
1626
1627         /* Done; Let PF make the BGX's RX and TX switches to ON position */
1628         nicvf_mbox_cfg_done(nic);
1629         return 0;
1630
1631 qset_rss_error:
1632         nicvf_rss_term(nic);
1633 start_rxq_error:
1634         for (qidx = rx_start; qidx <= rx_end; qidx++)
1635                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1636 start_txq_error:
1637         for (qidx = tx_start; qidx <= tx_end; qidx++)
1638                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1639 qset_rbdr_reclaim:
1640         nicvf_qset_rbdr_reclaim(nic, 0);
1641         nicvf_rbdr_release_mbufs(dev, nic);
1642 qset_rbdr_free:
1643         if (nic->rbdr) {
1644                 rte_free(nic->rbdr);
1645                 nic->rbdr = NULL;
1646         }
1647 qset_reclaim:
1648         nicvf_qset_reclaim(nic);
1649         return ret;
1650 }
1651
1652 static int
1653 nicvf_dev_start(struct rte_eth_dev *dev)
1654 {
1655         uint16_t qidx;
1656         int ret;
1657         size_t i;
1658         struct nicvf *nic = nicvf_pmd_priv(dev);
1659         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1660         uint16_t mtu;
1661         uint32_t buffsz = 0, rbdrsz = 0;
1662         struct rte_pktmbuf_pool_private *mbp_priv;
1663         struct nicvf_rxq *rxq;
1664
1665         PMD_INIT_FUNC_TRACE();
1666
1667         /* This function must be called for a primary device */
1668         assert_primary(nic);
1669
1670         /* Validate RBDR buff size */
1671         for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1672                 rxq = dev->data->rx_queues[qidx];
1673                 mbp_priv = rte_mempool_get_priv(rxq->pool);
1674                 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1675                 if (buffsz % 128) {
1676                         PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1677                         return -EINVAL;
1678                 }
1679                 if (rbdrsz == 0)
1680                         rbdrsz = buffsz;
1681                 if (rbdrsz != buffsz) {
1682                         PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1683                                      qidx, rbdrsz, buffsz);
1684                         return -EINVAL;
1685                 }
1686         }
1687
1688         /* Configure loopback */
1689         ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1690         if (ret) {
1691                 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1692                 return ret;
1693         }
1694
1695         /* Reset all statistics counters attached to this port */
1696         ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1697         if (ret) {
1698                 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1699                 return ret;
1700         }
1701
1702         /* Setup scatter mode if needed by jumbo */
1703         if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1704                                             2 * VLAN_TAG_SIZE > buffsz)
1705                 dev->data->scattered_rx = 1;
1706         if (rx_conf->enable_scatter)
1707                 dev->data->scattered_rx = 1;
1708
1709         /* Setup MTU based on max_rx_pkt_len or default */
1710         mtu = dev->data->dev_conf.rxmode.jumbo_frame ?
1711                 dev->data->dev_conf.rxmode.max_rx_pkt_len
1712                         -  ETHER_HDR_LEN - ETHER_CRC_LEN
1713                 : ETHER_MTU;
1714
1715         if (nicvf_dev_set_mtu(dev, mtu)) {
1716                 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1717                 return -EBUSY;
1718         }
1719
1720         ret = nicvf_vf_start(dev, nic, rbdrsz);
1721         if (ret != 0)
1722                 return ret;
1723
1724         for (i = 0; i < nic->sqs_count; i++) {
1725                 assert(nic->snicvf[i]);
1726
1727                 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1728                 if (ret != 0)
1729                         return ret;
1730         }
1731
1732         /* Configure callbacks based on scatter mode */
1733         nicvf_set_tx_function(dev);
1734         nicvf_set_rx_function(dev);
1735
1736         return 0;
1737 }
1738
1739 static void
1740 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1741 {
1742         size_t i;
1743         int ret;
1744         struct nicvf *nic = nicvf_pmd_priv(dev);
1745
1746         PMD_INIT_FUNC_TRACE();
1747
1748         /* Teardown secondary vf first */
1749         for (i = 0; i < nic->sqs_count; i++) {
1750                 if (!nic->snicvf[i])
1751                         continue;
1752
1753                 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1754         }
1755
1756         /* Stop the primary VF now */
1757         nicvf_vf_stop(dev, nic, cleanup);
1758
1759         /* Disable loopback */
1760         ret = nicvf_loopback_config(nic, 0);
1761         if (ret)
1762                 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1763
1764         /* Reclaim CPI configuration */
1765         ret = nicvf_mbox_config_cpi(nic, 0);
1766         if (ret)
1767                 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1768 }
1769
1770 static void
1771 nicvf_dev_stop(struct rte_eth_dev *dev)
1772 {
1773         PMD_INIT_FUNC_TRACE();
1774
1775         nicvf_dev_stop_cleanup(dev, false);
1776 }
1777
1778 static void
1779 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1780 {
1781         int ret;
1782         uint16_t qidx;
1783         uint16_t tx_start, tx_end;
1784         uint16_t rx_start, rx_end;
1785
1786         PMD_INIT_FUNC_TRACE();
1787
1788         if (cleanup) {
1789                 /* Let PF make the BGX's RX and TX switches to OFF position */
1790                 nicvf_mbox_shutdown(nic);
1791         }
1792
1793         /* Disable VLAN Strip */
1794         nicvf_vlan_hw_strip(nic, 0);
1795
1796         /* Get queue ranges for this VF */
1797         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1798
1799         for (qidx = tx_start; qidx <= tx_end; qidx++)
1800                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1801
1802         /* Get queue ranges for this VF */
1803         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1804
1805         /* Reclaim rq */
1806         for (qidx = rx_start; qidx <= rx_end; qidx++)
1807                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1808
1809         /* Reclaim RBDR */
1810         ret = nicvf_qset_rbdr_reclaim(nic, 0);
1811         if (ret)
1812                 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1813
1814         /* Move all charged buffers in RBDR back to pool */
1815         if (nic->rbdr != NULL)
1816                 nicvf_rbdr_release_mbufs(dev, nic);
1817
1818         /* Disable qset */
1819         ret = nicvf_qset_reclaim(nic);
1820         if (ret)
1821                 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1822
1823         /* Disable all interrupts */
1824         nicvf_disable_all_interrupts(nic);
1825
1826         /* Free RBDR SW structure */
1827         if (nic->rbdr) {
1828                 rte_free(nic->rbdr);
1829                 nic->rbdr = NULL;
1830         }
1831 }
1832
1833 static void
1834 nicvf_dev_close(struct rte_eth_dev *dev)
1835 {
1836         size_t i;
1837         struct nicvf *nic = nicvf_pmd_priv(dev);
1838
1839         PMD_INIT_FUNC_TRACE();
1840
1841         nicvf_dev_stop_cleanup(dev, true);
1842         nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1843
1844         for (i = 0; i < nic->sqs_count; i++) {
1845                 if (!nic->snicvf[i])
1846                         continue;
1847
1848                 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1849         }
1850 }
1851
1852 static int
1853 nicvf_request_sqs(struct nicvf *nic)
1854 {
1855         size_t i;
1856
1857         assert_primary(nic);
1858         assert(nic->sqs_count > 0);
1859         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1860
1861         /* Set no of Rx/Tx queues in each of the SQsets */
1862         for (i = 0; i < nic->sqs_count; i++) {
1863                 if (nicvf_svf_empty())
1864                         rte_panic("Cannot assign sufficient number of "
1865                                   "secondary queues to primary VF%" PRIu8 "\n",
1866                                   nic->vf_id);
1867
1868                 nic->snicvf[i] = nicvf_svf_pop();
1869                 nic->snicvf[i]->sqs_id = i;
1870         }
1871
1872         return nicvf_mbox_request_sqs(nic);
1873 }
1874
1875 static int
1876 nicvf_dev_configure(struct rte_eth_dev *dev)
1877 {
1878         struct rte_eth_dev_data *data = dev->data;
1879         struct rte_eth_conf *conf = &data->dev_conf;
1880         struct rte_eth_rxmode *rxmode = &conf->rxmode;
1881         struct rte_eth_txmode *txmode = &conf->txmode;
1882         struct nicvf *nic = nicvf_pmd_priv(dev);
1883         uint8_t cqcount;
1884
1885         PMD_INIT_FUNC_TRACE();
1886
1887         if (!rte_eal_has_hugepages()) {
1888                 PMD_INIT_LOG(INFO, "Huge page is not configured");
1889                 return -EINVAL;
1890         }
1891
1892         if (txmode->mq_mode) {
1893                 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1894                 return -EINVAL;
1895         }
1896
1897         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1898                 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1899                 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1900                 return -EINVAL;
1901         }
1902
1903         if (!rxmode->hw_strip_crc) {
1904                 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1905                 rxmode->hw_strip_crc = 1;
1906         }
1907
1908         if (rxmode->hw_ip_checksum) {
1909                 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
1910                 rxmode->hw_ip_checksum = 0;
1911         }
1912
1913         if (rxmode->split_hdr_size) {
1914                 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1915                 return -EINVAL;
1916         }
1917
1918         if (rxmode->hw_vlan_filter) {
1919                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
1920                 return -EINVAL;
1921         }
1922
1923         if (rxmode->hw_vlan_extend) {
1924                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
1925                 return -EINVAL;
1926         }
1927
1928         if (rxmode->enable_lro) {
1929                 PMD_INIT_LOG(INFO, "LRO not supported");
1930                 return -EINVAL;
1931         }
1932
1933         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1934                 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1935                 return -EINVAL;
1936         }
1937
1938         if (conf->dcb_capability_en) {
1939                 PMD_INIT_LOG(INFO, "DCB enable not supported");
1940                 return -EINVAL;
1941         }
1942
1943         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1944                 PMD_INIT_LOG(INFO, "Flow director not supported");
1945                 return -EINVAL;
1946         }
1947
1948         assert_primary(nic);
1949         NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1950         cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1951         if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1952                 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1953                 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1954         } else {
1955                 nic->sqs_count = 0;
1956         }
1957
1958         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1959
1960         if (nic->sqs_count > 0) {
1961                 if (nicvf_request_sqs(nic)) {
1962                         rte_panic("Cannot assign sufficient number of "
1963                                   "secondary queues to PORT%d VF%" PRIu8 "\n",
1964                                   dev->data->port_id, nic->vf_id);
1965                 }
1966         }
1967
1968         PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1969                 dev->data->port_id, nicvf_hw_cap(nic));
1970
1971         return 0;
1972 }
1973
1974 /* Initialize and register driver with DPDK Application */
1975 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1976         .dev_configure            = nicvf_dev_configure,
1977         .dev_start                = nicvf_dev_start,
1978         .dev_stop                 = nicvf_dev_stop,
1979         .link_update              = nicvf_dev_link_update,
1980         .dev_close                = nicvf_dev_close,
1981         .stats_get                = nicvf_dev_stats_get,
1982         .stats_reset              = nicvf_dev_stats_reset,
1983         .promiscuous_enable       = nicvf_dev_promisc_enable,
1984         .dev_infos_get            = nicvf_dev_info_get,
1985         .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1986         .mtu_set                  = nicvf_dev_set_mtu,
1987         .reta_update              = nicvf_dev_reta_update,
1988         .reta_query               = nicvf_dev_reta_query,
1989         .rss_hash_update          = nicvf_dev_rss_hash_update,
1990         .rss_hash_conf_get        = nicvf_dev_rss_hash_conf_get,
1991         .rx_queue_start           = nicvf_dev_rx_queue_start,
1992         .rx_queue_stop            = nicvf_dev_rx_queue_stop,
1993         .tx_queue_start           = nicvf_dev_tx_queue_start,
1994         .tx_queue_stop            = nicvf_dev_tx_queue_stop,
1995         .rx_queue_setup           = nicvf_dev_rx_queue_setup,
1996         .rx_queue_release         = nicvf_dev_rx_queue_release,
1997         .rx_queue_count           = nicvf_dev_rx_queue_count,
1998         .tx_queue_setup           = nicvf_dev_tx_queue_setup,
1999         .tx_queue_release         = nicvf_dev_tx_queue_release,
2000         .get_reg                  = nicvf_dev_get_regs,
2001 };
2002
2003 static int
2004 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
2005 {
2006         int ret;
2007         struct rte_pci_device *pci_dev;
2008         struct nicvf *nic = nicvf_pmd_priv(eth_dev);
2009
2010         PMD_INIT_FUNC_TRACE();
2011
2012         eth_dev->dev_ops = &nicvf_eth_dev_ops;
2013
2014         /* For secondary processes, the primary has done all the work */
2015         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2016                 if (nic) {
2017                         /* Setup callbacks for secondary process */
2018                         nicvf_set_tx_function(eth_dev);
2019                         nicvf_set_rx_function(eth_dev);
2020                         return 0;
2021                 } else {
2022                         /* If nic == NULL than it is secondary function
2023                          * so ethdev need to be released by caller */
2024                         return ENOTSUP;
2025                 }
2026         }
2027
2028         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2029         rte_eth_copy_pci_info(eth_dev, pci_dev);
2030
2031         nic->device_id = pci_dev->id.device_id;
2032         nic->vendor_id = pci_dev->id.vendor_id;
2033         nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
2034         nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2035
2036         PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
2037                         pci_dev->id.vendor_id, pci_dev->id.device_id,
2038                         pci_dev->addr.domain, pci_dev->addr.bus,
2039                         pci_dev->addr.devid, pci_dev->addr.function);
2040
2041         nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2042         if (!nic->reg_base) {
2043                 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2044                 ret = -ENODEV;
2045                 goto fail;
2046         }
2047
2048         nicvf_disable_all_interrupts(nic);
2049
2050         ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2051         if (ret) {
2052                 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2053                 goto fail;
2054         }
2055
2056         ret = nicvf_mbox_check_pf_ready(nic);
2057         if (ret) {
2058                 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2059                 goto alarm_fail;
2060         } else {
2061                 PMD_INIT_LOG(INFO,
2062                         "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2063                         nic->node, nic->vf_id,
2064                         nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2065                         nic->sqs_mode ? "true" : "false",
2066                         nic->loopback_supported ? "true" : "false"
2067                         );
2068         }
2069
2070         ret = nicvf_base_init(nic);
2071         if (ret) {
2072                 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2073                 goto malloc_fail;
2074         }
2075
2076         if (nic->sqs_mode) {
2077                 /* Push nic to stack of secondary vfs */
2078                 nicvf_svf_push(nic);
2079
2080                 /* Steal nic pointer from the device for further reuse */
2081                 eth_dev->data->dev_private = NULL;
2082
2083                 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2084                 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2085                 if (ret) {
2086                         PMD_INIT_LOG(ERR, "Failed to start period alarm");
2087                         goto fail;
2088                 }
2089
2090                 /* Detach port by returning positive error number */
2091                 return ENOTSUP;
2092         }
2093
2094         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2095         if (eth_dev->data->mac_addrs == NULL) {
2096                 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2097                 ret = -ENOMEM;
2098                 goto alarm_fail;
2099         }
2100         if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2101                 eth_random_addr(&nic->mac_addr[0]);
2102
2103         ether_addr_copy((struct ether_addr *)nic->mac_addr,
2104                         &eth_dev->data->mac_addrs[0]);
2105
2106         ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2107         if (ret) {
2108                 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2109                 goto malloc_fail;
2110         }
2111
2112         PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2113                 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2114                 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2115                 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2116
2117         return 0;
2118
2119 malloc_fail:
2120         rte_free(eth_dev->data->mac_addrs);
2121 alarm_fail:
2122         nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2123 fail:
2124         return ret;
2125 }
2126
2127 static const struct rte_pci_id pci_id_nicvf_map[] = {
2128         {
2129                 .class_id = RTE_CLASS_ANY_ID,
2130                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2131                 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2132                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2133                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2134         },
2135         {
2136                 .class_id = RTE_CLASS_ANY_ID,
2137                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2138                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2139                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2140                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2141         },
2142         {
2143                 .class_id = RTE_CLASS_ANY_ID,
2144                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2145                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2146                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2147                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2148         },
2149         {
2150                 .class_id = RTE_CLASS_ANY_ID,
2151                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2152                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2153                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2154                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2155         },
2156         {
2157                 .vendor_id = 0,
2158         },
2159 };
2160
2161 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2162         struct rte_pci_device *pci_dev)
2163 {
2164         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf),
2165                 nicvf_eth_dev_init);
2166 }
2167
2168 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev)
2169 {
2170         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2171 }
2172
2173 static struct rte_pci_driver rte_nicvf_pmd = {
2174         .id_table = pci_id_nicvf_map,
2175         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES |
2176                         RTE_PCI_DRV_INTR_LSC,
2177         .probe = nicvf_eth_pci_probe,
2178         .remove = nicvf_eth_pci_remove,
2179 };
2180
2181 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd);
2182 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2183 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci");