drivers/net/thunderx/nicvf_rxtx.c

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium, Inc. 2016.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium, Inc nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <unistd.h>
  34 #include <stdint.h>
  35 #include <stdio.h>
  36 #include <stdlib.h>
  37
  38 #include <rte_atomic.h>
  39 #include <rte_branch_prediction.h>
  40 #include <rte_byteorder.h>
  41 #include <rte_common.h>
  42 #include <rte_cycles.h>
  43 #include <rte_errno.h>
  44 #include <rte_ethdev.h>
  45 #include <rte_ether.h>
  46 #include <rte_log.h>
  47 #include <rte_mbuf.h>
  48 #include <rte_prefetch.h>
  49
  50 #include "base/nicvf_plat.h"
  51
  52 #include "nicvf_ethdev.h"
  53 #include "nicvf_rxtx.h"
  54 #include "nicvf_logs.h"
  55
  56 static inline void __hot
  57 fill_sq_desc_header(union sq_entry_t *entry, struct rte_mbuf *pkt)
  58 {
  59         /* Local variable sqe to avoid read from sq desc memory*/
  60         union sq_entry_t sqe;
  61         uint64_t ol_flags;
  62
  63         /* Fill SQ header descriptor */
  64         sqe.buff[0] = 0;
  65         sqe.hdr.subdesc_type = SQ_DESC_TYPE_HEADER;
  66         /* Number of sub-descriptors following this one */
  67         sqe.hdr.subdesc_cnt = pkt->nb_segs;
  68         sqe.hdr.tot_len = pkt->pkt_len;
  69
  70         ol_flags = pkt->ol_flags & NICVF_TX_OFFLOAD_MASK;
  71         if (unlikely(ol_flags)) {
  72                 /* L4 cksum */
  73                 uint64_t l4_flags = ol_flags & PKT_TX_L4_MASK;
  74                 if (l4_flags == PKT_TX_TCP_CKSUM)
  75                         sqe.hdr.csum_l4 = SEND_L4_CSUM_TCP;
  76                 else if (l4_flags == PKT_TX_UDP_CKSUM)
  77                         sqe.hdr.csum_l4 = SEND_L4_CSUM_UDP;
  78                 else
  79                         sqe.hdr.csum_l4 = SEND_L4_CSUM_DISABLE;
  80
  81                 sqe.hdr.l3_offset = pkt->l2_len;
  82                 sqe.hdr.l4_offset = pkt->l3_len + pkt->l2_len;
  83
  84                 /* L3 cksum */
  85                 if (ol_flags & PKT_TX_IP_CKSUM)
  86                         sqe.hdr.csum_l3 = 1;
  87         }
  88
  89         entry->buff[0] = sqe.buff[0];
  90 }
  91
  92 void __hot
  93 nicvf_single_pool_free_xmited_buffers(struct nicvf_txq *sq)
  94 {
  95         int j = 0;
  96         uint32_t curr_head;
  97         uint32_t head = sq->head;
  98         struct rte_mbuf **txbuffs = sq->txbuffs;
  99         void *obj_p[NICVF_MAX_TX_FREE_THRESH] __rte_cache_aligned;
 100
 101         curr_head = nicvf_addr_read(sq->sq_head) >> 4;
 102         while (head != curr_head) {
 103                 if (txbuffs[head])
 104                         obj_p[j++] = txbuffs[head];
 105
 106                 head = (head + 1) & sq->qlen_mask;
 107         }
 108
 109         rte_mempool_put_bulk(sq->pool, obj_p, j);
 110         sq->head = curr_head;
 111         sq->xmit_bufs -= j;
 112         NICVF_TX_ASSERT(sq->xmit_bufs >= 0);
 113 }
 114
 115 void __hot
 116 nicvf_multi_pool_free_xmited_buffers(struct nicvf_txq *sq)
 117 {
 118         uint32_t n = 0;
 119         uint32_t curr_head;
 120         uint32_t head = sq->head;
 121         struct rte_mbuf **txbuffs = sq->txbuffs;
 122
 123         curr_head = nicvf_addr_read(sq->sq_head) >> 4;
 124         while (head != curr_head) {
 125                 if (txbuffs[head]) {
 126                         rte_pktmbuf_free_seg(txbuffs[head]);
 127                         n++;
 128                 }
 129
 130                 head = (head + 1) & sq->qlen_mask;
 131         }
 132
 133         sq->head = curr_head;
 134         sq->xmit_bufs -= n;
 135         NICVF_TX_ASSERT(sq->xmit_bufs >= 0);
 136 }
 137
 138 static inline uint32_t __hot
 139 nicvf_free_tx_desc(struct nicvf_txq *sq)
 140 {
 141         return ((sq->head - sq->tail - 1) & sq->qlen_mask);
 142 }
 143
 144 /* Send Header + Packet */
 145 #define TX_DESC_PER_PKT 2
 146
 147 static inline uint32_t __hot
 148 nicvf_free_xmitted_buffers(struct nicvf_txq *sq, struct rte_mbuf **tx_pkts,
 149                             uint16_t nb_pkts)
 150 {
 151         uint32_t free_desc = nicvf_free_tx_desc(sq);
 152
 153         if (free_desc < nb_pkts * TX_DESC_PER_PKT ||
 154                         sq->xmit_bufs > sq->tx_free_thresh) {
 155                 if (unlikely(sq->pool == NULL))
 156                         sq->pool = tx_pkts[0]->pool;
 157
 158                 sq->pool_free(sq);
 159                 /* Freed now, let see the number of free descs again */
 160                 free_desc = nicvf_free_tx_desc(sq);
 161         }
 162         return free_desc;
 163 }
 164
 165 uint16_t __hot
 166 nicvf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 167 {
 168         int i;
 169         uint32_t free_desc;
 170         uint32_t tail;
 171         struct nicvf_txq *sq = tx_queue;
 172         union sq_entry_t *desc_ptr = sq->desc;
 173         struct rte_mbuf **txbuffs = sq->txbuffs;
 174         struct rte_mbuf *pkt;
 175         uint32_t qlen_mask = sq->qlen_mask;
 176
 177         tail = sq->tail;
 178         free_desc = nicvf_free_xmitted_buffers(sq, tx_pkts, nb_pkts);
 179
 180         for (i = 0; i < nb_pkts && (int)free_desc >= TX_DESC_PER_PKT; i++) {
 181                 pkt = tx_pkts[i];
 182
 183                 txbuffs[tail] = NULL;
 184                 fill_sq_desc_header(desc_ptr + tail, pkt);
 185                 tail = (tail + 1) & qlen_mask;
 186
 187                 txbuffs[tail] = pkt;
 188                 fill_sq_desc_gather(desc_ptr + tail, pkt);
 189                 tail = (tail + 1) & qlen_mask;
 190                 free_desc -= TX_DESC_PER_PKT;
 191         }
 192
 193         if (likely(i)) {
 194                 sq->tail = tail;
 195                 sq->xmit_bufs += i;
 196                 rte_wmb();
 197
 198                 /* Inform HW to xmit the packets */
 199                 nicvf_addr_write(sq->sq_door, i * TX_DESC_PER_PKT);
 200         }
 201         return i;
 202 }
 203
 204 uint16_t __hot
 205 nicvf_xmit_pkts_multiseg(void *tx_queue, struct rte_mbuf **tx_pkts,
 206                          uint16_t nb_pkts)
 207 {
 208         int i, k;
 209         uint32_t used_desc, next_used_desc, used_bufs, free_desc, tail;
 210         struct nicvf_txq *sq = tx_queue;
 211         union sq_entry_t *desc_ptr = sq->desc;
 212         struct rte_mbuf **txbuffs = sq->txbuffs;
 213         struct rte_mbuf *pkt, *seg;
 214         uint32_t qlen_mask = sq->qlen_mask;
 215         uint16_t nb_segs;
 216
 217         tail = sq->tail;
 218         used_desc = 0;
 219         used_bufs = 0;
 220
 221         free_desc = nicvf_free_xmitted_buffers(sq, tx_pkts, nb_pkts);
 222
 223         for (i = 0; i < nb_pkts; i++) {
 224                 pkt = tx_pkts[i];
 225
 226                 nb_segs = pkt->nb_segs;
 227
 228                 next_used_desc = used_desc + nb_segs + 1;
 229                 if (next_used_desc > free_desc)
 230                         break;
 231                 used_desc = next_used_desc;
 232                 used_bufs += nb_segs;
 233
 234                 txbuffs[tail] = NULL;
 235                 fill_sq_desc_header(desc_ptr + tail, pkt);
 236                 tail = (tail + 1) & qlen_mask;
 237
 238                 txbuffs[tail] = pkt;
 239                 fill_sq_desc_gather(desc_ptr + tail, pkt);
 240                 tail = (tail + 1) & qlen_mask;
 241
 242                 seg = pkt->next;
 243                 for (k = 1; k < nb_segs; k++) {
 244                         txbuffs[tail] = seg;
 245                         fill_sq_desc_gather(desc_ptr + tail, seg);
 246                         tail = (tail + 1) & qlen_mask;
 247                         seg = seg->next;
 248                 }
 249         }
 250
 251         if (likely(used_desc)) {
 252                 sq->tail = tail;
 253                 sq->xmit_bufs += used_bufs;
 254                 rte_wmb();
 255
 256                 /* Inform HW to xmit the packets */
 257                 nicvf_addr_write(sq->sq_door, used_desc);
 258         }
 259         return i;
 260 }
 261
 262 static const uint32_t ptype_table[16][16] __rte_cache_aligned = {
 263         [L3_NONE][L4_NONE] = RTE_PTYPE_UNKNOWN,
 264         [L3_NONE][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
 265         [L3_NONE][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
 266         [L3_NONE][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
 267         [L3_NONE][L4_TCP] = RTE_PTYPE_L4_TCP,
 268         [L3_NONE][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
 269         [L3_NONE][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
 270         [L3_NONE][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
 271         [L3_NONE][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 272         [L3_NONE][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 273         [L3_NONE][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
 274
 275         [L3_IPV4][L4_NONE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_UNKNOWN,
 276         [L3_IPV4][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L3_IPV4,
 277         [L3_IPV4][L4_IPFRAG] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_FRAG,
 278         [L3_IPV4][L4_IPCOMP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_UNKNOWN,
 279         [L3_IPV4][L4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 280         [L3_IPV4][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 281         [L3_IPV4][L4_GRE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_GRE,
 282         [L3_IPV4][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 283         [L3_IPV4][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_GENEVE,
 284         [L3_IPV4][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_VXLAN,
 285         [L3_IPV4][L4_NVGRE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_NVGRE,
 286
 287         [L3_IPV4_OPT][L4_NONE] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_UNKNOWN,
 288         [L3_IPV4_OPT][L4_IPSEC_ESP] =  RTE_PTYPE_L3_IPV4_EXT |
 289                                 RTE_PTYPE_L3_IPV4,
 290         [L3_IPV4_OPT][L4_IPFRAG] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_FRAG,
 291         [L3_IPV4_OPT][L4_IPCOMP] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_UNKNOWN,
 292         [L3_IPV4_OPT][L4_TCP] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
 293         [L3_IPV4_OPT][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
 294         [L3_IPV4_OPT][L4_GRE] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_GRE,
 295         [L3_IPV4_OPT][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
 296         [L3_IPV4_OPT][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV4_EXT |
 297                                 RTE_PTYPE_TUNNEL_GENEVE,
 298         [L3_IPV4_OPT][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV4_EXT |
 299                                 RTE_PTYPE_TUNNEL_VXLAN,
 300         [L3_IPV4_OPT][L4_NVGRE] = RTE_PTYPE_L3_IPV4_EXT |
 301                                 RTE_PTYPE_TUNNEL_NVGRE,
 302
 303         [L3_IPV6][L4_NONE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_UNKNOWN,
 304         [L3_IPV6][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L3_IPV4,
 305         [L3_IPV6][L4_IPFRAG] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_FRAG,
 306         [L3_IPV6][L4_IPCOMP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_UNKNOWN,
 307         [L3_IPV6][L4_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 308         [L3_IPV6][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 309         [L3_IPV6][L4_GRE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_GRE,
 310         [L3_IPV6][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 311         [L3_IPV6][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_GENEVE,
 312         [L3_IPV6][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_VXLAN,
 313         [L3_IPV6][L4_NVGRE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_NVGRE,
 314
 315         [L3_IPV6_OPT][L4_NONE] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_UNKNOWN,
 316         [L3_IPV6_OPT][L4_IPSEC_ESP] =  RTE_PTYPE_L3_IPV6_EXT |
 317                                         RTE_PTYPE_L3_IPV4,
 318         [L3_IPV6_OPT][L4_IPFRAG] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_FRAG,
 319         [L3_IPV6_OPT][L4_IPCOMP] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_UNKNOWN,
 320         [L3_IPV6_OPT][L4_TCP] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
 321         [L3_IPV6_OPT][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
 322         [L3_IPV6_OPT][L4_GRE] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_TUNNEL_GRE,
 323         [L3_IPV6_OPT][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
 324         [L3_IPV6_OPT][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV6_EXT |
 325                                         RTE_PTYPE_TUNNEL_GENEVE,
 326         [L3_IPV6_OPT][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV6_EXT |
 327                                         RTE_PTYPE_TUNNEL_VXLAN,
 328         [L3_IPV6_OPT][L4_NVGRE] = RTE_PTYPE_L3_IPV6_EXT |
 329                                         RTE_PTYPE_TUNNEL_NVGRE,
 330
 331         [L3_ET_STOP][L4_NONE] = RTE_PTYPE_UNKNOWN,
 332         [L3_ET_STOP][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
 333         [L3_ET_STOP][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
 334         [L3_ET_STOP][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
 335         [L3_ET_STOP][L4_TCP] = RTE_PTYPE_L4_TCP,
 336         [L3_ET_STOP][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
 337         [L3_ET_STOP][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
 338         [L3_ET_STOP][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
 339         [L3_ET_STOP][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 340         [L3_ET_STOP][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 341         [L3_ET_STOP][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
 342
 343         [L3_OTHER][L4_NONE] = RTE_PTYPE_UNKNOWN,
 344         [L3_OTHER][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
 345         [L3_OTHER][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
 346         [L3_OTHER][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
 347         [L3_OTHER][L4_TCP] = RTE_PTYPE_L4_TCP,
 348         [L3_OTHER][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
 349         [L3_OTHER][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
 350         [L3_OTHER][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
 351         [L3_OTHER][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 352         [L3_OTHER][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 353         [L3_OTHER][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
 354 };
 355
 356 static inline uint32_t __hot
 357 nicvf_rx_classify_pkt(cqe_rx_word0_t cqe_rx_w0)
 358 {
 359         return ptype_table[cqe_rx_w0.l3_type][cqe_rx_w0.l4_type];
 360 }
 361
 362 static inline int __hot
 363 nicvf_fill_rbdr(struct nicvf_rxq *rxq, int to_fill)
 364 {
 365         int i;
 366         uint32_t ltail, next_tail;
 367         struct nicvf_rbdr *rbdr = rxq->shared_rbdr;
 368         uint64_t mbuf_phys_off = rxq->mbuf_phys_off;
 369         struct rbdr_entry_t *desc = rbdr->desc;
 370         uint32_t qlen_mask = rbdr->qlen_mask;
 371         uintptr_t door = rbdr->rbdr_door;
 372         void *obj_p[NICVF_MAX_RX_FREE_THRESH] __rte_cache_aligned;
 373
 374         if (unlikely(rte_mempool_get_bulk(rxq->pool, obj_p, to_fill) < 0)) {
 375                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
 376                         to_fill;
 377                 return 0;
 378         }
 379
 380         NICVF_RX_ASSERT((unsigned int)to_fill <= (qlen_mask -
 381                 (nicvf_addr_read(rbdr->rbdr_status) & NICVF_RBDR_COUNT_MASK)));
 382
 383         next_tail = __atomic_fetch_add(&rbdr->next_tail, to_fill,
 384                                         __ATOMIC_ACQUIRE);
 385         ltail = next_tail;
 386         for (i = 0; i < to_fill; i++) {
 387                 struct rbdr_entry_t *entry = desc + (ltail & qlen_mask);
 388
 389                 entry->full_addr = nicvf_mbuff_virt2phy((uintptr_t)obj_p[i],
 390                                                         mbuf_phys_off);
 391                 ltail++;
 392         }
 393
 394         while (__atomic_load_n(&rbdr->tail, __ATOMIC_RELAXED) != next_tail)
 395                 rte_pause();
 396
 397         __atomic_store_n(&rbdr->tail, ltail, __ATOMIC_RELEASE);
 398         nicvf_addr_write(door, to_fill);
 399         return to_fill;
 400 }
 401
 402 static inline int32_t __hot
 403 nicvf_rx_pkts_to_process(struct nicvf_rxq *rxq, uint16_t nb_pkts,
 404                          int32_t available_space)
 405 {
 406         if (unlikely(available_space < nb_pkts))
 407                 rxq->available_space = nicvf_addr_read(rxq->cq_status)
 408                                                 & NICVF_CQ_CQE_COUNT_MASK;
 409
 410         return RTE_MIN(nb_pkts, available_space);
 411 }
 412
 413 static inline void __hot
 414 nicvf_rx_offload(cqe_rx_word0_t cqe_rx_w0, cqe_rx_word2_t cqe_rx_w2,
 415                  struct rte_mbuf *pkt)
 416 {
 417         if (likely(cqe_rx_w0.rss_alg)) {
 418                 pkt->hash.rss = cqe_rx_w2.rss_tag;
 419                 pkt->ol_flags |= PKT_RX_RSS_HASH;
 420         }
 421 }
 422
 423 uint16_t __hot
 424 nicvf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 425 {
 426         uint32_t i, to_process;
 427         struct cqe_rx_t *cqe_rx;
 428         struct rte_mbuf *pkt;
 429         cqe_rx_word0_t cqe_rx_w0;
 430         cqe_rx_word1_t cqe_rx_w1;
 431         cqe_rx_word2_t cqe_rx_w2;
 432         cqe_rx_word3_t cqe_rx_w3;
 433         struct nicvf_rxq *rxq = rx_queue;
 434         union cq_entry_t *desc = rxq->desc;
 435         const uint64_t cqe_mask = rxq->qlen_mask;
 436         uint64_t rb0_ptr, mbuf_phys_off = rxq->mbuf_phys_off;
 437         const uint64_t mbuf_init = rxq->mbuf_initializer.value;
 438         uint32_t cqe_head = rxq->head & cqe_mask;
 439         int32_t available_space = rxq->available_space;
 440         const uint8_t rbptr_offset = rxq->rbptr_offset;
 441
 442         to_process = nicvf_rx_pkts_to_process(rxq, nb_pkts, available_space);
 443
 444         for (i = 0; i < to_process; i++) {
 445                 rte_prefetch_non_temporal(&desc[cqe_head + 2]);
 446                 cqe_rx = (struct cqe_rx_t *)&desc[cqe_head];
 447                 NICVF_RX_ASSERT(((struct cq_entry_type_t *)cqe_rx)->cqe_type
 448                                                  == CQE_TYPE_RX);
 449
 450                 NICVF_LOAD_PAIR(cqe_rx_w0.u64, cqe_rx_w1.u64, cqe_rx);
 451                 NICVF_LOAD_PAIR(cqe_rx_w2.u64, cqe_rx_w3.u64, &cqe_rx->word2);
 452                 rb0_ptr = *((uint64_t *)cqe_rx + rbptr_offset);
 453                 pkt = (struct rte_mbuf *)nicvf_mbuff_phy2virt
 454                                 (rb0_ptr - cqe_rx_w1.align_pad, mbuf_phys_off);
 455                 pkt->ol_flags = 0;
 456                 pkt->data_len = cqe_rx_w3.rb0_sz;
 457                 pkt->pkt_len = cqe_rx_w3.rb0_sz;
 458                 pkt->packet_type = nicvf_rx_classify_pkt(cqe_rx_w0);
 459                 nicvf_mbuff_init_update(pkt, mbuf_init, cqe_rx_w1.align_pad);
 460                 nicvf_rx_offload(cqe_rx_w0, cqe_rx_w2, pkt);
 461                 rx_pkts[i] = pkt;
 462                 cqe_head = (cqe_head + 1) & cqe_mask;
 463                 nicvf_prefetch_store_keep(pkt);
 464         }
 465
 466         if (likely(to_process)) {
 467                 rxq->available_space -= to_process;
 468                 rxq->head = cqe_head;
 469                 nicvf_addr_write(rxq->cq_door, to_process);
 470                 rxq->recv_buffers += to_process;
 471         }
 472         if (rxq->recv_buffers > rxq->rx_free_thresh) {
 473                 rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rxq->rx_free_thresh);
 474                 NICVF_RX_ASSERT(rxq->recv_buffers >= 0);
 475         }
 476
 477         return to_process;
 478 }
 479
 480 static inline uint16_t __hot
 481 nicvf_process_cq_mseg_entry(struct cqe_rx_t *cqe_rx,
 482                         uint64_t mbuf_phys_off,
 483                         struct rte_mbuf **rx_pkt, uint8_t rbptr_offset,
 484                         uint64_t mbuf_init)
 485 {
 486         struct rte_mbuf *pkt, *seg, *prev;
 487         cqe_rx_word0_t cqe_rx_w0;
 488         cqe_rx_word1_t cqe_rx_w1;
 489         cqe_rx_word2_t cqe_rx_w2;
 490         uint16_t *rb_sz, nb_segs, seg_idx;
 491         uint64_t *rb_ptr;
 492
 493         NICVF_LOAD_PAIR(cqe_rx_w0.u64, cqe_rx_w1.u64, cqe_rx);
 494         NICVF_RX_ASSERT(cqe_rx_w0.cqe_type == CQE_TYPE_RX);
 495         cqe_rx_w2 = cqe_rx->word2;
 496         rb_sz = &cqe_rx->word3.rb0_sz;
 497         rb_ptr = (uint64_t *)cqe_rx + rbptr_offset;
 498         nb_segs = cqe_rx_w0.rb_cnt;
 499         pkt = (struct rte_mbuf *)nicvf_mbuff_phy2virt
 500                         (rb_ptr[0] - cqe_rx_w1.align_pad, mbuf_phys_off);
 501
 502         pkt->ol_flags = 0;
 503         pkt->pkt_len = cqe_rx_w1.pkt_len;
 504         pkt->data_len = rb_sz[nicvf_frag_num(0)];
 505         nicvf_mbuff_init_mseg_update(
 506                                 pkt, mbuf_init, cqe_rx_w1.align_pad, nb_segs);
 507         pkt->packet_type = nicvf_rx_classify_pkt(cqe_rx_w0);
 508         nicvf_rx_offload(cqe_rx_w0, cqe_rx_w2, pkt);
 509
 510         *rx_pkt = pkt;
 511         prev = pkt;
 512         for (seg_idx = 1; seg_idx < nb_segs; seg_idx++) {
 513                 seg = (struct rte_mbuf *)nicvf_mbuff_phy2virt
 514                         (rb_ptr[seg_idx], mbuf_phys_off);
 515
 516                 prev->next = seg;
 517                 seg->data_len = rb_sz[nicvf_frag_num(seg_idx)];
 518                 nicvf_mbuff_init_update(seg, mbuf_init, 0);
 519
 520                 prev = seg;
 521         }
 522         prev->next = NULL;
 523         return nb_segs;
 524 }
 525
 526 uint16_t __hot
 527 nicvf_recv_pkts_multiseg(void *rx_queue, struct rte_mbuf **rx_pkts,
 528                          uint16_t nb_pkts)
 529 {
 530         union cq_entry_t *cq_entry;
 531         struct cqe_rx_t *cqe_rx;
 532         struct nicvf_rxq *rxq = rx_queue;
 533         union cq_entry_t *desc = rxq->desc;
 534         const uint64_t cqe_mask = rxq->qlen_mask;
 535         uint64_t mbuf_phys_off = rxq->mbuf_phys_off;
 536         uint32_t i, to_process, cqe_head, buffers_consumed = 0;
 537         int32_t available_space = rxq->available_space;
 538         uint16_t nb_segs;
 539         const uint64_t mbuf_init = rxq->mbuf_initializer.value;
 540         const uint8_t rbptr_offset = rxq->rbptr_offset;
 541
 542         cqe_head = rxq->head & cqe_mask;
 543         to_process = nicvf_rx_pkts_to_process(rxq, nb_pkts, available_space);
 544
 545         for (i = 0; i < to_process; i++) {
 546                 rte_prefetch_non_temporal(&desc[cqe_head + 2]);
 547                 cq_entry = &desc[cqe_head];
 548                 cqe_rx = (struct cqe_rx_t *)cq_entry;
 549                 nb_segs = nicvf_process_cq_mseg_entry(cqe_rx, mbuf_phys_off,
 550                         rx_pkts + i, rbptr_offset, mbuf_init);
 551                 buffers_consumed += nb_segs;
 552                 cqe_head = (cqe_head + 1) & cqe_mask;
 553                 nicvf_prefetch_store_keep(rx_pkts[i]);
 554         }
 555
 556         if (likely(to_process)) {
 557                 rxq->available_space -= to_process;
 558                 rxq->head = cqe_head;
 559                 nicvf_addr_write(rxq->cq_door, to_process);
 560                 rxq->recv_buffers += buffers_consumed;
 561         }
 562         if (rxq->recv_buffers > rxq->rx_free_thresh) {
 563                 rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rxq->rx_free_thresh);
 564                 NICVF_RX_ASSERT(rxq->recv_buffers >= 0);
 565         }
 566
 567         return to_process;
 568 }
 569
 570 uint32_t
 571 nicvf_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
 572 {
 573         struct nicvf_rxq *rxq;
 574
 575         rxq = dev->data->rx_queues[queue_idx];
 576         return nicvf_addr_read(rxq->cq_status) & NICVF_CQ_CQE_COUNT_MASK;
 577 }
 578
 579 uint32_t
 580 nicvf_dev_rbdr_refill(struct rte_eth_dev *dev, uint16_t queue_idx)
 581 {
 582         struct nicvf_rxq *rxq;
 583         uint32_t to_process;
 584         uint32_t rx_free;
 585
 586         rxq = dev->data->rx_queues[queue_idx];
 587         to_process = rxq->recv_buffers;
 588         while (rxq->recv_buffers > 0) {
 589                 rx_free = RTE_MIN(rxq->recv_buffers, NICVF_MAX_RX_FREE_THRESH);
 590                 rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rx_free);
 591         }
 592
 593         assert(rxq->recv_buffers == 0);
 594         return to_process;
 595 }