drivers/net/thunderx/nicvf_rxtx.c

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium networks Ltd. 2016.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium networks nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <unistd.h>
  34 #include <stdint.h>
  35 #include <stdio.h>
  36 #include <stdlib.h>
  37
  38 #include <rte_atomic.h>
  39 #include <rte_branch_prediction.h>
  40 #include <rte_byteorder.h>
  41 #include <rte_common.h>
  42 #include <rte_cycles.h>
  43 #include <rte_errno.h>
  44 #include <rte_ethdev.h>
  45 #include <rte_ether.h>
  46 #include <rte_log.h>
  47 #include <rte_mbuf.h>
  48 #include <rte_prefetch.h>
  49
  50 #include "base/nicvf_plat.h"
  51
  52 #include "nicvf_ethdev.h"
  53 #include "nicvf_rxtx.h"
  54 #include "nicvf_logs.h"
  55
  56 static inline void __hot
  57 fill_sq_desc_header(union sq_entry_t *entry, struct rte_mbuf *pkt)
  58 {
  59         /* Local variable sqe to avoid read from sq desc memory*/
  60         union sq_entry_t sqe;
  61         uint64_t ol_flags;
  62
  63         /* Fill SQ header descriptor */
  64         sqe.buff[0] = 0;
  65         sqe.hdr.subdesc_type = SQ_DESC_TYPE_HEADER;
  66         /* Number of sub-descriptors following this one */
  67         sqe.hdr.subdesc_cnt = pkt->nb_segs;
  68         sqe.hdr.tot_len = pkt->pkt_len;
  69
  70         ol_flags = pkt->ol_flags & NICVF_TX_OFFLOAD_MASK;
  71         if (unlikely(ol_flags)) {
  72                 /* L4 cksum */
  73                 if (ol_flags & PKT_TX_TCP_CKSUM)
  74                         sqe.hdr.csum_l4 = SEND_L4_CSUM_TCP;
  75                 else if (ol_flags & PKT_TX_UDP_CKSUM)
  76                         sqe.hdr.csum_l4 = SEND_L4_CSUM_UDP;
  77                 else
  78                         sqe.hdr.csum_l4 = SEND_L4_CSUM_DISABLE;
  79                 sqe.hdr.l4_offset = pkt->l3_len + pkt->l2_len;
  80
  81                 /* L3 cksum */
  82                 if (ol_flags & PKT_TX_IP_CKSUM) {
  83                         sqe.hdr.csum_l3 = 1;
  84                         sqe.hdr.l3_offset = pkt->l2_len;
  85                 }
  86         }
  87
  88         entry->buff[0] = sqe.buff[0];
  89 }
  90
  91 void __hot
  92 nicvf_single_pool_free_xmited_buffers(struct nicvf_txq *sq)
  93 {
  94         int j = 0;
  95         uint32_t curr_head;
  96         uint32_t head = sq->head;
  97         struct rte_mbuf **txbuffs = sq->txbuffs;
  98         void *obj_p[NICVF_MAX_TX_FREE_THRESH] __rte_cache_aligned;
  99
 100         curr_head = nicvf_addr_read(sq->sq_head) >> 4;
 101         while (head != curr_head) {
 102                 if (txbuffs[head])
 103                         obj_p[j++] = txbuffs[head];
 104
 105                 head = (head + 1) & sq->qlen_mask;
 106         }
 107
 108         rte_mempool_put_bulk(sq->pool, obj_p, j);
 109         sq->head = curr_head;
 110         sq->xmit_bufs -= j;
 111         NICVF_TX_ASSERT(sq->xmit_bufs >= 0);
 112 }
 113
 114 void __hot
 115 nicvf_multi_pool_free_xmited_buffers(struct nicvf_txq *sq)
 116 {
 117         uint32_t n = 0;
 118         uint32_t curr_head;
 119         uint32_t head = sq->head;
 120         struct rte_mbuf **txbuffs = sq->txbuffs;
 121
 122         curr_head = nicvf_addr_read(sq->sq_head) >> 4;
 123         while (head != curr_head) {
 124                 if (txbuffs[head]) {
 125                         rte_pktmbuf_free_seg(txbuffs[head]);
 126                         n++;
 127                 }
 128
 129                 head = (head + 1) & sq->qlen_mask;
 130         }
 131
 132         sq->head = curr_head;
 133         sq->xmit_bufs -= n;
 134         NICVF_TX_ASSERT(sq->xmit_bufs >= 0);
 135 }
 136
 137 static inline uint32_t __hot
 138 nicvf_free_tx_desc(struct nicvf_txq *sq)
 139 {
 140         return ((sq->head - sq->tail - 1) & sq->qlen_mask);
 141 }
 142
 143 /* Send Header + Packet */
 144 #define TX_DESC_PER_PKT 2
 145
 146 static inline uint32_t __hot
 147 nicvf_free_xmitted_buffers(struct nicvf_txq *sq, struct rte_mbuf **tx_pkts,
 148                             uint16_t nb_pkts)
 149 {
 150         uint32_t free_desc = nicvf_free_tx_desc(sq);
 151
 152         if (free_desc < nb_pkts * TX_DESC_PER_PKT ||
 153                         sq->xmit_bufs > sq->tx_free_thresh) {
 154                 if (unlikely(sq->pool == NULL))
 155                         sq->pool = tx_pkts[0]->pool;
 156
 157                 sq->pool_free(sq);
 158                 /* Freed now, let see the number of free descs again */
 159                 free_desc = nicvf_free_tx_desc(sq);
 160         }
 161         return free_desc;
 162 }
 163
 164 uint16_t __hot
 165 nicvf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 166 {
 167         int i;
 168         uint32_t free_desc;
 169         uint32_t tail;
 170         struct nicvf_txq *sq = tx_queue;
 171         union sq_entry_t *desc_ptr = sq->desc;
 172         struct rte_mbuf **txbuffs = sq->txbuffs;
 173         struct rte_mbuf *pkt;
 174         uint32_t qlen_mask = sq->qlen_mask;
 175
 176         tail = sq->tail;
 177         free_desc = nicvf_free_xmitted_buffers(sq, tx_pkts, nb_pkts);
 178
 179         for (i = 0; i < nb_pkts && (int)free_desc >= TX_DESC_PER_PKT; i++) {
 180                 pkt = tx_pkts[i];
 181
 182                 txbuffs[tail] = NULL;
 183                 fill_sq_desc_header(desc_ptr + tail, pkt);
 184                 tail = (tail + 1) & qlen_mask;
 185
 186                 txbuffs[tail] = pkt;
 187                 fill_sq_desc_gather(desc_ptr + tail, pkt);
 188                 tail = (tail + 1) & qlen_mask;
 189                 free_desc -= TX_DESC_PER_PKT;
 190         }
 191
 192         sq->tail = tail;
 193         sq->xmit_bufs += i;
 194         rte_wmb();
 195
 196         /* Inform HW to xmit the packets */
 197         nicvf_addr_write(sq->sq_door, i * TX_DESC_PER_PKT);
 198         return i;
 199 }
 200
 201 uint16_t __hot
 202 nicvf_xmit_pkts_multiseg(void *tx_queue, struct rte_mbuf **tx_pkts,
 203                          uint16_t nb_pkts)
 204 {
 205         int i, k;
 206         uint32_t used_desc, next_used_desc, used_bufs, free_desc, tail;
 207         struct nicvf_txq *sq = tx_queue;
 208         union sq_entry_t *desc_ptr = sq->desc;
 209         struct rte_mbuf **txbuffs = sq->txbuffs;
 210         struct rte_mbuf *pkt, *seg;
 211         uint32_t qlen_mask = sq->qlen_mask;
 212         uint16_t nb_segs;
 213
 214         tail = sq->tail;
 215         used_desc = 0;
 216         used_bufs = 0;
 217
 218         free_desc = nicvf_free_xmitted_buffers(sq, tx_pkts, nb_pkts);
 219
 220         for (i = 0; i < nb_pkts; i++) {
 221                 pkt = tx_pkts[i];
 222
 223                 nb_segs = pkt->nb_segs;
 224
 225                 next_used_desc = used_desc + nb_segs + 1;
 226                 if (next_used_desc > free_desc)
 227                         break;
 228                 used_desc = next_used_desc;
 229                 used_bufs += nb_segs;
 230
 231                 txbuffs[tail] = NULL;
 232                 fill_sq_desc_header(desc_ptr + tail, pkt);
 233                 tail = (tail + 1) & qlen_mask;
 234
 235                 txbuffs[tail] = pkt;
 236                 fill_sq_desc_gather(desc_ptr + tail, pkt);
 237                 tail = (tail + 1) & qlen_mask;
 238
 239                 seg = pkt->next;
 240                 for (k = 1; k < nb_segs; k++) {
 241                         txbuffs[tail] = seg;
 242                         fill_sq_desc_gather(desc_ptr + tail, seg);
 243                         tail = (tail + 1) & qlen_mask;
 244                         seg = seg->next;
 245                 }
 246         }
 247
 248         sq->tail = tail;
 249         sq->xmit_bufs += used_bufs;
 250         rte_wmb();
 251
 252         /* Inform HW to xmit the packets */
 253         nicvf_addr_write(sq->sq_door, used_desc);
 254         return nb_pkts;
 255 }
 256
 257 static const uint32_t ptype_table[16][16] __rte_cache_aligned = {
 258         [L3_NONE][L4_NONE] = RTE_PTYPE_UNKNOWN,
 259         [L3_NONE][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
 260         [L3_NONE][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
 261         [L3_NONE][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
 262         [L3_NONE][L4_TCP] = RTE_PTYPE_L4_TCP,
 263         [L3_NONE][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
 264         [L3_NONE][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
 265         [L3_NONE][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
 266         [L3_NONE][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 267         [L3_NONE][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 268         [L3_NONE][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
 269
 270         [L3_IPV4][L4_NONE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_UNKNOWN,
 271         [L3_IPV4][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L3_IPV4,
 272         [L3_IPV4][L4_IPFRAG] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_FRAG,
 273         [L3_IPV4][L4_IPCOMP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_UNKNOWN,
 274         [L3_IPV4][L4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 275         [L3_IPV4][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 276         [L3_IPV4][L4_GRE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_GRE,
 277         [L3_IPV4][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 278         [L3_IPV4][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_GENEVE,
 279         [L3_IPV4][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_VXLAN,
 280         [L3_IPV4][L4_NVGRE] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_NVGRE,
 281
 282         [L3_IPV4_OPT][L4_NONE] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_UNKNOWN,
 283         [L3_IPV4_OPT][L4_IPSEC_ESP] =  RTE_PTYPE_L3_IPV4_EXT |
 284                                 RTE_PTYPE_L3_IPV4,
 285         [L3_IPV4_OPT][L4_IPFRAG] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_FRAG,
 286         [L3_IPV4_OPT][L4_IPCOMP] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_UNKNOWN,
 287         [L3_IPV4_OPT][L4_TCP] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_TCP,
 288         [L3_IPV4_OPT][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
 289         [L3_IPV4_OPT][L4_GRE] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_TUNNEL_GRE,
 290         [L3_IPV4_OPT][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_UDP,
 291         [L3_IPV4_OPT][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV4_EXT |
 292                                 RTE_PTYPE_TUNNEL_GENEVE,
 293         [L3_IPV4_OPT][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV4_EXT |
 294                                 RTE_PTYPE_TUNNEL_VXLAN,
 295         [L3_IPV4_OPT][L4_NVGRE] = RTE_PTYPE_L3_IPV4_EXT |
 296                                 RTE_PTYPE_TUNNEL_NVGRE,
 297
 298         [L3_IPV6][L4_NONE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_UNKNOWN,
 299         [L3_IPV6][L4_IPSEC_ESP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L3_IPV4,
 300         [L3_IPV6][L4_IPFRAG] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_FRAG,
 301         [L3_IPV6][L4_IPCOMP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_UNKNOWN,
 302         [L3_IPV6][L4_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 303         [L3_IPV6][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 304         [L3_IPV6][L4_GRE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_GRE,
 305         [L3_IPV6][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 306         [L3_IPV6][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_GENEVE,
 307         [L3_IPV6][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_VXLAN,
 308         [L3_IPV6][L4_NVGRE] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_TUNNEL_NVGRE,
 309
 310         [L3_IPV6_OPT][L4_NONE] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_UNKNOWN,
 311         [L3_IPV6_OPT][L4_IPSEC_ESP] =  RTE_PTYPE_L3_IPV6_EXT |
 312                                         RTE_PTYPE_L3_IPV4,
 313         [L3_IPV6_OPT][L4_IPFRAG] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_FRAG,
 314         [L3_IPV6_OPT][L4_IPCOMP] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_UNKNOWN,
 315         [L3_IPV6_OPT][L4_TCP] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
 316         [L3_IPV6_OPT][L4_UDP_PASS1] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
 317         [L3_IPV6_OPT][L4_GRE] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_TUNNEL_GRE,
 318         [L3_IPV6_OPT][L4_UDP_PASS2] = RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
 319         [L3_IPV6_OPT][L4_UDP_GENEVE] = RTE_PTYPE_L3_IPV6_EXT |
 320                                         RTE_PTYPE_TUNNEL_GENEVE,
 321         [L3_IPV6_OPT][L4_UDP_VXLAN] = RTE_PTYPE_L3_IPV6_EXT |
 322                                         RTE_PTYPE_TUNNEL_VXLAN,
 323         [L3_IPV6_OPT][L4_NVGRE] = RTE_PTYPE_L3_IPV6_EXT |
 324                                         RTE_PTYPE_TUNNEL_NVGRE,
 325
 326         [L3_ET_STOP][L4_NONE] = RTE_PTYPE_UNKNOWN,
 327         [L3_ET_STOP][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
 328         [L3_ET_STOP][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
 329         [L3_ET_STOP][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
 330         [L3_ET_STOP][L4_TCP] = RTE_PTYPE_L4_TCP,
 331         [L3_ET_STOP][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
 332         [L3_ET_STOP][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
 333         [L3_ET_STOP][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
 334         [L3_ET_STOP][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 335         [L3_ET_STOP][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 336         [L3_ET_STOP][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
 337
 338         [L3_OTHER][L4_NONE] = RTE_PTYPE_UNKNOWN,
 339         [L3_OTHER][L4_IPSEC_ESP] = RTE_PTYPE_UNKNOWN,
 340         [L3_OTHER][L4_IPFRAG] = RTE_PTYPE_L4_FRAG,
 341         [L3_OTHER][L4_IPCOMP] = RTE_PTYPE_UNKNOWN,
 342         [L3_OTHER][L4_TCP] = RTE_PTYPE_L4_TCP,
 343         [L3_OTHER][L4_UDP_PASS1] = RTE_PTYPE_L4_UDP,
 344         [L3_OTHER][L4_GRE] = RTE_PTYPE_TUNNEL_GRE,
 345         [L3_OTHER][L4_UDP_PASS2] = RTE_PTYPE_L4_UDP,
 346         [L3_OTHER][L4_UDP_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 347         [L3_OTHER][L4_UDP_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 348         [L3_OTHER][L4_NVGRE] = RTE_PTYPE_TUNNEL_NVGRE,
 349 };
 350
 351 static inline uint32_t __hot
 352 nicvf_rx_classify_pkt(cqe_rx_word0_t cqe_rx_w0)
 353 {
 354         return ptype_table[cqe_rx_w0.l3_type][cqe_rx_w0.l4_type];
 355 }
 356
 357 static inline int __hot
 358 nicvf_fill_rbdr(struct nicvf_rxq *rxq, int to_fill)
 359 {
 360         int i;
 361         uint32_t ltail, next_tail;
 362         struct nicvf_rbdr *rbdr = rxq->shared_rbdr;
 363         uint64_t mbuf_phys_off = rxq->mbuf_phys_off;
 364         struct rbdr_entry_t *desc = rbdr->desc;
 365         uint32_t qlen_mask = rbdr->qlen_mask;
 366         uintptr_t door = rbdr->rbdr_door;
 367         void *obj_p[NICVF_MAX_RX_FREE_THRESH] __rte_cache_aligned;
 368
 369         if (unlikely(rte_mempool_get_bulk(rxq->pool, obj_p, to_fill) < 0)) {
 370                 rxq->nic->eth_dev->data->rx_mbuf_alloc_failed += to_fill;
 371                 return 0;
 372         }
 373
 374         NICVF_RX_ASSERT((unsigned int)to_fill <= (qlen_mask -
 375                 (nicvf_addr_read(rbdr->rbdr_status) & NICVF_RBDR_COUNT_MASK)));
 376
 377         next_tail = __atomic_fetch_add(&rbdr->next_tail, to_fill,
 378                                         __ATOMIC_ACQUIRE);
 379         ltail = next_tail;
 380         for (i = 0; i < to_fill; i++) {
 381                 struct rbdr_entry_t *entry = desc + (ltail & qlen_mask);
 382
 383                 entry->full_addr = nicvf_mbuff_virt2phy((uintptr_t)obj_p[i],
 384                                                         mbuf_phys_off);
 385                 ltail++;
 386         }
 387
 388         while (__atomic_load_n(&rbdr->tail, __ATOMIC_RELAXED) != next_tail)
 389                 rte_pause();
 390
 391         __atomic_store_n(&rbdr->tail, ltail, __ATOMIC_RELEASE);
 392         nicvf_addr_write(door, to_fill);
 393         return to_fill;
 394 }
 395
 396 static inline int32_t __hot
 397 nicvf_rx_pkts_to_process(struct nicvf_rxq *rxq, uint16_t nb_pkts,
 398                          int32_t available_space)
 399 {
 400         if (unlikely(available_space < nb_pkts))
 401                 rxq->available_space = nicvf_addr_read(rxq->cq_status)
 402                                                 & NICVF_CQ_CQE_COUNT_MASK;
 403
 404         return RTE_MIN(nb_pkts, available_space);
 405 }
 406
 407 static inline void __hot
 408 nicvf_rx_offload(cqe_rx_word0_t cqe_rx_w0, cqe_rx_word2_t cqe_rx_w2,
 409                  struct rte_mbuf *pkt)
 410 {
 411         if (likely(cqe_rx_w0.rss_alg)) {
 412                 pkt->hash.rss = cqe_rx_w2.rss_tag;
 413                 pkt->ol_flags |= PKT_RX_RSS_HASH;
 414         }
 415 }
 416
 417 uint16_t __hot
 418 nicvf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 419 {
 420         uint32_t i, to_process;
 421         struct cqe_rx_t *cqe_rx;
 422         struct rte_mbuf *pkt;
 423         cqe_rx_word0_t cqe_rx_w0;
 424         cqe_rx_word1_t cqe_rx_w1;
 425         cqe_rx_word2_t cqe_rx_w2;
 426         cqe_rx_word3_t cqe_rx_w3;
 427         struct nicvf_rxq *rxq = rx_queue;
 428         union cq_entry_t *desc = rxq->desc;
 429         const uint64_t cqe_mask = rxq->qlen_mask;
 430         uint64_t rb0_ptr, mbuf_phys_off = rxq->mbuf_phys_off;
 431         uint32_t cqe_head = rxq->head & cqe_mask;
 432         int32_t available_space = rxq->available_space;
 433         uint8_t port_id = rxq->port_id;
 434         const uint8_t rbptr_offset = rxq->rbptr_offset;
 435
 436         to_process = nicvf_rx_pkts_to_process(rxq, nb_pkts, available_space);
 437
 438         for (i = 0; i < to_process; i++) {
 439                 rte_prefetch_non_temporal(&desc[cqe_head + 2]);
 440                 cqe_rx = (struct cqe_rx_t *)&desc[cqe_head];
 441                 NICVF_RX_ASSERT(((struct cq_entry_type_t *)cqe_rx)->cqe_type
 442                                                  == CQE_TYPE_RX);
 443
 444                 NICVF_LOAD_PAIR(cqe_rx_w0.u64, cqe_rx_w1.u64, cqe_rx);
 445                 NICVF_LOAD_PAIR(cqe_rx_w2.u64, cqe_rx_w3.u64, &cqe_rx->word2);
 446                 rb0_ptr = *((uint64_t *)cqe_rx + rbptr_offset);
 447                 pkt = (struct rte_mbuf *)nicvf_mbuff_phy2virt
 448                                 (rb0_ptr - cqe_rx_w1.align_pad, mbuf_phys_off);
 449
 450                 pkt->ol_flags = 0;
 451                 pkt->port = port_id;
 452                 pkt->data_len = cqe_rx_w3.rb0_sz;
 453                 pkt->data_off = RTE_PKTMBUF_HEADROOM + cqe_rx_w1.align_pad;
 454                 pkt->nb_segs = 1;
 455                 pkt->pkt_len = cqe_rx_w3.rb0_sz;
 456                 pkt->packet_type = nicvf_rx_classify_pkt(cqe_rx_w0);
 457
 458                 nicvf_rx_offload(cqe_rx_w0, cqe_rx_w2, pkt);
 459                 rte_mbuf_refcnt_set(pkt, 1);
 460                 rx_pkts[i] = pkt;
 461                 cqe_head = (cqe_head + 1) & cqe_mask;
 462                 nicvf_prefetch_store_keep(pkt);
 463         }
 464
 465         if (likely(to_process)) {
 466                 rxq->available_space -= to_process;
 467                 rxq->head = cqe_head;
 468                 nicvf_addr_write(rxq->cq_door, to_process);
 469                 rxq->recv_buffers += to_process;
 470                 if (rxq->recv_buffers > rxq->rx_free_thresh) {
 471                         rxq->recv_buffers -= nicvf_fill_rbdr(rxq,
 472                                                 rxq->rx_free_thresh);
 473                         NICVF_RX_ASSERT(rxq->recv_buffers >= 0);
 474                 }
 475         }
 476
 477         return to_process;
 478 }
 479
 480 static inline uint16_t __hot
 481 nicvf_process_cq_mseg_entry(struct cqe_rx_t *cqe_rx,
 482                         uint64_t mbuf_phys_off, uint8_t port_id,
 483                         struct rte_mbuf **rx_pkt, uint8_t rbptr_offset)
 484 {
 485         struct rte_mbuf *pkt, *seg, *prev;
 486         cqe_rx_word0_t cqe_rx_w0;
 487         cqe_rx_word1_t cqe_rx_w1;
 488         cqe_rx_word2_t cqe_rx_w2;
 489         uint16_t *rb_sz, nb_segs, seg_idx;
 490         uint64_t *rb_ptr;
 491
 492         NICVF_LOAD_PAIR(cqe_rx_w0.u64, cqe_rx_w1.u64, cqe_rx);
 493         NICVF_RX_ASSERT(cqe_rx_w0.cqe_type == CQE_TYPE_RX);
 494         cqe_rx_w2 = cqe_rx->word2;
 495         rb_sz = &cqe_rx->word3.rb0_sz;
 496         rb_ptr = (uint64_t *)cqe_rx + rbptr_offset;
 497         nb_segs = cqe_rx_w0.rb_cnt;
 498         pkt = (struct rte_mbuf *)nicvf_mbuff_phy2virt
 499                         (rb_ptr[0] - cqe_rx_w1.align_pad, mbuf_phys_off);
 500
 501         pkt->ol_flags = 0;
 502         pkt->port = port_id;
 503         pkt->data_off = RTE_PKTMBUF_HEADROOM + cqe_rx_w1.align_pad;
 504         pkt->nb_segs = nb_segs;
 505         pkt->pkt_len = cqe_rx_w1.pkt_len;
 506         pkt->data_len = rb_sz[nicvf_frag_num(0)];
 507         rte_mbuf_refcnt_set(pkt, 1);
 508         pkt->packet_type = nicvf_rx_classify_pkt(cqe_rx_w0);
 509         nicvf_rx_offload(cqe_rx_w0, cqe_rx_w2, pkt);
 510
 511         *rx_pkt = pkt;
 512         prev = pkt;
 513         for (seg_idx = 1; seg_idx < nb_segs; seg_idx++) {
 514                 seg = (struct rte_mbuf *)nicvf_mbuff_phy2virt
 515                         (rb_ptr[seg_idx], mbuf_phys_off);
 516
 517                 prev->next = seg;
 518                 seg->data_len = rb_sz[nicvf_frag_num(seg_idx)];
 519                 seg->port = port_id;
 520                 seg->data_off = RTE_PKTMBUF_HEADROOM;
 521                 rte_mbuf_refcnt_set(seg, 1);
 522
 523                 prev = seg;
 524         }
 525         prev->next = NULL;
 526         return nb_segs;
 527 }
 528
 529 uint16_t __hot
 530 nicvf_recv_pkts_multiseg(void *rx_queue, struct rte_mbuf **rx_pkts,
 531                          uint16_t nb_pkts)
 532 {
 533         union cq_entry_t *cq_entry;
 534         struct cqe_rx_t *cqe_rx;
 535         struct nicvf_rxq *rxq = rx_queue;
 536         union cq_entry_t *desc = rxq->desc;
 537         const uint64_t cqe_mask = rxq->qlen_mask;
 538         uint64_t mbuf_phys_off = rxq->mbuf_phys_off;
 539         uint32_t i, to_process, cqe_head, buffers_consumed = 0;
 540         int32_t available_space = rxq->available_space;
 541         uint16_t nb_segs;
 542         const uint8_t port_id = rxq->port_id;
 543         const uint8_t rbptr_offset = rxq->rbptr_offset;
 544
 545         cqe_head = rxq->head & cqe_mask;
 546         to_process = nicvf_rx_pkts_to_process(rxq, nb_pkts, available_space);
 547
 548         for (i = 0; i < to_process; i++) {
 549                 rte_prefetch_non_temporal(&desc[cqe_head + 2]);
 550                 cq_entry = &desc[cqe_head];
 551                 cqe_rx = (struct cqe_rx_t *)cq_entry;
 552                 nb_segs = nicvf_process_cq_mseg_entry(cqe_rx, mbuf_phys_off,
 553                                 port_id, rx_pkts + i, rbptr_offset);
 554                 buffers_consumed += nb_segs;
 555                 cqe_head = (cqe_head + 1) & cqe_mask;
 556                 nicvf_prefetch_store_keep(rx_pkts[i]);
 557         }
 558
 559         if (likely(to_process)) {
 560                 rxq->available_space -= to_process;
 561                 rxq->head = cqe_head;
 562                 nicvf_addr_write(rxq->cq_door, to_process);
 563                 rxq->recv_buffers += buffers_consumed;
 564                 if (rxq->recv_buffers > rxq->rx_free_thresh) {
 565                         rxq->recv_buffers -=
 566                                 nicvf_fill_rbdr(rxq, rxq->rx_free_thresh);
 567                         NICVF_RX_ASSERT(rxq->recv_buffers >= 0);
 568                 }
 569         }
 570
 571         return to_process;
 572 }
 573
 574 uint32_t
 575 nicvf_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)
 576 {
 577         struct nicvf_rxq *rxq;
 578
 579         rxq = dev->data->rx_queues[queue_idx];
 580         return nicvf_addr_read(rxq->cq_status) & NICVF_CQ_CQE_COUNT_MASK;
 581 }
 582
 583 uint32_t
 584 nicvf_dev_rbdr_refill(struct rte_eth_dev *dev, uint16_t queue_idx)
 585 {
 586         struct nicvf_rxq *rxq;
 587         uint32_t to_process;
 588         uint32_t rx_free;
 589
 590         rxq = dev->data->rx_queues[queue_idx];
 591         to_process = rxq->recv_buffers;
 592         while (rxq->recv_buffers > 0) {
 593                 rx_free = RTE_MIN(rxq->recv_buffers, NICVF_MAX_RX_FREE_THRESH);
 594                 rxq->recv_buffers -= nicvf_fill_rbdr(rxq, rx_free);
 595         }
 596
 597         assert(rxq->recv_buffers == 0);
 598         return to_process;
 599 }