drivers/raw/ifpga_rawdev/base/ifpga_defines.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #ifndef _IFPGA_DEFINES_H_
   6 #define _IFPGA_DEFINES_H_
   7
   8 #include "ifpga_compat.h"
   9
  10 #define MAX_FPGA_PORT_NUM  4
  11
  12 #define FME_FEATURE_HEADER          "fme_hdr"
  13 #define FME_FEATURE_THERMAL_MGMT    "fme_thermal"
  14 #define FME_FEATURE_POWER_MGMT      "fme_power"
  15 #define FME_FEATURE_GLOBAL_IPERF    "fme_iperf"
  16 #define FME_FEATURE_GLOBAL_ERR      "fme_error"
  17 #define FME_FEATURE_PR_MGMT         "fme_pr"
  18 #define FME_FEATURE_HSSI_ETH        "fme_hssi"
  19 #define FME_FEATURE_GLOBAL_DPERF    "fme_dperf"
  20 #define FME_FEATURE_QSPI_FLASH      "fme_qspi_flash"
  21
  22 #define PORT_FEATURE_HEADER         "port_hdr"
  23 #define PORT_FEATURE_UAFU           "port_uafu"
  24 #define PORT_FEATURE_ERR            "port_err"
  25 #define PORT_FEATURE_UMSG           "port_umsg"
  26 #define PORT_FEATURE_PR             "port_pr"
  27 #define PORT_FEATURE_UINT           "port_uint"
  28 #define PORT_FEATURE_STP            "port_stp"
  29
  30 /*
  31  * do not check the revision id as id may be dynamic under
  32  * some cases, e.g, UAFU.
  33  */
  34 #define SKIP_REVISION_CHECK             0xff
  35
  36 #define FME_HEADER_REVISION             1
  37 #define FME_THERMAL_MGMT_REVISION       0
  38 #define FME_POWER_MGMT_REVISION         1
  39 #define FME_GLOBAL_IPERF_REVISION       1
  40 #define FME_GLOBAL_ERR_REVISION         1
  41 #define FME_PR_MGMT_REVISION            2
  42 #define FME_HSSI_ETH_REVISION           0
  43 #define FME_GLOBAL_DPERF_REVISION       0
  44 #define FME_QSPI_REVISION               0
  45
  46 #define PORT_HEADER_REVISION            0
  47 /* UAFU's header info depends on the downloaded GBS */
  48 #define PORT_UAFU_REVISION              SKIP_REVISION_CHECK
  49 #define PORT_ERR_REVISION               1
  50 #define PORT_UMSG_REVISION              0
  51 #define PORT_UINT_REVISION              0
  52 #define PORT_STP_REVISION               1
  53
  54 #define FEATURE_TYPE_AFU        0x1
  55 #define FEATURE_TYPE_BBB        0x2
  56 #define FEATURE_TYPE_PRIVATE    0x3
  57 #define FEATURE_TYPE_FIU        0x4
  58
  59 #define FEATURE_FIU_ID_FME      0x0
  60 #define FEATURE_FIU_ID_PORT     0x1
  61
  62 #define FEATURE_ID_HEADER       0x0
  63 #define FEATURE_ID_AFU          0xff
  64
  65 enum fpga_id_type {
  66         FME_ID,
  67         PORT_ID,
  68         FPGA_ID_MAX,
  69 };
  70
  71 enum fme_feature_id {
  72         FME_FEATURE_ID_HEADER = 0x0,
  73
  74         FME_FEATURE_ID_THERMAL_MGMT     = 0x1,
  75         FME_FEATURE_ID_POWER_MGMT = 0x2,
  76         FME_FEATURE_ID_GLOBAL_IPERF = 0x3,
  77         FME_FEATURE_ID_GLOBAL_ERR = 0x4,
  78         FME_FEATURE_ID_PR_MGMT = 0x5,
  79         FME_FEATURE_ID_HSSI_ETH = 0x6,
  80         FME_FEATURE_ID_GLOBAL_DPERF = 0x7,
  81         FME_FEATURE_ID_QSPI_FLASH = 0x8,
  82
  83         /* one for fme header. */
  84         FME_FEATURE_ID_MAX = 0x9,
  85 };
  86
  87 enum port_feature_id {
  88         PORT_FEATURE_ID_HEADER = 0x0,
  89         PORT_FEATURE_ID_ERROR = 0x1,
  90         PORT_FEATURE_ID_UMSG = 0x2,
  91         PORT_FEATURE_ID_UINT = 0x3,
  92         PORT_FEATURE_ID_STP = 0x4,
  93         PORT_FEATURE_ID_UAFU = 0x5,
  94         PORT_FEATURE_ID_MAX = 0x6,
  95 };
  96
  97 /*
  98  * All headers and structures must be byte-packed to match the spec.
  99  */
 100 #pragma pack(push, 1)
 101
 102 struct feature_header {
 103         union {
 104                 u64 csr;
 105                 struct {
 106                         u16 id:12;
 107                         u8  revision:4;
 108                         u32 next_header_offset:24;
 109                         u8  end_of_list:1;
 110                         u32 reserved:19;
 111                         u8  type:4;
 112                 };
 113         };
 114 };
 115
 116 struct feature_bbb_header {
 117         struct uuid guid;
 118 };
 119
 120 struct feature_afu_header {
 121         struct uuid guid;
 122         union {
 123                 u64 csr;
 124                 struct {
 125                         u64 next_afu:24;
 126                         u64 reserved:40;
 127                 };
 128         };
 129 };
 130
 131 struct feature_fiu_header {
 132         struct uuid guid;
 133         union {
 134                 u64 csr;
 135                 struct {
 136                         u64 next_afu:24;
 137                         u64 reserved:40;
 138                 };
 139         };
 140 };
 141
 142 struct feature_fme_capability {
 143         union {
 144                 u64 csr;
 145                 struct {
 146                         u8  fabric_verid;       /* Fabric version ID */
 147                         u8  socket_id:1;        /* Socket id */
 148                         u8  rsvd1:3;            /* Reserved */
 149                         /* pci0 link available yes /no */
 150                         u8  pci0_link_avile:1;
 151                         /* pci1 link available yes /no */
 152                         u8  pci1_link_avile:1;
 153                         /* Coherent (QPI/UPI) link available yes /no */
 154                         u8  qpi_link_avile:1;
 155                         u8  rsvd2:1;            /* Reserved */
 156                         /* IOMMU or VT-d supported  yes/no */
 157                         u8  iommu_support:1;
 158                         u8  num_ports:3;        /* Number of ports */
 159                         u8  sf_fab_ctl:1;       /* Internal validation bit */
 160                         u8  rsvd3:3;            /* Reserved */
 161                         /*
 162                          * Address width supported in bits
 163                          * BXT -0x26 , SKX -0x30
 164                          */
 165                         u8  address_width_bits:6;
 166                         u8  rsvd4:2;            /* Reserved */
 167                         /* Size of cache supported in kb */
 168                         u16 cache_size:12;
 169                         u8  cache_assoc:4;      /* Cache Associativity */
 170                         u16 rsvd5:15;           /* Reserved */
 171                         u8  lock_bit:1;         /* Lock bit */
 172                 };
 173         };
 174 };
 175
 176 #define FME_AFU_ACCESS_PF               0
 177 #define FME_AFU_ACCESS_VF               1
 178
 179 struct feature_fme_port {
 180         union {
 181                 u64 csr;
 182                 struct {
 183                         u32 port_offset:24;
 184                         u8  reserved1;
 185                         u8  port_bar:3;
 186                         u32 reserved2:20;
 187                         u8  afu_access_control:1;
 188                         u8  reserved3:4;
 189                         u8  port_implemented:1;
 190                         u8  reserved4:3;
 191                 };
 192         };
 193 };
 194
 195 struct feature_fme_fab_status {
 196         union {
 197                 u64 csr;
 198                 struct {
 199                         u8  upilink_status:4;   /* UPI Link Status */
 200                         u8  rsvd1:4;            /* Reserved */
 201                         u8  pci0link_status:1;  /* pci0 link status */
 202                         u8  rsvd2:3;            /* Reserved */
 203                         u8  pci1link_status:1;  /* pci1 link status */
 204                         u64 rsvd3:51;           /* Reserved */
 205                 };
 206         };
 207 };
 208
 209 struct feature_fme_genprotrange2_base {
 210         union {
 211                 u64 csr;
 212                 struct {
 213                         u16 rsvd1;           /* Reserved */
 214                         /* Base Address of memory range */
 215                         u8  protected_base_addrss:4;
 216                         u64 rsvd2:44;           /* Reserved */
 217                 };
 218         };
 219 };
 220
 221 struct feature_fme_genprotrange2_limit {
 222         union {
 223                 u64 csr;
 224                 struct {
 225                         u16 rsvd1;           /* Reserved */
 226                         /* Limit Address of memory range */
 227                         u8  protected_limit_addrss:4;
 228                         u16 rsvd2:11;           /* Reserved */
 229                         u8  enable:1;        /* Enable GENPROTRANGE check */
 230                         u32 rsvd3;           /* Reserved */
 231                 };
 232         };
 233 };
 234
 235 struct feature_fme_dxe_lock {
 236         union {
 237                 u64 csr;
 238                 struct {
 239                         /*
 240                          * Determines write access to the DXE region CSRs
 241                          * 1 - CSR region is locked;
 242                          * 0 - it is open for write access.
 243                          */
 244                         u8  dxe_early_lock:1;
 245                         /*
 246                          * Determines write access to the HSSI CSR
 247                          * 1 - CSR region is locked;
 248                          * 0 - it is open for write access.
 249                          */
 250                         u8  dxe_late_lock:1;
 251                         u64 rsvd:62;
 252                 };
 253         };
 254 };
 255
 256 #define HSSI_ID_NO_HASSI        0
 257 #define HSSI_ID_PCIE_RP         1
 258 #define HSSI_ID_ETHERNET        2
 259
 260 struct feature_fme_bitstream_id {
 261         union {
 262                 u64 csr;
 263                 struct {
 264                         u32 gitrepo_hash:32;    /* GIT repository hash */
 265                         /*
 266                          * HSSI configuration identifier:
 267                          * 0 - No HSSI
 268                          * 1 - PCIe-RP
 269                          * 2 - Ethernet
 270                          */
 271                         u8  hssi_id:4;
 272                         u16 rsvd1:12;           /* Reserved */
 273                         /* Bitstream version patch number */
 274                         u8  bs_verpatch:4;
 275                         /* Bitstream version minor number */
 276                         u8  bs_verminor:4;
 277                         /* Bitstream version major number */
 278                         u8  bs_vermajor:4;
 279                         /* Bitstream version debug number */
 280                         u8  bs_verdebug:4;
 281                 };
 282         };
 283 };
 284
 285 struct feature_fme_bitstream_md {
 286         union {
 287                 u64 csr;
 288                 struct {
 289                         /* Seed number userd for synthesis flow */
 290                         u8  synth_seed:4;
 291                         /* Synthesis date(day number - 2 digits) */
 292                         u8  synth_day:8;
 293                         /* Synthesis date(month number - 2 digits) */
 294                         u8  synth_month:8;
 295                         /* Synthesis date(year number - 2 digits) */
 296                         u8  synth_year:8;
 297                         u64 rsvd:36;            /* Reserved */
 298                 };
 299         };
 300 };
 301
 302 struct feature_fme_iommu_ctrl {
 303         union {
 304                 u64 csr;
 305                 struct {
 306                         /* Disables IOMMU prefetcher for C0 channel */
 307                         u8 prefetch_disableC0:1;
 308                         /* Disables IOMMU prefetcher for C1 channel */
 309                         u8 prefetch_disableC1:1;
 310                         /* Disables IOMMU partial cache line writes */
 311                         u8 prefetch_wrdisable:1;
 312                         u8 rsvd1:1;             /* Reserved */
 313                         /*
 314                          * Select counter and read value from register
 315                          * iommu_stat.dbg_counters
 316                          * 0 - Number of 4K page translation response
 317                          * 1 - Number of 2M page translation response
 318                          * 2 - Number of 1G page translation response
 319                          */
 320                         u8 counter_sel:2;
 321                         u32 rsvd2:26;           /* Reserved */
 322                         /* Connected to IOMMU SIP Capabilities */
 323                         u32 capecap_defeature;
 324                 };
 325         };
 326 };
 327
 328 struct feature_fme_iommu_stat {
 329         union {
 330                 u64 csr;
 331                 struct {
 332                         /* Translation Enable bit from IOMMU SIP */
 333                         u8 translation_enable:1;
 334                         /* Drain request in progress */
 335                         u8 drain_req_inprog:1;
 336                         /* Invalidation current state */
 337                         u8 inv_state:3;
 338                         /* C0 Response Buffer current state */
 339                         u8 respbuffer_stateC0:3;
 340                         /* C1 Response Buffer current state */
 341                         u8 respbuffer_stateC1:3;
 342                         /* Last request ID to IOMMU SIP */
 343                         u8 last_reqID:4;
 344                         /* Last IOMMU SIP response ID value */
 345                         u8 last_respID:4;
 346                         /* Last IOMMU SIP response status value */
 347                         u8 last_respstatus:3;
 348                         /* C0 Transaction Buffer is not empty */
 349                         u8 transbuf_notEmptyC0:1;
 350                         /* C1 Transaction Buffer is not empty */
 351                         u8 transbuf_notEmptyC1:1;
 352                         /* C0 Request FIFO is not empty */
 353                         u8 reqFIFO_notemptyC0:1;
 354                         /* C1 Request FIFO is not empty */
 355                         u8 reqFIFO_notemptyC1:1;
 356                         /* C0 Response FIFO is not empty */
 357                         u8 respFIFO_notemptyC0:1;
 358                         /* C1 Response FIFO is not empty */
 359                         u8 respFIFO_notemptyC1:1;
 360                         /* C0 Response FIFO overflow detected */
 361                         u8 respFIFO_overflowC0:1;
 362                         /* C1 Response FIFO overflow detected */
 363                         u8 respFIFO_overflowC1:1;
 364                         /* C0 Transaction Buffer overflow detected */
 365                         u8 tranbuf_overflowC0:1;
 366                         /* C1 Transaction Buffer overflow detected */
 367                         u8 tranbuf_overflowC1:1;
 368                         /* Request FIFO overflow detected */
 369                         u8 reqFIFO_overflow:1;
 370                         /* IOMMU memory read in progress */
 371                         u8 memrd_inprog:1;
 372                         /* IOMMU memory write in progress */
 373                         u8 memwr_inprog:1;
 374                         u8 rsvd1:1;     /* Reserved */
 375                         /* Value of counter selected by iommu_ctl.counter_sel */
 376                         u16 dbg_counters:16;
 377                         u16 rsvd2:12;   /* Reserved */
 378                 };
 379         };
 380 };
 381
 382 struct feature_fme_pcie0_ctrl {
 383         union {
 384                 u64 csr;
 385                 struct {
 386                         u64 vtd_bar_lock:1;     /* Lock VT-D BAR register */
 387                         u64 rsvd1:3;
 388                         u64 rciep:1;            /* Configure PCIE0 as RCiEP */
 389                         u64 rsvd2:59;
 390                 };
 391         };
 392 };
 393
 394 struct feature_fme_llpr_smrr_base {
 395         union {
 396                 u64 csr;
 397                 struct {
 398                         u64 rsvd1:12;
 399                         u64 base:20;    /* SMRR2 memory range base address */
 400                         u64 rsvd2:32;
 401                 };
 402         };
 403 };
 404
 405 struct feature_fme_llpr_smrr_mask {
 406         union {
 407                 u64 csr;
 408                 struct {
 409                         u64 rsvd1:11;
 410                         u64 valid:1;    /* LLPR_SMRR rule is valid or not */
 411                         /*
 412                          * SMRR memory range mask which determines the range
 413                          * of region being mapped
 414                          */
 415                         u64 phys_mask:20;
 416                         u64 rsvd2:32;
 417                 };
 418         };
 419 };
 420
 421 struct feature_fme_llpr_smrr2_base {
 422         union {
 423                 u64 csr;
 424                 struct {
 425                         u64 rsvd1:12;
 426                         u64 base:20;    /* SMRR2 memory range base address */
 427                         u64 rsvd2:32;
 428                 };
 429         };
 430 };
 431
 432 struct feature_fme_llpr_smrr2_mask {
 433         union {
 434                 u64 csr;
 435                 struct {
 436                         u64 rsvd1:11;
 437                         u64 valid:1;    /* LLPR_SMRR2 rule is valid or not */
 438                         /*
 439                          * SMRR2 memory range mask which determines the range
 440                          * of region being mapped
 441                          */
 442                         u64 phys_mask:20;
 443                         u64 rsvd2:32;
 444                 };
 445         };
 446 };
 447
 448 struct feature_fme_llpr_meseg_base {
 449         union {
 450                 u64 csr;
 451                 struct {
 452                         /* A[45:19] of base address memory range */
 453                         u64 me_base:27;
 454                         u64 rsvd:37;
 455                 };
 456         };
 457 };
 458
 459 struct feature_fme_llpr_meseg_limit {
 460         union {
 461                 u64 csr;
 462                 struct {
 463                         /* A[45:19] of limit address memory range */
 464                         u64 me_limit:27;
 465                         u64 rsvd1:4;
 466                         u64 enable:1;   /* Enable LLPR MESEG rule */
 467                         u64 rsvd2:32;
 468                 };
 469         };
 470 };
 471
 472 struct feature_fme_header {
 473         struct feature_header header;
 474         struct feature_afu_header afu_header;
 475         u64 reserved;
 476         u64 scratchpad;
 477         struct feature_fme_capability capability;
 478         struct feature_fme_port port[MAX_FPGA_PORT_NUM];
 479         struct feature_fme_fab_status fab_status;
 480         struct feature_fme_bitstream_id bitstream_id;
 481         struct feature_fme_bitstream_md bitstream_md;
 482         struct feature_fme_genprotrange2_base genprotrange2_base;
 483         struct feature_fme_genprotrange2_limit genprotrange2_limit;
 484         struct feature_fme_dxe_lock dxe_lock;
 485         struct feature_fme_iommu_ctrl iommu_ctrl;
 486         struct feature_fme_iommu_stat iommu_stat;
 487         struct feature_fme_pcie0_ctrl pcie0_control;
 488         struct feature_fme_llpr_smrr_base smrr_base;
 489         struct feature_fme_llpr_smrr_mask smrr_mask;
 490         struct feature_fme_llpr_smrr2_base smrr2_base;
 491         struct feature_fme_llpr_smrr2_mask smrr2_mask;
 492         struct feature_fme_llpr_meseg_base meseg_base;
 493         struct feature_fme_llpr_meseg_limit meseg_limit;
 494 };
 495
 496 struct feature_port_capability {
 497         union {
 498                 u64 csr;
 499                 struct {
 500                         u8 port_number:2;       /* Port Number 0-3 */
 501                         u8 rsvd1:6;             /* Reserved */
 502                         u16 mmio_size;          /* User MMIO size in KB */
 503                         u8 rsvd2;               /* Reserved */
 504                         u8 sp_intr_num:4;       /* Supported interrupts num */
 505                         u32 rsvd3:28;           /* Reserved */
 506                 };
 507         };
 508 };
 509
 510 struct feature_port_control {
 511         union {
 512                 u64 csr;
 513                 struct {
 514                         u8 port_sftrst:1;       /* Port Soft Reset */
 515                         u8 rsvd1:1;             /* Reserved */
 516                         u8 latency_tolerance:1;/* '1' >= 40us, '0' < 40us */
 517                         u8 rsvd2:1;             /* Reserved */
 518                         u8 port_sftrst_ack:1;   /* HW ACK for Soft Reset */
 519                         u64 rsvd3:59;           /* Reserved */
 520                 };
 521         };
 522 };
 523
 524 #define PORT_POWER_STATE_NORMAL         0
 525 #define PORT_POWER_STATE_AP1            1
 526 #define PORT_POWER_STATE_AP2            2
 527 #define PORT_POWER_STATE_AP6            6
 528
 529 struct feature_port_status {
 530         union {
 531                 u64 csr;
 532                 struct {
 533                         u8 port_freeze:1;       /* '1' - freezed '0' - normal */
 534                         u8 rsvd1:7;             /* Reserved */
 535                         u8 power_state:4;       /* Power State */
 536                         u8 ap1_event:1;         /* AP1 event was detected  */
 537                         u8 ap2_event:1;         /* AP2 event was detected  */
 538                         u64 rsvd2:50;           /* Reserved */
 539                 };
 540         };
 541 };
 542
 543 /* Port Header Register Set */
 544 struct feature_port_header {
 545         struct feature_header header;
 546         struct feature_afu_header afu_header;
 547         u64 port_mailbox;
 548         u64 scratchpad;
 549         struct feature_port_capability capability;
 550         struct feature_port_control control;
 551         struct feature_port_status status;
 552         u64 rsvd2;
 553         u64 user_clk_freq_cmd0;
 554         u64 user_clk_freq_cmd1;
 555         u64 user_clk_freq_sts0;
 556         u64 user_clk_freq_sts1;
 557 };
 558
 559 struct feature_fme_tmp_threshold {
 560         union {
 561                 u64 csr;
 562                 struct {
 563                         u8  tmp_thshold1:7;       /* temperature Threshold 1 */
 564                         /* temperature Threshold 1 enable/disable */
 565                         u8  tmp_thshold1_enable:1;
 566                         u8  tmp_thshold2:7;       /* temperature Threshold 2 */
 567                         /* temperature Threshold 2 enable /disable */
 568                         u8  tmp_thshold2_enable:1;
 569                         u8  pro_hot_setpoint:7;   /* Proc Hot set point */
 570                         u8  rsvd4:1;              /* Reserved */
 571                         u8  therm_trip_thshold:7; /* Thermeal Trip Threshold */
 572                         u8  rsvd3:1;              /* Reserved */
 573                         u8  thshold1_status:1;    /* Threshold 1 Status */
 574                         u8  thshold2_status:1;    /* Threshold 2 Status */
 575                         u8  rsvd5:1;              /* Reserved */
 576                         /* Thermeal Trip Threshold status */
 577                         u8  therm_trip_thshold_status:1;
 578                         u8  rsvd6:4;              /* Reserved */
 579                         /* Validation mode- Force Proc Hot */
 580                         u8  valmodeforce:1;
 581                         /* Validation mode - Therm trip Hot */
 582                         u8  valmodetherm:1;
 583                         u8  rsvd2:2;              /* Reserved */
 584                         u8  thshold_policy:1;     /* threshold policy */
 585                         u32 rsvd:19;              /* Reserved */
 586                 };
 587         };
 588 };
 589
 590 /* Temperature Sensor Read values format 1 */
 591 struct feature_fme_temp_rdsensor_fmt1 {
 592         union {
 593                 u64 csr;
 594                 struct {
 595                         /* Reads out FPGA temperature in celsius */
 596                         u8  fpga_temp:7;
 597                         u8  rsvd0:1;                    /* Reserved */
 598                         /* Temperature reading sequence number */
 599                         u16 tmp_reading_seq_num;
 600                         /* Temperature reading is valid */
 601                         u8  tmp_reading_valid:1;
 602                         u8  rsvd1:7;                    /* Reserved */
 603                         u16 dbg_mode:10;                /* Debug mode */
 604                         u32 rsvd2:22;                   /* Reserved */
 605                 };
 606         };
 607 };
 608
 609 /* Temperature sensor read values format 2 */
 610 struct feature_fme_temp_rdsensor_fmt2 {
 611         u64 rsvd;       /* Reserved */
 612 };
 613
 614 /* Temperature Threshold Capability Register */
 615 struct feature_fme_tmp_threshold_cap {
 616         union {
 617                 u64 csr;
 618                 struct {
 619                         /* Temperature Threshold Unsupported */
 620                         u8  tmp_thshold_disabled:1;
 621                         u64 rsvd:63;                    /* Reserved */
 622                 };
 623         };
 624 };
 625
 626 /* FME THERNAL FEATURE */
 627 struct feature_fme_thermal {
 628         struct feature_header header;
 629         struct feature_fme_tmp_threshold threshold;
 630         struct feature_fme_temp_rdsensor_fmt1 rdsensor_fm1;
 631         struct feature_fme_temp_rdsensor_fmt2 rdsensor_fm2;
 632         struct feature_fme_tmp_threshold_cap threshold_cap;
 633 };
 634
 635 /* Power Status register */
 636 struct feature_fme_pm_status {
 637         union {
 638                 u64 csr;
 639                 struct {
 640                         /* FPGA Power consumed, The format is to be defined */
 641                         u32 pwr_consumed:18;
 642                         /* FPGA Latency Tolerance Reporting */
 643                         u8  fpga_latency_report:1;
 644                         u64 rsvd:45;                    /* Reserved */
 645                 };
 646         };
 647 };
 648
 649 /* AP Thresholds */
 650 struct feature_fme_pm_ap_threshold {
 651         union {
 652                 u64 csr;
 653                 struct {
 654                         /*
 655                          * Number of clocks (5ns period) for assertion
 656                          * of FME_data
 657                          */
 658                         u8  threshold1:7;
 659                         u8  rsvd1:1;
 660                         u8  threshold2:7;
 661                         u8  rsvd2:1;
 662                         u8  threshold1_status:1;
 663                         u8  threshold2_status:1;
 664                         u64 rsvd3:46;           /* Reserved */
 665                 };
 666         };
 667 };
 668
 669 /* Xeon Power Limit */
 670 struct feature_fme_pm_xeon_limit {
 671         union {
 672                 u64 csr;
 673                 struct {
 674                         /* Power limit in Watts in 12.3 format */
 675                         u16 pwr_limit:15;
 676                         /* Indicates that power limit has been written */
 677                         u8  enable:1;
 678                         /* 0 - Turbe range, 1 - Entire range */
 679                         u8  clamping:1;
 680                         /* Time constant in XXYYY format */
 681                         u8  time:7;
 682                         u64 rsvd:40;            /* Reserved */
 683                 };
 684         };
 685 };
 686
 687 /* FPGA Power Limit */
 688 struct feature_fme_pm_fpga_limit {
 689         union {
 690                 u64 csr;
 691                 struct {
 692                         /* Power limit in Watts in 12.3 format */
 693                         u16 pwr_limit:15;
 694                         /* Indicates that power limit has been written */
 695                         u8  enable:1;
 696                         /* 0 - Turbe range, 1 - Entire range */
 697                         u8  clamping:1;
 698                         /* Time constant in XXYYY format */
 699                         u8  time:7;
 700                         u64 rsvd:40;            /* Reserved */
 701                 };
 702         };
 703 };
 704
 705 /* FME POWER FEATURE */
 706 struct feature_fme_power {
 707         struct feature_header header;
 708         struct feature_fme_pm_status status;
 709         struct feature_fme_pm_ap_threshold threshold;
 710         struct feature_fme_pm_xeon_limit xeon_limit;
 711         struct feature_fme_pm_fpga_limit fpga_limit;
 712 };
 713
 714 #define CACHE_CHANNEL_RD        0
 715 #define CACHE_CHANNEL_WR        1
 716
 717 enum iperf_cache_events {
 718         IPERF_CACHE_RD_HIT,
 719         IPERF_CACHE_WR_HIT,
 720         IPERF_CACHE_RD_MISS,
 721         IPERF_CACHE_WR_MISS,
 722         IPERF_CACHE_RSVD, /* reserved */
 723         IPERF_CACHE_HOLD_REQ,
 724         IPERF_CACHE_DATA_WR_PORT_CONTEN,
 725         IPERF_CACHE_TAG_WR_PORT_CONTEN,
 726         IPERF_CACHE_TX_REQ_STALL,
 727         IPERF_CACHE_RX_REQ_STALL,
 728         IPERF_CACHE_EVICTIONS,
 729 };
 730
 731 /* FPMON Cache Control */
 732 struct feature_fme_ifpmon_ch_ctl {
 733         union {
 734                 u64 csr;
 735                 struct {
 736                         u8  reset_counters:1;   /* Reset Counters */
 737                         u8  rsvd1:7;            /* Reserved */
 738                         u8  freeze:1;           /* Freeze if set to 1 */
 739                         u8  rsvd2:7;            /* Reserved */
 740                         u8  cache_event:4;      /* Select the cache event */
 741                         u8  cci_chsel:1;        /* Select the channel */
 742                         u64 rsvd3:43;           /* Reserved */
 743                 };
 744         };
 745 };
 746
 747 /* FPMON Cache Counter */
 748 struct feature_fme_ifpmon_ch_ctr {
 749         union {
 750                 u64 csr;
 751                 struct {
 752                         /* Cache Counter for even addresse */
 753                         u64 cache_counter:48;
 754                         u16 rsvd:12;            /* Reserved */
 755                         /* Cache Event being reported */
 756                         u8  event_code:4;
 757                 };
 758         };
 759 };
 760
 761 enum iperf_fab_events {
 762         IPERF_FAB_PCIE0_RD,
 763         IPERF_FAB_PCIE0_WR,
 764         IPERF_FAB_PCIE1_RD,
 765         IPERF_FAB_PCIE1_WR,
 766         IPERF_FAB_UPI_RD,
 767         IPERF_FAB_UPI_WR,
 768         IPERF_FAB_MMIO_RD,
 769         IPERF_FAB_MMIO_WR,
 770 };
 771
 772 #define FAB_DISABLE_FILTER     0
 773 #define FAB_ENABLE_FILTER      1
 774
 775 /* FPMON FAB Control */
 776 struct feature_fme_ifpmon_fab_ctl {
 777         union {
 778                 u64 csr;
 779                 struct {
 780                         u8  reset_counters:1;   /* Reset Counters */
 781                         u8  rsvd:7;             /* Reserved */
 782                         u8  freeze:1;           /* Set to 1 frozen counter */
 783                         u8  rsvd1:7;            /* Reserved */
 784                         u8  fab_evtcode:4;      /* Fabric Event Code */
 785                         u8  port_id:2;          /* Port ID */
 786                         u8  rsvd2:1;            /* Reserved */
 787                         u8  port_filter:1;      /* Port Filter */
 788                         u64 rsvd3:40;           /* Reserved */
 789                 };
 790         };
 791 };
 792
 793 /* FPMON Event Counter */
 794 struct feature_fme_ifpmon_fab_ctr {
 795         union {
 796                 u64 csr;
 797                 struct {
 798                         u64 fab_cnt:60; /* Fabric event counter */
 799                         /* Fabric event code being reported */
 800                         u8  event_code:4;
 801                 };
 802         };
 803 };
 804
 805 /* FPMON Clock Counter */
 806 struct feature_fme_ifpmon_clk_ctr {
 807         u64 afu_interf_clock;           /* Clk_16UI (AFU clock) counter. */
 808 };
 809
 810 enum iperf_vtd_events {
 811         IPERF_VTD_AFU_MEM_RD_TRANS,
 812         IPERF_VTD_AFU_MEM_WR_TRANS,
 813         IPERF_VTD_AFU_DEVTLB_RD_HIT,
 814         IPERF_VTD_AFU_DEVTLB_WR_HIT,
 815         IPERF_VTD_DEVTLB_4K_FILL,
 816         IPERF_VTD_DEVTLB_2M_FILL,
 817         IPERF_VTD_DEVTLB_1G_FILL,
 818 };
 819
 820 /* VT-d control register */
 821 struct feature_fme_ifpmon_vtd_ctl {
 822         union {
 823                 u64 csr;
 824                 struct {
 825                         u8  reset_counters:1;   /* Reset Counters */
 826                         u8  rsvd:7;             /* Reserved */
 827                         u8  freeze:1;           /* Set to 1 frozen counter */
 828                         u8  rsvd1:7;            /* Reserved */
 829                         u8  vtd_evtcode:4;      /* VTd and TLB event code */
 830                         u64 rsvd2:44;           /* Reserved */
 831                 };
 832         };
 833 };
 834
 835 /* VT-d event counter */
 836 struct feature_fme_ifpmon_vtd_ctr {
 837         union {
 838                 u64 csr;
 839                 struct {
 840                         u64 vtd_counter:48;     /* VTd event counter */
 841                         u16 rsvd:12;            /* Reserved */
 842                         u8  event_code:4;       /* VTd event code */
 843                 };
 844         };
 845 };
 846
 847 enum iperf_vtd_sip_events {
 848         IPERF_VTD_SIP_IOTLB_4K_HIT,
 849         IPERF_VTD_SIP_IOTLB_2M_HIT,
 850         IPERF_VTD_SIP_IOTLB_1G_HIT,
 851         IPERF_VTD_SIP_SLPWC_L3_HIT,
 852         IPERF_VTD_SIP_SLPWC_L4_HIT,
 853         IPERF_VTD_SIP_RCC_HIT,
 854         IPERF_VTD_SIP_IOTLB_4K_MISS,
 855         IPERF_VTD_SIP_IOTLB_2M_MISS,
 856         IPERF_VTD_SIP_IOTLB_1G_MISS,
 857         IPERF_VTD_SIP_SLPWC_L3_MISS,
 858         IPERF_VTD_SIP_SLPWC_L4_MISS,
 859         IPERF_VTD_SIP_RCC_MISS,
 860 };
 861
 862 /* VT-d SIP control register */
 863 struct feature_fme_ifpmon_vtd_sip_ctl {
 864         union {
 865                 u64 csr;
 866                 struct {
 867                         u8  reset_counters:1;   /* Reset Counters */
 868                         u8  rsvd:7;             /* Reserved */
 869                         u8  freeze:1;           /* Set to 1 frozen counter */
 870                         u8  rsvd1:7;            /* Reserved */
 871                         u8  vtd_evtcode:4;      /* VTd and TLB event code */
 872                         u64 rsvd2:44;           /* Reserved */
 873                 };
 874         };
 875 };
 876
 877 /* VT-d SIP event counter */
 878 struct feature_fme_ifpmon_vtd_sip_ctr {
 879         union {
 880                 u64 csr;
 881                 struct {
 882                         u64 vtd_counter:48;     /* VTd event counter */
 883                         u16 rsvd:12;            /* Reserved */
 884                         u8 event_code:4;        /* VTd event code */
 885                 };
 886         };
 887 };
 888
 889 /* FME IPERF FEATURE */
 890 struct feature_fme_iperf {
 891         struct feature_header header;
 892         struct feature_fme_ifpmon_ch_ctl ch_ctl;
 893         struct feature_fme_ifpmon_ch_ctr ch_ctr0;
 894         struct feature_fme_ifpmon_ch_ctr ch_ctr1;
 895         struct feature_fme_ifpmon_fab_ctl fab_ctl;
 896         struct feature_fme_ifpmon_fab_ctr fab_ctr;
 897         struct feature_fme_ifpmon_clk_ctr clk;
 898         struct feature_fme_ifpmon_vtd_ctl vtd_ctl;
 899         struct feature_fme_ifpmon_vtd_ctr vtd_ctr;
 900         struct feature_fme_ifpmon_vtd_sip_ctl vtd_sip_ctl;
 901         struct feature_fme_ifpmon_vtd_sip_ctr vtd_sip_ctr;
 902 };
 903
 904 enum dperf_fab_events {
 905         DPERF_FAB_PCIE0_RD,
 906         DPERF_FAB_PCIE0_WR,
 907         DPERF_FAB_MMIO_RD = 6,
 908         DPERF_FAB_MMIO_WR,
 909 };
 910
 911 /* FPMON FAB Control */
 912 struct feature_fme_dfpmon_fab_ctl {
 913         union {
 914                 u64 csr;
 915                 struct {
 916                         u8  reset_counters:1;   /* Reset Counters */
 917                         u8  rsvd:7;             /* Reserved */
 918                         u8  freeze:1;           /* Set to 1 frozen counter */
 919                         u8  rsvd1:7;            /* Reserved */
 920                         u8  fab_evtcode:4;      /* Fabric Event Code */
 921                         u8  port_id:2;          /* Port ID */
 922                         u8  rsvd2:1;            /* Reserved */
 923                         u8  port_filter:1;      /* Port Filter */
 924                         u64 rsvd3:40;           /* Reserved */
 925                 };
 926         };
 927 };
 928
 929 /* FPMON Event Counter */
 930 struct feature_fme_dfpmon_fab_ctr {
 931         union {
 932                 u64 csr;
 933                 struct {
 934                         u64 fab_cnt:60; /* Fabric event counter */
 935                         /* Fabric event code being reported */
 936                         u8  event_code:4;
 937                 };
 938         };
 939 };
 940
 941 /* FPMON Clock Counter */
 942 struct feature_fme_dfpmon_clk_ctr {
 943         u64 afu_interf_clock;           /* Clk_16UI (AFU clock) counter. */
 944 };
 945
 946 /* FME DPERF FEATURE */
 947 struct feature_fme_dperf {
 948         struct feature_header header;
 949         u64 rsvd[3];
 950         struct feature_fme_dfpmon_fab_ctl fab_ctl;
 951         struct feature_fme_dfpmon_fab_ctr fab_ctr;
 952         struct feature_fme_dfpmon_clk_ctr clk;
 953 };
 954
 955 struct feature_fme_error0 {
 956 #define FME_ERROR0_MASK        0xFFUL
 957 #define FME_ERROR0_MASK_DEFAULT 0x40UL  /* pcode workaround */
 958         union {
 959                 u64 csr;
 960                 struct {
 961                         u8  fabric_err:1;       /* Fabric error */
 962                         u8  fabfifo_overflow:1; /* Fabric fifo overflow */
 963                         u8  kticdc_parity_err:2;/* KTI CDC Parity Error */
 964                         u8  iommu_parity_err:1; /* IOMMU Parity error */
 965                         /* AFU PF/VF access mismatch detected */
 966                         u8  afu_acc_mode_err:1;
 967                         u8  mbp_err:1;          /* Indicates an MBP event */
 968                         /* PCIE0 CDC Parity Error */
 969                         u8  pcie0cdc_parity_err:5;
 970                         /* PCIE1 CDC Parity Error */
 971                         u8  pcie1cdc_parity_err:5;
 972                         /* CVL CDC Parity Error */
 973                         u8  cvlcdc_parity_err:3;
 974                         u64 rsvd:44;            /* Reserved */
 975                 };
 976         };
 977 };
 978
 979 /* PCIe0 Error Status register */
 980 struct feature_fme_pcie0_error {
 981 #define FME_PCIE0_ERROR_MASK   0xFFUL
 982         union {
 983                 u64 csr;
 984                 struct {
 985                         u8  formattype_err:1;   /* TLP format/type error */
 986                         u8  MWAddr_err:1;       /* TLP MW address error */
 987                         u8  MWAddrLength_err:1; /* TLP MW length error */
 988                         u8  MRAddr_err:1;       /* TLP MR address error */
 989                         u8  MRAddrLength_err:1; /* TLP MR length error */
 990                         u8  cpl_tag_err:1;      /* TLP CPL tag error */
 991                         u8  cpl_status_err:1;   /* TLP CPL status error */
 992                         u8  cpl_timeout_err:1;  /* TLP CPL timeout */
 993                         u8  cci_parity_err:1;   /* CCI bridge parity error */
 994                         u8  rxpoison_tlp_err:1; /* Received a TLP with EP set */
 995                         u64 rsvd:52;            /* Reserved */
 996                         u8  vfnumb_err:1;       /* Number of error VF */
 997                         u8  funct_type_err:1;   /* Virtual (1) or Physical */
 998                 };
 999         };
1000 };
1001
1002 /* PCIe1 Error Status register */
1003 struct feature_fme_pcie1_error {
1004 #define FME_PCIE1_ERROR_MASK   0xFFUL
1005         union {
1006                 u64 csr;
1007                 struct {
1008                         u8  formattype_err:1;   /* TLP format/type error */
1009                         u8  MWAddr_err:1;       /* TLP MW address error */
1010                         u8  MWAddrLength_err:1; /* TLP MW length error */
1011                         u8  MRAddr_err:1;       /* TLP MR address error */
1012                         u8  MRAddrLength_err:1; /* TLP MR length error */
1013                         u8  cpl_tag_err:1;      /* TLP CPL tag error */
1014                         u8  cpl_status_err:1;   /* TLP CPL status error */
1015                         u8  cpl_timeout_err:1;  /* TLP CPL timeout */
1016                         u8  cci_parity_err:1;   /* CCI bridge parity error */
1017                         u8  rxpoison_tlp_err:1; /* Received a TLP with EP set */
1018                         u64 rsvd:54;            /* Reserved */
1019                 };
1020         };
1021 };
1022
1023 /* FME First Error register */
1024 struct feature_fme_first_error {
1025 #define FME_FIRST_ERROR_MASK   ((1ULL << 60) - 1)
1026         union {
1027                 u64 csr;
1028                 struct {
1029                         /*
1030                          * Indicates the Error Register that was
1031                          * triggered first
1032                          */
1033                         u64 err_reg_status:60;
1034                         /*
1035                          * Holds 60 LSBs from the Error register that was
1036                          * triggered first
1037                          */
1038                         u8 errReg_id:4;
1039                 };
1040         };
1041 };
1042
1043 /* FME Next Error register */
1044 struct feature_fme_next_error {
1045 #define FME_NEXT_ERROR_MASK    ((1ULL << 60) - 1)
1046         union {
1047                 u64 csr;
1048                 struct {
1049                         /*
1050                          * Indicates the Error Register that was
1051                          * triggered second
1052                          */
1053                         u64 err_reg_status:60;
1054                         /*
1055                          * Holds 60 LSBs from the Error register that was
1056                          * triggered second
1057                          */
1058                         u8  errReg_id:4;
1059                 };
1060         };
1061 };
1062
1063 /* RAS Non Fatal Error Status register */
1064 struct feature_fme_ras_nonfaterror {
1065         union {
1066                 u64 csr;
1067                 struct {
1068                         /* thremal threshold AP1 */
1069                         u8  temp_thresh_ap1:1;
1070                         /* thremal threshold AP2 */
1071                         u8  temp_thresh_ap2:1;
1072                         u8  pcie_error:1;       /* pcie Error */
1073                         u8  portfatal_error:1;  /* port fatal error */
1074                         u8  proc_hot:1;         /* Indicates a ProcHot event */
1075                         /* Indicates an AFU PF/VF access mismatch */
1076                         u8  afu_acc_mode_err:1;
1077                         /* Injected nonfata Error */
1078                         u8  injected_nonfata_err:1;
1079                         u8  rsvd1:2;
1080                         /* Temperature threshold triggered AP6*/
1081                         u8  temp_thresh_AP6:1;
1082                         /* Power threshold triggered AP1 */
1083                         u8  power_thresh_AP1:1;
1084                         /* Power threshold triggered AP2 */
1085                         u8  power_thresh_AP2:1;
1086                         /* Indicates a MBP event */
1087                         u8  mbp_err:1;
1088                         u64 rsvd2:51;           /* Reserved */
1089                 };
1090         };
1091 };
1092
1093 /* RAS Catastrophic Fatal Error Status register */
1094 struct feature_fme_ras_catfaterror {
1095         union {
1096                 u64 csr;
1097                 struct {
1098                         /* KTI Link layer error detected */
1099                         u8  ktilink_fatal_err:1;
1100                         /* tag-n-cache error detected */
1101                         u8  tagcch_fatal_err:1;
1102                         /* CCI error detected */
1103                         u8  cci_fatal_err:1;
1104                         /* KTI Protocol error detected */
1105                         u8  ktiprpto_fatal_err:1;
1106                         /* Fatal DRAM error detected */
1107                         u8  dram_fatal_err:1;
1108                         /* IOMMU detected */
1109                         u8  iommu_fatal_err:1;
1110                         /* Fabric Fatal Error */
1111                         u8  fabric_fatal_err:1;
1112                         /* PCIe possion Error */
1113                         u8  pcie_poison_err:1;
1114                         /* Injected fatal Error */
1115                         u8  inject_fata_err:1;
1116                         /* Catastrophic CRC Error */
1117                         u8  crc_catast_err:1;
1118                         /* Catastrophic Thermal Error */
1119                         u8  therm_catast_err:1;
1120                         /* Injected Catastrophic Error */
1121                         u8  injected_catast_err:1;
1122                         u64 rsvd:52;
1123                 };
1124         };
1125 };
1126
1127 /* RAS Error injection register */
1128 struct feature_fme_ras_error_inj {
1129 #define FME_RAS_ERROR_INJ_MASK      0x7UL
1130         union {
1131                 u64 csr;
1132                 struct {
1133                         u8  catast_error:1;     /* Catastrophic error flag */
1134                         u8  fatal_error:1;      /* Fatal error flag */
1135                         u8  nonfatal_error:1;   /* NonFatal error flag */
1136                         u64 rsvd:61;            /* Reserved */
1137                 };
1138         };
1139 };
1140
1141 /* FME error capabilities */
1142 struct feature_fme_error_capability {
1143         union {
1144         u64 csr;
1145                 struct {
1146                         u8 support_intr:1;
1147                         /* MSI-X vector table entry number */
1148                         u16 intr_vector_num:12;
1149                         u64 rsvd:51;    /* Reserved */
1150                 };
1151         };
1152 };
1153
1154 /* FME ERR FEATURE */
1155 struct feature_fme_err {
1156         struct feature_header header;
1157         struct feature_fme_error0 fme_err_mask;
1158         struct feature_fme_error0 fme_err;
1159         struct feature_fme_pcie0_error pcie0_err_mask;
1160         struct feature_fme_pcie0_error pcie0_err;
1161         struct feature_fme_pcie1_error pcie1_err_mask;
1162         struct feature_fme_pcie1_error pcie1_err;
1163         struct feature_fme_first_error fme_first_err;
1164         struct feature_fme_next_error fme_next_err;
1165         struct feature_fme_ras_nonfaterror ras_nonfat_mask;
1166         struct feature_fme_ras_nonfaterror ras_nonfaterr;
1167         struct feature_fme_ras_catfaterror ras_catfat_mask;
1168         struct feature_fme_ras_catfaterror ras_catfaterr;
1169         struct feature_fme_ras_error_inj ras_error_inj;
1170         struct feature_fme_error_capability fme_err_capability;
1171 };
1172
1173 /* FME Partial Reconfiguration Control */
1174 struct feature_fme_pr_ctl {
1175         union {
1176                 u64 csr;
1177                 struct {
1178                         u8  pr_reset:1;         /* Reset PR Engine */
1179                         u8  rsvd3:3;            /* Reserved */
1180                         u8  pr_reset_ack:1;     /* Reset PR Engine Ack */
1181                         u8  rsvd4:3;            /* Reserved */
1182                         u8  pr_regionid:2;      /* PR Region ID */
1183                         u8  rsvd1:2;            /* Reserved */
1184                         u8  pr_start_req:1;     /* PR Start Request */
1185                         u8  pr_push_complete:1; /* PR Data push complete */
1186                         u8  pr_kind:1;          /* PR Data push complete */
1187                         u32 rsvd:17;            /* Reserved */
1188                         u32 config_data;        /* Config data TBD */
1189                 };
1190         };
1191 };
1192
1193 /* FME Partial Reconfiguration Status */
1194 struct feature_fme_pr_status {
1195         union {
1196                 u64 csr;
1197                 struct {
1198                         u16 pr_credit:9;        /* PR Credits */
1199                         u8  rsvd2:7;            /* Reserved */
1200                         u8  pr_status:1;        /* PR status */
1201                         u8  rsvd:3;             /* Reserved */
1202                         /* Altra PR Controller Block status */
1203                         u8  pr_controller_status:3;
1204                         u8  rsvd1:1;            /* Reserved */
1205                         u8  pr_host_status:4;   /* PR Host status */
1206                         u8  rsvd3:4;            /* Reserved */
1207                         /* Security Block Status fields (TBD) */
1208                         u32 security_bstatus;
1209                 };
1210         };
1211 };
1212
1213 /* FME Partial Reconfiguration Data */
1214 struct feature_fme_pr_data {
1215         union {
1216                 u64 csr;        /* PR data from the raw-binary file */
1217                 struct {
1218                         /* PR data from the raw-binary file */
1219                         u32 pr_data_raw;
1220                         u32 rsvd;
1221                 };
1222         };
1223 };
1224
1225 /* FME PR Public Key */
1226 struct feature_fme_pr_key {
1227         u64 key;                /* FME PR Public Hash */
1228 };
1229
1230 /* FME PR FEATURE */
1231 struct feature_fme_pr {
1232         struct feature_header header;
1233         /*Partial Reconfiguration control */
1234         struct feature_fme_pr_ctl       ccip_fme_pr_control;
1235
1236         /* Partial Reconfiguration Status */
1237         struct feature_fme_pr_status    ccip_fme_pr_status;
1238
1239         /* Partial Reconfiguration data */
1240         struct feature_fme_pr_data      ccip_fme_pr_data;
1241
1242         /* Partial Reconfiguration data */
1243         u64                             ccip_fme_pr_err;
1244
1245         u64 rsvd1[3];
1246
1247         /* Partial Reconfiguration data registers */
1248         u64 fme_pr_data1;
1249         u64 fme_pr_data2;
1250         u64 fme_pr_data3;
1251         u64 fme_pr_data4;
1252         u64 fme_pr_data5;
1253         u64 fme_pr_data6;
1254         u64 fme_pr_data7;
1255         u64 fme_pr_data8;
1256
1257         u64 rsvd2[5];
1258
1259         /* PR Interface ID */
1260         u64 fme_pr_intfc_id_l;
1261         u64 fme_pr_intfc_id_h;
1262
1263         /* MSIX filed to be Added */
1264 };
1265
1266 /* FME HSSI Control */
1267 struct feature_fme_hssi_eth_ctrl {
1268         union {
1269                 u64 csr;
1270                 struct {
1271                         u32 data:32;            /* HSSI data */
1272                         u16 address:16;         /* HSSI address */
1273                         /*
1274                          * HSSI comamnd
1275                          * 0x0 - No request
1276                          * 0x08 - SW register RD request
1277                          * 0x10 - SW register WR request
1278                          * 0x40 - Auxiliar bus RD request
1279                          * 0x80 - Auxiliar bus WR request
1280                          */
1281                         u16 cmd:16;
1282                 };
1283         };
1284 };
1285
1286 /* FME HSSI Status */
1287 struct feature_fme_hssi_eth_stat {
1288         union {
1289                 u64 csr;
1290                 struct {
1291                         u32 data:32;            /* HSSI data */
1292                         u8  acknowledge:1;      /* HSSI acknowledge */
1293                         u8  spare:1;            /* HSSI spare */
1294                         u32 rsvd:30;            /* Reserved */
1295                 };
1296         };
1297 };
1298
1299 /* FME HSSI FEATURE */
1300 struct feature_fme_hssi {
1301         struct feature_header header;
1302         struct feature_fme_hssi_eth_ctrl        hssi_control;
1303         struct feature_fme_hssi_eth_stat        hssi_status;
1304 };
1305
1306 #define PORT_ERR_MASK           0xfff0703ff001f
1307 struct feature_port_err_key {
1308         union {
1309                 u64 csr;
1310                 struct {
1311                         /* Tx Channel0: Overflow */
1312                         u8 tx_ch0_overflow:1;
1313                         /* Tx Channel0: Invalid request encoding */
1314                         u8 tx_ch0_invaldreq :1;
1315                         /* Tx Channel0: Request with cl_len=3 not supported */
1316                         u8 tx_ch0_cl_len3:1;
1317                         /* Tx Channel0: Request with cl_len=2 not aligned 2CL */
1318                         u8 tx_ch0_cl_len2:1;
1319                         /* Tx Channel0: Request with cl_len=4 not aligned 4CL */
1320                         u8 tx_ch0_cl_len4:1;
1321
1322                         u16 rsvd1:4;                    /* Reserved */
1323
1324                         /* AFU MMIO RD received while PORT is in reset */
1325                         u8 mmio_rd_whilerst:1;
1326                         /* AFU MMIO WR received while PORT is in reset */
1327                         u8 mmio_wr_whilerst:1;
1328
1329                         u16 rsvd2:5;                    /* Reserved */
1330
1331                         /* Tx Channel1: Overflow */
1332                         u8 tx_ch1_overflow:1;
1333                         /* Tx Channel1: Invalid request encoding */
1334                         u8 tx_ch1_invaldreq:1;
1335                         /* Tx Channel1: Request with cl_len=3 not supported */
1336                         u8 tx_ch1_cl_len3:1;
1337                         /* Tx Channel1: Request with cl_len=2 not aligned 2CL */
1338                         u8 tx_ch1_cl_len2:1;
1339                         /* Tx Channel1: Request with cl_len=4 not aligned 4CL */
1340                         u8 tx_ch1_cl_len4:1;
1341
1342                         /* Tx Channel1: Insufficient data payload */
1343                         u8 tx_ch1_insuff_data:1;
1344                         /* Tx Channel1: Data payload overrun */
1345                         u8 tx_ch1_data_overrun:1;
1346                         /* Tx Channel1 : Incorrect address */
1347                         u8 tx_ch1_incorr_addr:1;
1348                         /* Tx Channel1 : NON-Zero SOP Detected */
1349                         u8 tx_ch1_nzsop:1;
1350                         /* Tx Channel1 : Illegal VC_SEL, atomic request VLO */
1351                         u8 tx_ch1_illegal_vcsel:1;
1352
1353                         u8 rsvd3:6;                     /* Reserved */
1354
1355                         /* MMIO Read Timeout in AFU */
1356                         u8 mmioread_timeout:1;
1357
1358                         /* Tx Channel2: FIFO Overflow */
1359                         u8 tx_ch2_fifo_overflow:1;
1360
1361                         /* MMIO read is not matching pending request */
1362                         u8 unexp_mmio_resp:1;
1363
1364                         u8 rsvd4:5;                     /* Reserved */
1365
1366                         /* Number of pending Requests: counter overflow */
1367                         u8 tx_req_counter_overflow:1;
1368                         /* Req with Address violating SMM Range */
1369                         u8 llpr_smrr_err:1;
1370                         /* Req with Address violating second SMM Range */
1371                         u8 llpr_smrr2_err:1;
1372                         /* Req with Address violating ME Stolen message */
1373                         u8 llpr_mesg_err:1;
1374                         /* Req with Address violating Generic Protected Range */
1375                         u8 genprot_range_err:1;
1376                         /* Req with Address violating Legacy Range low */
1377                         u8 legrange_low_err:1;
1378                         /* Req with Address violating Legacy Range High */
1379                         u8 legrange_high_err:1;
1380                         /* Req with Address violating VGA memory range */
1381                         u8 vgmem_range_err:1;
1382                         u8 page_fault_err:1;            /* Page fault */
1383                         u8 pmr_err:1;                   /* PMR Error */
1384                         u8 ap6_event:1;                 /* AP6 event */
1385                         /* VF FLR detected on Port with PF access control */
1386                         u8 vfflr_access_err:1;
1387                         u16 rsvd5:12;                   /* Reserved */
1388                 };
1389         };
1390 };
1391
1392 /* Port first error register, not contain all error bits in error register. */
1393 struct feature_port_first_err_key {
1394         union {
1395                 u64 csr;
1396                 struct {
1397                         u8 tx_ch0_overflow:1;
1398                         u8 tx_ch0_invaldreq :1;
1399                         u8 tx_ch0_cl_len3:1;
1400                         u8 tx_ch0_cl_len2:1;
1401                         u8 tx_ch0_cl_len4:1;
1402                         u8 rsvd1:4;                     /* Reserved */
1403                         u8 mmio_rd_whilerst:1;
1404                         u8 mmio_wr_whilerst:1;
1405                         u8 rsvd2:5;                     /* Reserved */
1406                         u8 tx_ch1_overflow:1;
1407                         u8 tx_ch1_invaldreq:1;
1408                         u8 tx_ch1_cl_len3:1;
1409                         u8 tx_ch1_cl_len2:1;
1410                         u8 tx_ch1_cl_len4:1;
1411                         u8 tx_ch1_insuff_data:1;
1412                         u8 tx_ch1_data_overrun:1;
1413                         u8 tx_ch1_incorr_addr:1;
1414                         u8 tx_ch1_nzsop:1;
1415                         u8 tx_ch1_illegal_vcsel:1;
1416                         u8 rsvd3:6;                     /* Reserved */
1417                         u8 mmioread_timeout:1;
1418                         u8 tx_ch2_fifo_overflow:1;
1419                         u8 rsvd4:6;                     /* Reserved */
1420                         u8 tx_req_counter_overflow:1;
1421                         u32 rsvd5:23;                   /* Reserved */
1422                 };
1423         };
1424 };
1425
1426 /* Port malformed Req0 */
1427 struct feature_port_malformed_req0 {
1428         u64 header_lsb;
1429 };
1430
1431 /* Port malformed Req1 */
1432 struct feature_port_malformed_req1 {
1433         u64 header_msb;
1434 };
1435
1436 /* Port debug register */
1437 struct feature_port_debug {
1438         u64 port_debug;
1439 };
1440
1441 /* Port error capabilities */
1442 struct feature_port_err_capability {
1443         union {
1444                 u64 csr;
1445                 struct {
1446                         u8  support_intr:1;
1447                         /* MSI-X vector table entry number */
1448                         u16 intr_vector_num:12;
1449                         u64 rsvd:51;            /* Reserved */
1450                 };
1451         };
1452 };
1453
1454 /* PORT FEATURE ERROR */
1455 struct feature_port_error {
1456         struct feature_header header;
1457         struct feature_port_err_key error_mask;
1458         struct feature_port_err_key port_error;
1459         struct feature_port_first_err_key port_first_error;
1460         struct feature_port_malformed_req0 malreq0;
1461         struct feature_port_malformed_req1 malreq1;
1462         struct feature_port_debug port_debug;
1463         struct feature_port_err_capability error_capability;
1464 };
1465
1466 /* Port UMSG Capability */
1467 struct feature_port_umsg_cap {
1468         union {
1469                 u64 csr;
1470                 struct {
1471                         /* Number of umsg allocated to this port */
1472                         u8 umsg_allocated;
1473                         /* Enable / Disable UMsg engine for this port */
1474                         u8 umsg_enable:1;
1475                         /* Usmg initialization status */
1476                         u8 umsg_init_complete:1;
1477                         /* IOMMU can not translate the umsg base address */
1478                         u8 umsg_trans_error:1;
1479                         u64 rsvd:53;            /* Reserved */
1480                 };
1481         };
1482 };
1483
1484 /* Port UMSG base address */
1485 struct feature_port_umsg_baseaddr {
1486         union {
1487                 u64 csr;
1488                 struct {
1489                         u64 base_addr:48;       /* 48 bit physical address */
1490                         u16 rsvd;               /* Reserved */
1491                 };
1492         };
1493 };
1494
1495 struct feature_port_umsg_mode {
1496         union {
1497                 u64 csr;
1498                 struct {
1499                         u32 umsg_hint_enable;   /* UMSG hint enable/disable */
1500                         u32 rsvd;               /* Reserved */
1501                 };
1502         };
1503 };
1504
1505 /* PORT FEATURE UMSG */
1506 struct feature_port_umsg {
1507         struct feature_header header;
1508         struct feature_port_umsg_cap capability;
1509         struct feature_port_umsg_baseaddr baseaddr;
1510         struct feature_port_umsg_mode mode;
1511 };
1512
1513 #define UMSG_EN_POLL_INVL 10 /* us */
1514 #define UMSG_EN_POLL_TIMEOUT 1000 /* us */
1515
1516 /* Port UINT Capability */
1517 struct feature_port_uint_cap {
1518         union {
1519                 u64 csr;
1520                 struct {
1521                         u16 intr_num:12;        /* Supported interrupts num */
1522                         /* First MSI-X vector table entry number */
1523                         u16 first_vec_num:12;
1524                         u64 rsvd:40;
1525                 };
1526         };
1527 };
1528
1529 /* PORT FEATURE UINT */
1530 struct feature_port_uint {
1531         struct feature_header header;
1532         struct feature_port_uint_cap capability;
1533 };
1534
1535 /* STP region supports mmap operation, so use page aligned size. */
1536 #define PORT_FEATURE_STP_REGION_SIZE \
1537         IFPGA_PAGE_ALIGN(sizeof(struct feature_port_stp))
1538
1539 /* Port STP status register (for debug only)*/
1540 struct feature_port_stp_status {
1541         union {
1542                 u64 csr;
1543                 struct {
1544                         /* SLD Hub end-point read/write timeout */
1545                         u8 sld_ep_timeout:1;
1546                         /* Remote STP in reset/disable */
1547                         u8 rstp_disabled:1;
1548                         u8 unsupported_read:1;
1549                         /* MMIO timeout detected and faked with a response */
1550                         u8 mmio_timeout:1;
1551                         u8 txfifo_count:4;
1552                         u8 rxfifo_count:4;
1553                         u8 txfifo_overflow:1;
1554                         u8 txfifo_underflow:1;
1555                         u8 rxfifo_overflow:1;
1556                         u8 rxfifo_underflow:1;
1557                         /* Number of MMIO write requests */
1558                         u16 write_requests;
1559                         /* Number of MMIO read requests */
1560                         u16 read_requests;
1561                         /* Number of MMIO read responses */
1562                         u16 read_responses;
1563                 };
1564         };
1565 };
1566
1567 /*
1568  * PORT FEATURE STP
1569  * Most registers in STP region are not touched by driver, but mmapped to user
1570  * space. So they are not defined in below data structure, as its actual size
1571  * is 0x18c per spec.
1572  */
1573 struct feature_port_stp {
1574         struct feature_header header;
1575         struct feature_port_stp_status stp_status;
1576 };
1577
1578 /**
1579  * enum fpga_pr_states - fpga PR states
1580  * @FPGA_PR_STATE_UNKNOWN: can't determine state
1581  * @FPGA_PR_STATE_WRITE_INIT: preparing FPGA for programming
1582  * @FPGA_PR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage
1583  * @FPGA_PR_STATE_WRITE: writing image to FPGA
1584  * @FPGA_PR_STATE_WRITE_ERR: Error while writing FPGA
1585  * @FPGA_PR_STATE_WRITE_COMPLETE: Doing post programming steps
1586  * @FPGA_PR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE
1587  * @FPGA_PR_STATE_OPERATING: FPGA PR done
1588  */
1589 enum fpga_pr_states {
1590         /* canot determine state states */
1591         FPGA_PR_STATE_UNKNOWN,
1592
1593         /* write sequence: init, write, complete */
1594         FPGA_PR_STATE_WRITE_INIT,
1595         FPGA_PR_STATE_WRITE_INIT_ERR,
1596         FPGA_PR_STATE_WRITE,
1597         FPGA_PR_STATE_WRITE_ERR,
1598         FPGA_PR_STATE_WRITE_COMPLETE,
1599         FPGA_PR_STATE_WRITE_COMPLETE_ERR,
1600
1601         /* FPGA PR done */
1602         FPGA_PR_STATE_DONE,
1603 };
1604
1605 /*
1606  * FPGA Manager flags
1607  * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported
1608  */
1609 #define FPGA_MGR_PARTIAL_RECONFIG       BIT(0)
1610
1611 /**
1612  * struct fpga_pr_info - specific information to a FPGA PR
1613  * @flags: boolean flags as defined above
1614  * @pr_err: PR error code
1615  * @state: fpga manager state
1616  * @port_id: port id
1617  */
1618 struct fpga_pr_info {
1619         u32 flags;
1620         u64 pr_err;
1621         enum fpga_pr_states state;
1622         int port_id;
1623 };
1624
1625 #define DEFINE_FPGA_PR_ERR_MSG(_name_)                  \
1626 static const char * const _name_[] = {                  \
1627         "PR operation error detected",                  \
1628         "PR CRC error detected",                        \
1629         "PR incompatiable bitstream error detected",    \
1630         "PR IP protocol error detected",                \
1631         "PR FIFO overflow error detected",              \
1632         "PR timeout error detected",                    \
1633         "PR secure load error detected",                \
1634 }
1635
1636 #define RST_POLL_INVL 10 /* us */
1637 #define RST_POLL_TIMEOUT 1000 /* us */
1638
1639 #define PR_WAIT_TIMEOUT   15000000
1640
1641 #define PR_HOST_STATUS_IDLE     0
1642 #define PR_MAX_ERR_NUM  7
1643
1644 DEFINE_FPGA_PR_ERR_MSG(pr_err_msg);
1645
1646 /*
1647  * green bitstream header must be byte-packed to match the
1648  * real file format.
1649  */
1650 struct bts_header {
1651         u64 guid_h;
1652         u64 guid_l;
1653         u32 metadata_len;
1654 };
1655
1656 #define GBS_GUID_H              0x414750466e6f6558
1657 #define GBS_GUID_L              0x31303076534247b7
1658 #define is_valid_bts(bts_hdr)                           \
1659         (((bts_hdr)->guid_h == GBS_GUID_H) &&           \
1660         ((bts_hdr)->guid_l == GBS_GUID_L))
1661
1662 #pragma pack(pop)
1663 #endif /* _BASE_IFPGA_DEFINES_H_ */