drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include "opae_hw_api.h"
   6 #include "ifpga_api.h"
   7
   8 #include "ifpga_hw.h"
   9 #include "ifpga_enumerate.h"
  10 #include "ifpga_feature_dev.h"
  11
  12 struct build_feature_devs_info {
  13         struct opae_adapter_data_pci *pci_data;
  14
  15         struct ifpga_afu_info *acc_info;
  16
  17         void *fiu;
  18         enum fpga_id_type current_type;
  19         int current_port_id;
  20
  21         void *ioaddr;
  22         void *ioend;
  23         uint64_t phys_addr;
  24         int current_bar;
  25
  26         void *pfme_hdr;
  27
  28         struct ifpga_hw *hw;
  29 };
  30
  31 struct feature_info {
  32         const char *name;
  33         u32 resource_size;
  34         int feature_index;
  35         int revision_id;
  36         unsigned int vec_start;
  37         unsigned int vec_cnt;
  38
  39         struct feature_ops *ops;
  40 };
  41
  42 /* indexed by fme feature IDs which are defined in 'enum fme_feature_id'. */
  43 static struct feature_info fme_features[] = {
  44         {
  45                 .name = FME_FEATURE_HEADER,
  46                 .resource_size = sizeof(struct feature_fme_header),
  47                 .feature_index = FME_FEATURE_ID_HEADER,
  48                 .revision_id = FME_HEADER_REVISION,
  49                 .ops = &fme_hdr_ops,
  50         },
  51         {
  52                 .name = FME_FEATURE_THERMAL_MGMT,
  53                 .resource_size = sizeof(struct feature_fme_thermal),
  54                 .feature_index = FME_FEATURE_ID_THERMAL_MGMT,
  55                 .revision_id = FME_THERMAL_MGMT_REVISION,
  56                 .ops = &fme_thermal_mgmt_ops,
  57         },
  58         {
  59                 .name = FME_FEATURE_POWER_MGMT,
  60                 .resource_size = sizeof(struct feature_fme_power),
  61                 .feature_index = FME_FEATURE_ID_POWER_MGMT,
  62                 .revision_id = FME_POWER_MGMT_REVISION,
  63                 .ops = &fme_power_mgmt_ops,
  64         },
  65         {
  66                 .name = FME_FEATURE_GLOBAL_IPERF,
  67                 .resource_size = sizeof(struct feature_fme_iperf),
  68                 .feature_index = FME_FEATURE_ID_GLOBAL_IPERF,
  69                 .revision_id = FME_GLOBAL_IPERF_REVISION,
  70                 .ops = &fme_global_iperf_ops,
  71         },
  72         {
  73                 .name = FME_FEATURE_GLOBAL_ERR,
  74                 .resource_size = sizeof(struct feature_fme_err),
  75                 .feature_index = FME_FEATURE_ID_GLOBAL_ERR,
  76                 .revision_id = FME_GLOBAL_ERR_REVISION,
  77                 .ops = &fme_global_err_ops,
  78         },
  79         {
  80                 .name = FME_FEATURE_PR_MGMT,
  81                 .resource_size = sizeof(struct feature_fme_pr),
  82                 .feature_index = FME_FEATURE_ID_PR_MGMT,
  83                 .revision_id = FME_PR_MGMT_REVISION,
  84                 .ops = &fme_pr_mgmt_ops,
  85         },
  86         {
  87                 .name = FME_FEATURE_HSSI_ETH,
  88                 .resource_size = sizeof(struct feature_fme_hssi),
  89                 .feature_index = FME_FEATURE_ID_HSSI_ETH,
  90                 .revision_id = FME_HSSI_ETH_REVISION
  91         },
  92         {
  93                 .name = FME_FEATURE_GLOBAL_DPERF,
  94                 .resource_size = sizeof(struct feature_fme_dperf),
  95                 .feature_index = FME_FEATURE_ID_GLOBAL_DPERF,
  96                 .revision_id = FME_GLOBAL_DPERF_REVISION,
  97                 .ops = &fme_global_dperf_ops,
  98         }
  99 };
 100
 101 static struct feature_info port_features[] = {
 102         {
 103                 .name = PORT_FEATURE_HEADER,
 104                 .resource_size = sizeof(struct feature_port_header),
 105                 .feature_index = PORT_FEATURE_ID_HEADER,
 106                 .revision_id = PORT_HEADER_REVISION,
 107                 .ops = &ifpga_rawdev_port_hdr_ops,
 108         },
 109         {
 110                 .name = PORT_FEATURE_ERR,
 111                 .resource_size = sizeof(struct feature_port_error),
 112                 .feature_index = PORT_FEATURE_ID_ERROR,
 113                 .revision_id = PORT_ERR_REVISION,
 114                 .ops = &ifpga_rawdev_port_error_ops,
 115         },
 116         {
 117                 .name = PORT_FEATURE_UMSG,
 118                 .resource_size = sizeof(struct feature_port_umsg),
 119                 .feature_index = PORT_FEATURE_ID_UMSG,
 120                 .revision_id = PORT_UMSG_REVISION,
 121         },
 122         {
 123                 .name = PORT_FEATURE_UINT,
 124                 .resource_size = sizeof(struct feature_port_uint),
 125                 .feature_index = PORT_FEATURE_ID_UINT,
 126                 .revision_id = PORT_UINT_REVISION,
 127                 .ops = &ifpga_rawdev_port_uint_ops,
 128         },
 129         {
 130                 .name = PORT_FEATURE_STP,
 131                 .resource_size = PORT_FEATURE_STP_REGION_SIZE,
 132                 .feature_index = PORT_FEATURE_ID_STP,
 133                 .revision_id = PORT_STP_REVISION,
 134                 .ops = &ifpga_rawdev_port_stp_ops,
 135         },
 136         {
 137                 .name = PORT_FEATURE_UAFU,
 138                 /* UAFU feature size should be read from PORT_CAP.MMIOSIZE.
 139                  * Will set uafu feature size while parse port device.
 140                  */
 141                 .resource_size = 0,
 142                 .feature_index = PORT_FEATURE_ID_UAFU,
 143                 .revision_id = PORT_UAFU_REVISION
 144         },
 145 };
 146
 147 static u64 feature_id(void __iomem *start)
 148 {
 149         struct feature_header header;
 150
 151         header.csr = readq(start);
 152
 153         switch (header.type) {
 154         case FEATURE_TYPE_FIU:
 155                 return FEATURE_ID_HEADER;
 156         case FEATURE_TYPE_PRIVATE:
 157                 return header.id;
 158         case FEATURE_TYPE_AFU:
 159                 return FEATURE_ID_AFU;
 160         }
 161
 162         WARN_ON(1);
 163         return 0;
 164 }
 165
 166 static int
 167 build_info_add_sub_feature(struct build_feature_devs_info *binfo,
 168                            struct feature_info *finfo, void __iomem *start)
 169 {
 170         struct ifpga_hw *hw = binfo->hw;
 171         struct feature *feature = NULL;
 172         int feature_idx = finfo->feature_index;
 173         unsigned int vec_start = finfo->vec_start;
 174         unsigned int vec_cnt = finfo->vec_cnt;
 175         struct feature_irq_ctx *ctx = NULL;
 176         int port_id, ret = 0;
 177         unsigned int i;
 178
 179         if (binfo->current_type == FME_ID) {
 180                 feature = &hw->fme.sub_feature[feature_idx];
 181                 feature->parent = &hw->fme;
 182         } else if (binfo->current_type == PORT_ID) {
 183                 port_id = binfo->current_port_id;
 184                 feature = &hw->port[port_id].sub_feature[feature_idx];
 185                 feature->parent = &hw->port[port_id];
 186         } else {
 187                 return -EFAULT;
 188         }
 189
 190         feature->state = IFPGA_FEATURE_ATTACHED;
 191         feature->addr = start;
 192         feature->id = feature_id(start);
 193         feature->size = finfo->resource_size;
 194         feature->name = finfo->name;
 195         feature->revision = finfo->revision_id;
 196         feature->ops = finfo->ops;
 197         feature->phys_addr = binfo->phys_addr +
 198                                 ((u8 *)start - (u8 *)binfo->ioaddr);
 199
 200         if (vec_cnt) {
 201                 if (vec_start + vec_cnt <= vec_start)
 202                         return -EINVAL;
 203
 204                 ctx = zmalloc(sizeof(*ctx) * vec_cnt);
 205                 if (!ctx)
 206                         return -ENOMEM;
 207
 208                 for (i = 0; i < vec_cnt; i++) {
 209                         ctx[i].eventfd = -1;
 210                         ctx[i].idx = vec_start + i;
 211                 }
 212         }
 213
 214         feature->ctx = ctx;
 215         feature->ctx_num = vec_cnt;
 216         feature->vfio_dev_fd = binfo->pci_data->vfio_dev_fd;
 217
 218         return ret;
 219 }
 220
 221 static int
 222 create_feature_instance(struct build_feature_devs_info *binfo,
 223                         void __iomem *start, struct feature_info *finfo)
 224 {
 225         struct feature_header *hdr = start;
 226
 227         if (finfo->revision_id != SKIP_REVISION_CHECK &&
 228             hdr->revision > finfo->revision_id) {
 229                 dev_err(binfo, "feature %s revision :default:%x, now at:%x, mis-match.\n",
 230                         finfo->name, finfo->revision_id, hdr->revision);
 231         }
 232
 233         return build_info_add_sub_feature(binfo, finfo, start);
 234 }
 235
 236 /*
 237  * UAFU GUID is dynamic as it can be changed after FME downloads different
 238  * Green Bitstream to the port, so we treat the unknown GUIDs which are
 239  * attached on port's feature list as UAFU.
 240  */
 241 static bool feature_is_UAFU(struct build_feature_devs_info *binfo)
 242 {
 243         if (binfo->current_type != PORT_ID)
 244                 return false;
 245
 246         return true;
 247 }
 248
 249 static int parse_feature_port_uafu(struct build_feature_devs_info *binfo,
 250                                    struct feature_header *hdr)
 251 {
 252         enum port_feature_id id = PORT_FEATURE_ID_UAFU;
 253         struct ifpga_afu_info *info;
 254         void *start = (void *)hdr;
 255         int ret;
 256
 257         if (port_features[id].resource_size) {
 258                 ret = create_feature_instance(binfo, hdr, &port_features[id]);
 259         } else {
 260                 dev_err(binfo, "the uafu feature header is mis-configured.\n");
 261                 ret = -EINVAL;
 262         }
 263
 264         if (ret)
 265                 return ret;
 266
 267         /* FIXME: need to figure out a better name */
 268         info = malloc(sizeof(*info));
 269         if (!info)
 270                 return -ENOMEM;
 271
 272         info->region[0].addr = start;
 273         info->region[0].phys_addr = binfo->phys_addr +
 274                         (uint8_t *)start - (uint8_t *)binfo->ioaddr;
 275         info->region[0].len = port_features[id].resource_size;
 276         port_features[id].resource_size = 0;
 277         info->num_regions = 1;
 278
 279         binfo->acc_info = info;
 280
 281         return ret;
 282 }
 283
 284 static int parse_feature_afus(struct build_feature_devs_info *binfo,
 285                               struct feature_header *hdr)
 286 {
 287         int ret;
 288         struct feature_afu_header *afu_hdr, header;
 289         u8 __iomem *start;
 290         u8 __iomem *end = binfo->ioend;
 291
 292         start = (u8 __iomem *)hdr;
 293         for (; start < end; start += header.next_afu) {
 294                 if ((unsigned int)(end - start) <
 295                         (unsigned int)(sizeof(*afu_hdr) + sizeof(*hdr)))
 296                         return -EINVAL;
 297
 298                 hdr = (struct feature_header *)start;
 299                 afu_hdr = (struct feature_afu_header *)(hdr + 1);
 300                 header.csr = readq(&afu_hdr->csr);
 301
 302                 if (feature_is_UAFU(binfo)) {
 303                         ret = parse_feature_port_uafu(binfo, hdr);
 304                         if (ret)
 305                                 return ret;
 306                 }
 307
 308                 if (!header.next_afu)
 309                         break;
 310         }
 311
 312         return 0;
 313 }
 314
 315 /* create and register proper private data */
 316 static int build_info_commit_dev(struct build_feature_devs_info *binfo)
 317 {
 318         struct ifpga_afu_info *info = binfo->acc_info;
 319         struct ifpga_hw *hw = binfo->hw;
 320         struct opae_manager *mgr;
 321         struct opae_bridge *br;
 322         struct opae_accelerator *acc;
 323
 324         if (!binfo->fiu)
 325                 return 0;
 326
 327         if (binfo->current_type == PORT_ID) {
 328                 /* return error if no valid acc info data structure */
 329                 if (!info)
 330                         return -EFAULT;
 331
 332                 br = opae_bridge_alloc(hw->adapter->name, &ifpga_br_ops,
 333                                        binfo->fiu);
 334                 if (!br)
 335                         return -ENOMEM;
 336
 337                 br->id = binfo->current_port_id;
 338
 339                 /* update irq info */
 340                 info->num_irqs = port_features[PORT_FEATURE_ID_UINT].vec_cnt;
 341
 342                 acc = opae_accelerator_alloc(hw->adapter->name,
 343                                              &ifpga_acc_ops, info);
 344                 if (!acc) {
 345                         opae_bridge_free(br);
 346                         return -ENOMEM;
 347                 }
 348
 349                 acc->br = br;
 350                 acc->index = br->id;
 351
 352                 opae_adapter_add_acc(hw->adapter, acc);
 353
 354         } else if (binfo->current_type == FME_ID) {
 355                 mgr = opae_manager_alloc(hw->adapter->name, &ifpga_mgr_ops,
 356                                          binfo->fiu);
 357                 if (!mgr)
 358                         return -ENOMEM;
 359
 360                 mgr->adapter = hw->adapter;
 361                 hw->adapter->mgr = mgr;
 362         }
 363
 364         binfo->fiu = NULL;
 365
 366         return 0;
 367 }
 368
 369 static int
 370 build_info_create_dev(struct build_feature_devs_info *binfo,
 371                       enum fpga_id_type type, unsigned int index)
 372 {
 373         int ret;
 374
 375         ret = build_info_commit_dev(binfo);
 376         if (ret)
 377                 return ret;
 378
 379         binfo->current_type = type;
 380
 381         if (type == FME_ID) {
 382                 binfo->fiu = &binfo->hw->fme;
 383         } else if (type == PORT_ID) {
 384                 binfo->fiu = &binfo->hw->port[index];
 385                 binfo->current_port_id = index;
 386         }
 387
 388         return 0;
 389 }
 390
 391 static int parse_feature_fme(struct build_feature_devs_info *binfo,
 392                              struct feature_header *start)
 393 {
 394         struct ifpga_hw *hw = binfo->hw;
 395         struct ifpga_fme_hw *fme = &hw->fme;
 396         int ret;
 397
 398         ret = build_info_create_dev(binfo, FME_ID, 0);
 399         if (ret)
 400                 return ret;
 401
 402         /* Update FME states */
 403         fme->state = IFPGA_FME_IMPLEMENTED;
 404         fme->parent = hw;
 405         spinlock_init(&fme->lock);
 406
 407         return create_feature_instance(binfo, start,
 408                                        &fme_features[FME_FEATURE_ID_HEADER]);
 409 }
 410
 411 static int parse_feature_port(struct build_feature_devs_info *binfo,
 412                               void __iomem *start)
 413 {
 414         struct feature_port_header *port_hdr;
 415         struct feature_port_capability capability;
 416         struct ifpga_hw *hw = binfo->hw;
 417         struct ifpga_port_hw *port;
 418         unsigned int port_id;
 419         int ret;
 420
 421         /* Get current port's id */
 422         port_hdr = (struct feature_port_header *)start;
 423         capability.csr = readq(&port_hdr->capability);
 424         port_id = capability.port_number;
 425
 426         ret = build_info_create_dev(binfo, PORT_ID, port_id);
 427         if (ret)
 428                 return ret;
 429
 430         /*found a Port device*/
 431         port = &hw->port[port_id];
 432         port->port_id = binfo->current_port_id;
 433         port->parent = hw;
 434         port->state = IFPGA_PORT_ATTACHED;
 435         spinlock_init(&port->lock);
 436
 437         return create_feature_instance(binfo, start,
 438                                       &port_features[PORT_FEATURE_ID_HEADER]);
 439 }
 440
 441 static void enable_port_uafu(struct build_feature_devs_info *binfo,
 442                              void __iomem *start)
 443 {
 444         enum port_feature_id id = PORT_FEATURE_ID_UAFU;
 445         struct feature_port_header *port_hdr;
 446         struct feature_port_capability capability;
 447         struct ifpga_port_hw *port = &binfo->hw->port[binfo->current_port_id];
 448
 449         port_hdr = (struct feature_port_header *)start;
 450         capability.csr = readq(&port_hdr->capability);
 451         port_features[id].resource_size = (capability.mmio_size << 10);
 452
 453         /*
 454          * From spec, to Enable UAFU, we should reset related port,
 455          * or the whole mmio space in this UAFU will be invalid
 456          */
 457         if (port_features[id].resource_size)
 458                 fpga_port_reset(port);
 459 }
 460
 461 static int parse_feature_fiu(struct build_feature_devs_info *binfo,
 462                              struct feature_header *hdr)
 463 {
 464         struct feature_header header;
 465         struct feature_fiu_header *fiu_hdr, fiu_header;
 466         u8 __iomem *start = (u8 __iomem *)hdr;
 467         int ret;
 468
 469         header.csr = readq(hdr);
 470
 471         switch (header.id) {
 472         case FEATURE_FIU_ID_FME:
 473                 ret = parse_feature_fme(binfo, hdr);
 474                 binfo->pfme_hdr = hdr;
 475                 if (ret)
 476                         return ret;
 477                 break;
 478         case FEATURE_FIU_ID_PORT:
 479                 ret = parse_feature_port(binfo, hdr);
 480                 enable_port_uafu(binfo, hdr);
 481                 if (ret)
 482                         return ret;
 483
 484                 /* Check Port FIU's next_afu pointer to User AFU DFH */
 485                 fiu_hdr = (struct feature_fiu_header *)(hdr + 1);
 486                 fiu_header.csr = readq(&fiu_hdr->csr);
 487
 488                 if (fiu_header.next_afu) {
 489                         start += fiu_header.next_afu;
 490                         ret = parse_feature_afus(binfo,
 491                                                 (struct feature_header *)start);
 492                         if (ret)
 493                                 return ret;
 494                 } else {
 495                         dev_info(binfo, "No AFUs detected on Port\n");
 496                 }
 497
 498                 break;
 499         default:
 500                 dev_info(binfo, "FIU TYPE %d is not supported yet.\n",
 501                          header.id);
 502         }
 503
 504         return 0;
 505 }
 506
 507 static void parse_feature_irqs(struct build_feature_devs_info *binfo,
 508                                void __iomem *start, struct feature_info *finfo)
 509 {
 510         finfo->vec_start = 0;
 511         finfo->vec_cnt = 0;
 512
 513         UNUSED(binfo);
 514
 515         if (!strcmp(finfo->name, PORT_FEATURE_UINT)) {
 516                 struct feature_port_uint *port_uint = start;
 517                 struct feature_port_uint_cap uint_cap;
 518
 519                 uint_cap.csr = readq(&port_uint->capability);
 520                 if (uint_cap.intr_num) {
 521                         finfo->vec_start = uint_cap.first_vec_num;
 522                         finfo->vec_cnt = uint_cap.intr_num;
 523                 } else {
 524                         dev_debug(binfo, "UAFU doesn't support interrupt\n");
 525                 }
 526         } else if (!strcmp(finfo->name, PORT_FEATURE_ERR)) {
 527                 struct feature_port_error *port_err = start;
 528                 struct feature_port_err_capability port_err_cap;
 529
 530                 port_err_cap.csr = readq(&port_err->error_capability);
 531                 if (port_err_cap.support_intr) {
 532                         finfo->vec_start = port_err_cap.intr_vector_num;
 533                         finfo->vec_cnt = 1;
 534                 } else {
 535                         dev_debug(&binfo, "Port error doesn't support interrupt\n");
 536                 }
 537
 538         } else if (!strcmp(finfo->name, FME_FEATURE_GLOBAL_ERR)) {
 539                 struct feature_fme_err *fme_err = start;
 540                 struct feature_fme_error_capability fme_err_cap;
 541
 542                 fme_err_cap.csr = readq(&fme_err->fme_err_capability);
 543                 if (fme_err_cap.support_intr) {
 544                         finfo->vec_start = fme_err_cap.intr_vector_num;
 545                         finfo->vec_cnt = 1;
 546                 } else {
 547                         dev_debug(&binfo, "FME error doesn't support interrupt\n");
 548                 }
 549         }
 550 }
 551
 552 static int parse_feature_fme_private(struct build_feature_devs_info *binfo,
 553                                      struct feature_header *hdr)
 554 {
 555         struct feature_header header;
 556
 557         header.csr = readq(hdr);
 558
 559         if (header.id >= ARRAY_SIZE(fme_features)) {
 560                 dev_err(binfo, "FME feature id %x is not supported yet.\n",
 561                         header.id);
 562                 return 0;
 563         }
 564
 565         parse_feature_irqs(binfo, hdr, &fme_features[header.id]);
 566
 567         return create_feature_instance(binfo, hdr, &fme_features[header.id]);
 568 }
 569
 570 static int parse_feature_port_private(struct build_feature_devs_info *binfo,
 571                                       struct feature_header *hdr)
 572 {
 573         struct feature_header header;
 574         enum port_feature_id id;
 575
 576         header.csr = readq(hdr);
 577         /*
 578          * the region of port feature id is [0x10, 0x13], + 1 to reserve 0
 579          * which is dedicated for port-hdr.
 580          */
 581         id = (header.id & 0x000f) + 1;
 582
 583         if (id >= ARRAY_SIZE(port_features)) {
 584                 dev_err(binfo, "Port feature id %x is not supported yet.\n",
 585                         header.id);
 586                 return 0;
 587         }
 588
 589         parse_feature_irqs(binfo, hdr, &port_features[id]);
 590
 591         return create_feature_instance(binfo, hdr, &port_features[id]);
 592 }
 593
 594 static int parse_feature_private(struct build_feature_devs_info *binfo,
 595                                  struct feature_header *hdr)
 596 {
 597         struct feature_header header;
 598
 599         header.csr = readq(hdr);
 600
 601         switch (binfo->current_type) {
 602         case FME_ID:
 603                 return parse_feature_fme_private(binfo, hdr);
 604         case PORT_ID:
 605                 return parse_feature_port_private(binfo, hdr);
 606         default:
 607                 dev_err(binfo, "private feature %x belonging to AFU %d (unknown_type) is not supported yet.\n",
 608                         header.id, binfo->current_type);
 609         }
 610         return 0;
 611 }
 612
 613 static int parse_feature(struct build_feature_devs_info *binfo,
 614                          struct feature_header *hdr)
 615 {
 616         struct feature_header header;
 617         int ret = 0;
 618
 619         header.csr = readq(hdr);
 620
 621         switch (header.type) {
 622         case FEATURE_TYPE_AFU:
 623                 ret = parse_feature_afus(binfo, hdr);
 624                 break;
 625         case FEATURE_TYPE_PRIVATE:
 626                 ret = parse_feature_private(binfo, hdr);
 627                 break;
 628         case FEATURE_TYPE_FIU:
 629                 ret = parse_feature_fiu(binfo, hdr);
 630                 break;
 631         default:
 632                 dev_err(binfo, "Feature Type %x is not supported.\n",
 633                         hdr->type);
 634         };
 635
 636         return ret;
 637 }
 638
 639 static int
 640 parse_feature_list(struct build_feature_devs_info *binfo, u8 __iomem *start)
 641 {
 642         struct feature_header *hdr, header;
 643         u8 __iomem *end = (u8 __iomem *)binfo->ioend;
 644         int ret = 0;
 645
 646         for (; start < end; start += header.next_header_offset) {
 647                 if ((unsigned int)(end - start) < (unsigned int)sizeof(*hdr)) {
 648                         dev_err(binfo, "The region is too small to contain a feature.\n");
 649                         ret =  -EINVAL;
 650                         break;
 651                 }
 652
 653                 hdr = (struct feature_header *)start;
 654                 ret = parse_feature(binfo, hdr);
 655                 if (ret)
 656                         return ret;
 657
 658                 header.csr = readq(hdr);
 659                 if (!header.next_header_offset)
 660                         break;
 661         }
 662
 663         return build_info_commit_dev(binfo);
 664 }
 665
 666 /* switch the memory mapping to BAR# @bar */
 667 static int parse_switch_to(struct build_feature_devs_info *binfo, int bar)
 668 {
 669         struct opae_adapter_data_pci *pci_data = binfo->pci_data;
 670
 671         if (!pci_data->region[bar].addr)
 672                 return -ENOMEM;
 673
 674         binfo->ioaddr = pci_data->region[bar].addr;
 675         binfo->ioend = (u8 __iomem *)binfo->ioaddr + pci_data->region[bar].len;
 676         binfo->phys_addr = pci_data->region[bar].phys_addr;
 677         binfo->current_bar = bar;
 678
 679         return 0;
 680 }
 681
 682 static int parse_ports_from_fme(struct build_feature_devs_info *binfo)
 683 {
 684         struct feature_fme_header *fme_hdr;
 685         struct feature_fme_port port;
 686         int i = 0, ret = 0;
 687
 688         if (!binfo->pfme_hdr) {
 689                 dev_info(binfo,  "VF is detected.\n");
 690                 return ret;
 691         }
 692
 693         fme_hdr = binfo->pfme_hdr;
 694
 695         do {
 696                 port.csr = readq(&fme_hdr->port[i]);
 697                 if (!port.port_implemented)
 698                         break;
 699
 700                 /* skip port which only could be accessed via VF */
 701                 if (port.afu_access_control == FME_AFU_ACCESS_VF)
 702                         continue;
 703
 704                 ret = parse_switch_to(binfo, port.port_bar);
 705                 if (ret)
 706                         break;
 707
 708                 ret = parse_feature_list(binfo,
 709                                          (u8 __iomem *)binfo->ioaddr +
 710                                           port.port_offset);
 711                 if (ret)
 712                         break;
 713         } while (++i < MAX_FPGA_PORT_NUM);
 714
 715         return ret;
 716 }
 717
 718 static struct build_feature_devs_info *
 719 build_info_alloc_and_init(struct ifpga_hw *hw)
 720 {
 721         struct build_feature_devs_info *binfo;
 722
 723         binfo = zmalloc(sizeof(*binfo));
 724         if (!binfo)
 725                 return binfo;
 726
 727         binfo->hw = hw;
 728         binfo->pci_data = hw->pci_data;
 729
 730         /* fpga feature list starts from BAR 0 */
 731         if (parse_switch_to(binfo, 0)) {
 732                 free(binfo);
 733                 return NULL;
 734         }
 735
 736         return binfo;
 737 }
 738
 739 static void build_info_free(struct build_feature_devs_info *binfo)
 740 {
 741         free(binfo);
 742 }
 743
 744 static void ifpga_print_device_feature_list(struct ifpga_hw *hw)
 745 {
 746         struct ifpga_fme_hw *fme = &hw->fme;
 747         struct ifpga_port_hw *port;
 748         struct feature *feature;
 749         int i, j;
 750
 751         dev_info(hw, "found fme_device, is in PF: %s\n",
 752                  is_ifpga_hw_pf(hw) ? "yes" : "no");
 753
 754         for (i = 0; i < FME_FEATURE_ID_MAX; i++) {
 755                 feature = &fme->sub_feature[i];
 756                 if (feature->state != IFPGA_FEATURE_ATTACHED)
 757                         continue;
 758
 759                 dev_info(hw, "%12s:     0x%p - 0x%p  - paddr: 0x%lx\n",
 760                          feature->name, feature->addr,
 761                          feature->addr + feature->size - 1,
 762                          (unsigned long)feature->phys_addr);
 763         }
 764
 765         for (i = 0; i < MAX_FPGA_PORT_NUM; i++) {
 766                 port = &hw->port[i];
 767
 768                 if (port->state != IFPGA_PORT_ATTACHED)
 769                         continue;
 770
 771                 dev_info(hw, "port device: %d\n", port->port_id);
 772
 773                 for (j = 0; j < PORT_FEATURE_ID_MAX; j++) {
 774                         feature = &port->sub_feature[j];
 775                         if (feature->state != IFPGA_FEATURE_ATTACHED)
 776                                 continue;
 777
 778                         dev_info(hw, "%12s:     0x%p - 0x%p  - paddr:0x%lx\n",
 779                                  feature->name,
 780                                  feature->addr,
 781                                  feature->addr +
 782                                  feature->size - 1,
 783                                  (unsigned long)feature->phys_addr);
 784                 }
 785         }
 786 }
 787
 788 int ifpga_bus_enumerate(struct ifpga_hw *hw)
 789 {
 790         struct build_feature_devs_info *binfo;
 791         int ret;
 792
 793         binfo = build_info_alloc_and_init(hw);
 794         if (!binfo)
 795                 return -ENOMEM;
 796
 797         ret = parse_feature_list(binfo, binfo->ioaddr);
 798         if (ret)
 799                 goto exit;
 800
 801         ret = parse_ports_from_fme(binfo);
 802         if (ret)
 803                 goto exit;
 804
 805         ifpga_print_device_feature_list(hw);
 806
 807 exit:
 808         build_info_free(binfo);
 809         return ret;
 810 }
 811
 812 int ifpga_bus_init(struct ifpga_hw *hw)
 813 {
 814         int i;
 815
 816         fme_hw_init(&hw->fme);
 817         for (i = 0; i < MAX_FPGA_PORT_NUM; i++)
 818                 port_hw_init(&hw->port[i]);
 819
 820         return 0;
 821 }