examples/eventdev_pipeline_sw_pmd/main.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2016-2017 Intel Corporation. All rights reserved.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Intel Corporation nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <getopt.h>
  34 #include <stdint.h>
  35 #include <stdio.h>
  36 #include <signal.h>
  37 #include <sched.h>
  38 #include <stdbool.h>
  39
  40 #include <rte_eal.h>
  41 #include <rte_mempool.h>
  42 #include <rte_mbuf.h>
  43 #include <rte_launch.h>
  44 #include <rte_malloc.h>
  45 #include <rte_random.h>
  46 #include <rte_cycles.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_eventdev.h>
  49
  50 #define MAX_NUM_STAGES 8
  51 #define BATCH_SIZE 16
  52 #define MAX_NUM_CORE 64
  53
  54 struct prod_data {
  55         uint8_t dev_id;
  56         uint8_t port_id;
  57         int32_t qid;
  58         unsigned int num_nic_ports;
  59 } __rte_cache_aligned;
  60
  61 struct cons_data {
  62         uint8_t dev_id;
  63         uint8_t port_id;
  64 } __rte_cache_aligned;
  65
  66 static struct prod_data prod_data;
  67 static struct cons_data cons_data;
  68
  69 struct worker_data {
  70         uint8_t dev_id;
  71         uint8_t port_id;
  72 } __rte_cache_aligned;
  73
  74 struct fastpath_data {
  75         volatile int done;
  76         uint32_t rx_lock;
  77         uint32_t tx_lock;
  78         uint32_t sched_lock;
  79         bool rx_single;
  80         bool tx_single;
  81         bool sched_single;
  82         unsigned int rx_core[MAX_NUM_CORE];
  83         unsigned int tx_core[MAX_NUM_CORE];
  84         unsigned int sched_core[MAX_NUM_CORE];
  85         unsigned int worker_core[MAX_NUM_CORE];
  86         struct rte_eth_dev_tx_buffer *tx_buf[RTE_MAX_ETHPORTS];
  87 };
  88
  89 static struct fastpath_data *fdata;
  90
  91 struct config_data {
  92         unsigned int active_cores;
  93         unsigned int num_workers;
  94         int64_t num_packets;
  95         unsigned int num_fids;
  96         int queue_type;
  97         int worker_cycles;
  98         int enable_queue_priorities;
  99         int quiet;
 100         int dump_dev;
 101         int dump_dev_signal;
 102         unsigned int num_stages;
 103         unsigned int worker_cq_depth;
 104         int16_t next_qid[MAX_NUM_STAGES+2];
 105         int16_t qid[MAX_NUM_STAGES];
 106 };
 107
 108 static struct config_data cdata = {
 109         .num_packets = (1L << 25), /* do ~32M packets */
 110         .num_fids = 512,
 111         .queue_type = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY,
 112         .next_qid = {-1},
 113         .qid = {-1},
 114         .num_stages = 1,
 115         .worker_cq_depth = 16
 116 };
 117
 118 static bool
 119 core_in_use(unsigned int lcore_id) {
 120         return (fdata->rx_core[lcore_id] || fdata->sched_core[lcore_id] ||
 121                 fdata->tx_core[lcore_id] || fdata->worker_core[lcore_id]);
 122 }
 123
 124 static void
 125 eth_tx_buffer_retry(struct rte_mbuf **pkts, uint16_t unsent,
 126                         void *userdata)
 127 {
 128         int port_id = (uintptr_t) userdata;
 129         unsigned int _sent = 0;
 130
 131         do {
 132                 /* Note: hard-coded TX queue */
 133                 _sent += rte_eth_tx_burst(port_id, 0, &pkts[_sent],
 134                                           unsent - _sent);
 135         } while (_sent != unsent);
 136 }
 137
 138 static int
 139 consumer(void)
 140 {
 141         const uint64_t freq_khz = rte_get_timer_hz() / 1000;
 142         struct rte_event packets[BATCH_SIZE];
 143
 144         static uint64_t received;
 145         static uint64_t last_pkts;
 146         static uint64_t last_time;
 147         static uint64_t start_time;
 148         unsigned int i, j;
 149         uint8_t dev_id = cons_data.dev_id;
 150         uint8_t port_id = cons_data.port_id;
 151
 152         uint16_t n = rte_event_dequeue_burst(dev_id, port_id,
 153                         packets, RTE_DIM(packets), 0);
 154
 155         if (n == 0) {
 156                 for (j = 0; j < rte_eth_dev_count(); j++)
 157                         rte_eth_tx_buffer_flush(j, 0, fdata->tx_buf[j]);
 158                 return 0;
 159         }
 160         if (start_time == 0)
 161                 last_time = start_time = rte_get_timer_cycles();
 162
 163         received += n;
 164         for (i = 0; i < n; i++) {
 165                 uint8_t outport = packets[i].mbuf->port;
 166                 rte_eth_tx_buffer(outport, 0, fdata->tx_buf[outport],
 167                                 packets[i].mbuf);
 168         }
 169
 170         /* Print out mpps every 1<22 packets */
 171         if (!cdata.quiet && received >= last_pkts + (1<<22)) {
 172                 const uint64_t now = rte_get_timer_cycles();
 173                 const uint64_t total_ms = (now - start_time) / freq_khz;
 174                 const uint64_t delta_ms = (now - last_time) / freq_khz;
 175                 uint64_t delta_pkts = received - last_pkts;
 176
 177                 printf("# consumer RX=%"PRIu64", time %"PRIu64 "ms, "
 178                         "avg %.3f mpps [current %.3f mpps]\n",
 179                                 received,
 180                                 total_ms,
 181                                 received / (total_ms * 1000.0),
 182                                 delta_pkts / (delta_ms * 1000.0));
 183                 last_pkts = received;
 184                 last_time = now;
 185         }
 186
 187         cdata.num_packets -= n;
 188         if (cdata.num_packets <= 0)
 189                 fdata->done = 1;
 190
 191         return 0;
 192 }
 193
 194 static int
 195 producer(void)
 196 {
 197         static uint8_t eth_port;
 198         struct rte_mbuf *mbufs[BATCH_SIZE+2];
 199         struct rte_event ev[BATCH_SIZE+2];
 200         uint32_t i, num_ports = prod_data.num_nic_ports;
 201         int32_t qid = prod_data.qid;
 202         uint8_t dev_id = prod_data.dev_id;
 203         uint8_t port_id = prod_data.port_id;
 204         uint32_t prio_idx = 0;
 205
 206         const uint16_t nb_rx = rte_eth_rx_burst(eth_port, 0, mbufs, BATCH_SIZE);
 207         if (++eth_port == num_ports)
 208                 eth_port = 0;
 209         if (nb_rx == 0) {
 210                 rte_pause();
 211                 return 0;
 212         }
 213
 214         for (i = 0; i < nb_rx; i++) {
 215                 ev[i].flow_id = mbufs[i]->hash.rss;
 216                 ev[i].op = RTE_EVENT_OP_NEW;
 217                 ev[i].sched_type = cdata.queue_type;
 218                 ev[i].queue_id = qid;
 219                 ev[i].event_type = RTE_EVENT_TYPE_ETHDEV;
 220                 ev[i].sub_event_type = 0;
 221                 ev[i].priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
 222                 ev[i].mbuf = mbufs[i];
 223                 RTE_SET_USED(prio_idx);
 224         }
 225
 226         const int nb_tx = rte_event_enqueue_burst(dev_id, port_id, ev, nb_rx);
 227         if (nb_tx != nb_rx) {
 228                 for (i = nb_tx; i < nb_rx; i++)
 229                         rte_pktmbuf_free(mbufs[i]);
 230         }
 231
 232         return 0;
 233 }
 234
 235 static inline void
 236 schedule_devices(uint8_t dev_id, unsigned int lcore_id)
 237 {
 238         if (fdata->rx_core[lcore_id] && (fdata->rx_single ||
 239             rte_atomic32_cmpset(&(fdata->rx_lock), 0, 1))) {
 240                 producer();
 241                 rte_atomic32_clear((rte_atomic32_t *)&(fdata->rx_lock));
 242         }
 243
 244         if (fdata->sched_core[lcore_id] && (fdata->sched_single ||
 245             rte_atomic32_cmpset(&(fdata->sched_lock), 0, 1))) {
 246                 rte_event_schedule(dev_id);
 247                 if (cdata.dump_dev_signal) {
 248                         rte_event_dev_dump(0, stdout);
 249                         cdata.dump_dev_signal = 0;
 250                 }
 251                 rte_atomic32_clear((rte_atomic32_t *)&(fdata->sched_lock));
 252         }
 253
 254         if (fdata->tx_core[lcore_id] && (fdata->tx_single ||
 255             rte_atomic32_cmpset(&(fdata->tx_lock), 0, 1))) {
 256                 consumer();
 257                 rte_atomic32_clear((rte_atomic32_t *)&(fdata->tx_lock));
 258         }
 259 }
 260
 261 static inline void
 262 work(struct rte_mbuf *m)
 263 {
 264         struct ether_hdr *eth;
 265         struct ether_addr addr;
 266
 267         /* change mac addresses on packet (to use mbuf data) */
 268         /*
 269          * FIXME Swap mac address properly and also handle the
 270          * case for both odd and even number of stages that the
 271          * addresses end up the same at the end of the pipeline
 272          */
 273         eth = rte_pktmbuf_mtod(m, struct ether_hdr *);
 274         ether_addr_copy(&eth->d_addr, &addr);
 275         ether_addr_copy(&addr, &eth->d_addr);
 276
 277         /* do a number of cycles of work per packet */
 278         volatile uint64_t start_tsc = rte_rdtsc();
 279         while (rte_rdtsc() < start_tsc + cdata.worker_cycles)
 280                 rte_pause();
 281 }
 282
 283 static int
 284 worker(void *arg)
 285 {
 286         struct rte_event events[BATCH_SIZE];
 287
 288         struct worker_data *data = (struct worker_data *)arg;
 289         uint8_t dev_id = data->dev_id;
 290         uint8_t port_id = data->port_id;
 291         size_t sent = 0, received = 0;
 292         unsigned int lcore_id = rte_lcore_id();
 293
 294         while (!fdata->done) {
 295                 uint16_t i;
 296
 297                 schedule_devices(dev_id, lcore_id);
 298
 299                 if (!fdata->worker_core[lcore_id]) {
 300                         rte_pause();
 301                         continue;
 302                 }
 303
 304                 const uint16_t nb_rx = rte_event_dequeue_burst(dev_id, port_id,
 305                                 events, RTE_DIM(events), 0);
 306
 307                 if (nb_rx == 0) {
 308                         rte_pause();
 309                         continue;
 310                 }
 311                 received += nb_rx;
 312
 313                 for (i = 0; i < nb_rx; i++) {
 314
 315                         /* The first worker stage does classification */
 316                         if (events[i].queue_id == cdata.qid[0])
 317                                 events[i].flow_id = events[i].mbuf->hash.rss
 318                                                         % cdata.num_fids;
 319
 320                         events[i].queue_id = cdata.next_qid[events[i].queue_id];
 321                         events[i].op = RTE_EVENT_OP_FORWARD;
 322                         events[i].sched_type = cdata.queue_type;
 323
 324                         work(events[i].mbuf);
 325                 }
 326                 uint16_t nb_tx = rte_event_enqueue_burst(dev_id, port_id,
 327                                 events, nb_rx);
 328                 while (nb_tx < nb_rx && !fdata->done)
 329                         nb_tx += rte_event_enqueue_burst(dev_id, port_id,
 330                                                         events + nb_tx,
 331                                                         nb_rx - nb_tx);
 332                 sent += nb_tx;
 333         }
 334
 335         if (!cdata.quiet)
 336                 printf("  worker %u thread done. RX=%zu TX=%zu\n",
 337                                 rte_lcore_id(), received, sent);
 338
 339         return 0;
 340 }
 341
 342 /*
 343  * Parse the coremask given as argument (hexadecimal string) and fill
 344  * the global configuration (core role and core count) with the parsed
 345  * value.
 346  */
 347 static int xdigit2val(unsigned char c)
 348 {
 349         int val;
 350
 351         if (isdigit(c))
 352                 val = c - '0';
 353         else if (isupper(c))
 354                 val = c - 'A' + 10;
 355         else
 356                 val = c - 'a' + 10;
 357         return val;
 358 }
 359
 360 static uint64_t
 361 parse_coremask(const char *coremask)
 362 {
 363         int i, j, idx = 0;
 364         unsigned int count = 0;
 365         char c;
 366         int val;
 367         uint64_t mask = 0;
 368         const int32_t BITS_HEX = 4;
 369
 370         if (coremask == NULL)
 371                 return -1;
 372         /* Remove all blank characters ahead and after .
 373          * Remove 0x/0X if exists.
 374          */
 375         while (isblank(*coremask))
 376                 coremask++;
 377         if (coremask[0] == '0' && ((coremask[1] == 'x')
 378                 || (coremask[1] == 'X')))
 379                 coremask += 2;
 380         i = strlen(coremask);
 381         while ((i > 0) && isblank(coremask[i - 1]))
 382                 i--;
 383         if (i == 0)
 384                 return -1;
 385
 386         for (i = i - 1; i >= 0 && idx < MAX_NUM_CORE; i--) {
 387                 c = coremask[i];
 388                 if (isxdigit(c) == 0) {
 389                         /* invalid characters */
 390                         return -1;
 391                 }
 392                 val = xdigit2val(c);
 393                 for (j = 0; j < BITS_HEX && idx < MAX_NUM_CORE; j++, idx++) {
 394                         if ((1 << j) & val) {
 395                                 mask |= (1UL << idx);
 396                                 count++;
 397                         }
 398                 }
 399         }
 400         for (; i >= 0; i--)
 401                 if (coremask[i] != '0')
 402                         return -1;
 403         if (count == 0)
 404                 return -1;
 405         return mask;
 406 }
 407
 408 static struct option long_options[] = {
 409         {"workers", required_argument, 0, 'w'},
 410         {"packets", required_argument, 0, 'n'},
 411         {"atomic-flows", required_argument, 0, 'f'},
 412         {"num_stages", required_argument, 0, 's'},
 413         {"rx-mask", required_argument, 0, 'r'},
 414         {"tx-mask", required_argument, 0, 't'},
 415         {"sched-mask", required_argument, 0, 'e'},
 416         {"cq-depth", required_argument, 0, 'c'},
 417         {"work-cycles", required_argument, 0, 'W'},
 418         {"queue-priority", no_argument, 0, 'P'},
 419         {"parallel", no_argument, 0, 'p'},
 420         {"ordered", no_argument, 0, 'o'},
 421         {"quiet", no_argument, 0, 'q'},
 422         {"dump", no_argument, 0, 'D'},
 423         {0, 0, 0, 0}
 424 };
 425
 426 static void
 427 usage(void)
 428 {
 429         const char *usage_str =
 430                 "  Usage: eventdev_demo [options]\n"
 431                 "  Options:\n"
 432                 "  -n, --packets=N              Send N packets (default ~32M), 0 implies no limit\n"
 433                 "  -f, --atomic-flows=N         Use N random flows from 1 to N (default 16)\n"
 434                 "  -s, --num_stages=N           Use N atomic stages (default 1)\n"
 435                 "  -r, --rx-mask=core mask      Run NIC rx on CPUs in core mask\n"
 436                 "  -w, --worker-mask=core mask  Run worker on CPUs in core mask\n"
 437                 "  -t, --tx-mask=core mask      Run NIC tx on CPUs in core mask\n"
 438                 "  -e  --sched-mask=core mask   Run scheduler on CPUs in core mask\n"
 439                 "  -c  --cq-depth=N             Worker CQ depth (default 16)\n"
 440                 "  -W  --work-cycles=N          Worker cycles (default 0)\n"
 441                 "  -P  --queue-priority         Enable scheduler queue prioritization\n"
 442                 "  -o, --ordered                Use ordered scheduling\n"
 443                 "  -p, --parallel               Use parallel scheduling\n"
 444                 "  -q, --quiet                  Minimize printed output\n"
 445                 "  -D, --dump                   Print detailed statistics before exit"
 446                 "\n";
 447         fprintf(stderr, "%s", usage_str);
 448         exit(1);
 449 }
 450
 451 static void
 452 parse_app_args(int argc, char **argv)
 453 {
 454         /* Parse cli options*/
 455         int option_index;
 456         int c;
 457         opterr = 0;
 458         uint64_t rx_lcore_mask = 0;
 459         uint64_t tx_lcore_mask = 0;
 460         uint64_t sched_lcore_mask = 0;
 461         uint64_t worker_lcore_mask = 0;
 462         int i;
 463
 464         for (;;) {
 465                 c = getopt_long(argc, argv, "r:t:e:c:w:n:f:s:poPqDW:",
 466                                 long_options, &option_index);
 467                 if (c == -1)
 468                         break;
 469
 470                 int popcnt = 0;
 471                 switch (c) {
 472                 case 'n':
 473                         cdata.num_packets = (int64_t)atol(optarg);
 474                         if (cdata.num_packets == 0)
 475                                 cdata.num_packets = INT64_MAX;
 476                         break;
 477                 case 'f':
 478                         cdata.num_fids = (unsigned int)atoi(optarg);
 479                         break;
 480                 case 's':
 481                         cdata.num_stages = (unsigned int)atoi(optarg);
 482                         break;
 483                 case 'c':
 484                         cdata.worker_cq_depth = (unsigned int)atoi(optarg);
 485                         break;
 486                 case 'W':
 487                         cdata.worker_cycles = (unsigned int)atoi(optarg);
 488                         break;
 489                 case 'P':
 490                         cdata.enable_queue_priorities = 1;
 491                         break;
 492                 case 'o':
 493                         cdata.queue_type = RTE_EVENT_QUEUE_CFG_ORDERED_ONLY;
 494                         break;
 495                 case 'p':
 496                         cdata.queue_type = RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY;
 497                         break;
 498                 case 'q':
 499                         cdata.quiet = 1;
 500                         break;
 501                 case 'D':
 502                         cdata.dump_dev = 1;
 503                         break;
 504                 case 'w':
 505                         worker_lcore_mask = parse_coremask(optarg);
 506                         break;
 507                 case 'r':
 508                         rx_lcore_mask = parse_coremask(optarg);
 509                         popcnt = __builtin_popcountll(rx_lcore_mask);
 510                         fdata->rx_single = (popcnt == 1);
 511                         break;
 512                 case 't':
 513                         tx_lcore_mask = parse_coremask(optarg);
 514                         popcnt = __builtin_popcountll(tx_lcore_mask);
 515                         fdata->tx_single = (popcnt == 1);
 516                         break;
 517                 case 'e':
 518                         sched_lcore_mask = parse_coremask(optarg);
 519                         popcnt = __builtin_popcountll(sched_lcore_mask);
 520                         fdata->sched_single = (popcnt == 1);
 521                         break;
 522                 default:
 523                         usage();
 524                 }
 525         }
 526
 527         if (worker_lcore_mask == 0 || rx_lcore_mask == 0 ||
 528             sched_lcore_mask == 0 || tx_lcore_mask == 0) {
 529                 printf("Core part of pipeline was not assigned any cores. "
 530                         "This will stall the pipeline, please check core masks "
 531                         "(use -h for details on setting core masks):\n"
 532                         "\trx: %"PRIu64"\n\ttx: %"PRIu64"\n\tsched: %"PRIu64
 533                         "\n\tworkers: %"PRIu64"\n",
 534                         rx_lcore_mask, tx_lcore_mask, sched_lcore_mask,
 535                         worker_lcore_mask);
 536                 rte_exit(-1, "Fix core masks\n");
 537         }
 538         if (cdata.num_stages == 0 || cdata.num_stages > MAX_NUM_STAGES)
 539                 usage();
 540
 541         for (i = 0; i < MAX_NUM_CORE; i++) {
 542                 fdata->rx_core[i] = !!(rx_lcore_mask & (1UL << i));
 543                 fdata->tx_core[i] = !!(tx_lcore_mask & (1UL << i));
 544                 fdata->sched_core[i] = !!(sched_lcore_mask & (1UL << i));
 545                 fdata->worker_core[i] = !!(worker_lcore_mask & (1UL << i));
 546
 547                 if (fdata->worker_core[i])
 548                         cdata.num_workers++;
 549                 if (core_in_use(i))
 550                         cdata.active_cores++;
 551         }
 552 }
 553
 554 /*
 555  * Initializes a given port using global settings and with the RX buffers
 556  * coming from the mbuf_pool passed as a parameter.
 557  */
 558 static inline int
 559 port_init(uint8_t port, struct rte_mempool *mbuf_pool)
 560 {
 561         static const struct rte_eth_conf port_conf_default = {
 562                 .rxmode = {
 563                         .mq_mode = ETH_MQ_RX_RSS,
 564                         .max_rx_pkt_len = ETHER_MAX_LEN
 565                 },
 566                 .rx_adv_conf = {
 567                         .rss_conf = {
 568                                 .rss_hf = ETH_RSS_IP |
 569                                           ETH_RSS_TCP |
 570                                           ETH_RSS_UDP,
 571                         }
 572                 }
 573         };
 574         const uint16_t rx_rings = 1, tx_rings = 1;
 575         const uint16_t rx_ring_size = 512, tx_ring_size = 512;
 576         struct rte_eth_conf port_conf = port_conf_default;
 577         int retval;
 578         uint16_t q;
 579
 580         if (port >= rte_eth_dev_count())
 581                 return -1;
 582
 583         /* Configure the Ethernet device. */
 584         retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);
 585         if (retval != 0)
 586                 return retval;
 587
 588         /* Allocate and set up 1 RX queue per Ethernet port. */
 589         for (q = 0; q < rx_rings; q++) {
 590                 retval = rte_eth_rx_queue_setup(port, q, rx_ring_size,
 591                                 rte_eth_dev_socket_id(port), NULL, mbuf_pool);
 592                 if (retval < 0)
 593                         return retval;
 594         }
 595
 596         /* Allocate and set up 1 TX queue per Ethernet port. */
 597         for (q = 0; q < tx_rings; q++) {
 598                 retval = rte_eth_tx_queue_setup(port, q, tx_ring_size,
 599                                 rte_eth_dev_socket_id(port), NULL);
 600                 if (retval < 0)
 601                         return retval;
 602         }
 603
 604         /* Start the Ethernet port. */
 605         retval = rte_eth_dev_start(port);
 606         if (retval < 0)
 607                 return retval;
 608
 609         /* Display the port MAC address. */
 610         struct ether_addr addr;
 611         rte_eth_macaddr_get(port, &addr);
 612         printf("Port %u MAC: %02" PRIx8 " %02" PRIx8 " %02" PRIx8
 613                            " %02" PRIx8 " %02" PRIx8 " %02" PRIx8 "\n",
 614                         (unsigned int)port,
 615                         addr.addr_bytes[0], addr.addr_bytes[1],
 616                         addr.addr_bytes[2], addr.addr_bytes[3],
 617                         addr.addr_bytes[4], addr.addr_bytes[5]);
 618
 619         /* Enable RX in promiscuous mode for the Ethernet device. */
 620         rte_eth_promiscuous_enable(port);
 621
 622         return 0;
 623 }
 624
 625 static int
 626 init_ports(unsigned int num_ports)
 627 {
 628         uint8_t portid;
 629         unsigned int i;
 630
 631         struct rte_mempool *mp = rte_pktmbuf_pool_create("packet_pool",
 632                         /* mbufs */ 16384 * num_ports,
 633                         /* cache_size */ 512,
 634                         /* priv_size*/ 0,
 635                         /* data_room_size */ RTE_MBUF_DEFAULT_BUF_SIZE,
 636                         rte_socket_id());
 637
 638         for (portid = 0; portid < num_ports; portid++)
 639                 if (port_init(portid, mp) != 0)
 640                         rte_exit(EXIT_FAILURE, "Cannot init port %"PRIu8 "\n",
 641                                         portid);
 642
 643         for (i = 0; i < num_ports; i++) {
 644                 void *userdata = (void *)(uintptr_t) i;
 645                 fdata->tx_buf[i] =
 646                         rte_malloc(NULL, RTE_ETH_TX_BUFFER_SIZE(32), 0);
 647                 if (fdata->tx_buf[i] == NULL)
 648                         rte_panic("Out of memory\n");
 649                 rte_eth_tx_buffer_init(fdata->tx_buf[i], 32);
 650                 rte_eth_tx_buffer_set_err_callback(fdata->tx_buf[i],
 651                                                    eth_tx_buffer_retry,
 652                                                    userdata);
 653         }
 654
 655         return 0;
 656 }
 657
 658 struct port_link {
 659         uint8_t queue_id;
 660         uint8_t priority;
 661 };
 662
 663 static int
 664 setup_eventdev(struct prod_data *prod_data,
 665                 struct cons_data *cons_data,
 666                 struct worker_data *worker_data)
 667 {
 668         const uint8_t dev_id = 0;
 669         /* +1 stages is for a SINGLE_LINK TX stage */
 670         const uint8_t nb_queues = cdata.num_stages + 1;
 671         /* + 2 is one port for producer and one for consumer */
 672         const uint8_t nb_ports = cdata.num_workers + 2;
 673         struct rte_event_dev_config config = {
 674                         .nb_event_queues = nb_queues,
 675                         .nb_event_ports = nb_ports,
 676                         .nb_events_limit  = 4096,
 677                         .nb_event_queue_flows = 1024,
 678                         .nb_event_port_dequeue_depth = 128,
 679                         .nb_event_port_enqueue_depth = 128,
 680         };
 681         struct rte_event_port_conf wkr_p_conf = {
 682                         .dequeue_depth = cdata.worker_cq_depth,
 683                         .enqueue_depth = 64,
 684                         .new_event_threshold = 4096,
 685         };
 686         struct rte_event_queue_conf wkr_q_conf = {
 687                         .event_queue_cfg = cdata.queue_type,
 688                         .priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
 689                         .nb_atomic_flows = 1024,
 690                         .nb_atomic_order_sequences = 1024,
 691         };
 692         struct rte_event_port_conf tx_p_conf = {
 693                         .dequeue_depth = 128,
 694                         .enqueue_depth = 128,
 695                         .new_event_threshold = 4096,
 696         };
 697         const struct rte_event_queue_conf tx_q_conf = {
 698                         .priority = RTE_EVENT_DEV_PRIORITY_HIGHEST,
 699                         .event_queue_cfg =
 700                                         RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY |
 701                                         RTE_EVENT_QUEUE_CFG_SINGLE_LINK,
 702                         .nb_atomic_flows = 1024,
 703                         .nb_atomic_order_sequences = 1024,
 704         };
 705
 706         struct port_link worker_queues[MAX_NUM_STAGES];
 707         struct port_link tx_queue;
 708         unsigned int i;
 709
 710         int ret, ndev = rte_event_dev_count();
 711         if (ndev < 1) {
 712                 printf("%d: No Eventdev Devices Found\n", __LINE__);
 713                 return -1;
 714         }
 715
 716         struct rte_event_dev_info dev_info;
 717         ret = rte_event_dev_info_get(dev_id, &dev_info);
 718         printf("\tEventdev %d: %s\n", dev_id, dev_info.driver_name);
 719
 720         if (dev_info.max_event_port_dequeue_depth <
 721                         config.nb_event_port_dequeue_depth)
 722                 config.nb_event_port_dequeue_depth =
 723                                 dev_info.max_event_port_dequeue_depth;
 724         if (dev_info.max_event_port_enqueue_depth <
 725                         config.nb_event_port_enqueue_depth)
 726                 config.nb_event_port_enqueue_depth =
 727                                 dev_info.max_event_port_enqueue_depth;
 728
 729         ret = rte_event_dev_configure(dev_id, &config);
 730         if (ret < 0) {
 731                 printf("%d: Error configuring device\n", __LINE__);
 732                 return -1;
 733         }
 734
 735         /* Q creation - one load balanced per pipeline stage*/
 736         printf("  Stages:\n");
 737         for (i = 0; i < cdata.num_stages; i++) {
 738                 if (rte_event_queue_setup(dev_id, i, &wkr_q_conf) < 0) {
 739                         printf("%d: error creating qid %d\n", __LINE__, i);
 740                         return -1;
 741                 }
 742                 cdata.qid[i] = i;
 743                 cdata.next_qid[i] = i+1;
 744                 worker_queues[i].queue_id = i;
 745                 if (cdata.enable_queue_priorities) {
 746                         /* calculate priority stepping for each stage, leaving
 747                          * headroom of 1 for the SINGLE_LINK TX below
 748                          */
 749                         const uint32_t prio_delta =
 750                                 (RTE_EVENT_DEV_PRIORITY_LOWEST-1) /  nb_queues;
 751
 752                         /* higher priority for queues closer to tx */
 753                         wkr_q_conf.priority =
 754                                 RTE_EVENT_DEV_PRIORITY_LOWEST - prio_delta * i;
 755                 }
 756
 757                 const char *type_str = "Atomic";
 758                 switch (wkr_q_conf.event_queue_cfg) {
 759                 case RTE_EVENT_QUEUE_CFG_ORDERED_ONLY:
 760                         type_str = "Ordered";
 761                         break;
 762                 case RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY:
 763                         type_str = "Parallel";
 764                         break;
 765                 }
 766                 printf("\tStage %d, Type %s\tPriority = %d\n", i, type_str,
 767                                 wkr_q_conf.priority);
 768         }
 769         printf("\n");
 770
 771         /* final queue for sending to TX core */
 772         if (rte_event_queue_setup(dev_id, i, &tx_q_conf) < 0) {
 773                 printf("%d: error creating qid %d\n", __LINE__, i);
 774                 return -1;
 775         }
 776         tx_queue.queue_id = i;
 777         tx_queue.priority = RTE_EVENT_DEV_PRIORITY_HIGHEST;
 778
 779         if (wkr_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth)
 780                 wkr_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth;
 781         if (wkr_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth)
 782                 wkr_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth;
 783
 784         /* set up one port per worker, linking to all stage queues */
 785         for (i = 0; i < cdata.num_workers; i++) {
 786                 struct worker_data *w = &worker_data[i];
 787                 w->dev_id = dev_id;
 788                 if (rte_event_port_setup(dev_id, i, &wkr_p_conf) < 0) {
 789                         printf("Error setting up port %d\n", i);
 790                         return -1;
 791                 }
 792
 793                 uint32_t s;
 794                 for (s = 0; s < cdata.num_stages; s++) {
 795                         if (rte_event_port_link(dev_id, i,
 796                                                 &worker_queues[s].queue_id,
 797                                                 &worker_queues[s].priority,
 798                                                 1) != 1) {
 799                                 printf("%d: error creating link for port %d\n",
 800                                                 __LINE__, i);
 801                                 return -1;
 802                         }
 803                 }
 804                 w->port_id = i;
 805         }
 806
 807         if (tx_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth)
 808                 tx_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth;
 809         if (tx_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth)
 810                 tx_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth;
 811
 812         /* port for consumer, linked to TX queue */
 813         if (rte_event_port_setup(dev_id, i, &tx_p_conf) < 0) {
 814                 printf("Error setting up port %d\n", i);
 815                 return -1;
 816         }
 817         if (rte_event_port_link(dev_id, i, &tx_queue.queue_id,
 818                                 &tx_queue.priority, 1) != 1) {
 819                 printf("%d: error creating link for port %d\n",
 820                                 __LINE__, i);
 821                 return -1;
 822         }
 823         /* port for producer, no links */
 824         struct rte_event_port_conf rx_p_conf = {
 825                         .dequeue_depth = 8,
 826                         .enqueue_depth = 8,
 827                         .new_event_threshold = 1200,
 828         };
 829
 830         if (rx_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth)
 831                 rx_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth;
 832         if (rx_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth)
 833                 rx_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth;
 834
 835         if (rte_event_port_setup(dev_id, i + 1, &rx_p_conf) < 0) {
 836                 printf("Error setting up port %d\n", i);
 837                 return -1;
 838         }
 839
 840         *prod_data = (struct prod_data){.dev_id = dev_id,
 841                                         .port_id = i + 1,
 842                                         .qid = cdata.qid[0] };
 843         *cons_data = (struct cons_data){.dev_id = dev_id,
 844                                         .port_id = i };
 845
 846         if (rte_event_dev_start(dev_id) < 0) {
 847                 printf("Error starting eventdev\n");
 848                 return -1;
 849         }
 850
 851         return dev_id;
 852 }
 853
 854 static void
 855 signal_handler(int signum)
 856 {
 857         if (fdata->done)
 858                 rte_exit(1, "Exiting on signal %d\n", signum);
 859         if (signum == SIGINT || signum == SIGTERM) {
 860                 printf("\n\nSignal %d received, preparing to exit...\n",
 861                                 signum);
 862                 fdata->done = 1;
 863         }
 864         if (signum == SIGTSTP)
 865                 rte_event_dev_dump(0, stdout);
 866 }
 867
 868 static inline uint64_t
 869 port_stat(int dev_id, int32_t p)
 870 {
 871         char statname[64];
 872         snprintf(statname, sizeof(statname), "port_%u_rx", p);
 873         return rte_event_dev_xstats_by_name_get(dev_id, statname, NULL);
 874 }
 875
 876 int
 877 main(int argc, char **argv)
 878 {
 879         struct worker_data *worker_data;
 880         unsigned int num_ports;
 881         int lcore_id;
 882         int err;
 883
 884         signal(SIGINT, signal_handler);
 885         signal(SIGTERM, signal_handler);
 886         signal(SIGTSTP, signal_handler);
 887
 888         err = rte_eal_init(argc, argv);
 889         if (err < 0)
 890                 rte_panic("Invalid EAL arguments\n");
 891
 892         argc -= err;
 893         argv += err;
 894
 895         fdata = rte_malloc(NULL, sizeof(struct fastpath_data), 0);
 896         if (fdata == NULL)
 897                 rte_panic("Out of memory\n");
 898
 899         /* Parse cli options*/
 900         parse_app_args(argc, argv);
 901
 902         num_ports = rte_eth_dev_count();
 903         if (num_ports == 0)
 904                 rte_panic("No ethernet ports found\n");
 905
 906         const unsigned int cores_needed = cdata.active_cores;
 907
 908         if (!cdata.quiet) {
 909                 printf("  Config:\n");
 910                 printf("\tports: %u\n", num_ports);
 911                 printf("\tworkers: %u\n", cdata.num_workers);
 912                 printf("\tpackets: %"PRIi64"\n", cdata.num_packets);
 913                 printf("\tQueue-prio: %u\n", cdata.enable_queue_priorities);
 914                 if (cdata.queue_type == RTE_EVENT_QUEUE_CFG_ORDERED_ONLY)
 915                         printf("\tqid0 type: ordered\n");
 916                 if (cdata.queue_type == RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY)
 917                         printf("\tqid0 type: atomic\n");
 918                 printf("\tCores available: %u\n", rte_lcore_count());
 919                 printf("\tCores used: %u\n", cores_needed);
 920         }
 921
 922         if (rte_lcore_count() < cores_needed)
 923                 rte_panic("Too few cores (%d < %d)\n", rte_lcore_count(),
 924                                 cores_needed);
 925
 926         const unsigned int ndevs = rte_event_dev_count();
 927         if (ndevs == 0)
 928                 rte_panic("No dev_id devs found. Pasl in a --vdev eventdev.\n");
 929         if (ndevs > 1)
 930                 fprintf(stderr, "Warning: More than one eventdev, using idx 0");
 931
 932         worker_data = rte_calloc(0, cdata.num_workers,
 933                         sizeof(worker_data[0]), 0);
 934         if (worker_data == NULL)
 935                 rte_panic("rte_calloc failed\n");
 936
 937         int dev_id = setup_eventdev(&prod_data, &cons_data, worker_data);
 938         if (dev_id < 0)
 939                 rte_exit(EXIT_FAILURE, "Error setting up eventdev\n");
 940
 941         prod_data.num_nic_ports = num_ports;
 942         init_ports(num_ports);
 943
 944         int worker_idx = 0;
 945         RTE_LCORE_FOREACH_SLAVE(lcore_id) {
 946                 if (lcore_id >= MAX_NUM_CORE)
 947                         break;
 948
 949                 if (!fdata->rx_core[lcore_id] &&
 950                         !fdata->worker_core[lcore_id] &&
 951                         !fdata->tx_core[lcore_id] &&
 952                         !fdata->sched_core[lcore_id])
 953                         continue;
 954
 955                 if (fdata->rx_core[lcore_id])
 956                         printf(
 957                                 "[%s()] lcore %d executing NIC Rx, and using eventdev port %u\n",
 958                                 __func__, lcore_id, prod_data.port_id);
 959
 960                 if (fdata->tx_core[lcore_id])
 961                         printf(
 962                                 "[%s()] lcore %d executing NIC Tx, and using eventdev port %u\n",
 963                                 __func__, lcore_id, cons_data.port_id);
 964
 965                 if (fdata->sched_core[lcore_id])
 966                         printf("[%s()] lcore %d executing scheduler\n",
 967                                         __func__, lcore_id);
 968
 969                 if (fdata->worker_core[lcore_id])
 970                         printf(
 971                                 "[%s()] lcore %d executing worker, using eventdev port %u\n",
 972                                 __func__, lcore_id,
 973                                 worker_data[worker_idx].port_id);
 974
 975                 err = rte_eal_remote_launch(worker, &worker_data[worker_idx],
 976                                             lcore_id);
 977                 if (err) {
 978                         rte_panic("Failed to launch worker on core %d\n",
 979                                         lcore_id);
 980                         continue;
 981                 }
 982                 if (fdata->worker_core[lcore_id])
 983                         worker_idx++;
 984         }
 985
 986         lcore_id = rte_lcore_id();
 987
 988         if (core_in_use(lcore_id))
 989                 worker(&worker_data[worker_idx++]);
 990
 991         rte_eal_mp_wait_lcore();
 992
 993         if (cdata.dump_dev)
 994                 rte_event_dev_dump(dev_id, stdout);
 995
 996         if (!cdata.quiet && (port_stat(dev_id, worker_data[0].port_id) !=
 997                         (uint64_t)-ENOTSUP)) {
 998                 printf("\nPort Workload distribution:\n");
 999                 uint32_t i;
1000                 uint64_t tot_pkts = 0;
1001                 uint64_t pkts_per_wkr[RTE_MAX_LCORE] = {0};
1002                 for (i = 0; i < cdata.num_workers; i++) {
1003                         pkts_per_wkr[i] =
1004                                 port_stat(dev_id, worker_data[i].port_id);
1005                         tot_pkts += pkts_per_wkr[i];
1006                 }
1007                 for (i = 0; i < cdata.num_workers; i++) {
1008                         float pc = pkts_per_wkr[i]  * 100 /
1009                                 ((float)tot_pkts);
1010                         printf("worker %i :\t%.1f %% (%"PRIu64" pkts)\n",
1011                                         i, pc, pkts_per_wkr[i]);
1012                 }
1013
1014         }
1015
1016         return 0;
1017 }