examples/ip_pipeline/config/edge_router_downstream.cfg

   1 ;   BSD LICENSE
   2 ;
   3 ;   Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
   4 ;   All rights reserved.
   5 ;
   6 ;   Redistribution and use in source and binary forms, with or without
   7 ;   modification, are permitted provided that the following conditions
   8 ;   are met:
   9 ;
  10 ;     * Redistributions of source code must retain the above copyright
  11 ;       notice, this list of conditions and the following disclaimer.
  12 ;     * Redistributions in binary form must reproduce the above copyright
  13 ;       notice, this list of conditions and the following disclaimer in
  14 ;       the documentation and/or other materials provided with the
  15 ;       distribution.
  16 ;     * Neither the name of Intel Corporation nor the names of its
  17 ;       contributors may be used to endorse or promote products derived
  18 ;       from this software without specific prior written permission.
  19 ;
  20 ;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21 ;   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22 ;   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23 ;   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24 ;   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25 ;   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26 ;   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27 ;   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28 ;   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29 ;   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30 ;   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32
  33 ;   An edge router typically sits between two networks such as the provider
  34 ;   core network and the provider access network. A typical packet processing
  35 ;   pipeline for the downstream traffic (i.e. traffic from core to access
  36 ;   network) contains the following functional blocks: Packet RX & Routing,
  37 ;   Traffic management and Packet TX. The input packets are assumed to be
  38 ;   IPv4, while the output packets are Q-in-Q IPv4.
  39 ;
  40 ;  A simple implementation for this functional pipeline is presented below.
  41 ;
  42 ;                  Packet Rx &                Traffic Management               Packet Tx
  43 ;                   Routing                    (Pass-Through)                (Pass-Through)
  44 ;             _____________________  SWQ0  ______________________  SWQ4  _____________________
  45 ; RXQ0.0 --->|                     |----->|                      |----->|                     |---> TXQ0.0
  46 ;            |                     | SWQ1 |                      | SWQ5 |                     |
  47 ; RXQ1.0 --->|                     |----->|                      |----->|                     |---> TXQ1.0
  48 ;            |        (P1)         | SWQ2 |         (P2)         | SWQ6 |        (P3)         |
  49 ; RXQ2.0 --->|                     |----->|                      |----->|                     |---> TXQ2.0
  50 ;            |                     | SWQ3 |                      | SWQ7 |                     |
  51 ; RXQ3.0 --->|                     |----->|                      |----->|                     |---> TXQ3.0
  52 ;            |_____________________|      |______________________|      |_____________________|
  53 ;                       |                  |  ^  |  ^  |  ^  |  ^
  54 ;                       |                  |__|  |__|  |__|  |__|
  55 ;                       +--> SINK0          TM0   TM1   TM2   TM3
  56 ;                      (Default)
  57 ;
  58 ; Input packet: Ethernet/IPv4
  59 ; Output packet: Ethernet/QinQ/IPv4
  60 ;
  61 ; Packet buffer layout:
  62 ; #     Field Name              Offset (Bytes)  Size (Bytes)
  63 ; 0     Mbuf                    0               128
  64 ; 1     Headroom                128             128
  65 ; 2     Ethernet header         256             14
  66 ; 3     IPv4 header             270             20
  67
  68 [EAL]
  69 log_level = 0
  70
  71 [PIPELINE0]
  72 type = MASTER
  73 core = 0
  74
  75 [PIPELINE1]
  76 type = ROUTING
  77 core = 1
  78 pktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0
  79 pktq_out = SWQ0 SWQ1 SWQ2 SWQ3 SINK0
  80 encap = ethernet_qinq
  81 qinq_sched = test
  82 ip_hdr_offset = 270
  83
  84 [PIPELINE2]
  85 type = PASS-THROUGH
  86 core = 2
  87 pktq_in = SWQ0 SWQ1 SWQ2 SWQ3 TM0 TM1 TM2 TM3
  88 pktq_out = TM0 TM1 TM2 TM3 SWQ4 SWQ5 SWQ6 SWQ7
  89
  90 [PIPELINE3]
  91 type = PASS-THROUGH
  92 core = 3
  93 pktq_in = SWQ4 SWQ5 SWQ6 SWQ7
  94 pktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0
  95
  96 [MEMPOOL0]
  97 pool_size = 2M