kernel/linux/kni/ethtool/igb/igb_regtest.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*******************************************************************************
   3
   4   Intel(R) Gigabit Ethernet Linux driver
   5   Copyright(c) 2007-2013 Intel Corporation.
   6
   7   Contact Information:
   8   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   9   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  10
  11 *******************************************************************************/
  12
  13 /* ethtool register test data */
  14 struct igb_reg_test {
  15         u16 reg;
  16         u16 reg_offset;
  17         u16 array_len;
  18         u16 test_type;
  19         u32 mask;
  20         u32 write;
  21 };
  22
  23 /* In the hardware, registers are laid out either singly, in arrays
  24  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
  25  * most tests take place on arrays or single registers (handled
  26  * as a single-element array) and special-case the tables.
  27  * Table tests are always pattern tests.
  28  *
  29  * We also make provision for some required setup steps by specifying
  30  * registers to be written without any read-back testing.
  31  */
  32
  33 #define PATTERN_TEST    1
  34 #define SET_READ_TEST   2
  35 #define WRITE_NO_TEST   3
  36 #define TABLE32_TEST    4
  37 #define TABLE64_TEST_LO 5
  38 #define TABLE64_TEST_HI 6
  39
  40 /* i210 reg test */
  41 static struct igb_reg_test reg_test_i210[] = {
  42         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  43         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  44         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  45         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  46         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  47         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  48         /* RDH is read-only for i210, only test RDT. */
  49         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  50         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0003FFF0, 0x0003FFF0 },
  51         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  52         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
  53         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  54         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  55         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  56         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  57         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
  58         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
  59         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
  60         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
  61         { E1000_RA,        0, 16, TABLE64_TEST_LO,
  62                                                 0xFFFFFFFF, 0xFFFFFFFF },
  63         { E1000_RA,        0, 16, TABLE64_TEST_HI,
  64                                                 0x900FFFFF, 0xFFFFFFFF },
  65         { E1000_MTA,       0, 128, TABLE32_TEST,
  66                                                 0xFFFFFFFF, 0xFFFFFFFF },
  67         { 0, 0, 0, 0 }
  68 };
  69
  70 /* i350 reg test */
  71 static struct igb_reg_test reg_test_i350[] = {
  72         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  73         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  74         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  75         /* VET is readonly on i350 */
  76         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  77         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  78         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  79         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  80         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  81         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  82         /* RDH is read-only for i350, only test RDT. */
  83         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  84         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  85         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
  86         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  87         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
  88         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  89         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  90         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  91         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  92         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  93         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  94         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  95         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  96         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
  97         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
  98         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
  99         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 100         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 101                                                 0xFFFFFFFF, 0xFFFFFFFF },
 102         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 103                                                 0xC3FFFFFF, 0xFFFFFFFF },
 104         { E1000_RA2,       0, 16, TABLE64_TEST_LO,
 105                                                 0xFFFFFFFF, 0xFFFFFFFF },
 106         { E1000_RA2,       0, 16, TABLE64_TEST_HI,
 107                                                 0xC3FFFFFF, 0xFFFFFFFF },
 108         { E1000_MTA,       0, 128, TABLE32_TEST,
 109                                                 0xFFFFFFFF, 0xFFFFFFFF },
 110         { 0, 0, 0, 0 }
 111 };
 112
 113 /* 82580 reg test */
 114 static struct igb_reg_test reg_test_82580[] = {
 115         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 116         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 117         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 118         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 119         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 120         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 121         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 122         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 123         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 124         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 125         /* RDH is read-only for 82580, only test RDT. */
 126         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 127         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 128         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 129         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 130         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 131         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 132         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 133         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 134         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 135         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 136         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 137         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 138         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 139         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 140         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 141         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 142         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 143         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 144                                                 0xFFFFFFFF, 0xFFFFFFFF },
 145         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 146                                                 0x83FFFFFF, 0xFFFFFFFF },
 147         { E1000_RA2,       0, 8, TABLE64_TEST_LO,
 148                                                 0xFFFFFFFF, 0xFFFFFFFF },
 149         { E1000_RA2,       0, 8, TABLE64_TEST_HI,
 150                                                 0x83FFFFFF, 0xFFFFFFFF },
 151         { E1000_MTA,       0, 128, TABLE32_TEST,
 152                                                 0xFFFFFFFF, 0xFFFFFFFF },
 153         { 0, 0, 0, 0 }
 154 };
 155
 156 /* 82576 reg test */
 157 static struct igb_reg_test reg_test_82576[] = {
 158         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 159         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 160         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 161         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 162         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 163         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 164         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 165         { E1000_RDBAL(4),  0x40,  12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 166         { E1000_RDBAH(4),  0x40,  12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 167         { E1000_RDLEN(4),  0x40,  12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 168         /* Enable all queues before testing. */
 169         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 170         { E1000_RXDCTL(4), 0x40,  12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 171         /* RDH is read-only for 82576, only test RDT. */
 172         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 173         { E1000_RDT(4),    0x40,  12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 174         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
 175         { E1000_RXDCTL(4), 0x40,  12, WRITE_NO_TEST, 0, 0 },
 176         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 177         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 178         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 179         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 180         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 181         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 182         { E1000_TDBAL(4),  0x40,  12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 183         { E1000_TDBAH(4),  0x40,  12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 184         { E1000_TDLEN(4),  0x40,  12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 185         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 186         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 187         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 188         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 189         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 190                                                 0xFFFFFFFF, 0xFFFFFFFF },
 191         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 192                                                 0x83FFFFFF, 0xFFFFFFFF },
 193         { E1000_RA2,       0, 8, TABLE64_TEST_LO,
 194                                                 0xFFFFFFFF, 0xFFFFFFFF },
 195         { E1000_RA2,       0, 8, TABLE64_TEST_HI,
 196                                                 0x83FFFFFF, 0xFFFFFFFF },
 197         { E1000_MTA,       0, 128, TABLE32_TEST,
 198                                                 0xFFFFFFFF, 0xFFFFFFFF },
 199         { 0, 0, 0, 0 }
 200 };
 201
 202 /* 82575 register test */
 203 static struct igb_reg_test reg_test_82575[] = {
 204         { E1000_FCAL,   0x100,  1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 205         { E1000_FCAH,   0x100,  1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 206         { E1000_FCT,    0x100,  1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 207         { E1000_VET,    0x100,  1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 208         { E1000_RDBAL(0),       0x100,  4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 209         { E1000_RDBAH(0),       0x100,  4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 210         { E1000_RDLEN(0),       0x100,  4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 211         /* Enable all four RX queues before testing. */
 212         { E1000_RXDCTL(0),      0x100,  4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 213         /* RDH is read-only for 82575, only test RDT. */
 214         { E1000_RDT(0), 0x100,  4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 215         { E1000_RXDCTL(0),      0x100,  4, WRITE_NO_TEST, 0, 0 },
 216         { E1000_FCRTH,  0x100,  1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 217         { E1000_FCTTV,  0x100,  1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 218         { E1000_TIPG,   0x100,  1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 219         { E1000_TDBAL(0),       0x100,  4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 220         { E1000_TDBAH(0),       0x100,  4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 221         { E1000_TDLEN(0),       0x100,  4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 222         { E1000_RCTL,   0x100,  1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 223         { E1000_RCTL,   0x100,  1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
 224         { E1000_RCTL,   0x100,  1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
 225         { E1000_TCTL,   0x100,  1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 226         { E1000_TXCW,   0x100,  1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
 227         { E1000_RA,     0,      16, TABLE64_TEST_LO,
 228                                                 0xFFFFFFFF, 0xFFFFFFFF },
 229         { E1000_RA,     0,      16, TABLE64_TEST_HI,
 230                                                 0x800FFFFF, 0xFFFFFFFF },
 231         { E1000_MTA,    0,      128, TABLE32_TEST,
 232                                                 0xFFFFFFFF, 0xFFFFFFFF },
 233         { 0, 0, 0, 0 }
 234 };