kernel/linux/kni/ethtool/ixgbe/ixgbe_x540.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*******************************************************************************
   3
   4   Intel 10 Gigabit PCI Express Linux driver
   5   Copyright(c) 1999 - 2012 Intel Corporation.
   6
   7   Contact Information:
   8   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   9   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  10
  11 *******************************************************************************/
  12
  13 #include "ixgbe_x540.h"
  14 #include "ixgbe_type.h"
  15 #include "ixgbe_api.h"
  16 #include "ixgbe_common.h"
  17 #include "ixgbe_phy.h"
  18
  19 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  20 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  21 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  22 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  23
  24 /**
  25  *  ixgbe_init_ops_X540 - Inits func ptrs and MAC type
  26  *  @hw: pointer to hardware structure
  27  *
  28  *  Initialize the function pointers and assign the MAC type for X540.
  29  *  Does not touch the hardware.
  30  **/
  31 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
  32 {
  33         struct ixgbe_mac_info *mac = &hw->mac;
  34         struct ixgbe_phy_info *phy = &hw->phy;
  35         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
  36         s32 ret_val;
  37
  38         ret_val = ixgbe_init_phy_ops_generic(hw);
  39         ret_val = ixgbe_init_ops_generic(hw);
  40
  41
  42         /* EEPROM */
  43         eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
  44         eeprom->ops.read = &ixgbe_read_eerd_X540;
  45         eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
  46         eeprom->ops.write = &ixgbe_write_eewr_X540;
  47         eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
  48         eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
  49         eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
  50         eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
  51
  52         /* PHY */
  53         phy->ops.init = &ixgbe_init_phy_ops_generic;
  54         phy->ops.reset = NULL;
  55
  56         /* MAC */
  57         mac->ops.reset_hw = &ixgbe_reset_hw_X540;
  58         mac->ops.get_media_type = &ixgbe_get_media_type_X540;
  59         mac->ops.get_supported_physical_layer =
  60                                     &ixgbe_get_supported_physical_layer_X540;
  61         mac->ops.read_analog_reg8 = NULL;
  62         mac->ops.write_analog_reg8 = NULL;
  63         mac->ops.start_hw = &ixgbe_start_hw_X540;
  64         mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
  65         mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
  66         mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
  67         mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
  68         mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
  69         mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
  70         mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
  71         mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
  72         mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
  73
  74         /* RAR, Multicast, VLAN */
  75         mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
  76         mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
  77         mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
  78         mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
  79         mac->rar_highwater = 1;
  80         mac->ops.set_vfta = &ixgbe_set_vfta_generic;
  81         mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
  82         mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
  83         mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
  84         mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
  85         mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
  86
  87         /* Link */
  88         mac->ops.get_link_capabilities =
  89                                 &ixgbe_get_copper_link_capabilities_generic;
  90         mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
  91         mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
  92         mac->ops.check_link = &ixgbe_check_mac_link_generic;
  93
  94         mac->mcft_size          = 128;
  95         mac->vft_size           = 128;
  96         mac->num_rar_entries    = 128;
  97         mac->rx_pb_size         = 384;
  98         mac->max_tx_queues      = 128;
  99         mac->max_rx_queues      = 128;
 100         mac->max_msix_vectors   = ixgbe_get_pcie_msix_count_generic(hw);
 101
 102         /*
 103          * FWSM register
 104          * ARC supported; valid only if manageability features are
 105          * enabled.
 106          */
 107         mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
 108                                    IXGBE_FWSM_MODE_MASK) ? true : false;
 109
 110         //hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 111
 112         /* LEDs */
 113         mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
 114         mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
 115
 116         /* Manageability interface */
 117         mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
 118
 119         return ret_val;
 120 }
 121
 122 /**
 123  *  ixgbe_get_link_capabilities_X540 - Determines link capabilities
 124  *  @hw: pointer to hardware structure
 125  *  @speed: pointer to link speed
 126  *  @autoneg: true when autoneg or autotry is enabled
 127  *
 128  *  Determines the link capabilities by reading the AUTOC register.
 129  **/
 130 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
 131                                      ixgbe_link_speed *speed,
 132                                      bool *autoneg)
 133 {
 134         ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
 135
 136         return 0;
 137 }
 138
 139 /**
 140  *  ixgbe_get_media_type_X540 - Get media type
 141  *  @hw: pointer to hardware structure
 142  *
 143  *  Returns the media type (fiber, copper, backplane)
 144  **/
 145 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
 146 {
 147         return ixgbe_media_type_copper;
 148 }
 149
 150 /**
 151  *  ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
 152  *  @hw: pointer to hardware structure
 153  *  @speed: new link speed
 154  *  @autoneg: true if autonegotiation enabled
 155  *  @autoneg_wait_to_complete: true when waiting for completion is needed
 156  **/
 157 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
 158                               ixgbe_link_speed speed, bool autoneg,
 159                               bool autoneg_wait_to_complete)
 160 {
 161         return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 162                                             autoneg_wait_to_complete);
 163 }
 164
 165 /**
 166  *  ixgbe_reset_hw_X540 - Perform hardware reset
 167  *  @hw: pointer to hardware structure
 168  *
 169  *  Resets the hardware by resetting the transmit and receive units, masks
 170  *  and clears all interrupts, and perform a reset.
 171  **/
 172 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
 173 {
 174         s32 status = 0;
 175
 176         /*
 177          * Userland DPDK takes the ownershiop of device
 178          * Kernel driver here used as the simple path for ethtool only
 179          * Won't real reset device anyway
 180          */
 181 #if 0
 182         u32 ctrl, i;
 183
 184         /* Call adapter stop to disable tx/rx and clear interrupts */
 185         status = hw->mac.ops.stop_adapter(hw);
 186         if (status != 0)
 187                 goto reset_hw_out;
 188
 189         /* flush pending Tx transactions */
 190         ixgbe_clear_tx_pending(hw);
 191
 192 mac_reset_top:
 193         ctrl = IXGBE_CTRL_RST;
 194         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 195         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 196         IXGBE_WRITE_FLUSH(hw);
 197
 198         /* Poll for reset bit to self-clear indicating reset is complete */
 199         for (i = 0; i < 10; i++) {
 200                 udelay(1);
 201                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 202                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
 203                         break;
 204         }
 205
 206         if (ctrl & IXGBE_CTRL_RST_MASK) {
 207                 status = IXGBE_ERR_RESET_FAILED;
 208                 hw_dbg(hw, "Reset polling failed to complete.\n");
 209         }
 210         msleep(100);
 211
 212         /*
 213          * Double resets are required for recovery from certain error
 214          * conditions.  Between resets, it is necessary to stall to allow time
 215          * for any pending HW events to complete.
 216          */
 217         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 218                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 219                 goto mac_reset_top;
 220         }
 221
 222         /* Set the Rx packet buffer size. */
 223         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 224
 225 #endif
 226
 227         /* Store the permanent mac address */
 228         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 229
 230         /*
 231          * Store MAC address from RAR0, clear receive address registers, and
 232          * clear the multicast table.  Also reset num_rar_entries to 128,
 233          * since we modify this value when programming the SAN MAC address.
 234          */
 235         hw->mac.num_rar_entries = 128;
 236         hw->mac.ops.init_rx_addrs(hw);
 237
 238         /* Store the permanent SAN mac address */
 239         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 240
 241         /* Add the SAN MAC address to the RAR only if it's a valid address */
 242         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 243                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 244                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 245
 246                 /* Save the SAN MAC RAR index */
 247                 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 248
 249                 /* Reserve the last RAR for the SAN MAC address */
 250                 hw->mac.num_rar_entries--;
 251         }
 252
 253         /* Store the alternative WWNN/WWPN prefix */
 254         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 255                                    &hw->mac.wwpn_prefix);
 256
 257 //reset_hw_out:
 258         return status;
 259 }
 260
 261 /**
 262  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 263  *  @hw: pointer to hardware structure
 264  *
 265  *  Starts the hardware using the generic start_hw function
 266  *  and the generation start_hw function.
 267  *  Then performs revision-specific operations, if any.
 268  **/
 269 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 270 {
 271         s32 ret_val = 0;
 272
 273         ret_val = ixgbe_start_hw_generic(hw);
 274         if (ret_val != 0)
 275                 goto out;
 276
 277         ret_val = ixgbe_start_hw_gen2(hw);
 278
 279 out:
 280         return ret_val;
 281 }
 282
 283 /**
 284  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 285  *  @hw: pointer to hardware structure
 286  *
 287  *  Determines physical layer capabilities of the current configuration.
 288  **/
 289 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 290 {
 291         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 292         u16 ext_ability = 0;
 293
 294         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 295         IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 296         if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 297                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 298         if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
 299                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 300         if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 301                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 302
 303         return physical_layer;
 304 }
 305
 306 /**
 307  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 308  *  @hw: pointer to hardware structure
 309  *
 310  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 311  *  ixgbe_hw struct in order to set up EEPROM access.
 312  **/
 313 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 314 {
 315         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 316         u32 eec;
 317         u16 eeprom_size;
 318
 319         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 320                 eeprom->semaphore_delay = 10;
 321                 eeprom->type = ixgbe_flash;
 322
 323                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 324                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 325                                     IXGBE_EEC_SIZE_SHIFT);
 326                 eeprom->word_size = 1 << (eeprom_size +
 327                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 328
 329                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 330                           eeprom->type, eeprom->word_size);
 331         }
 332
 333         return 0;
 334 }
 335
 336 /**
 337  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 338  *  @hw: pointer to hardware structure
 339  *  @offset: offset of  word in the EEPROM to read
 340  *  @data: word read from the EEPROM
 341  *
 342  *  Reads a 16 bit word from the EEPROM using the EERD register.
 343  **/
 344 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 345 {
 346         s32 status = 0;
 347
 348         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 349             0)
 350                 status = ixgbe_read_eerd_generic(hw, offset, data);
 351         else
 352                 status = IXGBE_ERR_SWFW_SYNC;
 353
 354         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 355         return status;
 356 }
 357
 358 /**
 359  *  ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
 360  *  @hw: pointer to hardware structure
 361  *  @offset: offset of  word in the EEPROM to read
 362  *  @words: number of words
 363  *  @data: word(s) read from the EEPROM
 364  *
 365  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 366  **/
 367 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 368                                 u16 offset, u16 words, u16 *data)
 369 {
 370         s32 status = 0;
 371
 372         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 373             0)
 374                 status = ixgbe_read_eerd_buffer_generic(hw, offset,
 375                                                         words, data);
 376         else
 377                 status = IXGBE_ERR_SWFW_SYNC;
 378
 379         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 380         return status;
 381 }
 382
 383 /**
 384  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 385  *  @hw: pointer to hardware structure
 386  *  @offset: offset of  word in the EEPROM to write
 387  *  @data: word write to the EEPROM
 388  *
 389  *  Write a 16 bit word to the EEPROM using the EEWR register.
 390  **/
 391 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 392 {
 393         s32 status = 0;
 394
 395         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 396             0)
 397                 status = ixgbe_write_eewr_generic(hw, offset, data);
 398         else
 399                 status = IXGBE_ERR_SWFW_SYNC;
 400
 401         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 402         return status;
 403 }
 404
 405 /**
 406  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 407  *  @hw: pointer to hardware structure
 408  *  @offset: offset of  word in the EEPROM to write
 409  *  @words: number of words
 410  *  @data: word(s) write to the EEPROM
 411  *
 412  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 413  **/
 414 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 415                                  u16 offset, u16 words, u16 *data)
 416 {
 417         s32 status = 0;
 418
 419         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 420             0)
 421                 status = ixgbe_write_eewr_buffer_generic(hw, offset,
 422                                                          words, data);
 423         else
 424                 status = IXGBE_ERR_SWFW_SYNC;
 425
 426         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 427         return status;
 428 }
 429
 430 /**
 431  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 432  *
 433  *  This function does not use synchronization for EERD and EEWR. It can
 434  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 435  *
 436  *  @hw: pointer to hardware structure
 437  **/
 438 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 439 {
 440         u16 i;
 441         u16 j;
 442         u16 checksum = 0;
 443         u16 length = 0;
 444         u16 pointer = 0;
 445         u16 word = 0;
 446
 447         /*
 448          * Do not use hw->eeprom.ops.read because we do not want to take
 449          * the synchronization semaphores here. Instead use
 450          * ixgbe_read_eerd_generic
 451          */
 452
 453         /* Include 0x0-0x3F in the checksum */
 454         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 455                 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) {
 456                         hw_dbg(hw, "EEPROM read failed\n");
 457                         break;
 458                 }
 459                 checksum += word;
 460         }
 461
 462         /*
 463          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 464          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 465          */
 466         for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
 467                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 468                         continue;
 469
 470                 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) {
 471                         hw_dbg(hw, "EEPROM read failed\n");
 472                         break;
 473                 }
 474
 475                 /* Skip pointer section if the pointer is invalid. */
 476                 if (pointer == 0xFFFF || pointer == 0 ||
 477                     pointer >= hw->eeprom.word_size)
 478                         continue;
 479
 480                 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
 481                     0) {
 482                         hw_dbg(hw, "EEPROM read failed\n");
 483                         break;
 484                 }
 485
 486                 /* Skip pointer section if length is invalid. */
 487                 if (length == 0xFFFF || length == 0 ||
 488                     (pointer + length) >= hw->eeprom.word_size)
 489                         continue;
 490
 491                 for (j = pointer+1; j <= pointer+length; j++) {
 492                         if (ixgbe_read_eerd_generic(hw, j, &word) !=
 493                             0) {
 494                                 hw_dbg(hw, "EEPROM read failed\n");
 495                                 break;
 496                         }
 497                         checksum += word;
 498                 }
 499         }
 500
 501         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 502
 503         return checksum;
 504 }
 505
 506 /**
 507  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 508  *  @hw: pointer to hardware structure
 509  *  @checksum_val: calculated checksum
 510  *
 511  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 512  *  caller does not need checksum_val, the value can be NULL.
 513  **/
 514 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 515                                         u16 *checksum_val)
 516 {
 517         s32 status;
 518         u16 checksum;
 519         u16 read_checksum = 0;
 520
 521         /*
 522          * Read the first word from the EEPROM. If this times out or fails, do
 523          * not continue or we could be in for a very long wait while every
 524          * EEPROM read fails
 525          */
 526         status = hw->eeprom.ops.read(hw, 0, &checksum);
 527
 528         if (status != 0) {
 529                 hw_dbg(hw, "EEPROM read failed\n");
 530                 goto out;
 531         }
 532
 533         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 534             0) {
 535                 checksum = hw->eeprom.ops.calc_checksum(hw);
 536
 537                 /*
 538                  * Do not use hw->eeprom.ops.read because we do not want to take
 539                  * the synchronization semaphores twice here.
 540                 */
 541                 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 542                                         &read_checksum);
 543
 544                 /*
 545                  * Verify read checksum from EEPROM is the same as
 546                  * calculated checksum
 547                  */
 548                 if (read_checksum != checksum)
 549                         status = IXGBE_ERR_EEPROM_CHECKSUM;
 550
 551                 /* If the user cares, return the calculated checksum */
 552                 if (checksum_val)
 553                         *checksum_val = checksum;
 554         } else {
 555                 status = IXGBE_ERR_SWFW_SYNC;
 556         }
 557
 558         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 559 out:
 560         return status;
 561 }
 562
 563 /**
 564  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 565  * @hw: pointer to hardware structure
 566  *
 567  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 568  * checksum and updates the EEPROM and instructs the hardware to update
 569  * the flash.
 570  **/
 571 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 572 {
 573         s32 status;
 574         u16 checksum;
 575
 576         /*
 577          * Read the first word from the EEPROM. If this times out or fails, do
 578          * not continue or we could be in for a very long wait while every
 579          * EEPROM read fails
 580          */
 581         status = hw->eeprom.ops.read(hw, 0, &checksum);
 582
 583         if (status != 0)
 584                 hw_dbg(hw, "EEPROM read failed\n");
 585
 586         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 587             0) {
 588                 checksum = hw->eeprom.ops.calc_checksum(hw);
 589
 590                 /*
 591                  * Do not use hw->eeprom.ops.write because we do not want to
 592                  * take the synchronization semaphores twice here.
 593                 */
 594                 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
 595                                                   checksum);
 596
 597         if (status == 0)
 598                 status = ixgbe_update_flash_X540(hw);
 599         else
 600                 status = IXGBE_ERR_SWFW_SYNC;
 601         }
 602
 603         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 604
 605         return status;
 606 }
 607
 608 /**
 609  *  ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 610  *  @hw: pointer to hardware structure
 611  *
 612  *  Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 613  *  EEPROM from shadow RAM to the flash device.
 614  **/
 615 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 616 {
 617         u32 flup;
 618         s32 status = IXGBE_ERR_EEPROM;
 619
 620         status = ixgbe_poll_flash_update_done_X540(hw);
 621         if (status == IXGBE_ERR_EEPROM) {
 622                 hw_dbg(hw, "Flash update time out\n");
 623                 goto out;
 624         }
 625
 626         flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
 627         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 628
 629         status = ixgbe_poll_flash_update_done_X540(hw);
 630         if (status == 0)
 631                 hw_dbg(hw, "Flash update complete\n");
 632         else
 633                 hw_dbg(hw, "Flash update time out\n");
 634
 635         if (hw->revision_id == 0) {
 636                 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 637
 638                 if (flup & IXGBE_EEC_SEC1VAL) {
 639                         flup |= IXGBE_EEC_FLUP;
 640                         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 641                 }
 642
 643                 status = ixgbe_poll_flash_update_done_X540(hw);
 644                 if (status == 0)
 645                         hw_dbg(hw, "Flash update complete\n");
 646                 else
 647                         hw_dbg(hw, "Flash update time out\n");
 648         }
 649 out:
 650         return status;
 651 }
 652
 653 /**
 654  *  ixgbe_poll_flash_update_done_X540 - Poll flash update status
 655  *  @hw: pointer to hardware structure
 656  *
 657  *  Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 658  *  flash update is done.
 659  **/
 660 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 661 {
 662         u32 i;
 663         u32 reg;
 664         s32 status = IXGBE_ERR_EEPROM;
 665
 666         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 667                 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
 668                 if (reg & IXGBE_EEC_FLUDONE) {
 669                         status = 0;
 670                         break;
 671                 }
 672                 udelay(5);
 673         }
 674         return status;
 675 }
 676
 677 /**
 678  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 679  *  @hw: pointer to hardware structure
 680  *  @mask: Mask to specify which semaphore to acquire
 681  *
 682  *  Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 683  *  the specified function (CSR, PHY0, PHY1, NVM, Flash)
 684  **/
 685 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 686 {
 687         u32 swfw_sync;
 688         u32 swmask = mask;
 689         u32 fwmask = mask << 5;
 690         u32 hwmask = 0;
 691         u32 timeout = 200;
 692         u32 i;
 693         s32 ret_val = 0;
 694
 695         if (swmask == IXGBE_GSSR_EEP_SM)
 696                 hwmask = IXGBE_GSSR_FLASH_SM;
 697
 698         /* SW only mask doesn't have FW bit pair */
 699         if (swmask == IXGBE_GSSR_SW_MNG_SM)
 700                 fwmask = 0;
 701
 702         for (i = 0; i < timeout; i++) {
 703                 /*
 704                  * SW NVM semaphore bit is used for access to all
 705                  * SW_FW_SYNC bits (not just NVM)
 706                  */
 707                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 708                         ret_val = IXGBE_ERR_SWFW_SYNC;
 709                         goto out;
 710                 }
 711
 712                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 713                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 714                         swfw_sync |= swmask;
 715                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 716                         ixgbe_release_swfw_sync_semaphore(hw);
 717                         msleep(5);
 718                         goto out;
 719                 } else {
 720                         /*
 721                          * Firmware currently using resource (fwmask), hardware
 722                          * currently using resource (hwmask), or other software
 723                          * thread currently using resource (swmask)
 724                          */
 725                         ixgbe_release_swfw_sync_semaphore(hw);
 726                         msleep(5);
 727                 }
 728         }
 729
 730         /* Failed to get SW only semaphore */
 731         if (swmask == IXGBE_GSSR_SW_MNG_SM) {
 732                 ret_val = IXGBE_ERR_SWFW_SYNC;
 733                 goto out;
 734         }
 735
 736         /* If the resource is not released by the FW/HW the SW can assume that
 737          * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
 738          * of the requested resource(s) while ignoring the corresponding FW/HW
 739          * bits in the SW_FW_SYNC register.
 740          */
 741         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 742         if (swfw_sync & (fwmask | hwmask)) {
 743                 if (ixgbe_get_swfw_sync_semaphore(hw)) {
 744                         ret_val = IXGBE_ERR_SWFW_SYNC;
 745                         goto out;
 746                 }
 747
 748                 swfw_sync |= swmask;
 749                 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 750                 ixgbe_release_swfw_sync_semaphore(hw);
 751                 msleep(5);
 752         }
 753
 754 out:
 755         return ret_val;
 756 }
 757
 758 /**
 759  *  ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 760  *  @hw: pointer to hardware structure
 761  *  @mask: Mask to specify which semaphore to release
 762  *
 763  *  Releases the SWFW semaphore through the SW_FW_SYNC register
 764  *  for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 765  **/
 766 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 767 {
 768         u32 swfw_sync;
 769         u32 swmask = mask;
 770
 771         ixgbe_get_swfw_sync_semaphore(hw);
 772
 773         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 774         swfw_sync &= ~swmask;
 775         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 776
 777         ixgbe_release_swfw_sync_semaphore(hw);
 778         msleep(5);
 779 }
 780
 781 /**
 782  *  ixgbe_get_nvm_semaphore - Get hardware semaphore
 783  *  @hw: pointer to hardware structure
 784  *
 785  *  Sets the hardware semaphores so SW/FW can gain control of shared resources
 786  **/
 787 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 788 {
 789         s32 status = IXGBE_ERR_EEPROM;
 790         u32 timeout = 2000;
 791         u32 i;
 792         u32 swsm;
 793
 794         /* Get SMBI software semaphore between device drivers first */
 795         for (i = 0; i < timeout; i++) {
 796                 /*
 797                  * If the SMBI bit is 0 when we read it, then the bit will be
 798                  * set and we have the semaphore
 799                  */
 800                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 801                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 802                         status = 0;
 803                         break;
 804                 }
 805                 udelay(50);
 806         }
 807
 808         /* Now get the semaphore between SW/FW through the REGSMP bit */
 809         if (status == 0) {
 810                 for (i = 0; i < timeout; i++) {
 811                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 812                         if (!(swsm & IXGBE_SWFW_REGSMP))
 813                                 break;
 814
 815                         udelay(50);
 816                 }
 817
 818                 /*
 819                  * Release semaphores and return error if SW NVM semaphore
 820                  * was not granted because we don't have access to the EEPROM
 821                  */
 822                 if (i >= timeout) {
 823                         hw_dbg(hw, "REGSMP Software NVM semaphore not "
 824                                  "granted.\n");
 825                         ixgbe_release_swfw_sync_semaphore(hw);
 826                         status = IXGBE_ERR_EEPROM;
 827                 }
 828         } else {
 829                 hw_dbg(hw, "Software semaphore SMBI between device drivers "
 830                          "not granted.\n");
 831         }
 832
 833         return status;
 834 }
 835
 836 /**
 837  *  ixgbe_release_nvm_semaphore - Release hardware semaphore
 838  *  @hw: pointer to hardware structure
 839  *
 840  *  This function clears hardware semaphore bits.
 841  **/
 842 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 843 {
 844         u32 swsm;
 845
 846         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 847
 848         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 849         swsm &= ~IXGBE_SWSM_SMBI;
 850         IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 851
 852         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 853         swsm &= ~IXGBE_SWFW_REGSMP;
 854         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 855
 856         IXGBE_WRITE_FLUSH(hw);
 857 }
 858
 859 /**
 860  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 861  * @hw: pointer to hardware structure
 862  * @index: led number to blink
 863  *
 864  * Devices that implement the version 2 interface:
 865  *   X540
 866  **/
 867 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 868 {
 869         u32 macc_reg;
 870         u32 ledctl_reg;
 871         ixgbe_link_speed speed;
 872         bool link_up;
 873
 874         /*
 875          * Link should be up in order for the blink bit in the LED control
 876          * register to work. Force link and speed in the MAC if link is down.
 877          * This will be reversed when we stop the blinking.
 878          */
 879         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 880         if (link_up == false) {
 881                 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 882                 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 883                 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 884         }
 885         /* Set the LED to LINK_UP + BLINK. */
 886         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 887         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 888         ledctl_reg |= IXGBE_LED_BLINK(index);
 889         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 890         IXGBE_WRITE_FLUSH(hw);
 891
 892         return 0;
 893 }
 894
 895 /**
 896  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 897  * @hw: pointer to hardware structure
 898  * @index: led number to stop blinking
 899  *
 900  * Devices that implement the version 2 interface:
 901  *   X540
 902  **/
 903 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 904 {
 905         u32 macc_reg;
 906         u32 ledctl_reg;
 907
 908         /* Restore the LED to its default value. */
 909         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 910         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 911         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 912         ledctl_reg &= ~IXGBE_LED_BLINK(index);
 913         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 914
 915         /* Unforce link and speed in the MAC. */
 916         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 917         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
 918         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 919         IXGBE_WRITE_FLUSH(hw);
 920
 921         return 0;
 922 }