1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #ifndef _E1000_DEFINES_H_
29 #define _E1000_DEFINES_H_
31 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
32 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
33 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
35 /* Definitions for power management and wakeup registers */
37 #define E1000_WUC_APME 0x00000001 /* APM Enable */
38 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
39 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
40 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
41 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
43 /* Wake Up Filter Control */
44 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
45 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
46 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
47 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
48 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
49 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
50 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
51 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
54 #define E1000_WUS_LNKC E1000_WUFC_LNKC
55 #define E1000_WUS_MAG E1000_WUFC_MAG
56 #define E1000_WUS_EX E1000_WUFC_EX
57 #define E1000_WUS_MC E1000_WUFC_MC
58 #define E1000_WUS_BC E1000_WUFC_BC
60 /* Extended Device Control */
61 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
62 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
63 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
64 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
65 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
66 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
67 /* Physical Func Reset Done Indication */
68 #define E1000_CTRL_EXT_PFRSTD 0x00004000
69 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
70 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
71 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */
72 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
73 /* Offset of the link mode field in Ctrl Ext register */
74 #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22
75 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
76 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
77 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
78 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
79 #define E1000_CTRL_EXT_EIAME 0x01000000
80 #define E1000_CTRL_EXT_IRCA 0x00000001
81 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
82 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
83 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
84 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
85 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
86 #define E1000_I2CCMD_OPCODE_READ 0x08000000
87 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
88 #define E1000_I2CCMD_READY 0x20000000
89 #define E1000_I2CCMD_ERROR 0x80000000
90 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
91 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
92 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
93 #define E1000_I2CCMD_PHY_TIMEOUT 200
94 #define E1000_IVAR_VALID 0x80
95 #define E1000_GPIE_NSICR 0x00000001
96 #define E1000_GPIE_MSIX_MODE 0x00000010
97 #define E1000_GPIE_EIAME 0x40000000
98 #define E1000_GPIE_PBA 0x80000000
100 /* Receive Descriptor bit definitions */
101 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
102 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
103 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
104 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
105 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
106 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
107 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
108 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
109 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
110 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
111 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
112 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
113 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
114 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
115 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
116 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
117 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
118 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
119 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
121 #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */
122 #define E1000_RXDEXT_STATERR_LB 0x00040000
123 #define E1000_RXDEXT_STATERR_CE 0x01000000
124 #define E1000_RXDEXT_STATERR_SE 0x02000000
125 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
126 #define E1000_RXDEXT_STATERR_CXE 0x10000000
127 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
128 #define E1000_RXDEXT_STATERR_IPE 0x40000000
129 #define E1000_RXDEXT_STATERR_RXE 0x80000000
131 /* mask to determine if packets should be dropped due to frame errors */
132 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
135 E1000_RXD_ERR_SEQ | \
136 E1000_RXD_ERR_CXE | \
139 /* Same mask, but for extended and packet split descriptors */
140 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
141 E1000_RXDEXT_STATERR_CE | \
142 E1000_RXDEXT_STATERR_SE | \
143 E1000_RXDEXT_STATERR_SEQ | \
144 E1000_RXDEXT_STATERR_CXE | \
145 E1000_RXDEXT_STATERR_RXE)
147 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
148 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
149 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
150 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
151 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
152 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
154 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
156 /* Management Control */
157 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
158 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
159 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
160 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
161 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
162 /* Enable MAC address filtering */
163 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
164 /* Enable MNG packets to host memory */
165 #define E1000_MANC_EN_MNG2HOST 0x00200000
167 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
168 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
169 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
170 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
172 /* Receive Control */
173 #define E1000_RCTL_RST 0x00000001 /* Software reset */
174 #define E1000_RCTL_EN 0x00000002 /* enable */
175 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
176 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
177 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
178 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
179 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
180 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
181 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
182 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
183 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
184 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
185 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
186 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
187 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
188 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
189 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
190 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
191 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
192 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
193 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
194 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
195 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
196 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
197 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
198 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
199 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
200 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
201 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
202 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
204 /* Use byte values for the following shift parameters
206 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
207 * E1000_PSRCTL_BSIZE0_MASK) |
208 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
209 * E1000_PSRCTL_BSIZE1_MASK) |
210 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
211 * E1000_PSRCTL_BSIZE2_MASK) |
212 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
213 * E1000_PSRCTL_BSIZE3_MASK))
214 * where value0 = [128..16256], default=256
215 * value1 = [1024..64512], default=4096
216 * value2 = [0..64512], default=4096
217 * value3 = [0..64512], default=0
220 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
221 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
222 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
223 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
225 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
226 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
227 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
228 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
230 /* SWFW_SYNC Definitions */
231 #define E1000_SWFW_EEP_SM 0x01
232 #define E1000_SWFW_PHY0_SM 0x02
233 #define E1000_SWFW_PHY1_SM 0x04
234 #define E1000_SWFW_CSR_SM 0x08
235 #define E1000_SWFW_PHY2_SM 0x20
236 #define E1000_SWFW_PHY3_SM 0x40
237 #define E1000_SWFW_SW_MNG_SM 0x400
240 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
241 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
242 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
243 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
244 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
245 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
246 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
247 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
248 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
249 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
250 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
251 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
252 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
253 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
254 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
255 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
256 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
257 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
258 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
259 #define E1000_CTRL_RST 0x04000000 /* Global reset */
260 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
261 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
262 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
263 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
264 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
267 #define E1000_CONNSW_ENRGSRC 0x4
268 #define E1000_CONNSW_PHYSD 0x400
269 #define E1000_CONNSW_PHY_PDN 0x800
270 #define E1000_CONNSW_SERDESD 0x200
271 #define E1000_CONNSW_AUTOSENSE_CONF 0x2
272 #define E1000_CONNSW_AUTOSENSE_EN 0x1
273 #define E1000_PCS_CFG_PCS_EN 8
274 #define E1000_PCS_LCTL_FLV_LINK_UP 1
275 #define E1000_PCS_LCTL_FSV_10 0
276 #define E1000_PCS_LCTL_FSV_100 2
277 #define E1000_PCS_LCTL_FSV_1000 4
278 #define E1000_PCS_LCTL_FDV_FULL 8
279 #define E1000_PCS_LCTL_FSD 0x10
280 #define E1000_PCS_LCTL_FORCE_LINK 0x20
281 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
282 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
283 #define E1000_PCS_LCTL_AN_RESTART 0x20000
284 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
285 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
287 #define E1000_PCS_LSTS_LINK_OK 1
288 #define E1000_PCS_LSTS_SPEED_100 2
289 #define E1000_PCS_LSTS_SPEED_1000 4
290 #define E1000_PCS_LSTS_DUPLEX_FULL 8
291 #define E1000_PCS_LSTS_SYNK_OK 0x10
292 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
295 #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */
296 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
297 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
298 #define E1000_STATUS_FUNC_SHIFT 2
299 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
300 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
301 #define E1000_STATUS_SPEED_MASK 0x000000C0
302 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
303 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
304 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
305 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */
306 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
307 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
308 #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */
309 #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */
312 #define SPEED_100 100
313 #define SPEED_1000 1000
314 #define SPEED_2500 2500
315 #define HALF_DUPLEX 1
316 #define FULL_DUPLEX 2
319 #define ADVERTISE_10_HALF 0x0001
320 #define ADVERTISE_10_FULL 0x0002
321 #define ADVERTISE_100_HALF 0x0004
322 #define ADVERTISE_100_FULL 0x0008
323 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
324 #define ADVERTISE_1000_FULL 0x0020
326 /* 1000/H is not supported, nor spec-compliant. */
327 #define E1000_ALL_SPEED_DUPLEX ( \
328 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
329 ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
330 #define E1000_ALL_NOT_GIG ( \
331 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
333 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
334 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
335 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
337 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
340 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
341 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
342 #define E1000_LEDCTL_LED0_IVRT 0x00000040
343 #define E1000_LEDCTL_LED0_BLINK 0x00000080
345 #define E1000_LEDCTL_MODE_LED_ON 0xE
346 #define E1000_LEDCTL_MODE_LED_OFF 0xF
348 /* Transmit Descriptor bit definitions */
349 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
350 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
351 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
352 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
353 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
354 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
355 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
356 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
357 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
358 #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
359 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
360 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
361 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
362 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
363 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
364 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
365 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
366 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
367 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
368 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
369 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
371 /* Transmit Control */
372 #define E1000_TCTL_EN 0x00000002 /* enable Tx */
373 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
374 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
375 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
376 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
377 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
379 /* Transmit Arbitration Count */
380 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
383 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
384 #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
386 /* Receive Checksum Control */
387 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
388 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
389 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
390 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
391 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
393 /* Header split receive */
394 #define E1000_RFCTL_NFSW_DIS 0x00000040
395 #define E1000_RFCTL_NFSR_DIS 0x00000080
396 #define E1000_RFCTL_ACK_DIS 0x00001000
397 #define E1000_RFCTL_EXTEN 0x00008000
398 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
399 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
400 #define E1000_RFCTL_LEF 0x00040000
402 /* Collision related configuration parameters */
403 #define E1000_COLLISION_THRESHOLD 15
404 #define E1000_CT_SHIFT 4
405 #define E1000_COLLISION_DISTANCE 63
406 #define E1000_COLD_SHIFT 12
408 /* Default values for the transmit IPG register */
409 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
410 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
412 #define E1000_TIPG_IPGT_MASK 0x000003FF
414 #define DEFAULT_82543_TIPG_IPGR1 8
415 #define E1000_TIPG_IPGR1_SHIFT 10
417 #define DEFAULT_82543_TIPG_IPGR2 6
418 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
419 #define E1000_TIPG_IPGR2_SHIFT 20
421 /* Ethertype field values */
422 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
424 #define ETHERNET_FCS_SIZE 4
425 #define MAX_JUMBO_FRAME_SIZE 0x3F00
427 /* Extended Configuration Control and Size */
428 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
429 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
430 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
431 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
432 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
433 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
434 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
435 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
436 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
438 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
439 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
440 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
441 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
443 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
446 #define E1000_PBA_8K 0x0008 /* 8KB */
447 #define E1000_PBA_10K 0x000A /* 10KB */
448 #define E1000_PBA_12K 0x000C /* 12KB */
449 #define E1000_PBA_14K 0x000E /* 14KB */
450 #define E1000_PBA_16K 0x0010 /* 16KB */
451 #define E1000_PBA_18K 0x0012
452 #define E1000_PBA_20K 0x0014
453 #define E1000_PBA_22K 0x0016
454 #define E1000_PBA_24K 0x0018
455 #define E1000_PBA_26K 0x001A
456 #define E1000_PBA_30K 0x001E
457 #define E1000_PBA_32K 0x0020
458 #define E1000_PBA_34K 0x0022
459 #define E1000_PBA_35K 0x0023
460 #define E1000_PBA_38K 0x0026
461 #define E1000_PBA_40K 0x0028
462 #define E1000_PBA_48K 0x0030 /* 48KB */
463 #define E1000_PBA_64K 0x0040 /* 64KB */
465 #define E1000_PBA_RXA_MASK 0xFFFF
467 #define E1000_PBS_16K E1000_PBA_16K
473 #define MIN_NUM_XMITS 1000
475 /* SW Semaphore Register */
476 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
477 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
478 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
480 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
482 /* Interrupt Cause Read */
483 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
484 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
485 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
486 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
487 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
488 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */
489 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
490 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */
491 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
492 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
493 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
494 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
495 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
496 #define E1000_ICR_TXD_LOW 0x00008000
497 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
498 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
499 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
500 /* If this bit asserted, the driver should claim the interrupt */
501 #define E1000_ICR_INT_ASSERTED 0x80000000
502 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
503 #define E1000_ICR_FER 0x00400000 /* Fatal Error */
505 #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/
506 #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */
509 /* Extended Interrupt Cause Read */
510 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
511 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
512 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
513 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
514 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
515 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
516 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
517 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
518 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
519 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
521 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
522 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
523 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
524 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
526 /* This defines the bits that are set in the Interrupt Mask
527 * Set/Read Register. Each bit is documented below:
528 * o RXT0 = Receiver Timer Interrupt (ring 0)
529 * o TXDW = Transmit Descriptor Written Back
530 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
531 * o RXSEQ = Receive Sequence Error
532 * o LSC = Link Status Change
534 #define IMS_ENABLE_MASK ( \
541 /* Interrupt Mask Set */
542 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */
543 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
544 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
545 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */
546 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
547 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
548 #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */
549 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
550 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
551 #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */
552 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
553 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
554 #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */
556 #define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
557 #define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */
558 /* Extended Interrupt Mask Set */
559 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
560 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
561 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
562 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
563 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
564 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
565 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
566 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
567 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
568 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
570 /* Interrupt Cause Set */
571 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
572 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
573 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
575 /* Extended Interrupt Cause Set */
576 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
577 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
578 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
579 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
580 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
581 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
582 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
583 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
584 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */
585 #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */
587 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF
588 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
589 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
590 #define E1000_EITR_INTERVAL 0x00007FFC
592 /* Transmit Descriptor Control */
593 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
594 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
595 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
596 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
597 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
598 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
599 /* Enable the counting of descriptors still to be processed. */
600 #define E1000_TXDCTL_COUNT_DESC 0x00400000
602 /* Flow Control Constants */
603 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
604 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
605 #define FLOW_CONTROL_TYPE 0x8808
607 /* 802.1q VLAN Packet Size */
608 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
609 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
612 * Number of high/low register pairs in the RAR. The RAR (Receive Address
613 * Registers) holds the directed and multicast addresses that we monitor.
614 * Technically, we have 16 spots. However, we reserve one of these spots
615 * (RAR[15]) for our directed address used by controllers with
616 * manageability enabled, allowing us room for 15 multicast addresses.
618 #define E1000_RAR_ENTRIES 15
619 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
620 #define E1000_RAL_MAC_ADDR_LEN 4
621 #define E1000_RAH_MAC_ADDR_LEN 2
622 #define E1000_RAH_QUEUE_MASK_82575 0x000C0000
623 #define E1000_RAH_POOL_1 0x00040000
626 #define E1000_SUCCESS 0
627 #define E1000_ERR_NVM 1
628 #define E1000_ERR_PHY 2
629 #define E1000_ERR_CONFIG 3
630 #define E1000_ERR_PARAM 4
631 #define E1000_ERR_MAC_INIT 5
632 #define E1000_ERR_PHY_TYPE 6
633 #define E1000_ERR_RESET 9
634 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
635 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
636 #define E1000_BLK_PHY_RESET 12
637 #define E1000_ERR_SWFW_SYNC 13
638 #define E1000_NOT_IMPLEMENTED 14
639 #define E1000_ERR_MBX 15
640 #define E1000_ERR_INVALID_ARGUMENT 16
641 #define E1000_ERR_NO_SPACE 17
642 #define E1000_ERR_NVM_PBA_SECTION 18
643 #define E1000_ERR_I2C 19
644 #define E1000_ERR_INVM_VALUE_NOT_FOUND 20
646 /* Loop limit on how long we wait for auto-negotiation to complete */
647 #define FIBER_LINK_UP_LIMIT 50
648 #define COPPER_LINK_UP_LIMIT 10
649 #define PHY_AUTO_NEG_LIMIT 45
650 #define PHY_FORCE_LIMIT 20
651 /* Number of 100 microseconds we wait for PCI Express master disable */
652 #define MASTER_DISABLE_TIMEOUT 800
653 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
654 #define PHY_CFG_TIMEOUT 100
655 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
656 #define MDIO_OWNERSHIP_TIMEOUT 10
657 /* Number of milliseconds for NVM auto read done after MAC reset. */
658 #define AUTO_READ_DONE_TIMEOUT 10
661 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
662 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
663 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
665 /* Transmit Configuration Word */
666 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
667 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
668 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
669 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
670 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
672 /* Receive Configuration Word */
673 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
674 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
675 #define E1000_RXCW_C 0x20000000 /* Receive config */
676 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
678 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
679 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
681 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
682 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
683 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
684 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
685 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
686 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08
687 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
688 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
689 #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
691 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
692 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
693 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
694 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
695 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
696 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
698 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
699 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
700 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
701 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
702 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
703 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
704 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
705 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
706 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
707 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
708 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
710 #define E1000_TIMINCA_16NS_SHIFT 24
711 #define E1000_TIMINCA_INCPERIOD_SHIFT 24
712 #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
714 #define E1000_TSICR_TXTS 0x00000002
715 #define E1000_TSIM_TXTS 0x00000002
716 /* TUPLE Filtering Configuration */
717 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
718 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
719 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
720 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
721 #define E1000_TTQF_PROTOCOL_TCP 0x0
722 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
723 #define E1000_TTQF_PROTOCOL_UDP 0x1
724 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
725 #define E1000_TTQF_PROTOCOL_SCTP 0x2
726 #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
727 #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
728 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
729 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
730 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
731 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
732 #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
733 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
735 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
736 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
737 #define E1000_MDICNFG_PHY_MASK 0x03E00000
738 #define E1000_MDICNFG_PHY_SHIFT 21
740 #define E1000_MEDIA_PORT_COPPER 1
741 #define E1000_MEDIA_PORT_OTHER 2
742 #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2
743 #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3
744 #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */
745 #define E1000_M88E1112_MAC_CTRL_1 0x10
746 #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */
747 #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7
748 #define E1000_M88E1112_PAGE_ADDR 0x16
749 #define E1000_M88E1112_STATUS 0x01
751 #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
752 #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
753 #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
754 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
755 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */
757 /* I350 EEE defines */
758 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
759 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
760 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
761 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
762 #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
764 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
765 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
766 #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
767 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
768 #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
769 #define E1000_M88E1543_EEE_CTRL_1 0x0
770 #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
771 #define E1000_EEE_ADV_DEV_I354 7
772 #define E1000_EEE_ADV_ADDR_I354 60
773 #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */
774 #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */
775 #define E1000_PCS_STATUS_DEV_I354 3
776 #define E1000_PCS_STATUS_ADDR_I354 1
777 #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
778 #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800
779 #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
780 #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */
781 #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */
782 /* PCI Express Control */
783 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
784 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
785 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
786 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
787 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
788 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
789 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
790 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
791 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
792 #define E1000_GCR_CAP_VER2 0x00040000
794 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
795 E1000_GCR_RXDSCW_NO_SNOOP | \
796 E1000_GCR_RXDSCR_NO_SNOOP | \
797 E1000_GCR_TXD_NO_SNOOP | \
798 E1000_GCR_TXDSCW_NO_SNOOP | \
799 E1000_GCR_TXDSCR_NO_SNOOP)
801 #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
803 /* mPHY address control and data registers */
804 #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */
805 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
806 #define E1000_MPHY_DATA 0x0E10 /* Data Register */
808 /* AFE CSR Offset for PCS CLK */
809 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004
810 /* Override for near end digital loopback. */
811 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
813 /* PHY Control Register */
814 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
815 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
816 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
817 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
818 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
819 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
820 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
821 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
822 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
823 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
824 #define MII_CR_SPEED_1000 0x0040
825 #define MII_CR_SPEED_100 0x2000
826 #define MII_CR_SPEED_10 0x0000
828 /* PHY Status Register */
829 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
830 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
831 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
832 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
833 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
834 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
835 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
836 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
837 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
838 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
839 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
840 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
841 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
842 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
843 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
845 /* Autoneg Advertisement Register */
846 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
847 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
848 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
849 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
850 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
851 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
852 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
853 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
854 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
855 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
857 /* Link Partner Ability Register (Base Page) */
858 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
859 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */
860 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
861 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
862 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
863 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
864 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
865 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
866 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */
867 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
868 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
870 /* Autoneg Expansion Register */
871 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
872 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */
873 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
874 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
875 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
877 /* 1000BASE-T Control Register */
878 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
879 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
880 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
881 /* 1=Repeater/switch device port 0=DTE device */
882 #define CR_1000T_REPEATER_DTE 0x0400
883 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
884 #define CR_1000T_MS_VALUE 0x0800
885 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
886 #define CR_1000T_MS_ENABLE 0x1000
887 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
888 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
889 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
890 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
891 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
893 /* 1000BASE-T Status Register */
894 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */
895 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
896 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
897 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
898 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
899 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
900 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
901 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
903 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
905 /* PHY 1000 MII Register/Bit Definitions */
906 /* PHY Registers defined by IEEE */
907 #define PHY_CONTROL 0x00 /* Control Register */
908 #define PHY_STATUS 0x01 /* Status Register */
909 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
910 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
911 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
912 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
913 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
914 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
915 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
916 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
917 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
918 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
920 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
923 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
924 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
925 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
926 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
927 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
928 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
929 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
930 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
931 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
932 #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */
933 #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */
934 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
935 /* NVM Addressing bits based on type 0=small, 1=large */
936 #define E1000_EECD_ADDR_BITS 0x00000400
937 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
938 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
939 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
940 #define E1000_EECD_SIZE_EX_SHIFT 11
941 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
942 #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */
943 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
944 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
945 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
946 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */
947 #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
948 #define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */
949 #define E1000_FLUDONE_ATTEMPTS 20000
950 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
951 #define E1000_I210_FIFO_SEL_RX 0x00
952 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
953 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
954 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
955 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
957 #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */
958 /* Secure FLASH mode requires removing MSb */
959 #define E1000_I210_FW_PTR_MASK 0x7FFF
960 /* Firmware code revision field word offset*/
961 #define E1000_I210_FW_VER_OFFSET 328
963 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */
964 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
965 #define E1000_NVM_RW_REG_START 1 /* Start operation */
966 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
967 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
968 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
969 #define E1000_FLASH_UPDATES 2000
971 /* NVM Word Offsets */
972 #define NVM_COMPAT 0x0003
973 #define NVM_ID_LED_SETTINGS 0x0004
974 #define NVM_VERSION 0x0005
975 #define E1000_I210_NVM_FW_MODULE_PTR 0x0010
976 #define E1000_I350_NVM_FW_MODULE_PTR 0x0051
977 #define NVM_FUTURE_INIT_WORD1 0x0019
978 #define NVM_ETRACK_WORD 0x0042
979 #define NVM_ETRACK_HIWORD 0x0043
980 #define NVM_COMB_VER_OFF 0x0083
981 #define NVM_COMB_VER_PTR 0x003d
983 /* NVM version defines */
984 #define NVM_MAJOR_MASK 0xF000
985 #define NVM_MINOR_MASK 0x0FF0
986 #define NVM_IMAGE_ID_MASK 0x000F
987 #define NVM_COMB_VER_MASK 0x00FF
988 #define NVM_MAJOR_SHIFT 12
989 #define NVM_MINOR_SHIFT 4
990 #define NVM_COMB_VER_SHFT 8
991 #define NVM_VER_INVALID 0xFFFF
992 #define NVM_ETRACK_SHIFT 16
993 #define NVM_ETRACK_VALID 0x8000
994 #define NVM_NEW_DEC_MASK 0x0F00
995 #define NVM_HEX_CONV 16
996 #define NVM_HEX_TENS 10
998 /* FW version defines */
999 /* Offset of "Loader patch ptr" in Firmware Header */
1000 #define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET 0x01
1001 /* Patch generation hour & minutes */
1002 #define E1000_I350_NVM_FW_VER_WORD1_OFFSET 0x04
1003 /* Patch generation month & day */
1004 #define E1000_I350_NVM_FW_VER_WORD2_OFFSET 0x05
1005 /* Patch generation year */
1006 #define E1000_I350_NVM_FW_VER_WORD3_OFFSET 0x06
1007 /* Patch major & minor numbers */
1008 #define E1000_I350_NVM_FW_VER_WORD4_OFFSET 0x07
1010 #define NVM_MAC_ADDR 0x0000
1011 #define NVM_SUB_DEV_ID 0x000B
1012 #define NVM_SUB_VEN_ID 0x000C
1013 #define NVM_DEV_ID 0x000D
1014 #define NVM_VEN_ID 0x000E
1015 #define NVM_INIT_CTRL_2 0x000F
1016 #define NVM_INIT_CTRL_4 0x0013
1017 #define NVM_LED_1_CFG 0x001C
1018 #define NVM_LED_0_2_CFG 0x001F
1020 #define NVM_COMPAT_VALID_CSUM 0x0001
1021 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
1023 #define NVM_ETS_CFG 0x003E
1024 #define NVM_ETS_LTHRES_DELTA_MASK 0x07C0
1025 #define NVM_ETS_LTHRES_DELTA_SHIFT 6
1026 #define NVM_ETS_TYPE_MASK 0x0038
1027 #define NVM_ETS_TYPE_SHIFT 3
1028 #define NVM_ETS_TYPE_EMC 0x000
1029 #define NVM_ETS_NUM_SENSORS_MASK 0x0007
1030 #define NVM_ETS_DATA_LOC_MASK 0x3C00
1031 #define NVM_ETS_DATA_LOC_SHIFT 10
1032 #define NVM_ETS_DATA_INDEX_MASK 0x0300
1033 #define NVM_ETS_DATA_INDEX_SHIFT 8
1034 #define NVM_ETS_DATA_HTHRESH_MASK 0x00FF
1035 #define NVM_INIT_CONTROL2_REG 0x000F
1036 #define NVM_INIT_CONTROL3_PORT_B 0x0014
1037 #define NVM_INIT_3GIO_3 0x001A
1038 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1039 #define NVM_INIT_CONTROL3_PORT_A 0x0024
1040 #define NVM_CFG 0x0012
1041 #define NVM_ALT_MAC_ADDR_PTR 0x0037
1042 #define NVM_CHECKSUM_REG 0x003F
1043 #define NVM_COMPATIBILITY_REG_3 0x0003
1044 #define NVM_COMPATIBILITY_BIT_MASK 0x8000
1046 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1047 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
1048 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
1049 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
1051 #define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0)
1053 /* Mask bits for fields in Word 0x24 of the NVM */
1054 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
1055 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */
1056 /* Offset of Link Mode bits for 82575/82576 */
1057 #define NVM_WORD24_LNK_MODE_OFFSET 8
1058 /* Offset of Link Mode bits for 82580 up */
1059 #define NVM_WORD24_82580_LNK_MODE_OFFSET 4
1062 /* Mask bits for fields in Word 0x0f of the NVM */
1063 #define NVM_WORD0F_PAUSE_MASK 0x3000
1064 #define NVM_WORD0F_PAUSE 0x1000
1065 #define NVM_WORD0F_ASM_DIR 0x2000
1067 /* Mask bits for fields in Word 0x1a of the NVM */
1068 #define NVM_WORD1A_ASPM_MASK 0x000C
1070 /* Mask bits for fields in Word 0x03 of the EEPROM */
1071 #define NVM_COMPAT_LOM 0x0800
1073 /* length of string needed to store PBA number */
1074 #define E1000_PBANUM_LENGTH 11
1076 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1077 #define NVM_SUM 0xBABA
1079 /* PBA (printed board assembly) number words */
1080 #define NVM_PBA_OFFSET_0 8
1081 #define NVM_PBA_OFFSET_1 9
1082 #define NVM_PBA_PTR_GUARD 0xFAFA
1083 #define NVM_RESERVED_WORD 0xFFFF
1084 #define NVM_WORD_SIZE_BASE_SHIFT 6
1086 /* NVM Commands - SPI */
1087 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1088 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1089 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1090 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1091 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1092 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1094 /* SPI NVM Status Register */
1095 #define NVM_STATUS_RDY_SPI 0x01
1097 /* Word definitions for ID LED Settings */
1098 #define ID_LED_RESERVED_0000 0x0000
1099 #define ID_LED_RESERVED_FFFF 0xFFFF
1100 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1101 (ID_LED_OFF1_OFF2 << 8) | \
1102 (ID_LED_DEF1_DEF2 << 4) | \
1104 #define ID_LED_DEF1_DEF2 0x1
1105 #define ID_LED_DEF1_ON2 0x2
1106 #define ID_LED_DEF1_OFF2 0x3
1107 #define ID_LED_ON1_DEF2 0x4
1108 #define ID_LED_ON1_ON2 0x5
1109 #define ID_LED_ON1_OFF2 0x6
1110 #define ID_LED_OFF1_DEF2 0x7
1111 #define ID_LED_OFF1_ON2 0x8
1112 #define ID_LED_OFF1_OFF2 0x9
1114 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1115 #define IGP_ACTIVITY_LED_ENABLE 0x0300
1116 #define IGP_LED3_MODE 0x07000000
1118 /* PCI/PCI-X/PCI-EX Config space */
1119 #define PCI_HEADER_TYPE_REGISTER 0x0E
1120 #define PCIE_LINK_STATUS 0x12
1121 #define PCIE_DEVICE_CONTROL2 0x28
1123 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
1124 #define PCIE_LINK_WIDTH_MASK 0x3F0
1125 #define PCIE_LINK_WIDTH_SHIFT 4
1126 #define PCIE_LINK_SPEED_MASK 0x0F
1127 #define PCIE_LINK_SPEED_2500 0x01
1128 #define PCIE_LINK_SPEED_5000 0x02
1129 #define PCIE_DEVICE_CONTROL2_16ms 0x0005
1131 #ifndef ETH_ADDR_LEN
1132 #define ETH_ADDR_LEN 6
1135 #define PHY_REVISION_MASK 0xFFFFFFF0
1136 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1137 #define MAX_PHY_MULTI_PAGE_REG 0xF
1139 /* Bit definitions for valid PHY IDs.
1143 #define M88E1000_E_PHY_ID 0x01410C50
1144 #define M88E1000_I_PHY_ID 0x01410C30
1145 #define M88E1011_I_PHY_ID 0x01410C20
1146 #define IGP01E1000_I_PHY_ID 0x02A80380
1147 #define M88E1111_I_PHY_ID 0x01410CC0
1148 #define M88E1543_E_PHY_ID 0x01410EA0
1149 #define M88E1112_E_PHY_ID 0x01410C90
1150 #define I347AT4_E_PHY_ID 0x01410DC0
1151 #define M88E1340M_E_PHY_ID 0x01410DF0
1152 #define GG82563_E_PHY_ID 0x01410CA0
1153 #define IGP03E1000_E_PHY_ID 0x02A80390
1154 #define IFE_E_PHY_ID 0x02A80330
1155 #define IFE_PLUS_E_PHY_ID 0x02A80320
1156 #define IFE_C_E_PHY_ID 0x02A80310
1157 #define I82580_I_PHY_ID 0x015403A0
1158 #define I350_I_PHY_ID 0x015403B0
1159 #define I210_I_PHY_ID 0x01410C00
1160 #define IGP04E1000_E_PHY_ID 0x02A80391
1161 #define M88_VENDOR 0x0141
1163 /* M88E1000 Specific Registers */
1164 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
1165 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */
1166 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */
1167 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1169 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */
1170 #define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */
1172 /* M88E1000 PHY Specific Control Register */
1173 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1174 /* MDI Crossover Mode bits 6:5 Manual MDI configuration */
1175 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
1176 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1177 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1178 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
1179 /* Auto crossover enabled all speeds */
1180 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
1181 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1183 /* M88E1000 PHY Specific Status Register */
1184 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1185 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1186 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1193 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
1194 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1195 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1196 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1197 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1199 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1201 /* Number of times we will attempt to autonegotiate before downshifting if we
1204 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1205 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1206 /* Number of times we will attempt to autonegotiate before downshifting if we
1209 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1210 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1211 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1213 /* Intel I347AT4 Registers */
1214 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
1215 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
1216 #define I347AT4_PAGE_SELECT 0x16
1218 /* I347AT4 Extended PHY Specific Control Register */
1220 /* Number of times we will attempt to autonegotiate before downshifting if we
1223 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
1224 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
1225 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
1226 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
1227 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
1228 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
1229 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
1230 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
1231 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
1232 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
1234 /* I347AT4 PHY Cable Diagnostics Control */
1235 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
1237 /* M88E1112 only registers */
1238 #define M88E1112_VCT_DSP_DISTANCE 0x001A
1240 /* M88EC018 Rev 2 specific DownShift settings */
1241 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1242 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1246 * 4-0: register offset
1248 #define GG82563_PAGE_SHIFT 5
1249 #define GG82563_REG(page, reg) \
1250 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1251 #define GG82563_MIN_ALT_REG 30
1253 /* GG82563 Specific Registers */
1254 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
1255 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
1256 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
1257 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
1259 /* MAC Specific Control Register */
1260 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
1262 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */
1264 /* Page 193 - Port Control Registers */
1265 /* Kumeran Mode Control */
1266 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16)
1267 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
1269 /* Page 194 - KMRN Registers */
1270 #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */
1273 #define E1000_MDIC_REG_MASK 0x001F0000
1274 #define E1000_MDIC_REG_SHIFT 16
1275 #define E1000_MDIC_PHY_MASK 0x03E00000
1276 #define E1000_MDIC_PHY_SHIFT 21
1277 #define E1000_MDIC_OP_WRITE 0x04000000
1278 #define E1000_MDIC_OP_READ 0x08000000
1279 #define E1000_MDIC_READY 0x10000000
1280 #define E1000_MDIC_ERROR 0x40000000
1281 #define E1000_MDIC_DEST 0x80000000
1283 /* SerDes Control */
1284 #define E1000_GEN_CTL_READY 0x80000000
1285 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
1286 #define E1000_GEN_POLL_TIMEOUT 640
1288 /* LinkSec register fields */
1289 #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1290 #define E1000_LSECTXCAP_SUM_SHIFT 16
1291 #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1292 #define E1000_LSECRXCAP_SUM_SHIFT 16
1294 #define E1000_LSECTXCTRL_EN_MASK 0x00000003
1295 #define E1000_LSECTXCTRL_DISABLE 0x0
1296 #define E1000_LSECTXCTRL_AUTH 0x1
1297 #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1298 #define E1000_LSECTXCTRL_AISCI 0x00000020
1299 #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1300 #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1302 #define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1303 #define E1000_LSECRXCTRL_EN_SHIFT 2
1304 #define E1000_LSECRXCTRL_DISABLE 0x0
1305 #define E1000_LSECRXCTRL_CHECK 0x1
1306 #define E1000_LSECRXCTRL_STRICT 0x2
1307 #define E1000_LSECRXCTRL_DROP 0x3
1308 #define E1000_LSECRXCTRL_PLSH 0x00000040
1309 #define E1000_LSECRXCTRL_RP 0x00000080
1310 #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1312 /* Tx Rate-Scheduler Config fields */
1313 #define E1000_RTTBCNRC_RS_ENA 0x80000000
1314 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1315 #define E1000_RTTBCNRC_RF_INT_SHIFT 14
1316 #define E1000_RTTBCNRC_RF_INT_MASK \
1317 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
1319 /* DMA Coalescing register fields */
1320 /* DMA Coalescing Watchdog Timer */
1321 #define E1000_DMACR_DMACWT_MASK 0x00003FFF
1322 /* DMA Coalescing Rx Threshold */
1323 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000
1324 #define E1000_DMACR_DMACTHR_SHIFT 16
1325 /* Lx when no PCIe transactions */
1326 #define E1000_DMACR_DMAC_LX_MASK 0x30000000
1327 #define E1000_DMACR_DMAC_LX_SHIFT 28
1328 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1329 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1330 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
1332 /* DMA Coalescing Transmit Threshold */
1333 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
1335 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
1337 /* Rx Traffic Rate Threshold */
1338 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
1339 /* Rx packet rate in current window */
1340 #define E1000_DMCRTRH_LRPRCW 0x80000000
1342 /* DMA Coal Rx Traffic Current Count */
1343 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
1345 /* Flow ctrl Rx Threshold High val */
1346 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
1347 #define E1000_FCRTC_RTH_COAL_SHIFT 4
1348 /* Lx power decision based on DMA coal */
1349 #define E1000_PCIEMISC_LX_DECISION 0x00000080
1351 #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1352 #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
1353 #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */
1355 /* Proxy Filter Control */
1356 #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1357 #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */
1358 #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */
1359 #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1360 #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */
1361 #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1362 #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
1363 #define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */
1364 #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */
1366 #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */
1368 /* Firmware Status */
1369 #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */
1371 #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */
1373 #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */
1374 /* Lan ID bit field offset in status register */
1375 #define E1000_STATUS_LAN_ID_OFFSET 2
1376 #define E1000_VFTA_ENTRIES 128
1377 #ifndef E1000_UNUSEDARG
1378 #define E1000_UNUSEDARG
1379 #endif /* E1000_UNUSEDARG */
1380 #endif /* _E1000_DEFINES_H_ */
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