lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "LICENSE.GPL".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_HW_H_
  29 #define _E1000_HW_H_
  30
  31 #include "e1000_osdep.h"
  32 #include "e1000_regs.h"
  33 #include "e1000_defines.h"
  34
  35 struct e1000_hw;
  36
  37 #define E1000_DEV_ID_82576                      0x10C9
  38 #define E1000_DEV_ID_82576_FIBER                0x10E6
  39 #define E1000_DEV_ID_82576_SERDES               0x10E7
  40 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
  41 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
  42 #define E1000_DEV_ID_82576_NS                   0x150A
  43 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
  44 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
  45 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
  46 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
  47 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
  48 #define E1000_DEV_ID_82580_COPPER               0x150E
  49 #define E1000_DEV_ID_82580_FIBER                0x150F
  50 #define E1000_DEV_ID_82580_SERDES               0x1510
  51 #define E1000_DEV_ID_82580_SGMII                0x1511
  52 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
  53 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
  54 #define E1000_DEV_ID_I350_COPPER                0x1521
  55 #define E1000_DEV_ID_I350_FIBER                 0x1522
  56 #define E1000_DEV_ID_I350_SERDES                0x1523
  57 #define E1000_DEV_ID_I350_SGMII                 0x1524
  58 #define E1000_DEV_ID_I350_DA4                   0x1546
  59 #define E1000_DEV_ID_I210_COPPER                0x1533
  60 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
  61 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
  62 #define E1000_DEV_ID_I210_FIBER                 0x1536
  63 #define E1000_DEV_ID_I210_SERDES                0x1537
  64 #define E1000_DEV_ID_I210_SGMII                 0x1538
  65 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
  66 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
  67 #define E1000_DEV_ID_I211_COPPER                0x1539
  68 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
  69 #define E1000_DEV_ID_I354_SGMII                 0x1F41
  70 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
  71 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
  72 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
  73 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
  74 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
  75
  76 #define E1000_REVISION_0        0
  77 #define E1000_REVISION_1        1
  78 #define E1000_REVISION_2        2
  79 #define E1000_REVISION_3        3
  80 #define E1000_REVISION_4        4
  81
  82 #define E1000_FUNC_0            0
  83 #define E1000_FUNC_1            1
  84 #define E1000_FUNC_2            2
  85 #define E1000_FUNC_3            3
  86
  87 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
  88 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
  89 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
  90 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
  91
  92 enum e1000_mac_type {
  93         e1000_undefined = 0,
  94         e1000_82575,
  95         e1000_82576,
  96         e1000_82580,
  97         e1000_i350,
  98         e1000_i354,
  99         e1000_i210,
 100         e1000_i211,
 101         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 102 };
 103
 104 enum e1000_media_type {
 105         e1000_media_type_unknown = 0,
 106         e1000_media_type_copper = 1,
 107         e1000_media_type_fiber = 2,
 108         e1000_media_type_internal_serdes = 3,
 109         e1000_num_media_types
 110 };
 111
 112 enum e1000_nvm_type {
 113         e1000_nvm_unknown = 0,
 114         e1000_nvm_none,
 115         e1000_nvm_eeprom_spi,
 116         e1000_nvm_flash_hw,
 117         e1000_nvm_invm,
 118         e1000_nvm_flash_sw
 119 };
 120
 121 enum e1000_nvm_override {
 122         e1000_nvm_override_none = 0,
 123         e1000_nvm_override_spi_small,
 124         e1000_nvm_override_spi_large,
 125 };
 126
 127 enum e1000_phy_type {
 128         e1000_phy_unknown = 0,
 129         e1000_phy_none,
 130         e1000_phy_m88,
 131         e1000_phy_igp,
 132         e1000_phy_igp_2,
 133         e1000_phy_gg82563,
 134         e1000_phy_igp_3,
 135         e1000_phy_ife,
 136         e1000_phy_82580,
 137         e1000_phy_vf,
 138         e1000_phy_i210,
 139 };
 140
 141 enum e1000_bus_type {
 142         e1000_bus_type_unknown = 0,
 143         e1000_bus_type_pci,
 144         e1000_bus_type_pcix,
 145         e1000_bus_type_pci_express,
 146         e1000_bus_type_reserved
 147 };
 148
 149 enum e1000_bus_speed {
 150         e1000_bus_speed_unknown = 0,
 151         e1000_bus_speed_33,
 152         e1000_bus_speed_66,
 153         e1000_bus_speed_100,
 154         e1000_bus_speed_120,
 155         e1000_bus_speed_133,
 156         e1000_bus_speed_2500,
 157         e1000_bus_speed_5000,
 158         e1000_bus_speed_reserved
 159 };
 160
 161 enum e1000_bus_width {
 162         e1000_bus_width_unknown = 0,
 163         e1000_bus_width_pcie_x1,
 164         e1000_bus_width_pcie_x2,
 165         e1000_bus_width_pcie_x4 = 4,
 166         e1000_bus_width_pcie_x8 = 8,
 167         e1000_bus_width_32,
 168         e1000_bus_width_64,
 169         e1000_bus_width_reserved
 170 };
 171
 172 enum e1000_1000t_rx_status {
 173         e1000_1000t_rx_status_not_ok = 0,
 174         e1000_1000t_rx_status_ok,
 175         e1000_1000t_rx_status_undefined = 0xFF
 176 };
 177
 178 enum e1000_rev_polarity {
 179         e1000_rev_polarity_normal = 0,
 180         e1000_rev_polarity_reversed,
 181         e1000_rev_polarity_undefined = 0xFF
 182 };
 183
 184 enum e1000_fc_mode {
 185         e1000_fc_none = 0,
 186         e1000_fc_rx_pause,
 187         e1000_fc_tx_pause,
 188         e1000_fc_full,
 189         e1000_fc_default = 0xFF
 190 };
 191
 192 enum e1000_ms_type {
 193         e1000_ms_hw_default = 0,
 194         e1000_ms_force_master,
 195         e1000_ms_force_slave,
 196         e1000_ms_auto
 197 };
 198
 199 enum e1000_smart_speed {
 200         e1000_smart_speed_default = 0,
 201         e1000_smart_speed_on,
 202         e1000_smart_speed_off
 203 };
 204
 205 enum e1000_serdes_link_state {
 206         e1000_serdes_link_down = 0,
 207         e1000_serdes_link_autoneg_progress,
 208         e1000_serdes_link_autoneg_complete,
 209         e1000_serdes_link_forced_up
 210 };
 211
 212 #ifndef __le16
 213 #define __le16 u16
 214 #endif
 215 #ifndef __le32
 216 #define __le32 u32
 217 #endif
 218 #ifndef __le64
 219 #define __le64 u64
 220 #endif
 221 /* Receive Descriptor */
 222 struct e1000_rx_desc {
 223         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 224         __le16 length;      /* Length of data DMAed into data buffer */
 225         __le16 csum; /* Packet checksum */
 226         u8  status;  /* Descriptor status */
 227         u8  errors;  /* Descriptor Errors */
 228         __le16 special;
 229 };
 230
 231 /* Receive Descriptor - Extended */
 232 union e1000_rx_desc_extended {
 233         struct {
 234                 __le64 buffer_addr;
 235                 __le64 reserved;
 236         } read;
 237         struct {
 238                 struct {
 239                         __le32 mrq; /* Multiple Rx Queues */
 240                         union {
 241                                 __le32 rss; /* RSS Hash */
 242                                 struct {
 243                                         __le16 ip_id;  /* IP id */
 244                                         __le16 csum;   /* Packet Checksum */
 245                                 } csum_ip;
 246                         } hi_dword;
 247                 } lower;
 248                 struct {
 249                         __le32 status_error;  /* ext status/error */
 250                         __le16 length;
 251                         __le16 vlan; /* VLAN tag */
 252                 } upper;
 253         } wb;  /* writeback */
 254 };
 255
 256 #define MAX_PS_BUFFERS 4
 257
 258 /* Number of packet split data buffers (not including the header buffer) */
 259 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 260
 261 /* Receive Descriptor - Packet Split */
 262 union e1000_rx_desc_packet_split {
 263         struct {
 264                 /* one buffer for protocol header(s), three data buffers */
 265                 __le64 buffer_addr[MAX_PS_BUFFERS];
 266         } read;
 267         struct {
 268                 struct {
 269                         __le32 mrq;  /* Multiple Rx Queues */
 270                         union {
 271                                 __le32 rss; /* RSS Hash */
 272                                 struct {
 273                                         __le16 ip_id;    /* IP id */
 274                                         __le16 csum;     /* Packet Checksum */
 275                                 } csum_ip;
 276                         } hi_dword;
 277                 } lower;
 278                 struct {
 279                         __le32 status_error;  /* ext status/error */
 280                         __le16 length0;  /* length of buffer 0 */
 281                         __le16 vlan;  /* VLAN tag */
 282                 } middle;
 283                 struct {
 284                         __le16 header_status;
 285                         /* length of buffers 1-3 */
 286                         __le16 length[PS_PAGE_BUFFERS];
 287                 } upper;
 288                 __le64 reserved;
 289         } wb; /* writeback */
 290 };
 291
 292 /* Transmit Descriptor */
 293 struct e1000_tx_desc {
 294         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 295         union {
 296                 __le32 data;
 297                 struct {
 298                         __le16 length;  /* Data buffer length */
 299                         u8 cso;  /* Checksum offset */
 300                         u8 cmd;  /* Descriptor control */
 301                 } flags;
 302         } lower;
 303         union {
 304                 __le32 data;
 305                 struct {
 306                         u8 status; /* Descriptor status */
 307                         u8 css;  /* Checksum start */
 308                         __le16 special;
 309                 } fields;
 310         } upper;
 311 };
 312
 313 /* Offload Context Descriptor */
 314 struct e1000_context_desc {
 315         union {
 316                 __le32 ip_config;
 317                 struct {
 318                         u8 ipcss;  /* IP checksum start */
 319                         u8 ipcso;  /* IP checksum offset */
 320                         __le16 ipcse;  /* IP checksum end */
 321                 } ip_fields;
 322         } lower_setup;
 323         union {
 324                 __le32 tcp_config;
 325                 struct {
 326                         u8 tucss;  /* TCP checksum start */
 327                         u8 tucso;  /* TCP checksum offset */
 328                         __le16 tucse;  /* TCP checksum end */
 329                 } tcp_fields;
 330         } upper_setup;
 331         __le32 cmd_and_length;
 332         union {
 333                 __le32 data;
 334                 struct {
 335                         u8 status;  /* Descriptor status */
 336                         u8 hdr_len;  /* Header length */
 337                         __le16 mss;  /* Maximum segment size */
 338                 } fields;
 339         } tcp_seg_setup;
 340 };
 341
 342 /* Offload data descriptor */
 343 struct e1000_data_desc {
 344         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 345         union {
 346                 __le32 data;
 347                 struct {
 348                         __le16 length;  /* Data buffer length */
 349                         u8 typ_len_ext;
 350                         u8 cmd;
 351                 } flags;
 352         } lower;
 353         union {
 354                 __le32 data;
 355                 struct {
 356                         u8 status;  /* Descriptor status */
 357                         u8 popts;  /* Packet Options */
 358                         __le16 special;
 359                 } fields;
 360         } upper;
 361 };
 362
 363 /* Statistics counters collected by the MAC */
 364 struct e1000_hw_stats {
 365         u64 crcerrs;
 366         u64 algnerrc;
 367         u64 symerrs;
 368         u64 rxerrc;
 369         u64 mpc;
 370         u64 scc;
 371         u64 ecol;
 372         u64 mcc;
 373         u64 latecol;
 374         u64 colc;
 375         u64 dc;
 376         u64 tncrs;
 377         u64 sec;
 378         u64 cexterr;
 379         u64 rlec;
 380         u64 xonrxc;
 381         u64 xontxc;
 382         u64 xoffrxc;
 383         u64 xofftxc;
 384         u64 fcruc;
 385         u64 prc64;
 386         u64 prc127;
 387         u64 prc255;
 388         u64 prc511;
 389         u64 prc1023;
 390         u64 prc1522;
 391         u64 gprc;
 392         u64 bprc;
 393         u64 mprc;
 394         u64 gptc;
 395         u64 gorc;
 396         u64 gotc;
 397         u64 rnbc;
 398         u64 ruc;
 399         u64 rfc;
 400         u64 roc;
 401         u64 rjc;
 402         u64 mgprc;
 403         u64 mgpdc;
 404         u64 mgptc;
 405         u64 tor;
 406         u64 tot;
 407         u64 tpr;
 408         u64 tpt;
 409         u64 ptc64;
 410         u64 ptc127;
 411         u64 ptc255;
 412         u64 ptc511;
 413         u64 ptc1023;
 414         u64 ptc1522;
 415         u64 mptc;
 416         u64 bptc;
 417         u64 tsctc;
 418         u64 tsctfc;
 419         u64 iac;
 420         u64 icrxptc;
 421         u64 icrxatc;
 422         u64 ictxptc;
 423         u64 ictxatc;
 424         u64 ictxqec;
 425         u64 ictxqmtc;
 426         u64 icrxdmtc;
 427         u64 icrxoc;
 428         u64 cbtmpc;
 429         u64 htdpmc;
 430         u64 cbrdpc;
 431         u64 cbrmpc;
 432         u64 rpthc;
 433         u64 hgptc;
 434         u64 htcbdpc;
 435         u64 hgorc;
 436         u64 hgotc;
 437         u64 lenerrs;
 438         u64 scvpc;
 439         u64 hrmpc;
 440         u64 doosync;
 441         u64 o2bgptc;
 442         u64 o2bspc;
 443         u64 b2ospc;
 444         u64 b2ogprc;
 445 };
 446
 447
 448 struct e1000_phy_stats {
 449         u32 idle_errors;
 450         u32 receive_errors;
 451 };
 452
 453 struct e1000_host_mng_dhcp_cookie {
 454         u32 signature;
 455         u8  status;
 456         u8  reserved0;
 457         u16 vlan_id;
 458         u32 reserved1;
 459         u16 reserved2;
 460         u8  reserved3;
 461         u8  checksum;
 462 };
 463
 464 /* Host Interface "Rev 1" */
 465 struct e1000_host_command_header {
 466         u8 command_id;
 467         u8 command_length;
 468         u8 command_options;
 469         u8 checksum;
 470 };
 471
 472 #define E1000_HI_MAX_DATA_LENGTH        252
 473 struct e1000_host_command_info {
 474         struct e1000_host_command_header command_header;
 475         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 476 };
 477
 478 /* Host Interface "Rev 2" */
 479 struct e1000_host_mng_command_header {
 480         u8  command_id;
 481         u8  checksum;
 482         u16 reserved1;
 483         u16 reserved2;
 484         u16 command_length;
 485 };
 486
 487 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 488 struct e1000_host_mng_command_info {
 489         struct e1000_host_mng_command_header command_header;
 490         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 491 };
 492
 493 #include "e1000_mac.h"
 494 #include "e1000_phy.h"
 495 #include "e1000_nvm.h"
 496 #include "e1000_manage.h"
 497 #include "e1000_mbx.h"
 498
 499 /* Function pointers for the MAC. */
 500 struct e1000_mac_operations {
 501         s32  (*init_params)(struct e1000_hw *);
 502         s32  (*id_led_init)(struct e1000_hw *);
 503         s32  (*blink_led)(struct e1000_hw *);
 504         bool (*check_mng_mode)(struct e1000_hw *);
 505         s32  (*check_for_link)(struct e1000_hw *);
 506         s32  (*cleanup_led)(struct e1000_hw *);
 507         void (*clear_hw_cntrs)(struct e1000_hw *);
 508         void (*clear_vfta)(struct e1000_hw *);
 509         s32  (*get_bus_info)(struct e1000_hw *);
 510         void (*set_lan_id)(struct e1000_hw *);
 511         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 512         s32  (*led_on)(struct e1000_hw *);
 513         s32  (*led_off)(struct e1000_hw *);
 514         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 515         s32  (*reset_hw)(struct e1000_hw *);
 516         s32  (*init_hw)(struct e1000_hw *);
 517         void (*shutdown_serdes)(struct e1000_hw *);
 518         void (*power_up_serdes)(struct e1000_hw *);
 519         s32  (*setup_link)(struct e1000_hw *);
 520         s32  (*setup_physical_interface)(struct e1000_hw *);
 521         s32  (*setup_led)(struct e1000_hw *);
 522         void (*write_vfta)(struct e1000_hw *, u32, u32);
 523         void (*config_collision_dist)(struct e1000_hw *);
 524         void (*rar_set)(struct e1000_hw *, u8*, u32);
 525         s32  (*read_mac_addr)(struct e1000_hw *);
 526         s32  (*validate_mdi_setting)(struct e1000_hw *);
 527         s32 (*get_thermal_sensor_data)(struct e1000_hw *);
 528         s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
 529         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 530         void (*release_swfw_sync)(struct e1000_hw *, u16);
 531 };
 532
 533 /* When to use various PHY register access functions:
 534  *
 535  *                 Func   Caller
 536  *   Function      Does   Does    When to use
 537  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 538  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 539  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 540  *                                on different pages
 541  *   X_reg_page    A      L,P     for multiple accesses of different regs
 542  *                                on the same page
 543  *
 544  * Where X=[read|write], L=locking, P=sets page, A=register access
 545  *
 546  */
 547 struct e1000_phy_operations {
 548         s32  (*init_params)(struct e1000_hw *);
 549         s32  (*acquire)(struct e1000_hw *);
 550         s32  (*check_polarity)(struct e1000_hw *);
 551         s32  (*check_reset_block)(struct e1000_hw *);
 552         s32  (*commit)(struct e1000_hw *);
 553         s32  (*force_speed_duplex)(struct e1000_hw *);
 554         s32  (*get_cfg_done)(struct e1000_hw *hw);
 555         s32  (*get_cable_length)(struct e1000_hw *);
 556         s32  (*get_info)(struct e1000_hw *);
 557         s32  (*set_page)(struct e1000_hw *, u16);
 558         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 559         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 560         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 561         void (*release)(struct e1000_hw *);
 562         s32  (*reset)(struct e1000_hw *);
 563         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 564         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 565         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 566         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 567         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 568         void (*power_up)(struct e1000_hw *);
 569         void (*power_down)(struct e1000_hw *);
 570         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 571         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 572 };
 573
 574 /* Function pointers for the NVM. */
 575 struct e1000_nvm_operations {
 576         s32  (*init_params)(struct e1000_hw *);
 577         s32  (*acquire)(struct e1000_hw *);
 578         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 579         void (*release)(struct e1000_hw *);
 580         void (*reload)(struct e1000_hw *);
 581         s32  (*update)(struct e1000_hw *);
 582         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 583         s32  (*validate)(struct e1000_hw *);
 584         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 585 };
 586
 587 #define E1000_MAX_SENSORS               3
 588
 589 struct e1000_thermal_diode_data {
 590         u8 location;
 591         u8 temp;
 592         u8 caution_thresh;
 593         u8 max_op_thresh;
 594 };
 595
 596 struct e1000_thermal_sensor_data {
 597         struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
 598 };
 599
 600 struct e1000_mac_info {
 601         struct e1000_mac_operations ops;
 602         u8 addr[ETH_ADDR_LEN];
 603         u8 perm_addr[ETH_ADDR_LEN];
 604
 605         enum e1000_mac_type type;
 606
 607         u32 collision_delta;
 608         u32 ledctl_default;
 609         u32 ledctl_mode1;
 610         u32 ledctl_mode2;
 611         u32 mc_filter_type;
 612         u32 tx_packet_delta;
 613         u32 txcw;
 614
 615         u16 current_ifs_val;
 616         u16 ifs_max_val;
 617         u16 ifs_min_val;
 618         u16 ifs_ratio;
 619         u16 ifs_step_size;
 620         u16 mta_reg_count;
 621         u16 uta_reg_count;
 622
 623         /* Maximum size of the MTA register table in all supported adapters */
 624         #define MAX_MTA_REG 128
 625         u32 mta_shadow[MAX_MTA_REG];
 626         u16 rar_entry_count;
 627
 628         u8  forced_speed_duplex;
 629
 630         bool adaptive_ifs;
 631         bool has_fwsm;
 632         bool arc_subsystem_valid;
 633         bool asf_firmware_present;
 634         bool autoneg;
 635         bool autoneg_failed;
 636         bool get_link_status;
 637         bool in_ifs_mode;
 638         enum e1000_serdes_link_state serdes_link_state;
 639         bool serdes_has_link;
 640         bool tx_pkt_filtering;
 641         struct e1000_thermal_sensor_data thermal_sensor_data;
 642 };
 643
 644 struct e1000_phy_info {
 645         struct e1000_phy_operations ops;
 646         enum e1000_phy_type type;
 647
 648         enum e1000_1000t_rx_status local_rx;
 649         enum e1000_1000t_rx_status remote_rx;
 650         enum e1000_ms_type ms_type;
 651         enum e1000_ms_type original_ms_type;
 652         enum e1000_rev_polarity cable_polarity;
 653         enum e1000_smart_speed smart_speed;
 654
 655         u32 addr;
 656         u32 id;
 657         u32 reset_delay_us; /* in usec */
 658         u32 revision;
 659
 660         enum e1000_media_type media_type;
 661
 662         u16 autoneg_advertised;
 663         u16 autoneg_mask;
 664         u16 cable_length;
 665         u16 max_cable_length;
 666         u16 min_cable_length;
 667
 668         u8 mdix;
 669
 670         bool disable_polarity_correction;
 671         bool is_mdix;
 672         bool polarity_correction;
 673         bool reset_disable;
 674         bool speed_downgraded;
 675         bool autoneg_wait_to_complete;
 676 };
 677
 678 struct e1000_nvm_info {
 679         struct e1000_nvm_operations ops;
 680         enum e1000_nvm_type type;
 681         enum e1000_nvm_override override;
 682
 683         u32 flash_bank_size;
 684         u32 flash_base_addr;
 685
 686         u16 word_size;
 687         u16 delay_usec;
 688         u16 address_bits;
 689         u16 opcode_bits;
 690         u16 page_size;
 691 };
 692
 693 struct e1000_bus_info {
 694         enum e1000_bus_type type;
 695         enum e1000_bus_speed speed;
 696         enum e1000_bus_width width;
 697
 698         u16 func;
 699         u16 pci_cmd_word;
 700 };
 701
 702 struct e1000_fc_info {
 703         u32 high_water;  /* Flow control high-water mark */
 704         u32 low_water;  /* Flow control low-water mark */
 705         u16 pause_time;  /* Flow control pause timer */
 706         u16 refresh_time;  /* Flow control refresh timer */
 707         bool send_xon;  /* Flow control send XON */
 708         bool strict_ieee;  /* Strict IEEE mode */
 709         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 710         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 711 };
 712
 713 struct e1000_mbx_operations {
 714         s32 (*init_params)(struct e1000_hw *hw);
 715         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 716         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 717         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 718         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 719         s32 (*check_for_msg)(struct e1000_hw *, u16);
 720         s32 (*check_for_ack)(struct e1000_hw *, u16);
 721         s32 (*check_for_rst)(struct e1000_hw *, u16);
 722 };
 723
 724 struct e1000_mbx_stats {
 725         u32 msgs_tx;
 726         u32 msgs_rx;
 727
 728         u32 acks;
 729         u32 reqs;
 730         u32 rsts;
 731 };
 732
 733 struct e1000_mbx_info {
 734         struct e1000_mbx_operations ops;
 735         struct e1000_mbx_stats stats;
 736         u32 timeout;
 737         u32 usec_delay;
 738         u16 size;
 739 };
 740
 741 struct e1000_dev_spec_82575 {
 742         bool sgmii_active;
 743         bool global_device_reset;
 744         bool eee_disable;
 745         bool module_plugged;
 746         bool clear_semaphore_once;
 747         u32 mtu;
 748         struct sfp_e1000_flags eth_flags;
 749         u8 media_port;
 750         bool media_changed;
 751 };
 752
 753 struct e1000_dev_spec_vf {
 754         u32 vf_number;
 755         u32 v2p_mailbox;
 756 };
 757
 758 struct e1000_hw {
 759         void *back;
 760
 761         u8 __iomem *hw_addr;
 762         u8 __iomem *flash_address;
 763         unsigned long io_base;
 764
 765         struct e1000_mac_info  mac;
 766         struct e1000_fc_info   fc;
 767         struct e1000_phy_info  phy;
 768         struct e1000_nvm_info  nvm;
 769         struct e1000_bus_info  bus;
 770         struct e1000_mbx_info mbx;
 771         struct e1000_host_mng_dhcp_cookie mng_cookie;
 772
 773         union {
 774                 struct e1000_dev_spec_82575 _82575;
 775                 struct e1000_dev_spec_vf vf;
 776         } dev_spec;
 777
 778         u16 device_id;
 779         u16 subsystem_vendor_id;
 780         u16 subsystem_device_id;
 781         u16 vendor_id;
 782
 783         u8  revision_id;
 784 };
 785
 786 #include "e1000_82575.h"
 787 #include "e1000_i210.h"
 788
 789 /* These functions must be implemented by drivers */
 790 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 791 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 792
 793 #endif