lib/librte_eal/linuxapp/kni/ethtool/igb/igb_ptp.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /******************************************************************************
  29  Copyright(c) 2011 Richard Cochran <richardcochran@gmail.com> for some of the
  30  82576 and 82580 code
  31 ******************************************************************************/
  32
  33 #include "igb.h"
  34
  35 #include <linux/module.h>
  36 #include <linux/device.h>
  37 #include <linux/pci.h>
  38 #include <linux/ptp_classify.h>
  39
  40 #define INCVALUE_MASK           0x7fffffff
  41 #define ISGN                    0x80000000
  42
  43 /*
  44  * The 82580 timesync updates the system timer every 8ns by 8ns,
  45  * and this update value cannot be reprogrammed.
  46  *
  47  * Neither the 82576 nor the 82580 offer registers wide enough to hold
  48  * nanoseconds time values for very long. For the 82580, SYSTIM always
  49  * counts nanoseconds, but the upper 24 bits are not available. The
  50  * frequency is adjusted by changing the 32 bit fractional nanoseconds
  51  * register, TIMINCA.
  52  *
  53  * For the 82576, the SYSTIM register time unit is affect by the
  54  * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
  55  * field are needed to provide the nominal 16 nanosecond period,
  56  * leaving 19 bits for fractional nanoseconds.
  57  *
  58  * We scale the NIC clock cycle by a large factor so that relatively
  59  * small clock corrections can be added or subtracted at each clock
  60  * tick. The drawbacks of a large factor are a) that the clock
  61  * register overflows more quickly (not such a big deal) and b) that
  62  * the increment per tick has to fit into 24 bits.  As a result we
  63  * need to use a shift of 19 so we can fit a value of 16 into the
  64  * TIMINCA register.
  65  *
  66  *
  67  *             SYSTIMH            SYSTIML
  68  *        +--------------+   +---+---+------+
  69  *  82576 |      32      |   | 8 | 5 |  19  |
  70  *        +--------------+   +---+---+------+
  71  *         \________ 45 bits _______/  fract
  72  *
  73  *        +----------+---+   +--------------+
  74  *  82580 |    24    | 8 |   |      32      |
  75  *        +----------+---+   +--------------+
  76  *          reserved  \______ 40 bits _____/
  77  *
  78  *
  79  * The 45 bit 82576 SYSTIM overflows every
  80  *   2^45 * 10^-9 / 3600 = 9.77 hours.
  81  *
  82  * The 40 bit 82580 SYSTIM overflows every
  83  *   2^40 * 10^-9 /  60  = 18.3 minutes.
  84  */
  85
  86 #define IGB_SYSTIM_OVERFLOW_PERIOD      (HZ * 60 * 9)
  87 #define IGB_PTP_TX_TIMEOUT              (HZ * 15)
  88 #define INCPERIOD_82576                 (1 << E1000_TIMINCA_16NS_SHIFT)
  89 #define INCVALUE_82576_MASK             ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
  90 #define INCVALUE_82576                  (16 << IGB_82576_TSYNC_SHIFT)
  91 #define IGB_NBITS_82580                 40
  92
  93 /*
  94  * SYSTIM read access for the 82576
  95  */
  96
  97 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
  98 {
  99         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
 100         struct e1000_hw *hw = &igb->hw;
 101         u64 val;
 102         u32 lo, hi;
 103
 104         lo = E1000_READ_REG(hw, E1000_SYSTIML);
 105         hi = E1000_READ_REG(hw, E1000_SYSTIMH);
 106
 107         val = ((u64) hi) << 32;
 108         val |= lo;
 109
 110         return val;
 111 }
 112
 113 /*
 114  * SYSTIM read access for the 82580
 115  */
 116
 117 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
 118 {
 119         struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
 120         struct e1000_hw *hw = &igb->hw;
 121         u64 val;
 122         u32 lo, hi;
 123
 124         /* The timestamp latches on lowest register read. For the 82580
 125          * the lowest register is SYSTIMR instead of SYSTIML.  However we only
 126          * need to provide nanosecond resolution, so we just ignore it.
 127          */
 128         E1000_READ_REG(hw, E1000_SYSTIMR);
 129         lo = E1000_READ_REG(hw, E1000_SYSTIML);
 130         hi = E1000_READ_REG(hw, E1000_SYSTIMH);
 131
 132         val = ((u64) hi) << 32;
 133         val |= lo;
 134
 135         return val;
 136 }
 137
 138 /*
 139  * SYSTIM read access for I210/I211
 140  */
 141
 142 static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts)
 143 {
 144         struct e1000_hw *hw = &adapter->hw;
 145         u32 sec, nsec;
 146
 147         /* The timestamp latches on lowest register read. For I210/I211, the
 148          * lowest register is SYSTIMR. Since we only need to provide nanosecond
 149          * resolution, we can ignore it.
 150          */
 151         E1000_READ_REG(hw, E1000_SYSTIMR);
 152         nsec = E1000_READ_REG(hw, E1000_SYSTIML);
 153         sec = E1000_READ_REG(hw, E1000_SYSTIMH);
 154
 155         ts->tv_sec = sec;
 156         ts->tv_nsec = nsec;
 157 }
 158
 159 static void igb_ptp_write_i210(struct igb_adapter *adapter,
 160                                const struct timespec *ts)
 161 {
 162         struct e1000_hw *hw = &adapter->hw;
 163
 164         /*
 165          * Writing the SYSTIMR register is not necessary as it only provides
 166          * sub-nanosecond resolution.
 167          */
 168         E1000_WRITE_REG(hw, E1000_SYSTIML, ts->tv_nsec);
 169         E1000_WRITE_REG(hw, E1000_SYSTIMH, ts->tv_sec);
 170 }
 171
 172 /**
 173  * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
 174  * @adapter: board private structure
 175  * @hwtstamps: timestamp structure to update
 176  * @systim: unsigned 64bit system time value.
 177  *
 178  * We need to convert the system time value stored in the RX/TXSTMP registers
 179  * into a hwtstamp which can be used by the upper level timestamping functions.
 180  *
 181  * The 'tmreg_lock' spinlock is used to protect the consistency of the
 182  * system time value. This is needed because reading the 64 bit time
 183  * value involves reading two (or three) 32 bit registers. The first
 184  * read latches the value. Ditto for writing.
 185  *
 186  * In addition, here have extended the system time with an overflow
 187  * counter in software.
 188  **/
 189 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
 190                                        struct skb_shared_hwtstamps *hwtstamps,
 191                                        u64 systim)
 192 {
 193         unsigned long flags;
 194         u64 ns;
 195
 196         switch (adapter->hw.mac.type) {
 197         case e1000_82576:
 198         case e1000_82580:
 199         case e1000_i350:
 200         case e1000_i354:
 201                 spin_lock_irqsave(&adapter->tmreg_lock, flags);
 202
 203                 ns = timecounter_cyc2time(&adapter->tc, systim);
 204
 205                 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 206
 207                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 208                 hwtstamps->hwtstamp = ns_to_ktime(ns);
 209                 break;
 210         case e1000_i210:
 211         case e1000_i211:
 212                 memset(hwtstamps, 0, sizeof(*hwtstamps));
 213                 /* Upper 32 bits contain s, lower 32 bits contain ns. */
 214                 hwtstamps->hwtstamp = ktime_set(systim >> 32,
 215                                                 systim & 0xFFFFFFFF);
 216                 break;
 217         default:
 218                 break;
 219         }
 220 }
 221
 222 /*
 223  * PTP clock operations
 224  */
 225
 226 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
 227 {
 228         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 229                                                ptp_caps);
 230         struct e1000_hw *hw = &igb->hw;
 231         int neg_adj = 0;
 232         u64 rate;
 233         u32 incvalue;
 234
 235         if (ppb < 0) {
 236                 neg_adj = 1;
 237                 ppb = -ppb;
 238         }
 239         rate = ppb;
 240         rate <<= 14;
 241         rate = div_u64(rate, 1953125);
 242
 243         incvalue = 16 << IGB_82576_TSYNC_SHIFT;
 244
 245         if (neg_adj)
 246                 incvalue -= rate;
 247         else
 248                 incvalue += rate;
 249
 250         E1000_WRITE_REG(hw, E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
 251
 252         return 0;
 253 }
 254
 255 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
 256 {
 257         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 258                                                ptp_caps);
 259         struct e1000_hw *hw = &igb->hw;
 260         int neg_adj = 0;
 261         u64 rate;
 262         u32 inca;
 263
 264         if (ppb < 0) {
 265                 neg_adj = 1;
 266                 ppb = -ppb;
 267         }
 268         rate = ppb;
 269         rate <<= 26;
 270         rate = div_u64(rate, 1953125);
 271
 272         /* At 2.5G speeds, the TIMINCA register on I354 updates the clock 2.5x
 273          * as quickly. Account for this by dividing the adjustment by 2.5.
 274          */
 275         if (hw->mac.type == e1000_i354) {
 276                 u32 status = E1000_READ_REG(hw, E1000_STATUS);
 277
 278                 if ((status & E1000_STATUS_2P5_SKU) &&
 279                     !(status & E1000_STATUS_2P5_SKU_OVER)) {
 280                         rate <<= 1;
 281                         rate = div_u64(rate, 5);
 282                 }
 283         }
 284
 285         inca = rate & INCVALUE_MASK;
 286         if (neg_adj)
 287                 inca |= ISGN;
 288
 289         E1000_WRITE_REG(hw, E1000_TIMINCA, inca);
 290
 291         return 0;
 292 }
 293
 294 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
 295 {
 296         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 297                                                ptp_caps);
 298         unsigned long flags;
 299         s64 now;
 300
 301         spin_lock_irqsave(&igb->tmreg_lock, flags);
 302
 303         now = timecounter_read(&igb->tc);
 304         now += delta;
 305         timecounter_init(&igb->tc, &igb->cc, now);
 306
 307         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 308
 309         return 0;
 310 }
 311
 312 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
 313 {
 314         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 315                                                ptp_caps);
 316         unsigned long flags;
 317         struct timespec now, then = ns_to_timespec(delta);
 318
 319         spin_lock_irqsave(&igb->tmreg_lock, flags);
 320
 321         igb_ptp_read_i210(igb, &now);
 322         now = timespec_add(now, then);
 323         igb_ptp_write_i210(igb, (const struct timespec *)&now);
 324
 325         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 326
 327         return 0;
 328 }
 329
 330 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
 331                                  struct timespec *ts)
 332 {
 333         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 334                                                ptp_caps);
 335         unsigned long flags;
 336         u64 ns;
 337         u32 remainder;
 338
 339         spin_lock_irqsave(&igb->tmreg_lock, flags);
 340
 341         ns = timecounter_read(&igb->tc);
 342
 343         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 344
 345         ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
 346         ts->tv_nsec = remainder;
 347
 348         return 0;
 349 }
 350
 351 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
 352                                 struct timespec *ts)
 353 {
 354         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 355                                                ptp_caps);
 356         unsigned long flags;
 357
 358         spin_lock_irqsave(&igb->tmreg_lock, flags);
 359
 360         igb_ptp_read_i210(igb, ts);
 361
 362         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 363
 364         return 0;
 365 }
 366
 367 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
 368                                  const struct timespec *ts)
 369 {
 370         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 371                                                ptp_caps);
 372         unsigned long flags;
 373         u64 ns;
 374
 375         ns = ts->tv_sec * 1000000000ULL;
 376         ns += ts->tv_nsec;
 377
 378         spin_lock_irqsave(&igb->tmreg_lock, flags);
 379
 380         timecounter_init(&igb->tc, &igb->cc, ns);
 381
 382         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 383
 384         return 0;
 385 }
 386
 387 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
 388                                 const struct timespec *ts)
 389 {
 390         struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
 391                                                ptp_caps);
 392         unsigned long flags;
 393
 394         spin_lock_irqsave(&igb->tmreg_lock, flags);
 395
 396         igb_ptp_write_i210(igb, ts);
 397
 398         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
 399
 400         return 0;
 401 }
 402
 403 static int igb_ptp_enable(struct ptp_clock_info *ptp,
 404                           struct ptp_clock_request *rq, int on)
 405 {
 406         return -EOPNOTSUPP;
 407 }
 408
 409 /**
 410  * igb_ptp_tx_work
 411  * @work: pointer to work struct
 412  *
 413  * This work function polls the TSYNCTXCTL valid bit to determine when a
 414  * timestamp has been taken for the current stored skb.
 415  */
 416 void igb_ptp_tx_work(struct work_struct *work)
 417 {
 418         struct igb_adapter *adapter = container_of(work, struct igb_adapter,
 419                                                    ptp_tx_work);
 420         struct e1000_hw *hw = &adapter->hw;
 421         u32 tsynctxctl;
 422
 423         if (!adapter->ptp_tx_skb)
 424                 return;
 425
 426         if (time_is_before_jiffies(adapter->ptp_tx_start +
 427                                    IGB_PTP_TX_TIMEOUT)) {
 428                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 429                 adapter->ptp_tx_skb = NULL;
 430                 adapter->tx_hwtstamp_timeouts++;
 431                 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang");
 432                 return;
 433         }
 434
 435         tsynctxctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
 436         if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
 437                 igb_ptp_tx_hwtstamp(adapter);
 438         else
 439                 /* reschedule to check later */
 440                 schedule_work(&adapter->ptp_tx_work);
 441 }
 442
 443 static void igb_ptp_overflow_check(struct work_struct *work)
 444 {
 445         struct igb_adapter *igb =
 446                 container_of(work, struct igb_adapter, ptp_overflow_work.work);
 447         struct timespec ts;
 448
 449         igb->ptp_caps.gettime(&igb->ptp_caps, &ts);
 450
 451         pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);
 452
 453         schedule_delayed_work(&igb->ptp_overflow_work,
 454                               IGB_SYSTIM_OVERFLOW_PERIOD);
 455 }
 456
 457 /**
 458  * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
 459  * @adapter: private network adapter structure
 460  *
 461  * This watchdog task is scheduled to detect error case where hardware has
 462  * dropped an Rx packet that was timestamped when the ring is full. The
 463  * particular error is rare but leaves the device in a state unable to timestamp
 464  * any future packets.
 465  */
 466 void igb_ptp_rx_hang(struct igb_adapter *adapter)
 467 {
 468         struct e1000_hw *hw = &adapter->hw;
 469         struct igb_ring *rx_ring;
 470         u32 tsyncrxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
 471         unsigned long rx_event;
 472         int n;
 473
 474         if (hw->mac.type != e1000_82576)
 475                 return;
 476
 477         /* If we don't have a valid timestamp in the registers, just update the
 478          * timeout counter and exit
 479          */
 480         if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
 481                 adapter->last_rx_ptp_check = jiffies;
 482                 return;
 483         }
 484
 485         /* Determine the most recent watchdog or rx_timestamp event */
 486         rx_event = adapter->last_rx_ptp_check;
 487         for (n = 0; n < adapter->num_rx_queues; n++) {
 488                 rx_ring = adapter->rx_ring[n];
 489                 if (time_after(rx_ring->last_rx_timestamp, rx_event))
 490                         rx_event = rx_ring->last_rx_timestamp;
 491         }
 492
 493         /* Only need to read the high RXSTMP register to clear the lock */
 494         if (time_is_before_jiffies(rx_event + 5 * HZ)) {
 495                 E1000_READ_REG(hw, E1000_RXSTMPH);
 496                 adapter->last_rx_ptp_check = jiffies;
 497                 adapter->rx_hwtstamp_cleared++;
 498                 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang");
 499         }
 500 }
 501
 502 /**
 503  * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 504  * @adapter: Board private structure.
 505  *
 506  * If we were asked to do hardware stamping and such a time stamp is
 507  * available, then it must have been for this skb here because we only
 508  * allow only one such packet into the queue.
 509  */
 510 void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
 511 {
 512         struct e1000_hw *hw = &adapter->hw;
 513         struct skb_shared_hwtstamps shhwtstamps;
 514         u64 regval;
 515
 516         regval = E1000_READ_REG(hw, E1000_TXSTMPL);
 517         regval |= (u64)E1000_READ_REG(hw, E1000_TXSTMPH) << 32;
 518
 519         igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
 520         skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
 521         dev_kfree_skb_any(adapter->ptp_tx_skb);
 522         adapter->ptp_tx_skb = NULL;
 523 }
 524
 525 /**
 526  * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
 527  * @q_vector: Pointer to interrupt specific structure
 528  * @va: Pointer to address containing Rx buffer
 529  * @skb: Buffer containing timestamp and packet
 530  *
 531  * This function is meant to retrieve a timestamp from the first buffer of an
 532  * incoming frame.  The value is stored in little endian format starting on
 533  * byte 8.
 534  */
 535 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
 536                          unsigned char *va,
 537                          struct sk_buff *skb)
 538 {
 539         __le64 *regval = (__le64 *)va;
 540
 541         /*
 542          * The timestamp is recorded in little endian format.
 543          * DWORD: 0        1        2        3
 544          * Field: Reserved Reserved SYSTIML  SYSTIMH
 545          */
 546         igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
 547                                    le64_to_cpu(regval[1]));
 548 }
 549
 550 /**
 551  * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
 552  * @q_vector: Pointer to interrupt specific structure
 553  * @skb: Buffer containing timestamp and packet
 554  *
 555  * This function is meant to retrieve a timestamp from the internal registers
 556  * of the adapter and store it in the skb.
 557  */
 558 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
 559                          struct sk_buff *skb)
 560 {
 561         struct igb_adapter *adapter = q_vector->adapter;
 562         struct e1000_hw *hw = &adapter->hw;
 563         u64 regval;
 564
 565         /*
 566          * If this bit is set, then the RX registers contain the time stamp. No
 567          * other packet will be time stamped until we read these registers, so
 568          * read the registers to make them available again. Because only one
 569          * packet can be time stamped at a time, we know that the register
 570          * values must belong to this one here and therefore we don't need to
 571          * compare any of the additional attributes stored for it.
 572          *
 573          * If nothing went wrong, then it should have a shared tx_flags that we
 574          * can turn into a skb_shared_hwtstamps.
 575          */
 576         if (!(E1000_READ_REG(hw, E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
 577                 return;
 578
 579         regval = E1000_READ_REG(hw, E1000_RXSTMPL);
 580         regval |= (u64)E1000_READ_REG(hw, E1000_RXSTMPH) << 32;
 581
 582         igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
 583 }
 584
 585 /**
 586  * igb_ptp_hwtstamp_ioctl - control hardware time stamping
 587  * @netdev:
 588  * @ifreq:
 589  * @cmd:
 590  *
 591  * Outgoing time stamping can be enabled and disabled. Play nice and
 592  * disable it when requested, although it shouldn't case any overhead
 593  * when no packet needs it. At most one packet in the queue may be
 594  * marked for time stamping, otherwise it would be impossible to tell
 595  * for sure to which packet the hardware time stamp belongs.
 596  *
 597  * Incoming time stamping has to be configured via the hardware
 598  * filters. Not all combinations are supported, in particular event
 599  * type has to be specified. Matching the kind of event packet is
 600  * not supported, with the exception of "all V2 events regardless of
 601  * level 2 or 4".
 602  *
 603  **/
 604 int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
 605                            struct ifreq *ifr, int cmd)
 606 {
 607         struct igb_adapter *adapter = netdev_priv(netdev);
 608         struct e1000_hw *hw = &adapter->hw;
 609         struct hwtstamp_config config;
 610         u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
 611         u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 612         u32 tsync_rx_cfg = 0;
 613         bool is_l4 = false;
 614         bool is_l2 = false;
 615         u32 regval;
 616
 617         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 618                 return -EFAULT;
 619
 620         /* reserved for future extensions */
 621         if (config.flags)
 622                 return -EINVAL;
 623
 624         switch (config.tx_type) {
 625         case HWTSTAMP_TX_OFF:
 626                 tsync_tx_ctl = 0;
 627         case HWTSTAMP_TX_ON:
 628                 break;
 629         default:
 630                 return -ERANGE;
 631         }
 632
 633         switch (config.rx_filter) {
 634         case HWTSTAMP_FILTER_NONE:
 635                 tsync_rx_ctl = 0;
 636                 break;
 637         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 638                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 639                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
 640                 is_l4 = true;
 641                 break;
 642         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 643                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
 644                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
 645                 is_l4 = true;
 646                 break;
 647         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 648         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 649         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 650         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 651         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 652         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 653         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 654         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 655         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 656                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
 657                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 658                 is_l2 = true;
 659                 is_l4 = true;
 660                 break;
 661         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 662         case HWTSTAMP_FILTER_ALL:
 663                 /*
 664                  * 82576 cannot timestamp all packets, which it needs to do to
 665                  * support both V1 Sync and Delay_Req messages
 666                  */
 667                 if (hw->mac.type != e1000_82576) {
 668                         tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 669                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 670                         break;
 671                 }
 672                 /* fall through */
 673         default:
 674                 config.rx_filter = HWTSTAMP_FILTER_NONE;
 675                 return -ERANGE;
 676         }
 677
 678         if (hw->mac.type == e1000_82575) {
 679                 if (tsync_rx_ctl | tsync_tx_ctl)
 680                         return -EINVAL;
 681                 return 0;
 682         }
 683
 684         /*
 685          * Per-packet timestamping only works if all packets are
 686          * timestamped, so enable timestamping in all packets as
 687          * long as one rx filter was configured.
 688          */
 689         if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
 690                 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
 691                 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
 692                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 693                 is_l2 = true;
 694                 is_l4 = true;
 695
 696                 if ((hw->mac.type == e1000_i210) ||
 697                     (hw->mac.type == e1000_i211)) {
 698                         regval = E1000_READ_REG(hw, E1000_RXPBS);
 699                         regval |= E1000_RXPBS_CFG_TS_EN;
 700                         E1000_WRITE_REG(hw, E1000_RXPBS, regval);
 701                 }
 702         }
 703
 704         /* enable/disable TX */
 705         regval = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
 706         regval &= ~E1000_TSYNCTXCTL_ENABLED;
 707         regval |= tsync_tx_ctl;
 708         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, regval);
 709
 710         /* enable/disable RX */
 711         regval = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
 712         regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
 713         regval |= tsync_rx_ctl;
 714         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, regval);
 715
 716         /* define which PTP packets are time stamped */
 717         E1000_WRITE_REG(hw, E1000_TSYNCRXCFG, tsync_rx_cfg);
 718
 719         /* define ethertype filter for timestamped packets */
 720         if (is_l2)
 721                 E1000_WRITE_REG(hw, E1000_ETQF(3),
 722                      (E1000_ETQF_FILTER_ENABLE | /* enable filter */
 723                       E1000_ETQF_1588 | /* enable timestamping */
 724                       ETH_P_1588));     /* 1588 eth protocol type */
 725         else
 726                 E1000_WRITE_REG(hw, E1000_ETQF(3), 0);
 727
 728         /* L4 Queue Filter[3]: filter by destination port and protocol */
 729         if (is_l4) {
 730                 u32 ftqf = (IPPROTO_UDP /* UDP */
 731                         | E1000_FTQF_VF_BP /* VF not compared */
 732                         | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
 733                         | E1000_FTQF_MASK); /* mask all inputs */
 734                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
 735
 736                 E1000_WRITE_REG(hw, E1000_IMIR(3), htons(PTP_EV_PORT));
 737                 E1000_WRITE_REG(hw, E1000_IMIREXT(3),
 738                      (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
 739                 if (hw->mac.type == e1000_82576) {
 740                         /* enable source port check */
 741                         E1000_WRITE_REG(hw, E1000_SPQF(3), htons(PTP_EV_PORT));
 742                         ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
 743                 }
 744                 E1000_WRITE_REG(hw, E1000_FTQF(3), ftqf);
 745         } else {
 746                 E1000_WRITE_REG(hw, E1000_FTQF(3), E1000_FTQF_MASK);
 747         }
 748         E1000_WRITE_FLUSH(hw);
 749
 750         /* clear TX/RX time stamp registers, just to be sure */
 751         regval = E1000_READ_REG(hw, E1000_TXSTMPL);
 752         regval = E1000_READ_REG(hw, E1000_TXSTMPH);
 753         regval = E1000_READ_REG(hw, E1000_RXSTMPL);
 754         regval = E1000_READ_REG(hw, E1000_RXSTMPH);
 755
 756         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 757                 -EFAULT : 0;
 758 }
 759
 760 void igb_ptp_init(struct igb_adapter *adapter)
 761 {
 762         struct e1000_hw *hw = &adapter->hw;
 763         struct net_device *netdev = adapter->netdev;
 764
 765         switch (hw->mac.type) {
 766         case e1000_82576:
 767                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 768                 adapter->ptp_caps.owner = THIS_MODULE;
 769                 adapter->ptp_caps.max_adj = 999999881;
 770                 adapter->ptp_caps.n_ext_ts = 0;
 771                 adapter->ptp_caps.pps = 0;
 772                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
 773                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
 774                 adapter->ptp_caps.gettime = igb_ptp_gettime_82576;
 775                 adapter->ptp_caps.settime = igb_ptp_settime_82576;
 776                 adapter->ptp_caps.enable = igb_ptp_enable;
 777                 adapter->cc.read = igb_ptp_read_82576;
 778                 adapter->cc.mask = CLOCKSOURCE_MASK(64);
 779                 adapter->cc.mult = 1;
 780                 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
 781                 /* Dial the nominal frequency. */
 782                 E1000_WRITE_REG(hw, E1000_TIMINCA, INCPERIOD_82576 |
 783                                                    INCVALUE_82576);
 784                 break;
 785         case e1000_82580:
 786         case e1000_i350:
 787         case e1000_i354:
 788                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 789                 adapter->ptp_caps.owner = THIS_MODULE;
 790                 adapter->ptp_caps.max_adj = 62499999;
 791                 adapter->ptp_caps.n_ext_ts = 0;
 792                 adapter->ptp_caps.pps = 0;
 793                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
 794                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
 795                 adapter->ptp_caps.gettime = igb_ptp_gettime_82576;
 796                 adapter->ptp_caps.settime = igb_ptp_settime_82576;
 797                 adapter->ptp_caps.enable = igb_ptp_enable;
 798                 adapter->cc.read = igb_ptp_read_82580;
 799                 adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580);
 800                 adapter->cc.mult = 1;
 801                 adapter->cc.shift = 0;
 802                 /* Enable the timer functions by clearing bit 31. */
 803                 E1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);
 804                 break;
 805         case e1000_i210:
 806         case e1000_i211:
 807                 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
 808                 adapter->ptp_caps.owner = THIS_MODULE;
 809                 adapter->ptp_caps.max_adj = 62499999;
 810                 adapter->ptp_caps.n_ext_ts = 0;
 811                 adapter->ptp_caps.pps = 0;
 812                 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
 813                 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
 814                 adapter->ptp_caps.gettime = igb_ptp_gettime_i210;
 815                 adapter->ptp_caps.settime = igb_ptp_settime_i210;
 816                 adapter->ptp_caps.enable = igb_ptp_enable;
 817                 /* Enable the timer functions by clearing bit 31. */
 818                 E1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);
 819                 break;
 820         default:
 821                 adapter->ptp_clock = NULL;
 822                 return;
 823         }
 824
 825         E1000_WRITE_FLUSH(hw);
 826
 827         spin_lock_init(&adapter->tmreg_lock);
 828         INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
 829
 830         /* Initialize the clock and overflow work for devices that need it. */
 831         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
 832                 struct timespec ts = ktime_to_timespec(ktime_get_real());
 833
 834                 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
 835         } else {
 836                 timecounter_init(&adapter->tc, &adapter->cc,
 837                                  ktime_to_ns(ktime_get_real()));
 838
 839                 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
 840                                   igb_ptp_overflow_check);
 841
 842                 schedule_delayed_work(&adapter->ptp_overflow_work,
 843                                       IGB_SYSTIM_OVERFLOW_PERIOD);
 844         }
 845
 846         /* Initialize the time sync interrupts for devices that support it. */
 847         if (hw->mac.type >= e1000_82580) {
 848                 E1000_WRITE_REG(hw, E1000_TSIM, E1000_TSIM_TXTS);
 849                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_TS);
 850         }
 851
 852         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
 853                                                 &adapter->pdev->dev);
 854         if (IS_ERR(adapter->ptp_clock)) {
 855                 adapter->ptp_clock = NULL;
 856                 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
 857         } else {
 858                 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
 859                          adapter->netdev->name);
 860                 adapter->flags |= IGB_FLAG_PTP;
 861         }
 862 }
 863
 864 /**
 865  * igb_ptp_stop - Disable PTP device and stop the overflow check.
 866  * @adapter: Board private structure.
 867  *
 868  * This function stops the PTP support and cancels the delayed work.
 869  **/
 870 void igb_ptp_stop(struct igb_adapter *adapter)
 871 {
 872         switch (adapter->hw.mac.type) {
 873         case e1000_82576:
 874         case e1000_82580:
 875         case e1000_i350:
 876         case e1000_i354:
 877                 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
 878                 break;
 879         case e1000_i210:
 880         case e1000_i211:
 881                 /* No delayed work to cancel. */
 882                 break;
 883         default:
 884                 return;
 885         }
 886
 887         cancel_work_sync(&adapter->ptp_tx_work);
 888         if (adapter->ptp_tx_skb) {
 889                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 890                 adapter->ptp_tx_skb = NULL;
 891         }
 892
 893         if (adapter->ptp_clock) {
 894                 ptp_clock_unregister(adapter->ptp_clock);
 895                 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
 896                          adapter->netdev->name);
 897                 adapter->flags &= ~IGB_FLAG_PTP;
 898         }
 899 }
 900
 901 /**
 902  * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
 903  * @adapter: Board private structure.
 904  *
 905  * This function handles the reset work required to re-enable the PTP device.
 906  **/
 907 void igb_ptp_reset(struct igb_adapter *adapter)
 908 {
 909         struct e1000_hw *hw = &adapter->hw;
 910
 911         if (!(adapter->flags & IGB_FLAG_PTP))
 912                 return;
 913
 914         switch (adapter->hw.mac.type) {
 915         case e1000_82576:
 916                 /* Dial the nominal frequency. */
 917                 E1000_WRITE_REG(hw, E1000_TIMINCA, INCPERIOD_82576 |
 918                                                    INCVALUE_82576);
 919                 break;
 920         case e1000_82580:
 921         case e1000_i350:
 922         case e1000_i354:
 923         case e1000_i210:
 924         case e1000_i211:
 925                 /* Enable the timer functions and interrupts. */
 926                 E1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);
 927                 E1000_WRITE_REG(hw, E1000_TSIM, E1000_TSIM_TXTS);
 928                 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_TS);
 929                 break;
 930         default:
 931                 /* No work to do. */
 932                 return;
 933         }
 934
 935         /* Re-initialize the timer. */
 936         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
 937                 struct timespec ts = ktime_to_timespec(ktime_get_real());
 938
 939                 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
 940         } else {
 941                 timecounter_init(&adapter->tc, &adapter->cc,
 942                                  ktime_to_ns(ktime_get_real()));
 943         }
 944 }